17179 lines
1.2 MiB
17179 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: MT2523 On-Chip Peripherals
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; @Props: Released
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; @Author: RSZ, BCA
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; @Changelog: 2017-10-05 BCA
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; @Manufacturer: MediaTek Inc.
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; @Doc: MT2523_Reference_Manual_Public.pdf (rev. 1.1 2016-12-14)
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; @Chip: MT2523
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; @Core: Cortex-M4F
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: permt2523.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; --------------------------------------------------------------------------------
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; Known problems:
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; Module Register Description
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; USB Many registers Unknown field types (A0, Other)
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "EINT (External Interrupt Controller)"
|
|
base ad:0xA2030300
|
|
width 28.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "EINT_STA,EINT Interrupt Status Register"
|
|
bitfld.long 0x00 31. " EINT_STA[31] ,External interrupt status bit [31]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,External interrupt status bit [30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,External interrupt status bit [29]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,External interrupt status bit [28]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,External interrupt status bit [27]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,External interrupt status bit [26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [25] ,External interrupt status bit [25]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,External interrupt status bit [24]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,External interrupt status bit [23]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,External interrupt status bit [22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,External interrupt status bit [21]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,External interrupt status bit [20]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,External interrupt status bit [19]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,External interrupt status bit [18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,External interrupt status bit [17]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,External interrupt status bit [16]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,External interrupt status bit [15]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,External interrupt status bit [14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,External interrupt status bit [13]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,External interrupt status bit [12]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,External interrupt status bit [11]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,External interrupt status bit [10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,External interrupt status bit [9]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,External interrupt status bit [8]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,External interrupt status bit [7]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,External interrupt status bit [6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,External interrupt status bit [5]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,External interrupt status bit [4]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,External interrupt status bit [3]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,External interrupt status bit [2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,External interrupt status bit [1]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,External interrupt status bit [0]" "No interrupt,Interrupt"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "EINT_INTACK,EINT Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 31. " EINT_INTACK[31] ,EINT31 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 30. " [30] ,EINT30 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 29. " [29] ,EINT29 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 28. " [28] ,EINT28 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,EINT27 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 26. " [26] ,EINT26 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 25. " [25] ,EINT25 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 24. " [24] ,EINT24 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,EINT23 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 22. " [22] ,EINT22 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 21. " [21] ,EINT21 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 20. " [20] ,EINT20 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,EINT19 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 18. " [18] ,EINT18 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 17. " [17] ,EINT17 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 16. " [16] ,EINT16 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,EINT15 interrupt request acknowledge" "No effect,Requested"
|
|
bitfld.long 0x00 14. " [14] ,EINT14 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 13. " [13] ,EINT13 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 12. " [12] ,EINT12 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,EINT11 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 10. " [10] ,EINT10 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 9. " [9] ,EINT9 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 8. " [8] ,EINT8 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,EINT7 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 6. " [6] ,EINT6 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 5. " [5] ,EINT5 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 4. " [4] ,EINT4 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,EINT3 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 2. " [2] ,EINT2 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 1. " [1] ,EINT1 interrupt request acknowledge" "No effect,Acknowledge"
|
|
bitfld.long 0x00 0. " [0] ,EINT0 interrupt request acknowledge" "No effect,Acknowledge"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EINT_EEVT,EINT Wakeup Event_b Status Register"
|
|
bitfld.long 0x00 0. " EEB ,EINT wake up sleep mode disable" "No,Yes"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EINT_MASK_SET/CLR,EINT Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " EINT_MASK[31] ,EINT31 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,EINT30 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,EINT29 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,EINT28 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,EINT27 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,EINT26 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,EINT25 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,EINT24 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,EINT23 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,EINT22 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,EINT21 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,EINT20 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,EINT19 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,EINT18 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,EINT17 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,EINT16 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,EINT15 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,EINT14 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,EINT13 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,EINT12 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,EINT11 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,EINT10 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,EINT9 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,EINT8 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,EINT7 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,EINT6 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,EINT5 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,EINT4 interrupt mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,EINT3 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,EINT2 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,EINT1 interrupt mask" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,EINT0 interrupt mask" "No interrupt,Interrupt"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "EINT_WAKEUP_MASK_SET/CLR,EINT Wakeup Event Mask Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " EINT_WAKEUP_MASK[31] ,EINT31 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,EINT30 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,EINT29 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,EINT28 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,EINT27 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,EINT26 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,EINT25 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,EINT24 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,EINT23 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,EINT22 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,EINT21 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,EINT20 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,EINT19 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,EINT18 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,EINT17 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,EINT16 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,EINT15 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,EINT14 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,EINT13 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,EINT12 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,EINT11 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,EINT10 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,EINT9 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,EINT8 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,EINT7 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,EINT6 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,EINT5 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,EINT4 wakeup event mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,EINT3 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,EINT2 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,EINT1 wakeup event mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,EINT0 wakeup event mask" "Not masked,Masked"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "EINT_SENS_SET/CLR,EINT Sensitivity Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " EINT_SENS[31] ,EINT31 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,EINT30 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,EINT29 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,EINT28 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,EINT27 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,EINT26 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,EINT25 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,EINT24 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,EINT23 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,EINT22 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,EINT21 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,EINT20 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,EINT19 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,EINT18 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,EINT17 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,EINT16 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,EINT15 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,EINT14 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,EINT13 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,EINT12 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,EINT11 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,EINT10 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,EINT9 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,EINT8 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,EINT7 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,EINT6 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,EINT5 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,EINT4 sensitivity type of external interrupt source" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,EINT3 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,EINT2 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,EINT1 sensitivity type of external interrupt source" "Edge,Level"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,EINT0 sensitivity type of external interrupt source" "Edge,Level"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "EINT_DUALEDGE_SENS_SET/CLR,EINT Dual Edge Sensitivity Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " EINT_DUALEDGE_SENS[31] ,EINT31 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,EINT30 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,EINT29 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,EINT28 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,EINT27 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,EINT26 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,EINT25 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,EINT24 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,EINT23 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,EINT22 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,EINT21 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,EINT20 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,EINT19 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,EINT18 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,EINT17 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,EINT16 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,EINT15 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,EINT14 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,EINT13 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,EINT12 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,EINT11 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,EINT10 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,EINT9 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,EINT8 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,EINT7 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,EINT6 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,EINT5 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,EINT4 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,EINT3 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,EINT2 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,EINT1 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,EINT0 dual edge sensitivity enable of external interrupt source" "Disabled,Enabled"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "EINT_SOFT_SET/CLR,EINT Software Interrupt Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " EINT_SOFT[31] ,EINT31 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,EINT30 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,EINT29 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,EINT28 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,EINT27 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,EINT26 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,EINT25 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,EINT24 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,EINT23 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,EINT22 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,EINT21 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,EINT20 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,EINT19 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,EINT18 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,EINT17 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,EINT16 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,EINT15 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,EINT14 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,EINT13 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,EINT12 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,EINT11 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,EINT10 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,EINT9 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,EINT8 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,EINT7 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,EINT6 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,EINT5 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,EINT4 software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,EINT3 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,EINT2 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,EINT1 software interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,EINT0 software interrupt" "No interrupt,Interrupt"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "EINT_D0EN,EINT Domain 0 Enable Register"
|
|
bitfld.long 0x00 31. " EINT_D0EN[31] ,EINT[31] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,EINT[30] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,EINT[29] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,EINT[28] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,EINT[27] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,EINT[26] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,EINT[25] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,EINT[24] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,EINT[23] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,EINT[22] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,EINT[21] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,EINT[20] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,EINT[19] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,EINT[18] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,EINT[17] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,EINT[16] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,EINT[15] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,EINT[14] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,EINT[13] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,EINT[12] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,EINT[11] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,EINT[10] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,EINT[9] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,EINT[8] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,EINT[7] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,EINT[6] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,EINT[5] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,EINT[4] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,EINT[3] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,EINT[2] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,EINT[1] enable config for domain 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,EINT[0] enable config for domain 0" "Disabled,Enabled"
|
|
textline " "
|
|
width 11.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "EINT0_CON,EINT0 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT0 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT0 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT0 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT0 debounce duration configuration"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "EINT1_CON,EINT1 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT1 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT1 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT1 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT1 debounce duration configuration"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "EINT2_CON,EINT2 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT2 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT2 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT2 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT2 debounce duration configuration"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "EINT3_CON,EINT3 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT3 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT3 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT3 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT3 debounce duration configuration"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "EINT4_CON,EINT4 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT4 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT4 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT4 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT4 debounce duration configuration"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "EINT5_CON,EINT5 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT5 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT5 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT5 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT5 debounce duration configuration"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "EINT6_CON,EINT6 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT6 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT6 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT6 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT6 debounce duration configuration"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "EINT7_CON,EINT7 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT7 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT7 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT7 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT7 debounce duration configuration"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "EINT8_CON,EINT8 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT8 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT8 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT8 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT8 debounce duration configuration"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "EINT9_CON,EINT9 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT9 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT9 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT9 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT9 debounce duration configuration"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "EINT10_CON,EINT10 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT10 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT10 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT10 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT10 debounce duration configuration"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "EINT11_CON,EINT11 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT11 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT11 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT11 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT11 debounce duration configuration"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "EINT12_CON,EINT12 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT12 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT12 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT12 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT12 debounce duration configuration"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "EINT13_CON,EINT13 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT13 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT13 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT13 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT13 debounce duration configuration"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "EINT14_CON,EINT14 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT14 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT14 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT14 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT14 debounce duration configuration"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "EINT15_CON,EINT15 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT15 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT15 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT15 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT15 debounce duration configuration"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EINT16_CON,EINT16 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT16 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT16 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT16 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT16 debounce duration configuration"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "EINT17_CON,EINT17 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT17 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT17 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT17 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT17 debounce duration configuration"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "EINT18_CON,EINT18 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT18 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT18 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT18 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT18 debounce duration configuration"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "EINT19_CON,EINT19 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT19 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT19 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT19 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT19 debounce duration configuration"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "EINT20_CON,EINT20 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT20 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT20 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT20 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT20 debounce duration configuration"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "EINT21_CON,EINT21 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT21 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT21 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT21 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT21 debounce duration configuration"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "EINT22_CON,EINT22 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT22 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT22 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT22 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT22 debounce duration configuration"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "EINT23_CON,EINT23 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT23 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT23 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT23 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT23 debounce duration configuration"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "EINT24_CON,EINT24 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT24 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT24 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT24 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT24 debounce duration configuration"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "EINT25_CON,EINT25 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT25 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT25 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT25 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT25 debounce duration configuration"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "EINT26_CON,EINT26 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT26 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT26 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT26 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT26 debounce duration configuration"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "EINT27_CON,EINT27 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT27 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT27 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT27 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT27 debounce duration configuration"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "EINT28_CON,EINT28 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT28 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT28 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT28 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT28 debounce duration configuration"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "EINT29_CON,EINT29 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT29 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT29 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT29 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT29 debounce duration configuration"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "EINT30_CON,EINT30 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT30 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT30 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT30 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT30 debounce duration configuration"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "EINT31_CON,EINT31 Config Register"
|
|
bitfld.long 0x00 31. " RSTDBC ,EINT31 debounce count reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " DBC_EN ,Enable EINT31 debounce circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,EINT31 debounce clock cycle period prescaler" "32.768Hz,16.384Hz,8.192Hz,4.096Hz,2.048Hz,1.024Hz,512Hz,256Hz"
|
|
bitfld.long 0x00 11. " POL ,Polarity configuration" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " DBC_CNT ,EINT31 debounce duration configuration"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0xA0000000
|
|
width 18.
|
|
tree "PD_DMA"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PD_DMA_GLBSTA,DMA Global Status Register"
|
|
bitfld.long 0x00 31. " IT16 ,Channel 16 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " RUN16 ,Channel 16 running status" "No run,Run"
|
|
bitfld.long 0x00 29. " IT15 ,Channel 15 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " RUN15 ,Channel 15 running status" "No run,Run"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IT14 ,Channel 14 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " RUN14 ,Channel 14 running status" "No run,Run"
|
|
bitfld.long 0x00 25. " IT13 ,Channel 13 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " RUN13 ,Channel 13 running status" "No run,Run"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IT12 ,Channel 12 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " RUN12 ,Channel 12 running status" "No run,Run"
|
|
bitfld.long 0x00 21. " IT11 ,Channel 11 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " RUN11 ,Channel 11 running status" "No run,Run"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IT10 ,Channel 10 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RUN10 ,Channel 10 running status" "No run,Run"
|
|
bitfld.long 0x00 17. " IT9 ,Channel 9 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " RUN9 ,Channel 9 running status" "No run,Run"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IT3 ,Channel 3 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RUN3 ,Channel 3 running status" "No run,Run"
|
|
bitfld.long 0x00 3. " IT2 ,Channel 2 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RUN2 ,Channel 2 running status" "No run,Run"
|
|
bitfld.long 0x00 1. " IT1 ,Channel 1 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RUN1 ,Channel 1 running status" "No run,Run"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PD_DMA_GLB_SWRST,DMA Global Software Reset"
|
|
bitfld.long 0x00 0. " SW_RESET ,Software reset" "No reset,Reset"
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "GDMA1_SRC,DMA Channel 1 Source Address Register"
|
|
line.long 0x04 "GDMA1_DST,DMA Channel 1 Destination Address Register"
|
|
line.long 0x08 "GDMA1_WPPT,DMA Channel 1 Wrap Point Address Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x0C "GDMA1_WPTO,DMA Channel 1 Wrap To Address Register"
|
|
line.long 0x10 "GDMA1_COUNT,DMA Channel 1 Transfer Count Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x14 "GDMA1_CON,DMA Channel 1 Control Register"
|
|
bitfld.long 0x14 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x14 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x14 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x14 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x18 "GDMA1_START,DMA Channel 1 Start Register"
|
|
bitfld.long 0x18 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x1C "GDMA1_INTSTA,DMA Channel 1 Interrupt Status Register"
|
|
bitfld.long 0x1C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "GDMA1_ACKINT,DMA Channel 1 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Acknowledge"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "GDMA1_RLCT,DMA Channel 1 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
width 15.
|
|
tree "PDMA2 (Half-Size DMA) Registers"
|
|
group.long (0x200+0x08)++0x13
|
|
line.long 0x00 "PDMA2_WPPT,DMA Channel 2 Wrap Point Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x04 "PDMA2_WPTO,DMA Channel 2 Wrap To Address Register"
|
|
line.long 0x08 "PDMA2_COUNT,DMA Channel 2 Transfer Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x0C "PDMA2_CON,DMA Channel 2 Control Register"
|
|
bitfld.long 0x0C 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x0C 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x0C 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x0C 5. " B2W ,Byte to word enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x0C 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x10 "PDMA2_START,DMA Channel 2 Start Register"
|
|
bitfld.long 0x10 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
rgroup.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "PDMA2_INTSTA,DMA Channel 2 Interrupt Status Register"
|
|
bitfld.long 0x00 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PDMA2_ACKINT,DMA Channel 2 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
rgroup.long (0x200+0x24)++0x03
|
|
line.long 0x00 "PDMA2_RLCT,DMA Channel 2 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
group.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "PDMA2_PGMADDR,DMA Channel 2 Programmable Address Register"
|
|
tree.end
|
|
width 15.
|
|
tree "PDMA3 (Half-Size DMA) Registers"
|
|
group.long (0x300+0x08)++0x13
|
|
line.long 0x00 "PDMA3_WPPT,DMA Channel 3 Wrap Point Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x04 "PDMA3_WPTO,DMA Channel 3 Wrap To Address Register"
|
|
line.long 0x08 "PDMA3_COUNT,DMA Channel 3 Transfer Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x0C "PDMA3_CON,DMA Channel 3 Control Register"
|
|
bitfld.long 0x0C 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x0C 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x0C 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x0C 5. " B2W ,Byte to word enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x0C 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x10 "PDMA3_START,DMA Channel 3 Start Register"
|
|
bitfld.long 0x10 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
rgroup.long (0x300+0x1C)++0x03
|
|
line.long 0x00 "PDMA3_INTSTA,DMA Channel 3 Interrupt Status Register"
|
|
bitfld.long 0x00 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x300+0x20)++0x03
|
|
line.long 0x00 "PDMA3_ACKINT,DMA Channel 3 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
rgroup.long (0x300+0x24)++0x03
|
|
line.long 0x00 "PDMA3_RLCT,DMA Channel 3 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
group.long (0x300+0x2C)++0x03
|
|
line.long 0x00 "PDMA3_PGMADDR,DMA Channel 3 Programmable Address Register"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA9 (Virtual FIFO DMA) Registers"
|
|
group.long (0x900+0x10)++0x0F
|
|
line.long 0x00 "VDMA9_COUNT,DMA Channel 9 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA9_CON,DMA Channel 9 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA9_START,DMA Channel 9 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA9_INTSTA,DMA Channel 9 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x900+0x20)++0x03
|
|
line.long 0x00 "VDMA9_ACKINT,DMA Channel 9 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0x900+0x2C)++0x03
|
|
line.long 0x00 "VDMA9_PGMADDR,DMA Channel 9 Programmable Address Register"
|
|
rgroup.long (0x900+0x30)++0x0F
|
|
line.long 0x00 "VDMA9_WRPTR,DMA Channel 9 Write Pointer"
|
|
line.long 0x04 "VDMA9_RDPTR,DMA Channel 9 Read Pointer"
|
|
line.long 0x08 "VDMA9_FFCNT,DMA Channel 9 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA9_FFSTA,DMA Channel 9 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0x900+0x40)++0x07
|
|
line.long 0x00 "VDMA9_ALTLEN,DMA Channel 9 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA9_FFSIZE,DMA Channel 9 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA10 (Virtual FIFO DMA) Registers"
|
|
group.long (0xA00+0x10)++0x0F
|
|
line.long 0x00 "VDMA10_COUNT,DMA Channel 10 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA10_CON,DMA Channel 10 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA10_START,DMA Channel 10 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA10_INTSTA,DMA Channel 10 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xA00+0x20)++0x03
|
|
line.long 0x00 "VDMA10_ACKINT,DMA Channel 10 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xA00+0x2C)++0x03
|
|
line.long 0x00 "VDMA10_PGMADDR,DMA Channel 10 Programmable Address Register"
|
|
rgroup.long (0xA00+0x30)++0x0F
|
|
line.long 0x00 "VDMA10_WRPTR,DMA Channel 10 Write Pointer"
|
|
line.long 0x04 "VDMA10_RDPTR,DMA Channel 10 Read Pointer"
|
|
line.long 0x08 "VDMA10_FFCNT,DMA Channel 10 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA10_FFSTA,DMA Channel 10 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xA00+0x40)++0x07
|
|
line.long 0x00 "VDMA10_ALTLEN,DMA Channel 10 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA10_FFSIZE,DMA Channel 10 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA11 (Virtual FIFO DMA) Registers"
|
|
group.long (0xB00+0x10)++0x0F
|
|
line.long 0x00 "VDMA11_COUNT,DMA Channel 11 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA11_CON,DMA Channel 11 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA11_START,DMA Channel 11 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA11_INTSTA,DMA Channel 11 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xB00+0x20)++0x03
|
|
line.long 0x00 "VDMA11_ACKINT,DMA Channel 11 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xB00+0x2C)++0x03
|
|
line.long 0x00 "VDMA11_PGMADDR,DMA Channel 11 Programmable Address Register"
|
|
rgroup.long (0xB00+0x30)++0x0F
|
|
line.long 0x00 "VDMA11_WRPTR,DMA Channel 11 Write Pointer"
|
|
line.long 0x04 "VDMA11_RDPTR,DMA Channel 11 Read Pointer"
|
|
line.long 0x08 "VDMA11_FFCNT,DMA Channel 11 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA11_FFSTA,DMA Channel 11 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xB00+0x40)++0x07
|
|
line.long 0x00 "VDMA11_ALTLEN,DMA Channel 11 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA11_FFSIZE,DMA Channel 11 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA12 (Virtual FIFO DMA) Registers"
|
|
group.long (0xC00+0x10)++0x0F
|
|
line.long 0x00 "VDMA12_COUNT,DMA Channel 12 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA12_CON,DMA Channel 12 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA12_START,DMA Channel 12 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA12_INTSTA,DMA Channel 12 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xC00+0x20)++0x03
|
|
line.long 0x00 "VDMA12_ACKINT,DMA Channel 12 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xC00+0x2C)++0x03
|
|
line.long 0x00 "VDMA12_PGMADDR,DMA Channel 12 Programmable Address Register"
|
|
rgroup.long (0xC00+0x30)++0x0F
|
|
line.long 0x00 "VDMA12_WRPTR,DMA Channel 12 Write Pointer"
|
|
line.long 0x04 "VDMA12_RDPTR,DMA Channel 12 Read Pointer"
|
|
line.long 0x08 "VDMA12_FFCNT,DMA Channel 12 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA12_FFSTA,DMA Channel 12 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xC00+0x40)++0x07
|
|
line.long 0x00 "VDMA12_ALTLEN,DMA Channel 12 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA12_FFSIZE,DMA Channel 12 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA13 (Virtual FIFO DMA) Registers"
|
|
group.long (0xD00+0x10)++0x0F
|
|
line.long 0x00 "VDMA13_COUNT,DMA Channel 13 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA13_CON,DMA Channel 13 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA13_START,DMA Channel 13 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA13_INTSTA,DMA Channel 13 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xD00+0x20)++0x03
|
|
line.long 0x00 "VDMA13_ACKINT,DMA Channel 13 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xD00+0x2C)++0x03
|
|
line.long 0x00 "VDMA13_PGMADDR,DMA Channel 13 Programmable Address Register"
|
|
rgroup.long (0xD00+0x30)++0x0F
|
|
line.long 0x00 "VDMA13_WRPTR,DMA Channel 13 Write Pointer"
|
|
line.long 0x04 "VDMA13_RDPTR,DMA Channel 13 Read Pointer"
|
|
line.long 0x08 "VDMA13_FFCNT,DMA Channel 13 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA13_FFSTA,DMA Channel 13 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xD00+0x40)++0x07
|
|
line.long 0x00 "VDMA13_ALTLEN,DMA Channel 13 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA13_FFSIZE,DMA Channel 13 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA14 (Virtual FIFO DMA) Registers"
|
|
group.long (0xE00+0x10)++0x0F
|
|
line.long 0x00 "VDMA14_COUNT,DMA Channel 14 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA14_CON,DMA Channel 14 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA14_START,DMA Channel 14 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA14_INTSTA,DMA Channel 14 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xE00+0x20)++0x03
|
|
line.long 0x00 "VDMA14_ACKINT,DMA Channel 14 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xE00+0x2C)++0x03
|
|
line.long 0x00 "VDMA14_PGMADDR,DMA Channel 14 Programmable Address Register"
|
|
rgroup.long (0xE00+0x30)++0x0F
|
|
line.long 0x00 "VDMA14_WRPTR,DMA Channel 14 Write Pointer"
|
|
line.long 0x04 "VDMA14_RDPTR,DMA Channel 14 Read Pointer"
|
|
line.long 0x08 "VDMA14_FFCNT,DMA Channel 14 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA14_FFSTA,DMA Channel 14 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xE00+0x40)++0x07
|
|
line.long 0x00 "VDMA14_ALTLEN,DMA Channel 14 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA14_FFSIZE,DMA Channel 14 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA15 (Virtual FIFO DMA) Registers"
|
|
group.long (0xF00+0x10)++0x0F
|
|
line.long 0x00 "VDMA15_COUNT,DMA Channel 15 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA15_CON,DMA Channel 15 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA15_START,DMA Channel 15 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA15_INTSTA,DMA Channel 15 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xF00+0x20)++0x03
|
|
line.long 0x00 "VDMA15_ACKINT,DMA Channel 15 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xF00+0x2C)++0x03
|
|
line.long 0x00 "VDMA15_PGMADDR,DMA Channel 15 Programmable Address Register"
|
|
rgroup.long (0xF00+0x30)++0x0F
|
|
line.long 0x00 "VDMA15_WRPTR,DMA Channel 15 Write Pointer"
|
|
line.long 0x04 "VDMA15_RDPTR,DMA Channel 15 Read Pointer"
|
|
line.long 0x08 "VDMA15_FFCNT,DMA Channel 15 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA15_FFSTA,DMA Channel 15 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xF00+0x40)++0x07
|
|
line.long 0x00 "VDMA15_ALTLEN,DMA Channel 15 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA15_FFSIZE,DMA Channel 15 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA16 (Virtual FIFO DMA) Registers"
|
|
group.long (0x1000+0x10)++0x0F
|
|
line.long 0x00 "VDMA16_COUNT,DMA Channel 16 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA16_CON,DMA Channel 16 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA16_START,DMA Channel 16 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA16_INTSTA,DMA Channel 16 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x1000+0x20)++0x03
|
|
line.long 0x00 "VDMA16_ACKINT,DMA Channel 16 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0x1000+0x2C)++0x03
|
|
line.long 0x00 "VDMA16_PGMADDR,DMA Channel 16 Programmable Address Register"
|
|
rgroup.long (0x1000+0x30)++0x0F
|
|
line.long 0x00 "VDMA16_WRPTR,DMA Channel 16 Write Pointer"
|
|
line.long 0x04 "VDMA16_RDPTR,DMA Channel 16 Read Pointer"
|
|
line.long 0x08 "VDMA16_FFCNT,DMA Channel 16 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA16_FFSTA,DMA Channel 16 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0x1000+0x40)++0x07
|
|
line.long 0x00 "VDMA16_ALTLEN,DMA Channel 16 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA16_FFSIZE,DMA Channel 16 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA17 (Virtual FIFO DMA) Registers"
|
|
group.long (0x1100+0x10)++0x0F
|
|
line.long 0x00 "VDMA17_COUNT,DMA Channel 17 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA17_CON,DMA Channel 17 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA17_START,DMA Channel 17 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA17_INTSTA,DMA Channel 17 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x1100+0x20)++0x03
|
|
line.long 0x00 "VDMA17_ACKINT,DMA Channel 17 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0x1100+0x2C)++0x03
|
|
line.long 0x00 "VDMA17_PGMADDR,DMA Channel 17 Programmable Address Register"
|
|
rgroup.long (0x1100+0x30)++0x0F
|
|
line.long 0x00 "VDMA17_WRPTR,DMA Channel 17 Write Pointer"
|
|
line.long 0x04 "VDMA17_RDPTR,DMA Channel 17 Read Pointer"
|
|
line.long 0x08 "VDMA17_FFCNT,DMA Channel 17 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA17_FFSTA,DMA Channel 17 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0x1100+0x40)++0x07
|
|
line.long 0x00 "VDMA17_ALTLEN,DMA Channel 17 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA17_FFSIZE,DMA Channel 17 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
tree.end
|
|
tree "AO_DMA"
|
|
base (ad:0xA2070000)
|
|
width 18.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "AO_DMA_GLBSTA,DMA Global Status Register"
|
|
bitfld.long 0x00 19. " IT18 ,Channel 18 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RUN18 ,Channel 18 running status" "No run,Run"
|
|
bitfld.long 0x00 17. " IT17 ,Channel 17 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " RUN17 ,Channel 17 running status" "No run,Run"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AO_DMA_GLB_SWRST,DMA Global Software Reset"
|
|
bitfld.long 0x00 0. " SW_RESET ,Software reset" "No reset,Reset"
|
|
width 16.
|
|
tree "VDMA17 (Virtual FIFO DMA) Registers"
|
|
group.long (0x900+0x10)++0x0F
|
|
line.long 0x00 "VDMA17_COUNT,DMA Channel 17 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA17_CON,DMA Channel 17 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA17_START,DMA Channel 17 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA17_INTSTA,DMA Channel 17 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x900+0x20)++0x03
|
|
line.long 0x00 "VDMA17_ACKINT,DMA Channel 17 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0x900+0x2C)++0x03
|
|
line.long 0x00 "VDMA17_PGMADDR,DMA Channel 17 Programmable Address Register"
|
|
rgroup.long (0x900+0x30)++0x0F
|
|
line.long 0x00 "VDMA17_WRPTR,DMA Channel 17 Write Pointer"
|
|
line.long 0x04 "VDMA17_RDPTR,DMA Channel 17 Read Pointer"
|
|
line.long 0x08 "VDMA17_FFCNT,DMA Channel 17 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA17_FFSTA,DMA Channel 17 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0x900+0x40)++0x07
|
|
line.long 0x00 "VDMA17_ALTLEN,DMA Channel 17 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA17_FFSIZE,DMA Channel 17 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
width 16.
|
|
tree "VDMA18 (Virtual FIFO DMA) Registers"
|
|
group.long (0xA00+0x10)++0x0F
|
|
line.long 0x00 "VDMA18_COUNT,DMA Channel 18 Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,FIFO threshold"
|
|
line.long 0x04 "VDMA18_CON,DMA Channel 18 Control Register"
|
|
bitfld.long 0x04 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x04 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x08 "VDMA18_START,DMA Channel 18 Start Register"
|
|
bitfld.long 0x08 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
line.long 0x0C "VDMA18_INTSTA,DMA Channel 18 Interrupt Status Register"
|
|
bitfld.long 0x0C 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0xA00+0x20)++0x03
|
|
line.long 0x00 "VDMA18_ACKINT,DMA Channel 18 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
group.long (0xA00+0x2C)++0x03
|
|
line.long 0x00 "VDMA18_PGMADDR,DMA Channel 18 Programmable Address Register"
|
|
rgroup.long (0xA00+0x30)++0x0F
|
|
line.long 0x00 "VDMA18_WRPTR,DMA Channel 18 Write Pointer"
|
|
line.long 0x04 "VDMA18_RDPTR,DMA Channel 18 Read Pointer"
|
|
line.long 0x08 "VDMA18_FFCNT,DMA Channel 18 FIFO Count"
|
|
hexmask.long.word 0x08 0.--15. 1. " FFCNT ,Number of data stored in FIFO"
|
|
line.long 0x0C "VDMA18_FFSTA,DMA Channel 18 FIFO Status"
|
|
bitfld.long 0x0C 2. " ALT ,FIFO count larger than ALTLEN" "Not reached,Reached"
|
|
bitfld.long 0x0C 1. " EMPTY ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x0C 0. " FULL ,FIFO full" "Not full,Full"
|
|
group.long (0xA00+0x40)++0x07
|
|
line.long 0x00 "VDMA18_ALTLEN,DMA Channel 18 Alert Length"
|
|
bitfld.long 0x00 0.--5. " ALTLEN ,Alert length of virtual FIFO DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VDMA18_FFSIZE,DMA Channel 18 FIFO Size"
|
|
hexmask.long.word 0x04 0.--15. 1. " FFSIZE ,FIFO size of virtual FIFO DMA"
|
|
tree.end
|
|
tree.end
|
|
tree "SENSOR_DMA"
|
|
base (ad:0xA0230000)
|
|
width 22.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SENSOR_DMA_GLBSTA,DMA Global Status Register"
|
|
bitfld.long 0x00 9. " IT7 ,Channel 10 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RUN7 ,Channel 10 running status" "No run,Run"
|
|
bitfld.long 0x00 7. " IT6 ,Channel 4 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RUN6 ,Channel 4 running status" "No run,Run"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IT5 ,Channel 3 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RUN5 ,Channel 3 running status" "No run,Run"
|
|
bitfld.long 0x00 3. " IT4 ,Channel 2 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RUN4 ,Channel 2 running status" "No run,Run"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SENSOR_DMA_GLB_SWRST,DMA Global Software Reset"
|
|
bitfld.long 0x00 0. " SW_RESET ,Software reset" "No reset,Reset"
|
|
width 15.
|
|
tree "PDMA4 (Half-Size DMA) Registers"
|
|
group.long (0x200+0x08)++0x13
|
|
line.long 0x00 "PDMA4_WPPT,DMA Channel 4 Wrap Point Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x04 "PDMA4_WPTO,DMA Channel 4 Wrap To Address Register"
|
|
line.long 0x08 "PDMA4_COUNT,DMA Channel 4 Transfer Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x0C "PDMA4_CON,DMA Channel 4 Control Register"
|
|
bitfld.long 0x0C 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x0C 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x0C 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x0C 5. " B2W ,Byte to word enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x0C 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x10 "PDMA4_START,DMA Channel 4 Start Register"
|
|
bitfld.long 0x10 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
rgroup.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "PDMA4_INTSTA,DMA Channel 4 Interrupt Status Register"
|
|
bitfld.long 0x00 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PDMA4_ACKINT,DMA Channel 4 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
rgroup.long (0x200+0x24)++0x03
|
|
line.long 0x00 "PDMA4_RLCT,DMA Channel 4 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
group.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "PDMA4_PGMADDR,DMA Channel 4 Programmable Address Register"
|
|
tree.end
|
|
width 15.
|
|
tree "PDMA5 (Half-Size DMA) Registers"
|
|
group.long (0x300+0x08)++0x13
|
|
line.long 0x00 "PDMA5_WPPT,DMA Channel 5 Wrap Point Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x04 "PDMA5_WPTO,DMA Channel 5 Wrap To Address Register"
|
|
line.long 0x08 "PDMA5_COUNT,DMA Channel 5 Transfer Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x0C "PDMA5_CON,DMA Channel 5 Control Register"
|
|
bitfld.long 0x0C 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x0C 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x0C 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x0C 5. " B2W ,Byte to word enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x0C 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x10 "PDMA5_START,DMA Channel 5 Start Register"
|
|
bitfld.long 0x10 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
rgroup.long (0x300+0x1C)++0x03
|
|
line.long 0x00 "PDMA5_INTSTA,DMA Channel 5 Interrupt Status Register"
|
|
bitfld.long 0x00 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x300+0x20)++0x03
|
|
line.long 0x00 "PDMA5_ACKINT,DMA Channel 5 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
rgroup.long (0x300+0x24)++0x03
|
|
line.long 0x00 "PDMA5_RLCT,DMA Channel 5 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
group.long (0x300+0x2C)++0x03
|
|
line.long 0x00 "PDMA5_PGMADDR,DMA Channel 5 Programmable Address Register"
|
|
tree.end
|
|
width 15.
|
|
tree "PDMA6 (Half-Size DMA) Registers"
|
|
group.long (0x400+0x08)++0x13
|
|
line.long 0x00 "PDMA6_WPPT,DMA Channel 6 Wrap Point Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x04 "PDMA6_WPTO,DMA Channel 6 Wrap To Address Register"
|
|
line.long 0x08 "PDMA6_COUNT,DMA Channel 6 Transfer Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x0C "PDMA6_CON,DMA Channel 6 Control Register"
|
|
bitfld.long 0x0C 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x0C 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x0C 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x0C 5. " B2W ,Byte to word enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x0C 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x10 "PDMA6_START,DMA Channel 6 Start Register"
|
|
bitfld.long 0x10 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
rgroup.long (0x400+0x1C)++0x03
|
|
line.long 0x00 "PDMA6_INTSTA,DMA Channel 6 Interrupt Status Register"
|
|
bitfld.long 0x00 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x400+0x20)++0x03
|
|
line.long 0x00 "PDMA6_ACKINT,DMA Channel 6 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
rgroup.long (0x400+0x24)++0x03
|
|
line.long 0x00 "PDMA6_RLCT,DMA Channel 6 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
group.long (0x400+0x2C)++0x03
|
|
line.long 0x00 "PDMA6_PGMADDR,DMA Channel 6 Programmable Address Register"
|
|
tree.end
|
|
width 15.
|
|
tree "PDMA7 (Half-Size DMA) Registers"
|
|
group.long (0x500+0x08)++0x13
|
|
line.long 0x00 "PDMA7_WPPT,DMA Channel 7 Wrap Point Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WPPT ,Transfer counts before jump"
|
|
line.long 0x04 "PDMA7_WPTO,DMA Channel 7 Wrap To Address Register"
|
|
line.long 0x08 "PDMA7_COUNT,DMA Channel 7 Transfer Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Amount of total transfer counts"
|
|
line.long 0x0C "PDMA7_CON,DMA Channel 7 Control Register"
|
|
bitfld.long 0x0C 18. " DIR ,Direction of PDMA transfer" "Periph TX,Periph RX"
|
|
bitfld.long 0x0C 17. " WPEN ,Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " WPSD ,Address-wrapping select" "On source,On destination"
|
|
bitfld.long 0x0C 15. " ITEN ,DMA transfer completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " BURST ,Transfer type" "Single,,4-beat inc burst,?..."
|
|
bitfld.long 0x0C 5. " B2W ,Byte to word enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQ ,Throttle and handshake control for DMA transfer" "No throttle control,Hardware handshake"
|
|
bitfld.long 0x0C 3. " DINC ,Increment destination address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SINC ,Increment source address" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Data size within the confine of a bus cycle per transfer" "1byte,2bytes,4bytes,?..."
|
|
line.long 0x10 "PDMA7_START,DMA Channel 7 Start Register"
|
|
bitfld.long 0x10 15. " STR ,Start control for a DMA channel" "Stopped,Started"
|
|
rgroup.long (0x500+0x1C)++0x03
|
|
line.long 0x00 "PDMA7_INTSTA,DMA Channel 7 Interrupt Status Register"
|
|
bitfld.long 0x00 15. " INT ,Interrupt status for DMA channel" "No interrupt,Interrupt"
|
|
wgroup.long (0x500+0x20)++0x03
|
|
line.long 0x00 "PDMA7_ACKINT,DMA Channel 7 Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 15. " ACK ,Interrupt acknowledge for the DMA channel" "No effect,Interrupt request"
|
|
rgroup.long (0x500+0x24)++0x03
|
|
line.long 0x00 "PDMA7_RLCT,DMA Channel 7 Remaining Length Of Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " RLCT ,Reflects left count of transfer"
|
|
group.long (0x500+0x2C)++0x03
|
|
line.long 0x00 "PDMA7_PGMADDR,DMA Channel 7 Programmable Address Register"
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0xA21E0000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "RTC_BBPU,Baseband Power Up"
|
|
hexmask.word.byte 0x00 8.--15. 1. " KEY_BBPU ,Baseband power up key"
|
|
rbitfld.word 0x00 6. " CBUSY ,Read/Write between RTC/Core busy" "Not busy,Busy"
|
|
bitfld.word 0x00 5. " RELOAD ,Reload values from RTC domain to core domain" "Not reloaded,Reloaded"
|
|
eventfld.word 0x00 2. " ALARM_PU ,PMU powered on by alarm occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " PWREN ,RTC alarm occurred" "Not occurred,Occurred"
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RTC_IRQ_STA,RTC IRQ Status"
|
|
in
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "RTC_IRQ_EN,RTC IRQ Enable"
|
|
bitfld.word 0x00 3. " LP_EN ,Enable control bit for IRQ generation if the low power is detected" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ONESHOT ,Automatic reset of AL_EN and TC_EN" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TC_EN ,Enable control bit for IRQ generation if the tick condition has been met" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_EN ,Enable control bit for IRQ generation if the alarm condition has been met" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "RTC_CII_EN,Counter Increment IRQ Enable"
|
|
bitfld.word 0x00 9. " SECCII_1_8 ,Activate IRQ at each one-eighth of a second update" "Not activated,Activated"
|
|
bitfld.word 0x00 8. " SECCII_1_4 ,Activate IRQ at each one-fourth of a second update" "Not activated,Activated"
|
|
bitfld.word 0x00 7. " SECCII_1_2 ,Activate IRQ at each one-half of a second update" "Not activated,Activated"
|
|
bitfld.word 0x00 6. " YEACII ,Activate IRQ at each year update" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MTHCII ,Activate IRQ at each month update" "Not activated,Activated"
|
|
bitfld.word 0x00 4. " DOWCII ,Activate IRQ at each day-of-week update" "Not activated,Activated"
|
|
bitfld.word 0x00 3. " DOMCII ,Activate IRQ at each day-of-month update" "Not activated,Activated"
|
|
bitfld.word 0x00 2. " HOUCII ,Activate IRQ at each hour update" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.word 0x00 1. " MINCII ,Activate IRQ at each minute update" "Not activated,Activated"
|
|
bitfld.word 0x00 0. " SECCII ,Activate IRQ at each second update" "Not activated,Activated"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RTC_AL_MASK,RTC Alarm Mask"
|
|
bitfld.word 0x00 6. " YEA_MSK ,Year time counter mask" "Not masked,Masked"
|
|
bitfld.word 0x00 5. " MTH_MSK ,Month time counter mask" "Not masked,Masked"
|
|
bitfld.word 0x00 4. " DOW_MSK ,Day-of-week time counter mask" "Not masked,Masked"
|
|
bitfld.word 0x00 3. " DOM_MSK ,Day-of-month time counter mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HOU_MSK ,Hours time counter mask" "Not masked,Masked"
|
|
bitfld.word 0x00 1. " MIN_MSK ,Minutes time counter mask" "Not masked,Masked"
|
|
bitfld.word 0x00 0. " SEC_MSK ,Seconds time counter mask" "Not masked,Masked"
|
|
textline " "
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "RTC_TC_SEC,RTC Seconds Time Counter Register"
|
|
bitfld.word 0x00 0.--5. " TC_SECOND ,Second initial value for the time counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "RTC_TC_MIN,RTC Minutes Time Counter Register"
|
|
bitfld.word 0x00 0.--5. " TC_MINUTE ,Minute initial value for the time counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RTC_TC_HOU,RTC Hours Time Counter Register"
|
|
bitfld.word 0x00 0.--4. " TC_HOUR ,Hour initial value for the time counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-"
|
|
if (((per.w(ad:0xA21E0000+0x28)&0x0F)==((0x01)||(0x03)||(0x05)||(0x07)||(0x08)||(0x0A)||(0x0C))))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "RTC_TC_DOM,RTC Day-Of-Month Time Counter Register"
|
|
bitfld.word 0x00 0.--4. " TC_DOM ,Day-of-month initial value for the time counter" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (((per.w(ad:0xA21E0000+0x28)&0x0F)==0x02))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "RTC_TC_DOM,RTC Day-Of-Month Time Counter Register"
|
|
bitfld.word 0x00 0.--4. " TC_DOM ,Day-of-month initial value for the time counter" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,-,-"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "RTC_TC_DOM,RTC Day-Of-Month Time Counter Register"
|
|
bitfld.word 0x00 0.--4. " TC_DOM ,Day-of-month initial value for the time counter" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,-"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "RTC_TC_DOW,RTC Day-Of-Week Time Counter Register"
|
|
bitfld.word 0x00 0.--2. " TC_DOW ,Day-of-week initial value for the time counter" "-,1,2,3,4,5,6,7"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "RTC_TC_MTH,RTC Month Time Counter Register"
|
|
bitfld.word 0x00 0.--3. " TC_MONTH ,Month initial value for the time counter" "-,1,2,3,4,5,6,7,8,9,10,11,12,-,-,-"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "RTC_TC_YEA,RTC Year Time Counter Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " TC_YEAR ,Year initial value for the time counter"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "RTC_AL_SEC,RTC Second Alarm Setting Register"
|
|
bitfld.word 0x00 12.--13. " RTC_LPD_OPT ,LPD option" "XOSC LPD|EOSC LPD,EOSC LPD,XOSC LPD,No LPD"
|
|
bitfld.word 0x00 0.--5. " AL_SECOND ,Second value of the alarm counter setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "RTC_AL_MIN,RTC Minute Alarm Setting Register"
|
|
bitfld.word 0x00 0.--5. " AL_MINUTE ,Minute value of the alarm counter setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "RTC_AL_HOU,RTC Hour Alarm Setting Register"
|
|
bitfld.word 0x00 0.--4. " AL_HOUR ,Hour value of the alarm counter setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-"
|
|
if (((per.w(ad:0xA21E0000+0x44)&0x0F)==((0x01)||(0x03)||(0x05)||(0x07)||(0x08)||(0x0A)||(0x0C))))
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "RTC_AL_DOM,RTC Day-Of-Month Alarm Setting Register"
|
|
bitfld.word 0x00 0.--4. " AL_DOM ,Day-of-month value of the alarm counter setting" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (((per.w(ad:0xA21E0000+0x44)&0x0F)==0x01))
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "RTC_AL_DOM,RTC Day-Of-Month Alarm Setting Register"
|
|
bitfld.word 0x00 0.--4. " AL_DOM ,Day-of-month value of the alarm counter setting" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,-,-"
|
|
else
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "RTC_AL_DOM,RTC Day-Of-Month Alarm Setting Register"
|
|
bitfld.word 0x00 0.--4. " AL_DOM ,Day-of-month value of the alarm counter setting" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,-"
|
|
endif
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "RTC_AL_DOW,RTC Day-Of-Week Alarm Setting Register"
|
|
bitfld.word 0x00 0.--2. " AL_DOW ,Day-of-week value of the alarm counter setting" "-,1,2,3,4,5,6,7"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "RTC_AL_MTH,RTC Month Alarm Setting Register"
|
|
bitfld.word 0x00 0.--3. " AL_MONTH ,Month value of the alarm counter setting" "-,1,2,3,4,5,6,7,8,9,10,11,12,-,-,-"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "RTC_AL_YEA,RTC Year Alarm Setting Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " AL_YEAR ,Year value of the alarm counter setting"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "RTC_POWERKEY1,RTC_POWERKEY1 Register"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "RTC_POWERKEY2,RTC_POWERKEY2 Register"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "RTC_PDN1,PDN1"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "RTC_PDN2,PDN2"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "RTC_PROT,Lock/Unlock Scheme To Prevent RTC Miswriting"
|
|
textline " "
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "RTC_DIFF,One-Time Calibration Offset"
|
|
bitfld.word 0x00 15. " CALI_RD_SEL ,RTC_CALI read select" "Normal RTC_CALI,K_EOSC32_RTC_CALI"
|
|
rbitfld.word 0x00 12. " POWER_DETECTED ,Power detected status" "Not matched,RTC_POWERKEY[1..2] RTC_POWERKEY[1..2]_NEW matched"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " RTC_DIFF ,Finer time unit value to adjust internal counter of RTC"
|
|
textline " "
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "RTC_CALI,Repeat Calibration Offset"
|
|
bitfld.word 0x00 15. " K_EOSC32_OVERFLOW ,EOSC32 calibration overflow" "Not overflowed,Overflowed"
|
|
bitfld.word 0x00 14. " CALI_WR_SEL ,EOSC32 cali value write enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " RTC_CALI ,Repeat calibration scheme"
|
|
wgroup.word 0x74++0x01
|
|
line.word 0x00 "RTC_WRTGR,Enable The Transfers From Core To RTC In The Queue"
|
|
bitfld.word 0x00 0. " WRTGR ,Enable transfer from core to RTC" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART0"
|
|
base ad:0xA00D0000
|
|
width 9.
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0x80)==0x00)
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "RBR/THR,Receive/Transmit,Buffer/Holding Register"
|
|
in
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DLL,Divisor Latch (LS)"
|
|
endif
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0x80)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 2. " ELSI ,Interrupt enable when BI, FE, PE or OE is set" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ETBEI ,Interrupt enable when TX holding register is empty or the contents of the TX FIFO have been reduced to its trigger level" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ERBFI ,Interrupt enable when RX data are placed in RX buffer register or the RX trigger level is reached" "No interrupt,Interrupt"
|
|
elif (((per.long(ad:0xA00D0000+0x0C)&0x80)==0x00)&&((per.long(ad:0xA00D0000+0x08)&0x10)==0x10))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " CTSI ,Mask interrupt when rising edge is detected on the CTS modem control line" "Not masked,Masked"
|
|
bitfld.byte 0x00 6. " RTSI ,Inhibit interrupt when rising edge is detected on the RTS modem control line" "Not inhibited,Inhibited"
|
|
bitfld.byte 0x00 5. " XOFFI ,Mask interrupt enable when XOFF character is received" "Not masked,Masked"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DLM,Divisor Latch (LM)"
|
|
endif
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0xBF)!=0xBF)
|
|
hgroup.byte 0x08++0x00
|
|
hide.byte 0x00 "IIR/FCR,Interrupt/FIFO,Identification/Control Register"
|
|
in
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 7. " AUTO_CTS ,Enable hardware transmission flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " AUTO_RTS ,Enable hardware reception flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ENABLE_E ,Enable enhancement feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SW_FLOW_CONT ,Software flow control bits" "No TX flow control,Transmit XON1/XOFF1,No RX flow control,Receive XON1/XOFF1,?..."
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "No access,Access"
|
|
bitfld.byte 0x00 6. " SB ,Set up break" "No effect,TX break"
|
|
bitfld.byte 0x00 5. " SP ,Stick parity" "No effect,Enabled"
|
|
bitfld.byte 0x00 4. " EPS ,Select even parity" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " STB ,Number of STOP bits" "One,Two"
|
|
bitfld.byte 0x00 0.--1. " WLS1_WLS0 ,Word length select" "5bits,6bits,7bits,8bits"
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
elif (((per.long(ad:0xA00D0000+0x0C)&0xBF)!=0xBF)&&((per.long(ad:0xA00D0000+0x08)&0x10)==0x10))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 7. " XOFF_STATUS ,XOFF status" "XON received,XOFF received"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "XON1,XON1 Char Register"
|
|
endif
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0xBF)!=0xBF)
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 7. " FIFOERR ,RX FIFO error indicator" "No error,Error"
|
|
bitfld.byte 0x00 6. " TEMT ,TX holding register (or TX FIFO) and the TX shift register are empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 5. " THRE ,There is room for TX holding register or TX FIFO is reduced to its trigger level" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " BI ,Break interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FE ,Framing error" "No error,Error"
|
|
bitfld.byte 0x00 2. " PE ,Parity error" "No error,Error"
|
|
bitfld.byte 0x00 1. " OE ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 0. " DR ,Data ready" "Not ready,Ready"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "LSR,Line Status Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0xBF)==0xBF)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA00D0000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCR,Scratch Register"
|
|
else
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCR,Scratch Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
width 16.
|
|
if (((per.b(ad:0xA00D0000+0x20)&0x01)==0x01))
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
rbitfld.byte 0x00 2. " SLEEP_ACK_SEL ,Sleep ack when autobaud_en" "Not supported,Supported"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "HIGHSPEED,High Speed Mode Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,UART sample counter base" "16*baud_pulse,8*baud_pulse,4*baud_pulse,Sample_count*baud_pulse"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SAMPLE_COUNT,Sample Counter Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SAMPLE_POINT,Sample Point Register"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "AUTOBAUD_REG,Auto Baud Monitor Register"
|
|
bitfld.byte 0x00 4.--7. " BAUD_STAT ,Autobaud state" "Detected,AT_7N1,AT_7O1,AT_7E1,AT_8N1,AT_8O1,AT_8E1,AT_7N1,AT_7E1,AT_7O1,AT_8N1,AT_8E1,AT_8O1,Failed,?..."
|
|
bitfld.byte 0x00 0.--3. " BAUD_RATE ,Autobaud baud rate" "115.200,57.600,38.400,19.200,9.600,4.800,2.400,1.200,300,110,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "RATEFIX_AD,Clock Rate Fix Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_RATE_FIX ,Autobaud rate fix" "26MHz,13MHz"
|
|
bitfld.byte 0x00 0. " RATE_FIX ,Rate fix" "26MHz,13MHz"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "AUTOBAUDSAMPLE,Auto Baud Sample Register"
|
|
bitfld.byte 0x00 0.--5. " AUTOBAUDSAMPLE ,Clk division for autobaud rate detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "GUARD,Guard Time Added Register"
|
|
bitfld.byte 0x00 4. " GUARD_EN ,Guard interval add" "Not added,Added"
|
|
bitfld.byte 0x00 0.--3. " GUARD_CNT ,Guard interval count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "ESCAPE_DAT,Escape Character Register"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "ESCAPE_EN,Escape Enable Register"
|
|
bitfld.byte 0x00 0. " ESC_EN ,Add escape character to transmitter and remove it for receiver by UART" "Disabled,Enabled"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "SLEEP_EN,Sleep Enable Register"
|
|
bitfld.byte 0x00 0. " SLEEP_EN ,Sleep mode enable" "Disabled,Enabled"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "DMA_EN,DMA Enable Register"
|
|
bitfld.byte 0x00 3. " FIFO_LSR_SEL ,Select FIFO LSR mode" "LSR hold first line status,LSR auto-update"
|
|
bitfld.byte 0x00 2. " TO_CNT_AUTORST ,Time-out counter auto reset register" "Reset after RX time-out,Auto-reset"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_DMA_EN ,TX_DMA mechanism enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RX_DMA_EN ,RX_DMA mechanism enable" "Disabled,Enabled"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "RXTRI_AD,Rx Trigger Address"
|
|
bitfld.byte 0x00 0.--3. " RXTRIG ,RX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "FRACDIV_L,Fractional Divider LSB Address"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "FRACDIV_M,Fractional Divider MSB Address"
|
|
bitfld.byte 0x00 0.--1. " FRACDIV_M ,Adds sampling count when in state stop to parity to contribute fractional divisor" "0,1,2,3"
|
|
rgroup.byte 0x5C++0x00
|
|
line.byte 0x00 "FCR_RD,FIFO Control Register"
|
|
bitfld.byte 0x00 6.--7. " RFTL1_RFTL0 ,RX FIFO trigger threshold" "1,6,12,RX TRIG data"
|
|
bitfld.byte 0x00 4.--5. " TFTL1_TFTL0 ,TX FIFO trigger threshold" "1,4,8,14"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CLRT ,Clear TX FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 1. " CLRR ,Clear RX FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FIFOE ,FIFO enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0xA00E0000
|
|
width 9.
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0x80)==0x00)
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "RBR/THR,Receive/Transmit,Buffer/Holding Register"
|
|
in
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DLL,Divisor Latch (LS)"
|
|
endif
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0x80)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 2. " ELSI ,Interrupt enable when BI, FE, PE or OE is set" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ETBEI ,Interrupt enable when TX holding register is empty or the contents of the TX FIFO have been reduced to its trigger level" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ERBFI ,Interrupt enable when RX data are placed in RX buffer register or the RX trigger level is reached" "No interrupt,Interrupt"
|
|
elif (((per.long(ad:0xA00E0000+0x0C)&0x80)==0x00)&&((per.long(ad:0xA00E0000+0x08)&0x10)==0x10))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " CTSI ,Mask interrupt when rising edge is detected on the CTS modem control line" "Not masked,Masked"
|
|
bitfld.byte 0x00 6. " RTSI ,Inhibit interrupt when rising edge is detected on the RTS modem control line" "Not inhibited,Inhibited"
|
|
bitfld.byte 0x00 5. " XOFFI ,Mask interrupt enable when XOFF character is received" "Not masked,Masked"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DLM,Divisor Latch (LM)"
|
|
endif
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0xBF)!=0xBF)
|
|
hgroup.byte 0x08++0x00
|
|
hide.byte 0x00 "IIR/FCR,Interrupt/FIFO,Identification/Control Register"
|
|
in
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 7. " AUTO_CTS ,Enable hardware transmission flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " AUTO_RTS ,Enable hardware reception flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ENABLE_E ,Enable enhancement feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SW_FLOW_CONT ,Software flow control bits" "No TX flow control,Transmit XON1/XOFF1,No RX flow control,Receive XON1/XOFF1,?..."
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "No access,Access"
|
|
bitfld.byte 0x00 6. " SB ,Set up break" "No effect,TX break"
|
|
bitfld.byte 0x00 5. " SP ,Stick parity" "No effect,Enabled"
|
|
bitfld.byte 0x00 4. " EPS ,Select even parity" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " STB ,Number of STOP bits" "One,Two"
|
|
bitfld.byte 0x00 0.--1. " WLS1_WLS0 ,Word length select" "5bits,6bits,7bits,8bits"
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
elif (((per.long(ad:0xA00E0000+0x0C)&0xBF)!=0xBF)&&((per.long(ad:0xA00E0000+0x08)&0x10)==0x10))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 7. " XOFF_STATUS ,XOFF status" "XON received,XOFF received"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "XON1,XON1 Char Register"
|
|
endif
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0xBF)!=0xBF)
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 7. " FIFOERR ,RX FIFO error indicator" "No error,Error"
|
|
bitfld.byte 0x00 6. " TEMT ,TX holding register (or TX FIFO) and the TX shift register are empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 5. " THRE ,There is room for TX holding register or TX FIFO is reduced to its trigger level" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " BI ,Break interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FE ,Framing error" "No error,Error"
|
|
bitfld.byte 0x00 2. " PE ,Parity error" "No error,Error"
|
|
bitfld.byte 0x00 1. " OE ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 0. " DR ,Data ready" "Not ready,Ready"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "LSR,Line Status Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0xBF)==0xBF)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA00E0000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCR,Scratch Register"
|
|
else
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCR,Scratch Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
width 16.
|
|
if (((per.b(ad:0xA00E0000+0x20)&0x01)==0x01))
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
rbitfld.byte 0x00 2. " SLEEP_ACK_SEL ,Sleep ack when autobaud_en" "Not supported,Supported"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "HIGHSPEED,High Speed Mode Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,UART sample counter base" "16*baud_pulse,8*baud_pulse,4*baud_pulse,Sample_count*baud_pulse"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SAMPLE_COUNT,Sample Counter Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SAMPLE_POINT,Sample Point Register"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "AUTOBAUD_REG,Auto Baud Monitor Register"
|
|
bitfld.byte 0x00 4.--7. " BAUD_STAT ,Autobaud state" "Detected,AT_7N1,AT_7O1,AT_7E1,AT_8N1,AT_8O1,AT_8E1,AT_7N1,AT_7E1,AT_7O1,AT_8N1,AT_8E1,AT_8O1,Failed,?..."
|
|
bitfld.byte 0x00 0.--3. " BAUD_RATE ,Autobaud baud rate" "115.200,57.600,38.400,19.200,9.600,4.800,2.400,1.200,300,110,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "RATEFIX_AD,Clock Rate Fix Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_RATE_FIX ,Autobaud rate fix" "26MHz,13MHz"
|
|
bitfld.byte 0x00 0. " RATE_FIX ,Rate fix" "26MHz,13MHz"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "AUTOBAUDSAMPLE,Auto Baud Sample Register"
|
|
bitfld.byte 0x00 0.--5. " AUTOBAUDSAMPLE ,Clk division for autobaud rate detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "GUARD,Guard Time Added Register"
|
|
bitfld.byte 0x00 4. " GUARD_EN ,Guard interval add" "Not added,Added"
|
|
bitfld.byte 0x00 0.--3. " GUARD_CNT ,Guard interval count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "ESCAPE_DAT,Escape Character Register"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "ESCAPE_EN,Escape Enable Register"
|
|
bitfld.byte 0x00 0. " ESC_EN ,Add escape character to transmitter and remove it for receiver by UART" "Disabled,Enabled"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "SLEEP_EN,Sleep Enable Register"
|
|
bitfld.byte 0x00 0. " SLEEP_EN ,Sleep mode enable" "Disabled,Enabled"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "DMA_EN,DMA Enable Register"
|
|
bitfld.byte 0x00 3. " FIFO_LSR_SEL ,Select FIFO LSR mode" "LSR hold first line status,LSR auto-update"
|
|
bitfld.byte 0x00 2. " TO_CNT_AUTORST ,Time-out counter auto reset register" "Reset after RX time-out,Auto-reset"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_DMA_EN ,TX_DMA mechanism enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RX_DMA_EN ,RX_DMA mechanism enable" "Disabled,Enabled"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "RXTRI_AD,Rx Trigger Address"
|
|
bitfld.byte 0x00 0.--3. " RXTRIG ,RX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "FRACDIV_L,Fractional Divider LSB Address"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "FRACDIV_M,Fractional Divider MSB Address"
|
|
bitfld.byte 0x00 0.--1. " FRACDIV_M ,Adds sampling count when in state stop to parity to contribute fractional divisor" "0,1,2,3"
|
|
rgroup.byte 0x5C++0x00
|
|
line.byte 0x00 "FCR_RD,FIFO Control Register"
|
|
bitfld.byte 0x00 6.--7. " RFTL1_RFTL0 ,RX FIFO trigger threshold" "1,6,12,RX TRIG data"
|
|
bitfld.byte 0x00 4.--5. " TFTL1_TFTL0 ,TX FIFO trigger threshold" "1,4,8,14"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CLRT ,Clear TX FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 1. " CLRR ,Clear RX FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FIFOE ,FIFO enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0xA00F0000
|
|
width 9.
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0x80)==0x00)
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "RBR/THR,Receive/Transmit,Buffer/Holding Register"
|
|
in
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DLL,Divisor Latch (LS)"
|
|
endif
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0x80)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 2. " ELSI ,Interrupt enable when BI, FE, PE or OE is set" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ETBEI ,Interrupt enable when TX holding register is empty or the contents of the TX FIFO have been reduced to its trigger level" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ERBFI ,Interrupt enable when RX data are placed in RX buffer register or the RX trigger level is reached" "No interrupt,Interrupt"
|
|
elif (((per.long(ad:0xA00F0000+0x0C)&0x80)==0x00)&&((per.long(ad:0xA00F0000+0x08)&0x10)==0x10))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " CTSI ,Mask interrupt when rising edge is detected on the CTS modem control line" "Not masked,Masked"
|
|
bitfld.byte 0x00 6. " RTSI ,Inhibit interrupt when rising edge is detected on the RTS modem control line" "Not inhibited,Inhibited"
|
|
bitfld.byte 0x00 5. " XOFFI ,Mask interrupt enable when XOFF character is received" "Not masked,Masked"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DLM,Divisor Latch (LM)"
|
|
endif
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0xBF)!=0xBF)
|
|
hgroup.byte 0x08++0x00
|
|
hide.byte 0x00 "IIR/FCR,Interrupt/FIFO,Identification/Control Register"
|
|
in
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 7. " AUTO_CTS ,Enable hardware transmission flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " AUTO_RTS ,Enable hardware reception flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ENABLE_E ,Enable enhancement feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SW_FLOW_CONT ,Software flow control bits" "No TX flow control,Transmit XON1/XOFF1,No RX flow control,Receive XON1/XOFF1,?..."
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "No access,Access"
|
|
bitfld.byte 0x00 6. " SB ,Set up break" "No effect,TX break"
|
|
bitfld.byte 0x00 5. " SP ,Stick parity" "No effect,Enabled"
|
|
bitfld.byte 0x00 4. " EPS ,Select even parity" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " STB ,Number of STOP bits" "One,Two"
|
|
bitfld.byte 0x00 0.--1. " WLS1_WLS0 ,Word length select" "5bits,6bits,7bits,8bits"
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
elif (((per.long(ad:0xA00F0000+0x0C)&0xBF)!=0xBF)&&((per.long(ad:0xA00F0000+0x08)&0x10)==0x10))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 7. " XOFF_STATUS ,XOFF status" "XON received,XOFF received"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "XON1,XON1 Char Register"
|
|
endif
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0xBF)!=0xBF)
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 7. " FIFOERR ,RX FIFO error indicator" "No error,Error"
|
|
bitfld.byte 0x00 6. " TEMT ,TX holding register (or TX FIFO) and the TX shift register are empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 5. " THRE ,There is room for TX holding register or TX FIFO is reduced to its trigger level" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " BI ,Break interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FE ,Framing error" "No error,Error"
|
|
bitfld.byte 0x00 2. " PE ,Parity error" "No error,Error"
|
|
bitfld.byte 0x00 1. " OE ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 0. " DR ,Data ready" "Not ready,Ready"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "LSR,Line Status Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0xBF)==0xBF)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA00F0000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCR,Scratch Register"
|
|
else
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCR,Scratch Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
width 16.
|
|
if (((per.b(ad:0xA00F0000+0x20)&0x01)==0x01))
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
rbitfld.byte 0x00 2. " SLEEP_ACK_SEL ,Sleep ack when autobaud_en" "Not supported,Supported"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "HIGHSPEED,High Speed Mode Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,UART sample counter base" "16*baud_pulse,8*baud_pulse,4*baud_pulse,Sample_count*baud_pulse"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SAMPLE_COUNT,Sample Counter Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SAMPLE_POINT,Sample Point Register"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "AUTOBAUD_REG,Auto Baud Monitor Register"
|
|
bitfld.byte 0x00 4.--7. " BAUD_STAT ,Autobaud state" "Detected,AT_7N1,AT_7O1,AT_7E1,AT_8N1,AT_8O1,AT_8E1,AT_7N1,AT_7E1,AT_7O1,AT_8N1,AT_8E1,AT_8O1,Failed,?..."
|
|
bitfld.byte 0x00 0.--3. " BAUD_RATE ,Autobaud baud rate" "115.200,57.600,38.400,19.200,9.600,4.800,2.400,1.200,300,110,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "RATEFIX_AD,Clock Rate Fix Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_RATE_FIX ,Autobaud rate fix" "26MHz,13MHz"
|
|
bitfld.byte 0x00 0. " RATE_FIX ,Rate fix" "26MHz,13MHz"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "AUTOBAUDSAMPLE,Auto Baud Sample Register"
|
|
bitfld.byte 0x00 0.--5. " AUTOBAUDSAMPLE ,Clk division for autobaud rate detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "GUARD,Guard Time Added Register"
|
|
bitfld.byte 0x00 4. " GUARD_EN ,Guard interval add" "Not added,Added"
|
|
bitfld.byte 0x00 0.--3. " GUARD_CNT ,Guard interval count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "ESCAPE_DAT,Escape Character Register"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "ESCAPE_EN,Escape Enable Register"
|
|
bitfld.byte 0x00 0. " ESC_EN ,Add escape character to transmitter and remove it for receiver by UART" "Disabled,Enabled"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "SLEEP_EN,Sleep Enable Register"
|
|
bitfld.byte 0x00 0. " SLEEP_EN ,Sleep mode enable" "Disabled,Enabled"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "DMA_EN,DMA Enable Register"
|
|
bitfld.byte 0x00 3. " FIFO_LSR_SEL ,Select FIFO LSR mode" "LSR hold first line status,LSR auto-update"
|
|
bitfld.byte 0x00 2. " TO_CNT_AUTORST ,Time-out counter auto reset register" "Reset after RX time-out,Auto-reset"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_DMA_EN ,TX_DMA mechanism enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RX_DMA_EN ,RX_DMA mechanism enable" "Disabled,Enabled"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "RXTRI_AD,Rx Trigger Address"
|
|
bitfld.byte 0x00 0.--3. " RXTRIG ,RX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "FRACDIV_L,Fractional Divider LSB Address"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "FRACDIV_M,Fractional Divider MSB Address"
|
|
bitfld.byte 0x00 0.--1. " FRACDIV_M ,Adds sampling count when in state stop to parity to contribute fractional divisor" "0,1,2,3"
|
|
rgroup.byte 0x5C++0x00
|
|
line.byte 0x00 "FCR_RD,FIFO Control Register"
|
|
bitfld.byte 0x00 6.--7. " RFTL1_RFTL0 ,RX FIFO trigger threshold" "1,6,12,RX TRIG data"
|
|
bitfld.byte 0x00 4.--5. " TFTL1_TFTL0 ,TX FIFO trigger threshold" "1,4,8,14"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CLRT ,Clear TX FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 1. " CLRR ,Clear RX FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FIFOE ,FIFO enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART3"
|
|
base ad:0xA0100000
|
|
width 9.
|
|
if ((per.long(ad:0xA0100000+0x0C)&0x80)==0x00)
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "RBR/THR,Receive/Transmit,Buffer/Holding Register"
|
|
in
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DLL,Divisor Latch (LS)"
|
|
endif
|
|
if ((per.long(ad:0xA0100000+0x0C)&0x80)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 2. " ELSI ,Interrupt enable when BI, FE, PE or OE is set" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ETBEI ,Interrupt enable when TX holding register is empty or the contents of the TX FIFO have been reduced to its trigger level" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ERBFI ,Interrupt enable when RX data are placed in RX buffer register or the RX trigger level is reached" "No interrupt,Interrupt"
|
|
elif (((per.long(ad:0xA0100000+0x0C)&0x80)==0x00)&&((per.long(ad:0xA0100000+0x08)&0x10)==0x10))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " CTSI ,Mask interrupt when rising edge is detected on the CTS modem control line" "Not masked,Masked"
|
|
bitfld.byte 0x00 6. " RTSI ,Inhibit interrupt when rising edge is detected on the RTS modem control line" "Not inhibited,Inhibited"
|
|
bitfld.byte 0x00 5. " XOFFI ,Mask interrupt enable when XOFF character is received" "Not masked,Masked"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DLM,Divisor Latch (LM)"
|
|
endif
|
|
if ((per.long(ad:0xA0100000+0x0C)&0xBF)!=0xBF)
|
|
hgroup.byte 0x08++0x00
|
|
hide.byte 0x00 "IIR/FCR,Interrupt/FIFO,Identification/Control Register"
|
|
in
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 7. " AUTO_CTS ,Enable hardware transmission flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " AUTO_RTS ,Enable hardware reception flow control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ENABLE_E ,Enable enhancement feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SW_FLOW_CONT ,Software flow control bits" "No TX flow control,Transmit XON1/XOFF1,No RX flow control,Receive XON1/XOFF1,?..."
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "No access,Access"
|
|
bitfld.byte 0x00 6. " SB ,Set up break" "No effect,TX break"
|
|
bitfld.byte 0x00 5. " SP ,Stick parity" "No effect,Enabled"
|
|
bitfld.byte 0x00 4. " EPS ,Select even parity" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " STB ,Number of STOP bits" "One,Two"
|
|
bitfld.byte 0x00 0.--1. " WLS1_WLS0 ,Word length select" "5bits,6bits,7bits,8bits"
|
|
if ((per.long(ad:0xA0100000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
elif (((per.long(ad:0xA0100000+0x0C)&0xBF)!=0xBF)&&((per.long(ad:0xA0100000+0x08)&0x10)==0x10))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register"
|
|
bitfld.byte 0x00 7. " XOFF_STATUS ,XOFF status" "XON received,XOFF received"
|
|
bitfld.byte 0x00 4. " LOOP ,Loop-back mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,State of the output NRTS" "Always 1,Flow control condition"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "XON1,XON1 Char Register"
|
|
endif
|
|
if ((per.long(ad:0xA0100000+0x0C)&0xBF)!=0xBF)
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 7. " FIFOERR ,RX FIFO error indicator" "No error,Error"
|
|
bitfld.byte 0x00 6. " TEMT ,TX holding register (or TX FIFO) and the TX shift register are empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 5. " THRE ,There is room for TX holding register or TX FIFO is reduced to its trigger level" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " BI ,Break interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FE ,Framing error" "No error,Error"
|
|
bitfld.byte 0x00 2. " PE ,Parity error" "No error,Error"
|
|
bitfld.byte 0x00 1. " OE ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 0. " DR ,Data ready" "Not ready,Ready"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "LSR,Line Status Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA0100000+0x0C)&0xBF)==0xBF)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "XOFF1,XOFF1 Char Register"
|
|
in
|
|
endif
|
|
if ((per.long(ad:0xA0100000+0x0C)&0xBF)!=0xBF)
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCR,Scratch Register"
|
|
else
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCR,Scratch Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
width 16.
|
|
if (((per.b(ad:0xA0100000+0x20)&0x01)==0x01))
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
rbitfld.byte 0x00 2. " SLEEP_ACK_SEL ,Sleep ack when autobaud_en" "Not supported,Supported"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "AUTOBAUD_EN,Auto Baud Detect Enable Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_SEL ,Select auto-baud" "Standard,Autobaud"
|
|
bitfld.byte 0x00 0. " AUTOBAUD_EN ,Autobaud enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "HIGHSPEED,High Speed Mode Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,UART sample counter base" "16*baud_pulse,8*baud_pulse,4*baud_pulse,Sample_count*baud_pulse"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SAMPLE_COUNT,Sample Counter Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SAMPLE_POINT,Sample Point Register"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "AUTOBAUD_REG,Auto Baud Monitor Register"
|
|
bitfld.byte 0x00 4.--7. " BAUD_STAT ,Autobaud state" "Detected,AT_7N1,AT_7O1,AT_7E1,AT_8N1,AT_8O1,AT_8E1,AT_7N1,AT_7E1,AT_7O1,AT_8N1,AT_8E1,AT_8O1,Failed,?..."
|
|
bitfld.byte 0x00 0.--3. " BAUD_RATE ,Autobaud baud rate" "115.200,57.600,38.400,19.200,9.600,4.800,2.400,1.200,300,110,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "RATEFIX_AD,Clock Rate Fix Register"
|
|
bitfld.byte 0x00 1. " AUTOBAUD_RATE_FIX ,Autobaud rate fix" "26MHz,13MHz"
|
|
bitfld.byte 0x00 0. " RATE_FIX ,Rate fix" "26MHz,13MHz"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "AUTOBAUDSAMPLE,Auto Baud Sample Register"
|
|
bitfld.byte 0x00 0.--5. " AUTOBAUDSAMPLE ,Clk division for autobaud rate detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "GUARD,Guard Time Added Register"
|
|
bitfld.byte 0x00 4. " GUARD_EN ,Guard interval add" "Not added,Added"
|
|
bitfld.byte 0x00 0.--3. " GUARD_CNT ,Guard interval count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "ESCAPE_DAT,Escape Character Register"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "ESCAPE_EN,Escape Enable Register"
|
|
bitfld.byte 0x00 0. " ESC_EN ,Add escape character to transmitter and remove it for receiver by UART" "Disabled,Enabled"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "SLEEP_EN,Sleep Enable Register"
|
|
bitfld.byte 0x00 0. " SLEEP_EN ,Sleep mode enable" "Disabled,Enabled"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "DMA_EN,DMA Enable Register"
|
|
bitfld.byte 0x00 3. " FIFO_LSR_SEL ,Select FIFO LSR mode" "LSR hold first line status,LSR auto-update"
|
|
bitfld.byte 0x00 2. " TO_CNT_AUTORST ,Time-out counter auto reset register" "Reset after RX time-out,Auto-reset"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_DMA_EN ,TX_DMA mechanism enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RX_DMA_EN ,RX_DMA mechanism enable" "Disabled,Enabled"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "RXTRI_AD,Rx Trigger Address"
|
|
bitfld.byte 0x00 0.--3. " RXTRIG ,RX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "FRACDIV_L,Fractional Divider LSB Address"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "FRACDIV_M,Fractional Divider MSB Address"
|
|
bitfld.byte 0x00 0.--1. " FRACDIV_M ,Adds sampling count when in state stop to parity to contribute fractional divisor" "0,1,2,3"
|
|
rgroup.byte 0x5C++0x00
|
|
line.byte 0x00 "FCR_RD,FIFO Control Register"
|
|
bitfld.byte 0x00 6.--7. " RFTL1_RFTL0 ,RX FIFO trigger threshold" "1,6,12,RX TRIG data"
|
|
bitfld.byte 0x00 4.--5. " TFTL1_TFTL0 ,TX FIFO trigger threshold" "1,4,8,14"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CLRT ,Clear TX FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 1. " CLRR ,Clear RX FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FIFOE ,FIFO enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI_MSTR (Serial Peripheral Interface Master Controller)"
|
|
tree "SPI0"
|
|
base ad:0xA0110000
|
|
width 20.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SPI0_CFG0,SPI0 Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CS_SETUP_COUNT ,Chip select setup time"
|
|
hexmask.long.word 0x00 0.--15. 1. " CS_HOLD_COUNT ,Chip select hold time"
|
|
line.long 0x04 "SPI0_CFG1,SPI0 Configuration 1 Register"
|
|
bitfld.long 0x04 29.--31. " GET_TICK_DLY ,Get_tick timing tolerate value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 26. " DEVICE_SEL ,Device 1 or device 0 MISO data" "Device 0,Device 1"
|
|
hexmask.long.word 0x04 16.--25. 1. " PACKET_LENGTH ,Packet length"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PACKET_LOOP_CNT ,Packet loop counter"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CS_IDLE_COUNT ,Chip select idle time"
|
|
if (((per.l(ad:0xA0110000+0x18)&0x800)==0x800))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPI0_TX_SRC,SPI0 TX Source Address Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_TX_SRC,SPI0 TX Source Address Register"
|
|
endif
|
|
if (((per.l(ad:0xA0110000+0x18)&0x400)==0x400))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SPI0_RX_DST,SPI0 RX Destination Address Register"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SPI0_RX_DST,SPI0 RX Destination Address Register"
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SPI0_TX_DATA,SPI0 TX DATA FIFO"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SPI0_RX_DATA,SPI0 RX DATA FIFO"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SPI0_CMD,SPI0 Command Register"
|
|
bitfld.long 0x00 17. " PAUSE_IE ,Interrupt enable bit of pause flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " FINISH_IE ,Interrupt enable bit of finish flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TX_ENDIAN ,Reverse endian order of the data DMA from memory" "No reverse,Reverse"
|
|
bitfld.long 0x00 14. " RX_ENDIAN ,Reverse endian order of the data DMA to memory" "No reverse,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMSBF ,Data received from MISO line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 12. " TXMSBF ,Data sent on MOSI line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 11. " TX_DMA_EN ,DMA mode enable bit of data to be transmitted" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX_DMA_EN ,DMA mode enable bit of data being received" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,SCK polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock format 0 or SPI clock format 1 during transmission" "Low,High"
|
|
bitfld.long 0x00 7. " CS_POL ,Chip select polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " SAMPLE_SEL ,Sample edge of MISO" "Positive edge,Negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_DEASSERT_EN ,Chip select de-assertion mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PAUSE_EN ,Pause mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " RESUME ,Resume transfer from pause idle state" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ACT ,Start transaction" "Not started,Started"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SPI0_STATUS0,SPI0 Status 0 Register"
|
|
in
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SPI0_STATUS1,SPI0 Status 1 Register"
|
|
bitfld.long 0x00 0. " BUSY ,SPI controller busy" "Busy,Idle"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "SPI0_PAD_MACRO_SEL,SPI0 Pad Macro Selection Register"
|
|
bitfld.long 0x00 0.--2. " PAD_MACRO_SEL ,PAD group SPI select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SPI0_CFG2,SPI0 Configuration 2 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " SCK_LOW_COUNT ,SCK clock low time"
|
|
hexmask.long.word 0x04 0.--15. 1. " SCK_HIGH_COUNT ,SCK clock high time"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0xA0120000
|
|
width 20.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SPI1_CFG0,SPI1 Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CS_SETUP_COUNT ,Chip select setup time"
|
|
hexmask.long.word 0x00 0.--15. 1. " CS_HOLD_COUNT ,Chip select hold time"
|
|
line.long 0x04 "SPI1_CFG1,SPI1 Configuration 1 Register"
|
|
bitfld.long 0x04 29.--31. " GET_TICK_DLY ,Get_tick timing tolerate value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 26. " DEVICE_SEL ,Device 1 or device 0 MISO data" "Device 0,Device 1"
|
|
hexmask.long.word 0x04 16.--25. 1. " PACKET_LENGTH ,Packet length"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PACKET_LOOP_CNT ,Packet loop counter"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CS_IDLE_COUNT ,Chip select idle time"
|
|
if (((per.l(ad:0xA0120000+0x18)&0x800)==0x800))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPI1_TX_SRC,SPI1 TX Source Address Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_TX_SRC,SPI1 TX Source Address Register"
|
|
endif
|
|
if (((per.l(ad:0xA0120000+0x18)&0x400)==0x400))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SPI1_RX_DST,SPI1 RX Destination Address Register"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SPI1_RX_DST,SPI1 RX Destination Address Register"
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SPI1_TX_DATA,SPI1 TX DATA FIFO"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SPI1_RX_DATA,SPI1 RX DATA FIFO"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SPI1_CMD,SPI1 Command Register"
|
|
bitfld.long 0x00 17. " PAUSE_IE ,Interrupt enable bit of pause flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " FINISH_IE ,Interrupt enable bit of finish flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TX_ENDIAN ,Reverse endian order of the data DMA from memory" "No reverse,Reverse"
|
|
bitfld.long 0x00 14. " RX_ENDIAN ,Reverse endian order of the data DMA to memory" "No reverse,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMSBF ,Data received from MISO line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 12. " TXMSBF ,Data sent on MOSI line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 11. " TX_DMA_EN ,DMA mode enable bit of data to be transmitted" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX_DMA_EN ,DMA mode enable bit of data being received" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,SCK polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock format 0 or SPI clock format 1 during transmission" "Low,High"
|
|
bitfld.long 0x00 7. " CS_POL ,Chip select polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " SAMPLE_SEL ,Sample edge of MISO" "Positive edge,Negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_DEASSERT_EN ,Chip select de-assertion mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PAUSE_EN ,Pause mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " RESUME ,Resume transfer from pause idle state" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ACT ,Start transaction" "Not started,Started"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SPI1_STATUS0,SPI1 Status 0 Register"
|
|
in
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SPI1_STATUS1,SPI1 Status 1 Register"
|
|
bitfld.long 0x00 0. " BUSY ,SPI controller busy" "Busy,Idle"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "SPI1_PAD_MACRO_SEL,SPI1 Pad Macro Selection Register"
|
|
bitfld.long 0x00 0.--2. " PAD_MACRO_SEL ,PAD group SPI select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SPI1_CFG2,SPI1 Configuration 2 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " SCK_LOW_COUNT ,SCK clock low time"
|
|
hexmask.long.word 0x04 0.--15. 1. " SCK_HIGH_COUNT ,SCK clock high time"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0xA0130000
|
|
width 20.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SPI2_CFG0,SPI2 Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CS_SETUP_COUNT ,Chip select setup time"
|
|
hexmask.long.word 0x00 0.--15. 1. " CS_HOLD_COUNT ,Chip select hold time"
|
|
line.long 0x04 "SPI2_CFG1,SPI2 Configuration 1 Register"
|
|
bitfld.long 0x04 29.--31. " GET_TICK_DLY ,Get_tick timing tolerate value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 26. " DEVICE_SEL ,Device 1 or device 0 MISO data" "Device 0,Device 1"
|
|
hexmask.long.word 0x04 16.--25. 1. " PACKET_LENGTH ,Packet length"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PACKET_LOOP_CNT ,Packet loop counter"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CS_IDLE_COUNT ,Chip select idle time"
|
|
if (((per.l(ad:0xA0130000+0x18)&0x800)==0x800))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPI2_TX_SRC,SPI2 TX Source Address Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI2_TX_SRC,SPI2 TX Source Address Register"
|
|
endif
|
|
if (((per.l(ad:0xA0130000+0x18)&0x400)==0x400))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SPI2_RX_DST,SPI2 RX Destination Address Register"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SPI2_RX_DST,SPI2 RX Destination Address Register"
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SPI2_TX_DATA,SPI2 TX DATA FIFO"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SPI2_RX_DATA,SPI2 RX DATA FIFO"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SPI2_CMD,SPI2 Command Register"
|
|
bitfld.long 0x00 17. " PAUSE_IE ,Interrupt enable bit of pause flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " FINISH_IE ,Interrupt enable bit of finish flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TX_ENDIAN ,Reverse endian order of the data DMA from memory" "No reverse,Reverse"
|
|
bitfld.long 0x00 14. " RX_ENDIAN ,Reverse endian order of the data DMA to memory" "No reverse,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMSBF ,Data received from MISO line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 12. " TXMSBF ,Data sent on MOSI line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 11. " TX_DMA_EN ,DMA mode enable bit of data to be transmitted" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX_DMA_EN ,DMA mode enable bit of data being received" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,SCK polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock format 0 or SPI clock format 1 during transmission" "Low,High"
|
|
bitfld.long 0x00 7. " CS_POL ,Chip select polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " SAMPLE_SEL ,Sample edge of MISO" "Positive edge,Negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_DEASSERT_EN ,Chip select de-assertion mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PAUSE_EN ,Pause mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " RESUME ,Resume transfer from pause idle state" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ACT ,Start transaction" "Not started,Started"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SPI2_STATUS0,SPI2 Status 0 Register"
|
|
in
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SPI2_STATUS1,SPI2 Status 1 Register"
|
|
bitfld.long 0x00 0. " BUSY ,SPI controller busy" "Busy,Idle"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "SPI2_PAD_MACRO_SEL,SPI2 Pad Macro Selection Register"
|
|
bitfld.long 0x00 0.--2. " PAD_MACRO_SEL ,PAD group SPI select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SPI2_CFG2,SPI2 Configuration 2 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " SCK_LOW_COUNT ,SCK clock low time"
|
|
hexmask.long.word 0x04 0.--15. 1. " SCK_HIGH_COUNT ,SCK clock high time"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0xA0140000
|
|
width 20.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SPI3_CFG0,SPI3 Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CS_SETUP_COUNT ,Chip select setup time"
|
|
hexmask.long.word 0x00 0.--15. 1. " CS_HOLD_COUNT ,Chip select hold time"
|
|
line.long 0x04 "SPI3_CFG1,SPI3 Configuration 1 Register"
|
|
bitfld.long 0x04 29.--31. " GET_TICK_DLY ,Get_tick timing tolerate value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 26. " DEVICE_SEL ,Device 1 or device 0 MISO data" "Device 0,Device 1"
|
|
hexmask.long.word 0x04 16.--25. 1. " PACKET_LENGTH ,Packet length"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PACKET_LOOP_CNT ,Packet loop counter"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CS_IDLE_COUNT ,Chip select idle time"
|
|
if (((per.l(ad:0xA0140000+0x18)&0x800)==0x800))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPI3_TX_SRC,SPI3 TX Source Address Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI3_TX_SRC,SPI3 TX Source Address Register"
|
|
endif
|
|
if (((per.l(ad:0xA0140000+0x18)&0x400)==0x400))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SPI3_RX_DST,SPI3 RX Destination Address Register"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SPI3_RX_DST,SPI3 RX Destination Address Register"
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SPI3_TX_DATA,SPI3 TX DATA FIFO"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SPI3_RX_DATA,SPI3 RX DATA FIFO"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SPI3_CMD,SPI3 Command Register"
|
|
bitfld.long 0x00 17. " PAUSE_IE ,Interrupt enable bit of pause flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " FINISH_IE ,Interrupt enable bit of finish flag in SPI status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TX_ENDIAN ,Reverse endian order of the data DMA from memory" "No reverse,Reverse"
|
|
bitfld.long 0x00 14. " RX_ENDIAN ,Reverse endian order of the data DMA to memory" "No reverse,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMSBF ,Data received from MISO line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 12. " TXMSBF ,Data sent on MOSI line is MSB first" "No MSB first,MSB first"
|
|
bitfld.long 0x00 11. " TX_DMA_EN ,DMA mode enable bit of data to be transmitted" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX_DMA_EN ,DMA mode enable bit of data being received" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,SCK polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock format 0 or SPI clock format 1 during transmission" "Low,High"
|
|
bitfld.long 0x00 7. " CS_POL ,Chip select polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " SAMPLE_SEL ,Sample edge of MISO" "Positive edge,Negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_DEASSERT_EN ,Chip select de-assertion mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PAUSE_EN ,Pause mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " RESUME ,Resume transfer from pause idle state" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ACT ,Start transaction" "Not started,Started"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SPI3_STATUS0,SPI3 Status 0 Register"
|
|
in
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SPI3_STATUS1,SPI3 Status 1 Register"
|
|
bitfld.long 0x00 0. " BUSY ,SPI controller busy" "Busy,Idle"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "SPI3_PAD_MACRO_SEL,SPI3 Pad Macro Selection Register"
|
|
bitfld.long 0x00 0.--2. " PAD_MACRO_SEL ,PAD group SPI select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SPI3_CFG2,SPI3 Configuration 2 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " SCK_LOW_COUNT ,SCK clock low time"
|
|
hexmask.long.word 0x04 0.--15. 1. " SCK_HIGH_COUNT ,SCK clock high time"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI_SLV (Serial Peripheral Interface Slave Controller)"
|
|
base ad:0xA0150000
|
|
width 28.
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "SPISLV_TRANS_TYPE,SPISLV Transfer Information Register"
|
|
bitfld.long 0x00 9.--10. " DBG_AHB_STATUS ,DBG AHB status" "Bust transfer,Single word transfer,Idle,Single byte transfer"
|
|
bitfld.long 0x00 8. " DIR ,Read/Write DMA memory select" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMD_RECEIVED ,Command spislv receives"
|
|
line.long 0x04 "SPISLV_TRANS_LENGTH,SPISLV Transfer Length Register"
|
|
line.long 0x08 "SPISLV_TRANS_ADDR,SPISLV Transfer Address Register"
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SPISLV_CTRL,SPISLV Control Register"
|
|
bitfld.long 0x00 16. " POWER_ON_INT_EN ,Power on command interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SW_DECODE_ADDRESS_EN ,Enable software decode address sent by SPI master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_DMA_SW_READY ,TX DMA software ready" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " RX_DMA_SW_READY ,RX DMA software ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TXMSBF ,Data sent on MISO line is MSB first" "Not MSB first,MSB first"
|
|
bitfld.long 0x00 11. " RXMSBF ,Data received from MISO line is MSB first" "Not MSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POWER_OFF_INT_EN ,Power off command interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WR_CFG_FINISH_INT_EN ,CW configure finishing interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RD_CFG_FINISH_INT_EN ,CR configure finishing interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RD_TRANS_FINISH_INT_EN ,RD data finishing interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TMOUT_ERR_INT_EN ,TIMEOUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WR_TRANS_FINISH_INT_EN ,WR data finishing interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WR_DATA_ERR_INT_EN ,WR data error IRQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RD_DATA_ERR_INT_EN ,RD data error IRQ enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPOL ,SCK polarity" "0,1"
|
|
bitfld.long 0x00 1. " CPHA , SPI Clock Format 0 or SPI Clock Format 1 during transmission" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIZE_OF_ADDR ,CW/CR command format" "2 byte transfer address + 2 byte transfer length,4 byte transfer address + 4 byte transfer length"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SPISLV_STATUS,SPISLV Status Register"
|
|
bitfld.long 0x00 13. " SR_POWER_ON ,SPI SLAVE received power-on command" "Not received,Received"
|
|
bitfld.long 0x00 12. " SR_POWER_OFF ,SPI SLAVE received power-off command" "Not received,Received"
|
|
bitfld.long 0x00 11. " SR_WR_FINISH ,SPI SLAVE write data finished" "Not finished,Finished"
|
|
bitfld.long 0x00 10. " SR_RD_FINISH ,SPI SLAVE read data finished" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SR_CFG_WRITE_FINISH ,SPI receive CFG READ CMD is finished" "Not finished,Finished"
|
|
bitfld.long 0x00 8. " SR_CFG_READ_FINISH ,SPI receive CFG READ CMD is finished" "Not finished,Finished"
|
|
bitfld.long 0x00 7. " SR_CMD_ERROR ,SPI master sends an error command" "Not finished,Finished"
|
|
bitfld.long 0x00 6. " SR_TIMOUT_ERR ,Time-out and SPI slave does not receive or send data for some time" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SR_RDWR ,SPI master RD/WR is finished" "Not finished,Finished"
|
|
bitfld.long 0x00 4. " SR_WR_ERR ,SPI master WR error" "No error,Error"
|
|
bitfld.long 0x00 3. " SR_RD_ERR ,SPI master RD error" "No error,Error"
|
|
bitfld.long 0x00 2. " SR_TXRX_FIFO_RDY ,TX/RX FIFO ready" "No ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SR_CFG_SUCESS ,SPI master configured successfully" "No success,Success"
|
|
bitfld.long 0x00 0. " SLV_ON ,SPI slave on" "Slave off,Slave on"
|
|
textline " "
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "SPISLV_TIMOUT_THR,SPISLV Timeout Threshold Register"
|
|
line.long 0x04 "SPISLV_SW_RST,SPISLV SW Reset Register"
|
|
bitfld.long 0x04 0. " SPI_SW_RST ,Software reset" "No reset,Reset"
|
|
line.long 0x08 "SPISLV_BUFFER_BASE_ADDR,SPISLV Buffer Base Address Register"
|
|
line.long 0x0C "SPISLV_BUFFER_SIZE,SPISLV Buffer Size Register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "SPISLV_IRQ,SPISLV IRQ Register"
|
|
in
|
|
textline " "
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "SPISLV_MISO_EARLY_HALF_SCK,SPISLV MISO EARLY HALF SCK Register"
|
|
bitfld.long 0x00 0. " SPI_MISO_EARLY_HALF_SCK ,Send MISO early harf sck cycle" "Disabled,Enabled"
|
|
line.long 0x04 "SPISLV_CMD_DEFINE0,SPISLV Command0 Define"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CMD_WS ,Write status (WR) command value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CMD_RS ,Read status (RS) command value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CMD_WR ,Write data (WD) command value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CMD_RD ,Read data (RD) command value"
|
|
line.long 0x08 "SPISLV_CMD_DEFINE1,SPISLV Command0 Define"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CMD_POWEROFF ,Power-off command value"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CMD_POWERON ,Power-on command value"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CMD_CW ,Configure write (CW) command value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CMD_CR ,Configure read (CR) command value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit Controller)"
|
|
tree "I2C0"
|
|
base ad:0xA0210000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_PORT,Data Port Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA_PORT ,FIFO access port"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SLAVE_ADDR,Slave Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " SLAVE_ADDR[7:1] ,Slave address of the device to be accessed"
|
|
bitfld.word 0x00 0. " [0] ,Transfer direction" "Master write,Master read"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.word 0x00 2. " MASK_HS_NACKER ,Mask HS_NACKERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " MASK_ACKERR ,Mask ACK_ERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " MASK_TRANSAC_COMP ,Mask TRANSAC_COMP interrupt signal" "Masked,Not masked"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "INTR_STAT,Interrupt Status Register"
|
|
bitfld.word 0x00 2. " HS_NACKERR ,HS master code NACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " ACKERR ,ACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " TRANSAC_COMP ,Transaction complete interrupt status" "Not succeed,Succeed"
|
|
if (((per.w(ad:0xA0210000+0x48)&0x01)==0x00))
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" ",Repeated start"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" "Stopped,Repeated start"
|
|
endif
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TRANSFER_LEN,Transfer Length Register"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN ,Number of data bytes to be transferred in 1 transfer unit" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TRANSAC_LEN,Transaction Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TRANSAC_LEN ,Number of transfers to be transferred in 1 transaction"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "DELAY_LEN,Inter Delay Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DELAY_LEN ,Delay between consecutive transfers when RS_STOP bit is set to 0"
|
|
if (((per.w(ad:0xA0210000+0x20)&0x8000)==0x8000))
|
|
if (((per.w(ad:0xA0210000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xA0210000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "START,Start Register"
|
|
bitfld.word 0x00 0. " START ,Start transaction on the bus" "Not started,Started"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CLOCK_DIV,Clock Divergence Of I2C Source Clock"
|
|
bitfld.word 0x00 0.--2. " CLOCK_DIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "FIFO_STAT,FIFO Status Register"
|
|
bitfld.word 0x00 12.--15. " RD_ADDR ,Current RD address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " WR_ADDR ,Current WR address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " FIFO_OFFSET ,FIFO offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 1. " WR_FULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RD_EMPTY ,FIFO is empty" "Not empty,Empty"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "FIFO_ADDR_CLR,FIFO Address Clear Register"
|
|
bitfld.word 0x00 0. " FIFO_ADDR_CLR ,FIFO address clear" "Not cleared,Cleared"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IO_CONFIG,IO Config Register"
|
|
bitfld.word 0x00 3. " IDLE_OE_EN ,Drive bus idle state enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SDA_IO_CONFIG ,SDA I/O configuration" "Tristate,Open-drain"
|
|
bitfld.word 0x00 0. " SCL_IO_CONFIG ,SCL I/O configuration" "Tristate,Open-drain"
|
|
if (((per.w(ad:0xA0210000+0x10)&0x02)==0x02))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "HS,High Speed Mode Register"
|
|
bitfld.word 0x00 12.--14. " HS_SAMPLE_CNT_DIV ,High speed sample counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " HS_STEP_CNT_DIV ,High speed step counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " MASTER_CODE ,Master code to be transmitted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 1. " HS_NACKERR_DET_EN ,NACKERR detection during the master code transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " HS_EN ,High-speed transaction enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "HS,High Speed Mode Register"
|
|
endif
|
|
wgroup.word 0x50++0x01
|
|
line.word 0x00 "SOFTRESET,Soft Reset Register"
|
|
bitfld.word 0x00 0. " SOFT_RESET ,Soft reset to reset I2C internal hardware circuits" "No reset,Reset"
|
|
textline " "
|
|
if (((per.w(ad:0xA0210000+0x48)&0x01)==0x01))
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,Master preparing data bit of master code,Master sending data bit of master code,Master/Slave preparing NACK bit,Master/Slave transmitting NACK bit,?..."
|
|
textline " "
|
|
else
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,?..."
|
|
textline " "
|
|
endif
|
|
width 18.
|
|
if (((per.w(ad:0xA0210000+0x68)&0x01)==0x01))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 1. " APB_DEBUG_RD ,Generate pulsed FIFO APB RD signal" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
endif
|
|
if ((per.word(ad:0xA0210000+0x10)&0x10)==0x10)||((per.word(ad:0xA0210000+0x10)&0x40)==0x40)
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "TRANSFER_LEN_AUX,Transfer Length Register (Number Of Bytes Per Transfer)"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN_AUX ,Number of data bytes to be transferred in 1 transfer unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0xA0220000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_PORT,Data Port Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA_PORT ,FIFO access port"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SLAVE_ADDR,Slave Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " SLAVE_ADDR[7:1] ,Slave address of the device to be accessed"
|
|
bitfld.word 0x00 0. " [0] ,Transfer direction" "Master write,Master read"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.word 0x00 2. " MASK_HS_NACKER ,Mask HS_NACKERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " MASK_ACKERR ,Mask ACK_ERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " MASK_TRANSAC_COMP ,Mask TRANSAC_COMP interrupt signal" "Masked,Not masked"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "INTR_STAT,Interrupt Status Register"
|
|
bitfld.word 0x00 2. " HS_NACKERR ,HS master code NACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " ACKERR ,ACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " TRANSAC_COMP ,Transaction complete interrupt status" "Not succeed,Succeed"
|
|
if (((per.w(ad:0xA0220000+0x48)&0x01)==0x00))
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" ",Repeated start"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" "Stopped,Repeated start"
|
|
endif
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TRANSFER_LEN,Transfer Length Register"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN ,Number of data bytes to be transferred in 1 transfer unit" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TRANSAC_LEN,Transaction Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TRANSAC_LEN ,Number of transfers to be transferred in 1 transaction"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "DELAY_LEN,Inter Delay Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DELAY_LEN ,Delay between consecutive transfers when RS_STOP bit is set to 0"
|
|
if (((per.w(ad:0xA0220000+0x20)&0x8000)==0x8000))
|
|
if (((per.w(ad:0xA0220000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xA0220000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "START,Start Register"
|
|
bitfld.word 0x00 0. " START ,Start transaction on the bus" "Not started,Started"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CLOCK_DIV,Clock Divergence Of I2C Source Clock"
|
|
bitfld.word 0x00 0.--2. " CLOCK_DIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "FIFO_STAT,FIFO Status Register"
|
|
bitfld.word 0x00 12.--15. " RD_ADDR ,Current RD address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " WR_ADDR ,Current WR address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " FIFO_OFFSET ,FIFO offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 1. " WR_FULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RD_EMPTY ,FIFO is empty" "Not empty,Empty"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "FIFO_ADDR_CLR,FIFO Address Clear Register"
|
|
bitfld.word 0x00 0. " FIFO_ADDR_CLR ,FIFO address clear" "Not cleared,Cleared"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IO_CONFIG,IO Config Register"
|
|
bitfld.word 0x00 3. " IDLE_OE_EN ,Drive bus idle state enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SDA_IO_CONFIG ,SDA I/O configuration" "Tristate,Open-drain"
|
|
bitfld.word 0x00 0. " SCL_IO_CONFIG ,SCL I/O configuration" "Tristate,Open-drain"
|
|
if (((per.w(ad:0xA0220000+0x10)&0x02)==0x02))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "HS,High Speed Mode Register"
|
|
bitfld.word 0x00 12.--14. " HS_SAMPLE_CNT_DIV ,High speed sample counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " HS_STEP_CNT_DIV ,High speed step counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " MASTER_CODE ,Master code to be transmitted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 1. " HS_NACKERR_DET_EN ,NACKERR detection during the master code transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " HS_EN ,High-speed transaction enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "HS,High Speed Mode Register"
|
|
endif
|
|
wgroup.word 0x50++0x01
|
|
line.word 0x00 "SOFTRESET,Soft Reset Register"
|
|
bitfld.word 0x00 0. " SOFT_RESET ,Soft reset to reset I2C internal hardware circuits" "No reset,Reset"
|
|
textline " "
|
|
if (((per.w(ad:0xA0220000+0x48)&0x01)==0x01))
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,Master preparing data bit of master code,Master sending data bit of master code,Master/Slave preparing NACK bit,Master/Slave transmitting NACK bit,?..."
|
|
textline " "
|
|
else
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,?..."
|
|
textline " "
|
|
endif
|
|
width 18.
|
|
if (((per.w(ad:0xA0220000+0x68)&0x01)==0x01))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 1. " APB_DEBUG_RD ,Generate pulsed FIFO APB RD signal" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
endif
|
|
if ((per.word(ad:0xA0220000+0x10)&0x10)==0x10)||((per.word(ad:0xA0220000+0x10)&0x40)==0x40)
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "TRANSFER_LEN_AUX,Transfer Length Register (Number Of Bytes Per Transfer)"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN_AUX ,Number of data bytes to be transferred in 1 transfer unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0xA01B0000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_PORT,Data Port Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA_PORT ,FIFO access port"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SLAVE_ADDR,Slave Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " SLAVE_ADDR[7:1] ,Slave address of the device to be accessed"
|
|
bitfld.word 0x00 0. " [0] ,Transfer direction" "Master write,Master read"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.word 0x00 2. " MASK_HS_NACKER ,Mask HS_NACKERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " MASK_ACKERR ,Mask ACK_ERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " MASK_TRANSAC_COMP ,Mask TRANSAC_COMP interrupt signal" "Masked,Not masked"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "INTR_STAT,Interrupt Status Register"
|
|
bitfld.word 0x00 2. " HS_NACKERR ,HS master code NACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " ACKERR ,ACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " TRANSAC_COMP ,Transaction complete interrupt status" "Not succeed,Succeed"
|
|
if (((per.w(ad:0xA01B0000+0x48)&0x01)==0x00))
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" ",Repeated start"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" "Stopped,Repeated start"
|
|
endif
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TRANSFER_LEN,Transfer Length Register"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN ,Number of data bytes to be transferred in 1 transfer unit" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TRANSAC_LEN,Transaction Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TRANSAC_LEN ,Number of transfers to be transferred in 1 transaction"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "DELAY_LEN,Inter Delay Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DELAY_LEN ,Delay between consecutive transfers when RS_STOP bit is set to 0"
|
|
if (((per.w(ad:0xA01B0000+0x20)&0x8000)==0x8000))
|
|
if (((per.w(ad:0xA01B0000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xA01B0000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "START,Start Register"
|
|
bitfld.word 0x00 0. " START ,Start transaction on the bus" "Not started,Started"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CLOCK_DIV,Clock Divergence Of I2C Source Clock"
|
|
bitfld.word 0x00 0.--2. " CLOCK_DIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "FIFO_STAT,FIFO Status Register"
|
|
bitfld.word 0x00 12.--15. " RD_ADDR ,Current RD address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " WR_ADDR ,Current WR address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " FIFO_OFFSET ,FIFO offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 1. " WR_FULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RD_EMPTY ,FIFO is empty" "Not empty,Empty"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "FIFO_ADDR_CLR,FIFO Address Clear Register"
|
|
bitfld.word 0x00 0. " FIFO_ADDR_CLR ,FIFO address clear" "Not cleared,Cleared"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IO_CONFIG,IO Config Register"
|
|
bitfld.word 0x00 3. " IDLE_OE_EN ,Drive bus idle state enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SDA_IO_CONFIG ,SDA I/O configuration" "Tristate,Open-drain"
|
|
bitfld.word 0x00 0. " SCL_IO_CONFIG ,SCL I/O configuration" "Tristate,Open-drain"
|
|
if (((per.w(ad:0xA01B0000+0x10)&0x02)==0x02))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "HS,High Speed Mode Register"
|
|
bitfld.word 0x00 12.--14. " HS_SAMPLE_CNT_DIV ,High speed sample counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " HS_STEP_CNT_DIV ,High speed step counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " MASTER_CODE ,Master code to be transmitted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 1. " HS_NACKERR_DET_EN ,NACKERR detection during the master code transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " HS_EN ,High-speed transaction enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "HS,High Speed Mode Register"
|
|
endif
|
|
wgroup.word 0x50++0x01
|
|
line.word 0x00 "SOFTRESET,Soft Reset Register"
|
|
bitfld.word 0x00 0. " SOFT_RESET ,Soft reset to reset I2C internal hardware circuits" "No reset,Reset"
|
|
textline " "
|
|
if (((per.w(ad:0xA01B0000+0x48)&0x01)==0x01))
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,Master preparing data bit of master code,Master sending data bit of master code,Master/Slave preparing NACK bit,Master/Slave transmitting NACK bit,?..."
|
|
textline " "
|
|
else
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,?..."
|
|
textline " "
|
|
endif
|
|
width 18.
|
|
if (((per.w(ad:0xA01B0000+0x68)&0x01)==0x01))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 1. " APB_DEBUG_RD ,Generate pulsed FIFO APB RD signal" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
endif
|
|
if ((per.word(ad:0xA01B0000+0x10)&0x10)==0x10)||((per.word(ad:0xA01B0000+0x10)&0x40)==0x40)
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "TRANSFER_LEN_AUX,Transfer Length Register (Number Of Bytes Per Transfer)"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN_AUX ,Number of data bytes to be transferred in 1 transfer unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C_D2D"
|
|
base ad:0xA2150000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_PORT,Data Port Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA_PORT ,FIFO access port"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SLAVE_ADDR,Slave Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " SLAVE_ADDR[7:1] ,Slave address of the device to be accessed"
|
|
bitfld.word 0x00 0. " [0] ,Transfer direction" "Master write,Master read"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.word 0x00 2. " MASK_HS_NACKER ,Mask HS_NACKERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " MASK_ACKERR ,Mask ACK_ERR interrupt signal" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " MASK_TRANSAC_COMP ,Mask TRANSAC_COMP interrupt signal" "Masked,Not masked"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "INTR_STAT,Interrupt Status Register"
|
|
bitfld.word 0x00 2. " HS_NACKERR ,HS master code NACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " ACKERR ,ACK error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " TRANSAC_COMP ,Transaction complete interrupt status" "Not succeed,Succeed"
|
|
if (((per.w(ad:0xA2150000+0x48)&0x01)==0x00))
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" ",Repeated start"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 6. " TRANSFER_LEN_CHANGE ,Transfer length change enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACKERR_DET_EN ,Slave ack error detection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DIR_CHANGE ,Change transfer direction from write to read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_EXT_EN ,Master controller enter high wait state until slave releases SCL line enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMA_EN ,DMA requests enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RS_STOP ,REPEATED-START condition used between transfers" "Stopped,Repeated start"
|
|
endif
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TRANSFER_LEN,Transfer Length Register"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN ,Number of data bytes to be transferred in 1 transfer unit" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TRANSAC_LEN,Transaction Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TRANSAC_LEN ,Number of transfers to be transferred in 1 transaction"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "DELAY_LEN,Inter Delay Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DELAY_LEN ,Delay between consecutive transfers when RS_STOP bit is set to 0"
|
|
if (((per.w(ad:0xA2150000+0x20)&0x8000)==0x8000))
|
|
if (((per.w(ad:0xA2150000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 12.--14. " DATA_READ_TIME ,Data read time" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xA2150000+0x48)&0x01)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 8.--10. " SAMPLE_CNT_DIV ,Sample count divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMING,Timing Control Register"
|
|
bitfld.word 0x00 15. " DATA_READ_ADJ ,Data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value" "Not adjusted,Adjusted"
|
|
bitfld.word 0x00 0.--5. " STEP_CNT_DIV ,Number of samples per half pulse width" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "START,Start Register"
|
|
bitfld.word 0x00 0. " START ,Start transaction on the bus" "Not started,Started"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CLOCK_DIV,Clock Divergence Of I2C Source Clock"
|
|
bitfld.word 0x00 0.--2. " CLOCK_DIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "FIFO_STAT,FIFO Status Register"
|
|
bitfld.word 0x00 12.--15. " RD_ADDR ,Current RD address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " WR_ADDR ,Current WR address pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " FIFO_OFFSET ,FIFO offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 1. " WR_FULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RD_EMPTY ,FIFO is empty" "Not empty,Empty"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "FIFO_ADDR_CLR,FIFO Address Clear Register"
|
|
bitfld.word 0x00 0. " FIFO_ADDR_CLR ,FIFO address clear" "Not cleared,Cleared"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IO_CONFIG,IO Config Register"
|
|
bitfld.word 0x00 3. " IDLE_OE_EN ,Drive bus idle state enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SDA_IO_CONFIG ,SDA I/O configuration" "Tristate,Open-drain"
|
|
bitfld.word 0x00 0. " SCL_IO_CONFIG ,SCL I/O configuration" "Tristate,Open-drain"
|
|
if (((per.w(ad:0xA2150000+0x10)&0x02)==0x02))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "HS,High Speed Mode Register"
|
|
bitfld.word 0x00 12.--14. " HS_SAMPLE_CNT_DIV ,High speed sample counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " HS_STEP_CNT_DIV ,High speed step counter divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " MASTER_CODE ,Master code to be transmitted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.word 0x00 1. " HS_NACKERR_DET_EN ,NACKERR detection during the master code transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " HS_EN ,High-speed transaction enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "HS,High Speed Mode Register"
|
|
endif
|
|
wgroup.word 0x50++0x01
|
|
line.word 0x00 "SOFTRESET,Soft Reset Register"
|
|
bitfld.word 0x00 0. " SOFT_RESET ,Soft reset to reset I2C internal hardware circuits" "No reset,Reset"
|
|
textline " "
|
|
if (((per.w(ad:0xA2150000+0x48)&0x01)==0x01))
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,Master preparing data bit of master code,Master sending data bit of master code,Master/Slave preparing NACK bit,Master/Slave transmitting NACK bit,?..."
|
|
textline " "
|
|
else
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "DEBUGSTAT,Debug Status Register"
|
|
bitfld.word 0x00 6. " MASTER_WRITE ,Current transfer in master write direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASTER_READ ,Current transfer in master read direction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " MASTER_STATE ,Reads back the current master_state" "Idle,Master preparing start bit,Master sending start bit,Master/Slave preparing data bit,Master/Slave transmitting data bit,Master/Slave preparing ACK bit,Master/Slave transmitting ACK bit,Master preparing stop bit/repeated start bit,Master sending stop bit/repeated start bit,Master in delay,Master in FIFO wait state,,?..."
|
|
textline " "
|
|
endif
|
|
width 18.
|
|
if (((per.w(ad:0xA2150000+0x68)&0x01)==0x01))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 1. " APB_DEBUG_RD ,Generate pulsed FIFO APB RD signal" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 0. " FIFO_APB_DEBUG ,Block normal APB read access" "Not blocked,Blocked"
|
|
endif
|
|
if ((per.word(ad:0xA2150000+0x10)&0x10)==0x10)||((per.word(ad:0xA2150000+0x10)&0x40)==0x40)
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "TRANSFER_LEN_AUX,Transfer Length Register (Number Of Bytes Per Transfer)"
|
|
bitfld.word 0x00 0.--3. " TRANSFER_LEN_AUX ,Number of data bytes to be transferred in 1 transfer unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SD_MEM_CARD_CON (SD Memory Card Controller)"
|
|
tree "MSDC0"
|
|
base ad:0xA0020000
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MSDC_CFG,SD Memory Card Controller Configuration Register"
|
|
bitfld.long 0x00 24.--27. " FIFOTHD ,FIFO threshold" ",1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 23. " CLKSRC_PAT ,CLKSRC patch" "Not patched,Patched"
|
|
bitfld.long 0x00 21. " VDDPD ,VDDPD pin output" "Low,High"
|
|
bitfld.long 0x00 20. " RCDEN ,RCDEN output pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRQEN ,Data request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PINEN ,Pin interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLKF ,Controls clock frequency of serial clock on SD bus"
|
|
bitfld.long 0x00 7. " SCLKON ,Serial clock always on" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CRED ,Rising/Falling edge data" "Rising,Falling"
|
|
bitfld.long 0x00 5. " STDBY ,Standby mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CLKSRC ,Source clock of memory card select" "CLKSQ_F26M_CK,LFOSC_F26M_CK,MPLL_DIV3P5_CK,MPLL_DIV4_CK"
|
|
bitfld.long 0x00 2. " NOCRC ,CRC disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RST ,Reset of SD controller" "No reset,Reset"
|
|
bitfld.long 0x00 0. " MSDC ,Configures the controller as SD memory card mode" "Disabled,Enabled"
|
|
line.long 0x04 "MSDC_STA,SD Memory Card Controller Status Register"
|
|
rbitfld.long 0x04 15. " BUSY ,Status of the controller" "Busy,Idle"
|
|
eventfld.long 0x04 14. " FIFOCLR ,Clear FIFO" "Not cleared,Cleared"
|
|
rbitfld.long 0x04 4.--7. " FIFOCNT ,FIFO count" "0,1,2,3,4,5,6,7,8,?..."
|
|
rbitfld.long 0x04 3. " INT ,Interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " DRQ ,Data transfer required" "Not requested,Requested"
|
|
rbitfld.long 0x04 1. " BE ,FIFO in SD controller empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 0. " BF ,FIFO in SD controller full" "Not full,Full"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "MSDC_INT,SD Memory Card Controller Interrupt Register"
|
|
in
|
|
textline " "
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "MSDC_DAT,SD Memory Card Controller Data Register"
|
|
line.long 0x04 "MSDC_IOCON,SD Memory Card Controller IO Control Register"
|
|
bitfld.long 0x04 24.--25. " SAMPLEDLY ,Select the turn around delay cycle between write data end bit and CRC status for SD card" "0-T,1-T,2-T,3-T"
|
|
bitfld.long 0x04 22.--23. " FIXDLY ,Select the delay cycle after clock fix high for the host controller to SD card" "0-T,1-T,2-T,3-T"
|
|
bitfld.long 0x04 21. " SAMPON ,Data sample enable always on" "Not always on,Always on"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CRCDIS ,CRC check disable for SD read data" "No,Yes"
|
|
bitfld.long 0x04 19. " CMDSEL ,Host latch response with 1-T delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17.--18. " INTLH ,Selects latch timing for SDIO multi-block read interrupt" "0-T,1-T,2-T,3-T"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSW ,Latch data with 1-T delay or not" "With 1-T,Without 1-T"
|
|
bitfld.long 0x04 15. " CMDRE ,Latch response token at rising or falling edge of serial clock" "Rising,Falling"
|
|
bitfld.long 0x04 10. " HIGH_SPEED ,High speed mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " DMABURST ,DMA burst mode" "Single,4-beat inc,8-beat inc,?..."
|
|
bitfld.long 0x04 7. " SRCFG1 ,Output driving capability the pins DAT0, DAT1, DAT2 and DAT3" "Fast slew rate,Slow slew rate"
|
|
bitfld.long 0x04 6. " SRCFG0 ,Output driving capability the pins CMD/BS and SCLK" "Fast slew rate,Slow slew rate"
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " ODCCFG1 ,Output driving capability the pins DAT0, DAT1, DAT2 and DAT3" "4mA,8mA,12mA,16mA,?..."
|
|
bitfld.long 0x04 0.--2. " ODCCFG0 ,Output driving capability the pins CMD/BS and SCLK" "4mA,8mA,12mA,16mA,?..."
|
|
line.long 0x08 "MSDC_IOCON1,SD Memory Card Controller IO Control Register"
|
|
bitfld.long 0x08 18. " PRCFG_RST/WP ,Pull up/down register configuration for pin RST/WP" "Pull up/enabled,Pull down/enabled"
|
|
bitfld.long 0x08 16.--17. " PRVAL_RST/WP ,Pull up/down register value for pin RST/WP" "Disabled,47k,47k,23.5k"
|
|
bitfld.long 0x08 14. " PRCFG_CK ,Configures pull up/down register for pin CK" "Pull up/enabled,Pull down/enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " PRVAL_CK ,Pull up/down register value for pin CLK" "Disabled,47k,47k,23.5k"
|
|
bitfld.long 0x08 10. " PRCFG_CM ,Configures pull up/down register for the pin CM" "Pull up/enabled,Pull down/enabled"
|
|
bitfld.long 0x08 8.--9. " PRVAL_DA ,Pull up/down register value for pin CMD/BS" "Disabled,47k,47k,23.5k"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PRCFG_DA ,Configures pull up/down register for pin DAT0, DAT1, DAT2, DAT3" "Pull up enabled,Pull down enabled"
|
|
bitfld.long 0x08 4.--5. " PRVAL_DA ,Pull up/down register value for pin DAT0, DAT1, DAT2, DAT3" "Disabled,47k,47k,23.5k"
|
|
bitfld.long 0x08 2. " PRCFG_INS ,Configures pull up/down register for pin INS" "Pull up/enabled,Pull down/enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " PRVAL_INS ,Pull up/down register value for pin INS" "Disabled,47k,47k,23.5k"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "SDC_CFG,SD Memory Card Controller Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DTOC ,Data timeout counter"
|
|
bitfld.long 0x00 20.--23. " WDOD ,Write data output delay (in serial clock cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. " SDIO ,Enables SDIO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MDLEN ,Enables multiple data line" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SIEN ,Enables serial interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " BSYDLY ,Expand the time between the command end bit and end of detection period (in serial clock cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " BLKLEN ,Block length"
|
|
line.long 0x04 "SDC_CMD,SD Memory Card Controller Command Register"
|
|
bitfld.long 0x04 16. " CMDFAIL ,Wait stop command or wait data state machine idle" "Wait stop command,Wait data state machine"
|
|
bitfld.long 0x04 15. " INTC ,GO_IRQ_STATE indicator" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " STOP ,Stop transmission command occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RW ,Read/Write command occurred" "Read,Write"
|
|
bitfld.long 0x04 11.--12. " DTYPE ,Data token type for the command" "No data token,Single block,Multiple block,Stream"
|
|
bitfld.long 0x04 10. " IDRT ,Identification response time" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7.--9. " RSPTYP ,Defines response type for the command" "No response,R1,R2,R3,R4,R5,R6,R1b"
|
|
bitfld.long 0x04 6. " BREAK ,Break pending GO_IRQ_MODE command" "No break,Break"
|
|
bitfld.long 0x04 0.--5. " CMD ,SD memory card command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "SDC_ARG,SD Memory Card Controller Argument"
|
|
rgroup.long 0x2C++0x13
|
|
line.long 0x00 "SDC_STA,SD Memory Card Controller Status Register"
|
|
bitfld.long 0x00 19. " WP ,Status of write protection switch on SD memory card" "Off,On"
|
|
bitfld.long 0x00 4. " FEDATBUSY ,Status of transmission on DAT line on SD bus" "No transmission,Transmission"
|
|
bitfld.long 0x00 3. " FECMDBUSY ,Status of transmission on CMD line on SD bus" "No transmission,Transmission"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BEDATBUSY ,Status of transmission on DAT line on SD bus (backend SDC controller)" "No transmission,Transmission"
|
|
bitfld.long 0x00 1. " BECMDBUSY ,Status of transmission on CMD line on SD bus (backend SDC controller)" "No transmission,Transmission"
|
|
bitfld.long 0x00 0. " BESDCBUSY ,Backend controller's SDC busy state" "Idle,Busy"
|
|
line.long 0x04 "SDC_RESP0,SD Memory Card Controller Response Register 0"
|
|
line.long 0x08 "SDC_RESP1,SD Memory Card Controller Response Register 1"
|
|
line.long 0x0C "SDC_RESP2,SD Memory Card Controller Response Register 2"
|
|
line.long 0x10 "SDC_RESP3,SD Memory Card Controller Response Register 3"
|
|
textline " "
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SDC_CMDSTA,SD Memory Card Controller Command Status Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "SDC_DATSTA,SD Memory Card Controller Data Status Register"
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in
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hgroup.long 0x48++0x03
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hide.long 0x00 "SDC_CSTA,SD Memory Card Status Register"
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in
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textline " "
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group.long 0x4C++0x0B
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line.long 0x00 "SDC_IRQMASK0,SD Memory Card IRQ Mask Register 0"
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bitfld.long 0x00 31. " IRQMASK ,IRQMASK_31" "0,1"
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bitfld.long 0x00 30. ",IRQMASK_30" "0,1"
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bitfld.long 0x00 29. ",IRQMASK_29" "0,1"
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bitfld.long 0x00 28. ",IRQMASK_28" "0,1"
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bitfld.long 0x00 27. ",IRQMASK_27" "0,1"
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bitfld.long 0x00 26. ",IRQMASK_26" "0,1"
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bitfld.long 0x00 25. ",IRQMASK_25" "0,1"
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bitfld.long 0x00 24. ",IRQMASK_24" "0,1"
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bitfld.long 0x00 23. ",IRQMASK_23" "0,1"
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bitfld.long 0x00 22. ",IRQMASK_22" "0,1"
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bitfld.long 0x00 21. ",IRQMASK_21" "0,1"
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bitfld.long 0x00 20. ",IRQMASK_20" "0,1"
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bitfld.long 0x00 19. ",IRQMASK_19" "0,1"
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bitfld.long 0x00 18. ",IRQMASK_18" "0,1"
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bitfld.long 0x00 17. ",IRQMASK_17" "0,1"
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bitfld.long 0x00 16. ",IRQMASK_16" "0,1"
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bitfld.long 0x00 15. ",IRQMASK_15" "0,1"
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bitfld.long 0x00 14. ",IRQMASK_14" "0,1"
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bitfld.long 0x00 13. ",IRQMASK_13" "0,1"
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bitfld.long 0x00 12. ",IRQMASK_12" "0,1"
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bitfld.long 0x00 11. ",IRQMASK_11" "0,1"
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bitfld.long 0x00 10. ",IRQMASK_10" "0,1"
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bitfld.long 0x00 9. ",IRQMASK_9" "0,1"
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bitfld.long 0x00 8. ",IRQMASK_8" "0,1"
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bitfld.long 0x00 7. ",IRQMASK_7" "0,1"
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bitfld.long 0x00 6. ",IRQMASK_6" "0,1"
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bitfld.long 0x00 5. ",IRQMASK_5" "0,1"
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bitfld.long 0x00 4. ",IRQMASK_4" "0,1"
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bitfld.long 0x00 3. ",IRQMASK_3" "0,1"
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bitfld.long 0x00 2. ",IRQMASK_2" "0,1"
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bitfld.long 0x00 1. ",IRQMASK_1" "0,1"
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bitfld.long 0x00 0. ",IRQMASK_0" "0,1"
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line.long 0x04 "SDC_IRQMASK1,SD Memory Card IRQ Mask Register 1"
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bitfld.long 0x04 31. " IRQMASK ,IRQMASK_63" "0,1"
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bitfld.long 0x04 30. ",IRQMASK_62" "0,1"
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bitfld.long 0x04 29. ",IRQMASK_61" "0,1"
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bitfld.long 0x04 28. ",IRQMASK_60" "0,1"
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bitfld.long 0x04 27. ",IRQMASK_59" "0,1"
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bitfld.long 0x04 26. ",IRQMASK_58" "0,1"
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bitfld.long 0x04 25. ",IRQMASK_57" "0,1"
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bitfld.long 0x04 24. ",IRQMASK_56" "0,1"
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bitfld.long 0x04 23. ",IRQMASK_55" "0,1"
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bitfld.long 0x04 22. ",IRQMASK_54" "0,1"
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bitfld.long 0x04 21. ",IRQMASK_53" "0,1"
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bitfld.long 0x04 20. ",IRQMASK_52" "0,1"
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bitfld.long 0x04 19. ",IRQMASK_51" "0,1"
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bitfld.long 0x04 18. ",IRQMASK_50" "0,1"
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bitfld.long 0x04 17. ",IRQMASK_49" "0,1"
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bitfld.long 0x04 16. ",IRQMASK_48" "0,1"
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bitfld.long 0x04 15. ",IRQMASK_47" "0,1"
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bitfld.long 0x04 14. ",IRQMASK_46" "0,1"
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bitfld.long 0x04 13. ",IRQMASK_45" "0,1"
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bitfld.long 0x04 12. ",IRQMASK_44" "0,1"
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bitfld.long 0x04 11. ",IRQMASK_43" "0,1"
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bitfld.long 0x04 10. ",IRQMASK_42" "0,1"
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bitfld.long 0x04 9. ",IRQMASK_41" "0,1"
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bitfld.long 0x04 8. ",IRQMASK_40" "0,1"
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bitfld.long 0x04 7. ",IRQMASK_39" "0,1"
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bitfld.long 0x04 6. ",IRQMASK_38" "0,1"
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bitfld.long 0x04 5. ",IRQMASK_37" "0,1"
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bitfld.long 0x04 4. ",IRQMASK_36" "0,1"
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bitfld.long 0x04 3. ",IRQMASK_35" "0,1"
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bitfld.long 0x04 2. ",IRQMASK_34" "0,1"
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bitfld.long 0x04 1. ",IRQMASK_33" "0,1"
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bitfld.long 0x04 0. ",IRQMASK_32" "0,1"
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textline " "
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line.long 0x08 "SDIO_CFG,SDIO Configuration Register"
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bitfld.long 0x08 5. " DISSEL ,Data block interrupt source select" "Detected,Ignored"
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bitfld.long 0x08 3. " INTCSEL ,Interrupt control select" "DAT1 low,DAT3/DAT2/DAT1/DAT0 1101"
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bitfld.long 0x08 2. " DSBSEL ,Data block start bit" "Data line 0,Received when data line [0..3] = low"
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bitfld.long 0x08 0. " INTEN ,Interrupt for SDIO enable" "Disabled,Enabled"
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textline " "
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rgroup.long 0x58++0x03
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line.long 0x00 "SDIO_STA,SDIO Status Register"
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bitfld.long 0x00 0. " IRQ ,SDIO interrupt on data line exist status" "Not exist,Exist"
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if (((per.l(ad:0xA0020000+0x80)&0x40)==0x40))
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group.long 0x80++0x03
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line.long 0x00 "CLK_RED,CLK Latch Configuration Register"
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bitfld.long 0x00 29. " CMD_RED ,Internal clock Rising/Falling edge to latch data" "Rising,Falling"
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bitfld.long 0x00 13. " DAT_RED ,Internal clock Rising/Falling edge to latch data" "Rising,Falling"
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bitfld.long 0x00 6. " CLK_LATCH ,Clock to latch data from card" "Internal feedback clock,Internal clock"
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else
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group.long 0x80++0x03
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line.long 0x00 "CLK_RED,CLK Latch Configuration Register"
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bitfld.long 0x00 7. " CLKPAD_RED ,Internal feedback clock Rising/Falling edge to latch data/response" "Rising,Falling"
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bitfld.long 0x00 6. " CLK_LATCH ,Clock to latch data from card" "Internal feedback clock,Internal clock"
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endif
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group.long 0x98++0x03
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line.long 0x00 "DAT_CHECKSUM,MSDC Rx Data Check Sum Register"
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width 0x0B
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tree.end
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tree "MSDC1"
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base ad:0xA0030000
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width 14.
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group.long 0x00++0x07
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line.long 0x00 "MSDC_CFG,SD Memory Card Controller Configuration Register"
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bitfld.long 0x00 24.--27. " FIFOTHD ,FIFO threshold" ",1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x00 23. " CLKSRC_PAT ,CLKSRC patch" "Not patched,Patched"
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bitfld.long 0x00 21. " VDDPD ,VDDPD pin output" "Low,High"
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bitfld.long 0x00 20. " RCDEN ,RCDEN output pin state" "Low,High"
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textline " "
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bitfld.long 0x00 19. " DIRQEN ,Data request interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " PINEN ,Pin interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " DMAEN ,DMA enabled" "Disabled,Enabled"
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bitfld.long 0x00 16. " INTEN ,Interrupt enable" "Disabled,Enabled"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " SCLKF ,Controls clock frequency of serial clock on SD bus"
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bitfld.long 0x00 7. " SCLKON ,Serial clock always on" "Disabled,Enabled"
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bitfld.long 0x00 6. " CRED ,Rising/Falling edge data" "Rising,Falling"
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bitfld.long 0x00 5. " STDBY ,Standby mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3.--4. " CLKSRC ,Source clock of memory card select" "CLKSQ_F26M_CK,LFOSC_F26M_CK,MPLL_DIV3P5_CK,MPLL_DIV4_CK"
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bitfld.long 0x00 2. " NOCRC ,CRC disable" "No,Yes"
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bitfld.long 0x00 1. " RST ,Reset of SD controller" "No reset,Reset"
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bitfld.long 0x00 0. " MSDC ,Configures the controller as SD memory card mode" "Disabled,Enabled"
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line.long 0x04 "MSDC_STA,SD Memory Card Controller Status Register"
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rbitfld.long 0x04 15. " BUSY ,Status of the controller" "Busy,Idle"
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eventfld.long 0x04 14. " FIFOCLR ,Clear FIFO" "Not cleared,Cleared"
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rbitfld.long 0x04 4.--7. " FIFOCNT ,FIFO count" "0,1,2,3,4,5,6,7,8,?..."
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rbitfld.long 0x04 3. " INT ,Interrupt request" "Not requested,Requested"
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textline " "
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rbitfld.long 0x04 2. " DRQ ,Data transfer required" "Not requested,Requested"
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rbitfld.long 0x04 1. " BE ,FIFO in SD controller empty" "Not empty,Empty"
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rbitfld.long 0x04 0. " BF ,FIFO in SD controller full" "Not full,Full"
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hgroup.long 0x08++0x03
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hide.long 0x00 "MSDC_INT,SD Memory Card Controller Interrupt Register"
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in
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textline " "
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group.long 0x10++0x0B
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line.long 0x00 "MSDC_DAT,SD Memory Card Controller Data Register"
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line.long 0x04 "MSDC_IOCON,SD Memory Card Controller IO Control Register"
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bitfld.long 0x04 24.--25. " SAMPLEDLY ,Select the turn around delay cycle between write data end bit and CRC status for SD card" "0-T,1-T,2-T,3-T"
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bitfld.long 0x04 22.--23. " FIXDLY ,Select the delay cycle after clock fix high for the host controller to SD card" "0-T,1-T,2-T,3-T"
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bitfld.long 0x04 21. " SAMPON ,Data sample enable always on" "Not always on,Always on"
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textline " "
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bitfld.long 0x04 20. " CRCDIS ,CRC check disable for SD read data" "No,Yes"
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bitfld.long 0x04 19. " CMDSEL ,Host latch response with 1-T delay enable" "Disabled,Enabled"
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bitfld.long 0x04 17.--18. " INTLH ,Selects latch timing for SDIO multi-block read interrupt" "0-T,1-T,2-T,3-T"
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textline " "
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bitfld.long 0x04 16. " DSW ,Latch data with 1-T delay or not" "With 1-T,Without 1-T"
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bitfld.long 0x04 15. " CMDRE ,Latch response token at rising or falling edge of serial clock" "Rising,Falling"
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bitfld.long 0x04 10. " HIGH_SPEED ,High speed mode enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 8.--9. " DMABURST ,DMA burst mode" "Single,4-beat inc,8-beat inc,?..."
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bitfld.long 0x04 7. " SRCFG1 ,Output driving capability the pins DAT0, DAT1, DAT2 and DAT3" "Fast slew rate,Slow slew rate"
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bitfld.long 0x04 6. " SRCFG0 ,Output driving capability the pins CMD/BS and SCLK" "Fast slew rate,Slow slew rate"
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textline " "
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bitfld.long 0x04 3.--5. " ODCCFG1 ,Output driving capability the pins DAT0, DAT1, DAT2 and DAT3" "4mA,8mA,12mA,16mA,?..."
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bitfld.long 0x04 0.--2. " ODCCFG0 ,Output driving capability the pins CMD/BS and SCLK" "4mA,8mA,12mA,16mA,?..."
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line.long 0x08 "MSDC_IOCON1,SD Memory Card Controller IO Control Register"
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bitfld.long 0x08 18. " PRCFG_RST/WP ,Pull up/down register configuration for pin RST/WP" "Pull up/enabled,Pull down/enabled"
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bitfld.long 0x08 16.--17. " PRVAL_RST/WP ,Pull up/down register value for pin RST/WP" "Disabled,47k,47k,23.5k"
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bitfld.long 0x08 14. " PRCFG_CK ,Configures pull up/down register for pin CK" "Pull up/enabled,Pull down/enabled"
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textline " "
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bitfld.long 0x08 12.--13. " PRVAL_CK ,Pull up/down register value for pin CLK" "Disabled,47k,47k,23.5k"
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bitfld.long 0x08 10. " PRCFG_CM ,Configures pull up/down register for the pin CM" "Pull up/enabled,Pull down/enabled"
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bitfld.long 0x08 8.--9. " PRVAL_DA ,Pull up/down register value for pin CMD/BS" "Disabled,47k,47k,23.5k"
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textline " "
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bitfld.long 0x08 6. " PRCFG_DA ,Configures pull up/down register for pin DAT0, DAT1, DAT2, DAT3" "Pull up enabled,Pull down enabled"
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bitfld.long 0x08 4.--5. " PRVAL_DA ,Pull up/down register value for pin DAT0, DAT1, DAT2, DAT3" "Disabled,47k,47k,23.5k"
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bitfld.long 0x08 2. " PRCFG_INS ,Configures pull up/down register for pin INS" "Pull up/enabled,Pull down/enabled"
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textline " "
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bitfld.long 0x08 0.--1. " PRVAL_INS ,Pull up/down register value for pin INS" "Disabled,47k,47k,23.5k"
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group.long 0x20++0x0B
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line.long 0x00 "SDC_CFG,SD Memory Card Controller Configuration Register"
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hexmask.long.byte 0x00 24.--31. 1. " DTOC ,Data timeout counter"
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bitfld.long 0x00 20.--23. " WDOD ,Write data output delay (in serial clock cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. " SDIO ,Enables SDIO" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 17. " MDLEN ,Enables multiple data line" "Disabled,Enabled"
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bitfld.long 0x00 16. " SIEN ,Enables serial interface" "Disabled,Enabled"
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bitfld.long 0x00 12.--15. " BSYDLY ,Expand the time between the command end bit and end of detection period (in serial clock cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 0.--11. 1. " BLKLEN ,Block length"
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line.long 0x04 "SDC_CMD,SD Memory Card Controller Command Register"
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bitfld.long 0x04 16. " CMDFAIL ,Wait stop command or wait data state machine idle" "Wait stop command,Wait data state machine"
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bitfld.long 0x04 15. " INTC ,GO_IRQ_STATE indicator" "Not occurred,Occurred"
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bitfld.long 0x04 14. " STOP ,Stop transmission command occurred" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 13. " RW ,Read/Write command occurred" "Read,Write"
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bitfld.long 0x04 11.--12. " DTYPE ,Data token type for the command" "No data token,Single block,Multiple block,Stream"
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bitfld.long 0x04 10. " IDRT ,Identification response time" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 7.--9. " RSPTYP ,Defines response type for the command" "No response,R1,R2,R3,R4,R5,R6,R1b"
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bitfld.long 0x04 6. " BREAK ,Break pending GO_IRQ_MODE command" "No break,Break"
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bitfld.long 0x04 0.--5. " CMD ,SD memory card command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x08 "SDC_ARG,SD Memory Card Controller Argument"
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rgroup.long 0x2C++0x13
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line.long 0x00 "SDC_STA,SD Memory Card Controller Status Register"
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bitfld.long 0x00 19. " WP ,Status of write protection switch on SD memory card" "Off,On"
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bitfld.long 0x00 4. " FEDATBUSY ,Status of transmission on DAT line on SD bus" "No transmission,Transmission"
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bitfld.long 0x00 3. " FECMDBUSY ,Status of transmission on CMD line on SD bus" "No transmission,Transmission"
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textline " "
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bitfld.long 0x00 2. " BEDATBUSY ,Status of transmission on DAT line on SD bus (backend SDC controller)" "No transmission,Transmission"
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bitfld.long 0x00 1. " BECMDBUSY ,Status of transmission on CMD line on SD bus (backend SDC controller)" "No transmission,Transmission"
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bitfld.long 0x00 0. " BESDCBUSY ,Backend controller's SDC busy state" "Idle,Busy"
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line.long 0x04 "SDC_RESP0,SD Memory Card Controller Response Register 0"
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line.long 0x08 "SDC_RESP1,SD Memory Card Controller Response Register 1"
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line.long 0x0C "SDC_RESP2,SD Memory Card Controller Response Register 2"
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line.long 0x10 "SDC_RESP3,SD Memory Card Controller Response Register 3"
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textline " "
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hgroup.long 0x40++0x03
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hide.long 0x00 "SDC_CMDSTA,SD Memory Card Controller Command Status Register"
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in
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hgroup.long 0x44++0x03
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hide.long 0x00 "SDC_DATSTA,SD Memory Card Controller Data Status Register"
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in
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hgroup.long 0x48++0x03
|
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hide.long 0x00 "SDC_CSTA,SD Memory Card Status Register"
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in
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textline " "
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group.long 0x4C++0x0B
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line.long 0x00 "SDC_IRQMASK0,SD Memory Card IRQ Mask Register 0"
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bitfld.long 0x00 31. " IRQMASK ,IRQMASK_31" "0,1"
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bitfld.long 0x00 30. ",IRQMASK_30" "0,1"
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bitfld.long 0x00 29. ",IRQMASK_29" "0,1"
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bitfld.long 0x00 28. ",IRQMASK_28" "0,1"
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bitfld.long 0x00 27. ",IRQMASK_27" "0,1"
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bitfld.long 0x00 26. ",IRQMASK_26" "0,1"
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bitfld.long 0x00 25. ",IRQMASK_25" "0,1"
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bitfld.long 0x00 24. ",IRQMASK_24" "0,1"
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bitfld.long 0x00 23. ",IRQMASK_23" "0,1"
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bitfld.long 0x00 22. ",IRQMASK_22" "0,1"
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bitfld.long 0x00 21. ",IRQMASK_21" "0,1"
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bitfld.long 0x00 20. ",IRQMASK_20" "0,1"
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bitfld.long 0x00 19. ",IRQMASK_19" "0,1"
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bitfld.long 0x00 18. ",IRQMASK_18" "0,1"
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bitfld.long 0x00 17. ",IRQMASK_17" "0,1"
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bitfld.long 0x00 16. ",IRQMASK_16" "0,1"
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bitfld.long 0x00 15. ",IRQMASK_15" "0,1"
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bitfld.long 0x00 14. ",IRQMASK_14" "0,1"
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bitfld.long 0x00 13. ",IRQMASK_13" "0,1"
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bitfld.long 0x00 12. ",IRQMASK_12" "0,1"
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bitfld.long 0x00 11. ",IRQMASK_11" "0,1"
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bitfld.long 0x00 10. ",IRQMASK_10" "0,1"
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bitfld.long 0x00 9. ",IRQMASK_9" "0,1"
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bitfld.long 0x00 8. ",IRQMASK_8" "0,1"
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bitfld.long 0x00 7. ",IRQMASK_7" "0,1"
|
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bitfld.long 0x00 6. ",IRQMASK_6" "0,1"
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bitfld.long 0x00 5. ",IRQMASK_5" "0,1"
|
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bitfld.long 0x00 4. ",IRQMASK_4" "0,1"
|
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bitfld.long 0x00 3. ",IRQMASK_3" "0,1"
|
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bitfld.long 0x00 2. ",IRQMASK_2" "0,1"
|
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bitfld.long 0x00 1. ",IRQMASK_1" "0,1"
|
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bitfld.long 0x00 0. ",IRQMASK_0" "0,1"
|
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line.long 0x04 "SDC_IRQMASK1,SD Memory Card IRQ Mask Register 1"
|
|
bitfld.long 0x04 31. " IRQMASK ,IRQMASK_63" "0,1"
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bitfld.long 0x04 30. ",IRQMASK_62" "0,1"
|
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bitfld.long 0x04 29. ",IRQMASK_61" "0,1"
|
|
bitfld.long 0x04 28. ",IRQMASK_60" "0,1"
|
|
bitfld.long 0x04 27. ",IRQMASK_59" "0,1"
|
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bitfld.long 0x04 26. ",IRQMASK_58" "0,1"
|
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bitfld.long 0x04 25. ",IRQMASK_57" "0,1"
|
|
bitfld.long 0x04 24. ",IRQMASK_56" "0,1"
|
|
bitfld.long 0x04 23. ",IRQMASK_55" "0,1"
|
|
bitfld.long 0x04 22. ",IRQMASK_54" "0,1"
|
|
bitfld.long 0x04 21. ",IRQMASK_53" "0,1"
|
|
bitfld.long 0x04 20. ",IRQMASK_52" "0,1"
|
|
bitfld.long 0x04 19. ",IRQMASK_51" "0,1"
|
|
bitfld.long 0x04 18. ",IRQMASK_50" "0,1"
|
|
bitfld.long 0x04 17. ",IRQMASK_49" "0,1"
|
|
bitfld.long 0x04 16. ",IRQMASK_48" "0,1"
|
|
bitfld.long 0x04 15. ",IRQMASK_47" "0,1"
|
|
bitfld.long 0x04 14. ",IRQMASK_46" "0,1"
|
|
bitfld.long 0x04 13. ",IRQMASK_45" "0,1"
|
|
bitfld.long 0x04 12. ",IRQMASK_44" "0,1"
|
|
bitfld.long 0x04 11. ",IRQMASK_43" "0,1"
|
|
bitfld.long 0x04 10. ",IRQMASK_42" "0,1"
|
|
bitfld.long 0x04 9. ",IRQMASK_41" "0,1"
|
|
bitfld.long 0x04 8. ",IRQMASK_40" "0,1"
|
|
bitfld.long 0x04 7. ",IRQMASK_39" "0,1"
|
|
bitfld.long 0x04 6. ",IRQMASK_38" "0,1"
|
|
bitfld.long 0x04 5. ",IRQMASK_37" "0,1"
|
|
bitfld.long 0x04 4. ",IRQMASK_36" "0,1"
|
|
bitfld.long 0x04 3. ",IRQMASK_35" "0,1"
|
|
bitfld.long 0x04 2. ",IRQMASK_34" "0,1"
|
|
bitfld.long 0x04 1. ",IRQMASK_33" "0,1"
|
|
bitfld.long 0x04 0. ",IRQMASK_32" "0,1"
|
|
textline " "
|
|
line.long 0x08 "SDIO_CFG,SDIO Configuration Register"
|
|
bitfld.long 0x08 5. " DISSEL ,Data block interrupt source select" "Detected,Ignored"
|
|
bitfld.long 0x08 3. " INTCSEL ,Interrupt control select" "DAT1 low,DAT3/DAT2/DAT1/DAT0 1101"
|
|
bitfld.long 0x08 2. " DSBSEL ,Data block start bit" "Data line 0,Received when data line [0..3] = low"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt for SDIO enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "SDIO_STA,SDIO Status Register"
|
|
bitfld.long 0x00 0. " IRQ ,SDIO interrupt on data line exist status" "Not exist,Exist"
|
|
if (((per.l(ad:0xA0030000+0x80)&0x40)==0x40))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CLK_RED,CLK Latch Configuration Register"
|
|
bitfld.long 0x00 29. " CMD_RED ,Internal clock Rising/Falling edge to latch data" "Rising,Falling"
|
|
bitfld.long 0x00 13. " DAT_RED ,Internal clock Rising/Falling edge to latch data" "Rising,Falling"
|
|
bitfld.long 0x00 6. " CLK_LATCH ,Clock to latch data from card" "Internal feedback clock,Internal clock"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CLK_RED,CLK Latch Configuration Register"
|
|
bitfld.long 0x00 7. " CLKPAD_RED ,Internal feedback clock Rising/Falling edge to latch data/response" "Rising,Falling"
|
|
bitfld.long 0x00 6. " CLK_LATCH ,Clock to latch data from card" "Internal feedback clock,Internal clock"
|
|
endif
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "DAT_CHECKSUM,MSDC Rx Data Check Sum Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USB2.0 High-Speed Device Controller"
|
|
base ad:0xA0900000
|
|
width 12.
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FADDR,Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 0x01 " FUNCTION_ADDRESS ,Function address"
|
|
else
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "FADDR,Function Address Register"
|
|
endif
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "POWER_PERI,Power Management Register"
|
|
bitfld.byte 0x00 7. " ISOUPDATE ,ISO update" "Not updated,Updated"
|
|
bitfld.byte 0x00 6. " SOFTCONN ,Soft connect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " HSENAB ,High speed mode enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4. " HSMODE ,High speed mode successfully negotiated during USB reset" "Not successfully,Successfully"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " RESET ,Reset signal" "No reset,Reset"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signalling from function suspend mode" "Not resumed,Resumed"
|
|
rbitfld.byte 0x00 1. " SUSPENDMODE ,Suspend mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ENABLESUSPENDM ,SUSPENDM output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "POWER_PERI,Power Management Register"
|
|
bitfld.byte 0x00 5. " HSENAB ,High speed mode enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4. " HSMODE ,High speed mode successfully negotiated during USB reset" "Not successfully,Successfully"
|
|
bitfld.byte 0x00 3. " RESET ,Reset signal" "No reset,Reset"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signalling from function suspend mode" "Not resumed,Resumed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SUSPENDMODE ,Suspend mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ENABLESUSPENDM ,SUSPENDM output enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x02++0x07
|
|
line.word 0x00 "INTRTX,Tx Interrupt Status Register"
|
|
eventfld.word 0x00 4. " EP4_TX ,T4 endpoint N interrupt event" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 3. " EP3_TX ,T3 endpoint N interrupt event" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " EP2_TX ,T2 endpoint N interrupt event" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " EP1_TX ,T1 endpoint N interrupt event" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 0. " EP0 ,Endpoint 0 interrupt event" "No interrupt,Interrupt"
|
|
line.word 0x02 "INTRRX,Rx Interrupt Status Register"
|
|
eventfld.word 0x02 2. " EP2_RX ,R2 endpoint N interrupt event" "No interrupt,Interrupt"
|
|
eventfld.word 0x02 1. " EP1_RX ,R1 endpoint N interrupt event" "No interrupt,Interrupt"
|
|
line.word 0x04 "INTRTXE,Tx Interrupt Enable Register"
|
|
bitfld.word 0x04 4. " EP4_TXE ,Tx endpoint N interrupt event enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 3. " EP3_TXE ,Tx endpoint N interrupt event enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " EP2_TXE ,Tx endpoint N interrupt event enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 1. " EP1_TXE ,Tx endpoint N interrupt event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 0. " EP0 ,Endpoint 0 interrupt event enable" "Disabled,Enabled"
|
|
line.word 0x06 "INTRRXE,Rx Interrupt Enable Register"
|
|
eventfld.word 0x06 2. " EP2_RXE ,R2 endpoint N interrupt event enable" "Disabled,Enabled"
|
|
eventfld.word 0x06 1. " EP1_RXE ,R1 endpoint N interrupt event enable" "Disabled,Enabled"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x80)==0x00)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "INTRUSB,Common USB Interrupt Register"
|
|
eventfld.byte 0x00 7. " VBUSERROR ,VBus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " SESSREQ ,Session request signal detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DISCON ,Device disconnected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " CONN ,Device connected interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " SOF ,New frame starts interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " RESET_BABLE ,Reset signalling detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " RESUME ,Resume signalling detected interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "INTRUSB,Common USB Interrupt Register"
|
|
eventfld.byte 0x00 5. " DISCON ,Device disconnected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " CONN ,Device connected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " SOF ,New frame starts interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " RESET_BABLE ,Reset signalling detected interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " RESUME ,Resume signalling detected interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
else
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x80)==0x00)
|
|
group.byte 0x0A++0x01
|
|
line.byte 0x00 "INTRUSB,Common USB Interrupt Register"
|
|
eventfld.byte 0x00 7. " VBUSERROR ,VBus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " SESSREQ ,Session request signal detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DISCON ,Device disconnected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " SOF ,New frame starts interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 2. " RESET_BABLE ,Reset signalling detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " RESUME ,Resume signalling detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " SUSPEND ,Suspend signalling detected interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x01 "INTRUSBE,Common USB Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " VBUSERROR_E ,VBus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " SESSREQ_E ,Session request signal detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " DISCON_E ,Device disconnected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " CONN_E ,Device connected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " SOF_E ,New frame starts interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " RESET_BABLE_E ,Reset signalling detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " RESUME_E ,Resume signalling detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SUSPEND_E ,Suspend signalling detected interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0A++0x01
|
|
line.byte 0x00 "INTRUSB,Common USB Interrupt Register"
|
|
eventfld.byte 0x00 5. " DISCON ,Device disconnected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " SOF ,New frame starts interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " RESET_BABLE ,Reset signalling detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " RESUME ,Resume signalling detected interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 0. " SUSPEND ,Suspend signalling detected interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x01 "INTRUSBE,Common USB Interrupt Enable Register"
|
|
bitfld.byte 0x01 5. " DISCON_E ,Device disconnected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " SOF_E ,New frame starts interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " RESET_BABLE_E ,Reset signalling detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " RESUME_E ,Resume signalling detected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " SUSPEND_E ,Suspend signalling detected interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "FRAME,Frame Number Register"
|
|
hexmask.word 0x00 0.--10. 1. " FRAME_NUMBER ,Received frame number"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "INDEX,Endpoint Selection Index Register"
|
|
bitfld.byte 0x00 0.--3. " SELECTED_ENDPOINT ,Accessed endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
if ((per.byte(ad:0xA0900000+0x0F)&0x30)==0x10)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "TESTMODE,Test Mode Enable Register"
|
|
bitfld.byte 0x00 7. " FORCE_HOST ,Force host mode" "Not forced,Forced"
|
|
bitfld.byte 0x00 6. " FIFO_ACCESS ,FIFO access" "No access,Access"
|
|
bitfld.byte 0x00 4.--5. " FORCE_FS/HS ,Force speed mode" "Low speed,High speed,Full speed,?..."
|
|
bitfld.byte 0x00 3. " TEST_PACKET ,Test_packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEST_K ,Test_k mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TEST_J ,Test_j mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEST_SE0_NAK ,Test_SE0_nak mode enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "TESTMODE,Test Mode Enable Register"
|
|
bitfld.byte 0x00 7. " FORCE_HOST ,Force host mode" "Not forced,Forced"
|
|
bitfld.byte 0x00 6. " FIFO_ACCESS ,FIFO access" "No access,Access"
|
|
bitfld.byte 0x00 4.--5. " FORCE_FS/HS ,Force speed mode" "Low speed,High speed,Full speed,?..."
|
|
endif
|
|
else
|
|
if ((per.byte(ad:0xA0900000+0x0F)&0x30)==0x10)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "TESTMODE,Test Mode Enable Register"
|
|
bitfld.byte 0x00 6. " FIFO_ACCESS ,FIFO access" "No access,Access"
|
|
bitfld.byte 0x00 4.--5. " FORCE_FS/HS ,Force speed mode" "Low speed,High speed,Full speed,?..."
|
|
bitfld.byte 0x00 3. " TEST_PACKET ,Test_packet mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEST_K ,Test_k mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TEST_J ,Test_j mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEST_SE0_NAK ,Test_SE0_nak mode enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "TESTMODE,Test Mode Enable Register"
|
|
bitfld.byte 0x00 6. " FIFO_ACCESS ,FIFO access" "No access,Access"
|
|
bitfld.byte 0x00 4.--5. " FORCE_FS/HS ,Force speed mode" "Low speed,High speed,Full speed,?..."
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TXMAP,TXMAP Register"
|
|
bitfld.word 0x00 11.--12. " M_1 ,Maximum payload size for indexed TX endpoint" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "TXCSR_PERI,Tx CSR Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,TxPktRdy autoset when data of the maximum packet size is loaded into the TxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Enable Tx endpoint for isochronous transfer" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,Enable the DMA request for TX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SETTXPKTRDY_TWICE ,TxPktRdy had been set while it is 1'b1 already" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete data transmitted" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Issue a STALL handshake to an IN token" "Not issued,Issued"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush the latest packet from the endpoint TxFIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,In token received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded loaded into FIFO" "Not loaded,Loaded"
|
|
else
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "TXCSR_PERI,Tx CSR Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,TxPktRdy autoset when data of the maximum packet size is loaded into the TxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,Enable the DMA request for TX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " SETTXPKTRDY_TWICE ,TxPktRdy had been set while it is 1'b1 already" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete data transmitted" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
bitfld.word 0x00 5. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SENDSTALL ,Issue a STALL handshake to an IN token" "Not issued,Issued"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush the latest packet from the endpoint TxFIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,In token received" "Not received,Received"
|
|
rbitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded loaded into FIFO" "Not loaded,Loaded"
|
|
endif
|
|
group.word 0x14++0x03
|
|
line.word 0x00 "RXMAP,RXMAP Register"
|
|
bitfld.word 0x00 11.--12. " M_1 ,Maximum payload size for indexed RX endpoint" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x02 "RXCSR_PERI,RX CSR Register"
|
|
bitfld.word 0x02 15. " AUTOCLEAR ,RxPktRdy autoclear when a packet of RxMaxP bytes has been unloaded from the RxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " ISO ,Enable Rx endpoint for isochronous transfer" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " DMAREQEN ,Enable the DMA request for RX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " DISNYET_PIDERR ,Disable the sending of NYET handshakes" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x02 11. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x02 9. " KEEPERRSTATUS ,Keep isochronous error, PIDERROR, INCOMPRX and DATAERROR" "Not kept,Kept"
|
|
bitfld.word 0x02 8. " INCOMPRX ,Incomplete data received error" "No error,Error"
|
|
bitfld.word 0x02 7. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x02 6. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x02 5. " SENDSTALL ,Issue a STALL handshake" "Not issued,Issued"
|
|
bitfld.word 0x02 4. " FLUSHFIFO ,Flush the next packet to be read from the endpoint RxFIFO" "Not flushed,Flushed"
|
|
rbitfld.word 0x02 3. " DATAERR ,Data packet CRC/bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x02 2. " OVERRUN ,OUT packet cannot be loaded into RxFIFO" "Not occurred,Occurred"
|
|
rbitfld.word 0x02 1. " FIFOFULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x02 0. " RXPKTRDY ,Data packet has been received" "Not received,Received"
|
|
if (((per.word(ad:0xA0900000+0x16)&0x01)==0x01))
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "RXCOUNT,Rx Count Register"
|
|
hexmask.word 0x00 0.--13. 1. " RXCOUNT ,Number of received data bytes in the packet in RxFIFO"
|
|
else
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "RXCOUNT,Rx Count Register"
|
|
endif
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "TXTYPE,TxType Register"
|
|
bitfld.byte 0x00 6.--7. " TX_SPEED ,Tx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " TX_PROTOCOL ,Tx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TX_TARGET_EP_NUMBER ,Tx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "TXINTERVAL,TxInterval Register"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "TXINTERVAL,TxInterval Register"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "RXTYPE,RxType Register"
|
|
bitfld.byte 0x00 6.--7. " RXSPEED ,Rx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " RX_PROTOCOL ,Rx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " RX_TARGET_EP_NUMBER ,Rx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "RXINTERVAL,RxInterval Register"
|
|
else
|
|
hgroup.byte 0x1D++0x00
|
|
hide.byte 0x00 "RXINTERVAL,RxInterval Register"
|
|
endif
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "FIFOSIZE,Configured FIFO Size Register"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSIZE ,RxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSIZE ,TxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 8.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FIFO0,USB Endpoint 0 FIFO Register"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FIFO1,USB Endpoint 1 FIFO Register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO2,USB Endpoint 2 FIFO Register"
|
|
textline " "
|
|
if (((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)&&((per.byte(ad:0xA0900000+0x60)&0x80)==0x80))
|
|
rgroup.byte 0x60++0x01
|
|
line.byte 0x00 "DEVCTL,Device Control Register"
|
|
bitfld.byte 0x00 7. " B_DEVICE ,USB2.0 device select" "A device,B device"
|
|
bitfld.byte 0x00 6. " FSDEV ,Device speed connected to the port" "High speed,Full speed"
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed device detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current Vbus level" "Below SessionEnd,Above SesionEnd,Above AValid,About VBusValid"
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB2.0 controller acting as a host" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Init host negotiation" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session" "Disabled,Enabled"
|
|
elif (((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)&&((per.byte(ad:0xA0900000+0x60)&0x80)==0x00))
|
|
rgroup.byte 0x60++0x01
|
|
line.byte 0x00 "DEVCTL,Device Control Register"
|
|
bitfld.byte 0x00 7. " B_DEVICE ,USB2.0 device select" "A device,B device"
|
|
bitfld.byte 0x00 6. " FSDEV ,Device speed connected to the port" "High speed,Full speed"
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed device detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current Vbus level" "Below SessionEnd,Above SesionEnd,Above AValid,About VBusValid"
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB2.0 controller acting as a host" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SESSION ,Session" "Disabled,Enabled"
|
|
elif (((per.byte(ad:0xA0900000+0x60)&0x04)==0x00)&&((per.byte(ad:0xA0900000+0x60)&0x80)==0x00))
|
|
rgroup.byte 0x60++0x01
|
|
line.byte 0x00 "DEVCTL,Device Control Register"
|
|
bitfld.byte 0x00 7. " B_DEVICE ,USB2.0 device select" "A device,B device"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current Vbus level" "Below SessionEnd,Above SesionEnd,Above AValid,About VBusValid"
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB2.0 controller acting as a host" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x60++0x01
|
|
line.byte 0x00 "DEVCTL,Device Control Register"
|
|
bitfld.byte 0x00 7. " B_DEVICE ,USB2.0 device select" "A device,B device"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current Vbus level" "Below SessionEnd,Above SesionEnd,Above AValid,About VBusValid"
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB2.0 controller acting as a host" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Init host negotiation" "Not initialized,Initialized"
|
|
bitfld.byte 0x00 0. " SESSION ,Session" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 11.
|
|
group.byte 0x61++0x02
|
|
line.byte 0x00 "PWRUPCNT,Power Up Counter Register"
|
|
bitfld.byte 0x00 0.--3. " PWRUPCNT ,Power up counter limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "TXFIFOSZ,Tx FIFO Size Register"
|
|
bitfld.byte 0x01 4. " TXDPB ,Double packet buffering support for TxFIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--3. " TXSZ ,Maximum packet size to be allowed for (in bytes)" "8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
line.byte 0x02 "RXFIFOSZ,Rx FIFO Size Register"
|
|
bitfld.byte 0x02 4. " RXDPB ,Double packet buffering support for RxFIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0.--3. " RXSZ ,Maximum packet size to be allowed for (in bytes)" "8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
group.word 0x64++0x03
|
|
line.word 0x00 "TXFIFOADD,Tx FIFO Address Register"
|
|
hexmask.word 0x00 0.--12. 0x01 " TXFIFOADD ,Start address of the selected Tx endpoint FIFO"
|
|
line.word 0x02 "RXFIFOADD,Rx FIFO Address Register"
|
|
bitfld.word 0x02 15. " DATAERRINTREN ,Data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " OVERRUNINTREN ,Over run interrupt enable" "Disabled,Enabled"
|
|
hexmask.word 0x02 0.--12. 0x01 " RXFIFOADD ,Start address of selected RX endpoint FIFO"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "HWCAPS,Hardware Capability Register"
|
|
rbitfld.word 0x00 15. " QMU_SUPPORT ,QMU feature support" "Not supported,Supported"
|
|
rbitfld.word 0x00 14. " HUB_SUPPORT ,HUB feature support" "Not supported,Supported"
|
|
rbitfld.word 0x00 13. " USB20_SUPPORT ,USB2.0 feature support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " USB11_SUPPORT ,USB1.1 feature support" "Not supported,Supported"
|
|
bitfld.word 0x00 10.--11. " MSTR_WRAP_INTFX ,AHB master interface configuration" "Mentor AHB,Asynchronous AHB,Asynchronous AXI,Asynchronous DX DRAM"
|
|
bitfld.word 0x00 8.--9. " SLAVE_WRAP_INTFX ,AHB slave interface configuration" "Mentor AHB,Asynchronous AHB,Asynchronous AXI,Asynchronous DX CPU"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--5. " USB_VERSION_CODE ,USB hardware version code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.word 0x6E++0x01
|
|
line.word 0x00 "HWSVERS,Version Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " USB_SUB_VERSION_CODE ,USB software version code"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x00)
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "BUSPERF1,USB Bus Performance Register 1"
|
|
bitfld.word 0x00 15. " CLRDMAREQEARLY_EN ,Clear DMAReq when 8 bytes of data remain in FIFO for RX or TXMAXP-8 bytes are loaded in FIFO for TX" "Not cleared,Cleared"
|
|
bitfld.word 0x00 14. " SOFT_DEBOUNCE ,Soft debounce enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " ISO_ERR_CNT_EN ,ISO error counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " ISO_RTY_DIS ,ISO retry disable" "No,Yes"
|
|
hexmask.word 0x00 0.--9. 1. " HOST_WAIT_EP0 ,Host waiting time of Endpoint 0"
|
|
else
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "BUSPERF1,USB Bus Performance Register 1"
|
|
bitfld.word 0x00 15. " CLRDMAREQEARLY_EN ,Clear DMAReq when 8 bytes of data remain in FIFO for RX or TXMAXP-8 bytes are loaded in FIFO for TX" "Not cleared,Cleared"
|
|
bitfld.word 0x00 14. " SOFT_DEBOUNCE ,Soft debounce enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " ISO_ERR_CNT_EN ,ISO error counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " ISO_RTY_DIS ,ISO retry disable" "No,Yes"
|
|
bitfld.word 0x00 10. " PREAMBLE_DELAY_EN ,Preamble delay enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--9. 1. " HOST_WAIT_EP0 ,Host waiting time of Endpoint 0"
|
|
endif
|
|
group.word 0x72++0x03
|
|
line.word 0x00 "BUSPERF2,USB Bus Performance Register 2"
|
|
bitfld.word 0x00 15. " HSR_ISOICHK_DIS ,ISO Rx 0-packet disable in host mode" "No,Yes"
|
|
bitfld.word 0x00 14. " HST_ISOOCHK_DIS ,ISO Tx 0-packet disable in host mode" "No,Yes"
|
|
hexmask.word 0x00 0.--13. 1. " HOST_WAIT_EPX ,Host waiting time of all endpoints except for Endpoint 0"
|
|
line.word 0x02 "BUSPERF3,USB Bus Performance Register 3"
|
|
bitfld.word 0x02 11. " VBUSERR_MODE ,VBUS error mode" "Reset USB controller,Set up VBUS err bit"
|
|
bitfld.word 0x02 9. " FLUSH_FIFO_EN ,Flush FIFO enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " NOISE_STILL_SOF ,Force transmitting SOF as babble interrupt" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 6. " BAB_CLR_EN ,Babble interrupt session close" "Not automatically,Automatically"
|
|
bitfld.word 0x02 3. " UNDO_SRPFIX ,Recover to the original circuit of USB2.0 IP about SRP" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " OTG_DEGLITCH_DISABLE ,Disable deglitch circuit of OTG signal group VBUSVALID,AVALID and SESSEND" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x02 1. " EP_SWRST ,USB MAC setting reset" "No reset,Reset"
|
|
bitfld.word 0x02 0. " DISUSBRESET ,Disable USB MAC setting" "No,Yes"
|
|
rgroup.byte 0x78++0x01
|
|
line.byte 0x00 "EPINFO,Number Of Tx And Rx Register"
|
|
bitfld.byte 0x00 4.--7. " RXENDPOINTS ,Number of Rx endpoints implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXENDPOINTS ,Number of Tx endpoints implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "RAMINFO,Width Of RAM And Number Of DMA Channel Register"
|
|
bitfld.byte 0x01 4.--7. " DMACHANS ,Number of DMA channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " RAMBITS ,Width of the RAM address bus-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x7A++0x04
|
|
line.byte 0x00 "LINKINFO,Delay To Be Applied Register"
|
|
bitfld.byte 0x00 4.--7. " WTCON ,Sets the wait to be applied to allow for the user's connect/disconnect filter in units of 533.3ns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " WTID ,Delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "VPLEN,Vbus Pulsing Charge Register"
|
|
line.byte 0x02 "HS_EOF1,Time Buffer Available On HS Transaction Register"
|
|
line.byte 0x03 "FS_EOF1,Time Buffer Available on FS Transaction Register"
|
|
line.byte 0x04 "LS_EOF1,Time Buffer Available on LS Transaction Register"
|
|
textline " "
|
|
width 16.
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x00)
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "RST_INFO,Reset Information Register"
|
|
bitfld.byte 0x00 4.--7. " WTFSSE0 ,SE0 signal duration before issuing the reset signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " WTCHRP ,Delay to be applied from detecting reset to sending chirp K" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte 0x7F++0x00
|
|
hide.byte 0x00 "RST_INFO,Reset Information Register"
|
|
endif
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "RXTOG,Rx Data Toggle Set/Status Register"
|
|
bitfld.word 0x00 2. " EP2RXTOG ,Receive logical endpoint n data toggle bit set/status" "Low,High"
|
|
bitfld.word 0x00 1. " EP1RXTOG ,Receive logical endpoint n data toggle bit set/status" "Low,High"
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "RXTOGEN,Rx Data Toggle Enable Register"
|
|
bitfld.word 0x00 2. " EP2RXTOGEN ,Enable receive logical endpoint n data toggle bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EP1RXTOGEN ,Enables receive logical endpoint n data toggle bit" "Disabled,Enabled"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "TXTOG,Tx Data Toggle Set/Status Register"
|
|
bitfld.word 0x00 4. " EP4TXTOG ,Transmit logical endpoint n data toggle bit set/status" "0,1"
|
|
bitfld.word 0x00 3. " EP3TXTOG ,Transmit logical endpoint n data toggle bit set/status" "0,1"
|
|
bitfld.word 0x00 2. " EP2TXTOG ,Transmit logical endpoint n data toggle bit set/status" "0,1"
|
|
bitfld.word 0x00 1. " EP1TXTOG ,Transmit logical endpoint n data toggle bit set/status" "0,1"
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "TXTOGEN,Tx Data Toggle Enable Register"
|
|
bitfld.word 0x00 4. " EP4TXTOGEN ,Enable receive logical endpoint 1 data toggle bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EP3TXTOGEN ,Enable receive logical endpoint 1 data toggle bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " EP2TXTOGEN ,Enable receive logical endpoint 1 data toggle bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EP1TXTOGEN ,Enable receive logical endpoint 1 data toggle bit" "Disabled,Enabled"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "USB_L1INTS,USB Level 1 Interrupt Status Register"
|
|
bitfld.long 0x00 11. " POWERDWN_INT_STATUS ,Power-down interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " DRVVBUS_INT_STATUS ,DRVVBUS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IDDIG_INT_STATUS ,IDDIG interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " VBUSVALID_INT_STATUS ,VBUSVALID interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DPDM_INT_STATUS ,DPDM interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " QHIF_INT_STATUS ,USBQ HIF command interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " QINT_STATUS ,USBQ interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PSR_INT_STATUS ,Packet sequence recorder interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMA_INT_STATUS ,DMA interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " USBCOM_INT_STATUS ,USB common interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RX_INT_STATUS ,Endpoint Rx interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TX_INT_STATUS ,Endpoint Tx interrupt status" "No interrupt,Interrupt"
|
|
group.long 0xA4++0x0B
|
|
line.long 0x00 "USB_L1INTM,USB Level 1 Interrupt Mask Register"
|
|
bitfld.long 0x00 11. " POWERDWN_INT_UNMASK ,Unmasks POWERDWN interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " DRVVBUS_INT_UNMASK ,Unmasks DRVVBUS interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " IDDIG_INT_UNMASK ,Unmasks IDDIG interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " VBUSVALID_INT_UNMASK ,Unmasks VBUSVALID interrupt" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DPDM_INT_UNMASK ,Unmasks DPDM interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " QHIF_INT_UNMASK ,Unmasks USBQ HIF command interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " QINT_UNMASK ,Unmasks USBQ interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " PSR_INT_UNMASK ,Unmasks packet sequence recorder interrupt" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMA_INT_UNMASK ,Unmasks DMA interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " USBCOM_INT_UNMASK ,Unmasks USB common interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " RX_INT_UNMASK ,Unmasks endpoint Rx interrupt" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TX_INT_UNMASK ,Unmasks endpoint Tx interrupt" "Masked,Not masked"
|
|
line.long 0x04 "USB_L1INTP,USB Level 1 Interrupt Polarity Register"
|
|
bitfld.long 0x04 11. " POWERDWN_INT_POL ,POWERDWN interrupt polarity" "Low,High"
|
|
bitfld.long 0x04 10. " DRVVBUS_INT_POL ,DRVVBUS interrupt polarity" "Low,High"
|
|
bitfld.long 0x04 9. " IDDIG_INT_POL ,IDDIG interrupt polarity" "Low,High"
|
|
bitfld.long 0x04 8. " VBUSVALID_INT_POL ,VBUSVALID interrupt polarity" "Low,High"
|
|
textline " "
|
|
line.long 0x08 "USB_L1INTC,USB Level 1 Interrupt Control Register"
|
|
bitfld.long 0x08 0. " USB_INT_SYNC ,USB interrupt synchronization" "Output directly,Synchronized by MCU BUS clock"
|
|
textline " "
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "CSR0_PERI,EP0 Control Status Register"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush the next packet to be transmitted/read from the Endpoint 0 FIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERVICESETUPEDN ,Clear the SetupEnd bit" "Not cleared,Cleared"
|
|
bitfld.word 0x00 6. " SERVICEDRXPKTRDY ,Clear the RxPktRdy bit" "Not cleared,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Transmit STALL handshake" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ended before DataEnd bit set" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " DATAEND ,Enable TxPktRdy for the last data packet" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Data packet loaded into the FIFO" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x108++0x01
|
|
line.word 0x00 "COUNT0,EP0 Received Bytes Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0_RX_COUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "TYPE0,EP0 Type Register"
|
|
bitfld.byte 0x00 6.--7. " EP0_TYPE ,Operating speed of the target device" ",High,Full,Low"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "NAKLIMT0,NAK Limit Register"
|
|
bitfld.byte 0x00 0.--4. " NAKLIMIT0 ,Number of frames/microframes after which Endpoint 0 should time out on receiving a stream of NAK responses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.byte 0x10B++0x00
|
|
hide.byte 0x00 "NAKLIMT0,NAK Limit Register"
|
|
endif
|
|
rgroup.word 0x10C++0x01
|
|
line.word 0x00 "SRAMCONFIGSIZE,SRAM Size Register"
|
|
rgroup.byte 0x10E++0x01
|
|
line.byte 0x00 "HBCONFIGDATA,High Bind-width Configuration Register"
|
|
bitfld.byte 0x00 4.--7. " NUM_HB_EPR ,Number of high bind-width RX endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " NUM_HB_EPT ,Number of high bind-width TX endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "CONFIGDATA,Core Configuration Register"
|
|
bitfld.byte 0x01 7. " MPRXE ,Automatic amalgamation of bulk packets enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " MPTXE ,Automatic splitting of bulk packets enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BIGENDIAN ,Big-endian ordering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " HBRXE ,High-bandwidth Rx ISO endpoint support enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " MPRXE ,High-bandwidth Tx ISO endpoint support enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " DYNFIFOSIZING ,Dynamic FIFO sizing option enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " SOFTCONE ,Soft connect/disconnect option enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " MPRXE ,UTMI+ data width" "8bits,16bits"
|
|
textline " "
|
|
group.word 0x110++0x07
|
|
line.word 0x00 "TX1MAP,TX1MAP Register"
|
|
bitfld.word 0x00 11.--12. " M_1 ,Maximum payload size for indexed TX endpoint" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x02 "TX1CSR_PERI,Tx1 CSR Register"
|
|
bitfld.word 0x02 15. " AUTOSET ,TxPktRdy autoset when data of the maximum packet size is loaded into the TxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " ISO ,Enable Tx endpoint for Isochronous transfer and clear it to enable Tx endpoint for bulk or interrupt transfer" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " DMAREQEN ,Enable DMA request for the Tx endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " FRCDATATOG ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 10. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " SETTXPKTRDY_TWICE ,TxPktRdy had been set while it is 1'b1 already" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " INCOMPTX ,Incomplete data transmitted" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x02 5. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x02 4. " SENDSTALL ,Issue a STALL handshake to an IN token" "Not issued,Issued"
|
|
bitfld.word 0x02 3. " FLUSHFIFO ,Flush the latest packet from the endpoint TxFIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x02 2. " UNDERRUN ,In token received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.word 0x02 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x02 0. " TXPKTRDY ,Data packet loaded loaded into FIFO" "Not loaded,Loaded"
|
|
line.word 0x04 "RX1MAP,RX1MAP Register"
|
|
bitfld.word 0x04 11.--12. " M_1 ,Maximum payload size for indexed RX endpoint" "0,1,2,3"
|
|
hexmask.word 0x04 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x06 "RX1CSR_PERI,RX1 CSR Register"
|
|
bitfld.word 0x06 15. " AUTOCLEAR ,RxPktRdy autoclear when a packet of RxMaxP bytes has been unloaded from the RxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " ISO ,Enable Rx endpoint for isochronous transfer" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DMAREQEN ,Enable the DMA request for RX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x06 12. " DISNYET_PIDERR ,Disable the sending of NYET handshakes" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x06 11. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x06 9. " KEEPERRSTATUS ,Keep isochronous error, PIDERROR, INCOMPRX and DATAERROR" "Not kept,Kept"
|
|
bitfld.word 0x06 8. " INCOMPRX ,Incomplete data received error" "No error,Error"
|
|
bitfld.word 0x06 7. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x06 6. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x06 5. " SENDSTALL ,Issue a STALL handshake" "Not issued,Issued"
|
|
bitfld.word 0x06 4. " FLUSHFIFO ,Flush the next packet to be read from the endpoint RxFIFO" "Not flushed,Flushed"
|
|
rbitfld.word 0x06 3. " DATAERR ,Data packet CRC/bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x06 2. " OVERRUN ,OUT packet cannot be loaded into RxFIFO" "Not occurred,Occurred"
|
|
rbitfld.word 0x06 1. " FIFOFULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x06 0. " RXPKTRDY ,Data packet has been received" "Not received,Received"
|
|
if (((per.word(ad:0xA0900000+0x16)&0x01)==0x01))
|
|
rgroup.word (0x110+0x08)++0x01
|
|
line.word 0x00 "RX1COUNT,Rx1 Count Register"
|
|
hexmask.word 0x00 0.--13. 1. " RXCOUNT ,Number of received data bytes in the packet in RxFIFO"
|
|
else
|
|
hgroup.word (0x110+0x08)++0x01
|
|
hide.word 0x00 "RX1COUNT,Rx1 Count Register"
|
|
endif
|
|
group.byte (0x110+0x0A)++0x00
|
|
line.byte 0x00 "TX1TYPE,Tx1Type Register"
|
|
bitfld.byte 0x00 6.--7. " TX_SPEED ,Tx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " TX_PROTOCOL ,Tx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TX_TARGET_EP_NUMBER ,Tx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte (0x110+0x0B)++0x00
|
|
line.byte 0x00 "TX1INTERVAL,Tx1Interval Register"
|
|
else
|
|
hgroup.byte (0x110+0x0B)++0x00
|
|
hide.byte 0x00 "TX1INTERVAL,Tx1Interval Register"
|
|
endif
|
|
group.byte (0x110+0x0C)++0x01
|
|
line.byte 0x00 "RX1TYPE,Rx1Type Register"
|
|
bitfld.byte 0x00 6.--7. " RXSPEED ,Rx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " RX_PROTOCOL ,Rx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " RX_TARGET_EP_NUMBER ,Rx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "RX1INTERVAL,Rx1Interval Register"
|
|
rgroup.byte (0x110+0x0F)++0x00
|
|
line.byte 0x00 "FIFOSIZE1,EP1 Configured FIFO Size Register"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSIZE ,Indicates the RxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSIZE ,Indicates the TxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x120++0x07
|
|
line.word 0x00 "TX2MAP,TX2MAP Register"
|
|
bitfld.word 0x00 11.--12. " M_1 ,Maximum payload size for indexed TX endpoint" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x02 "TX2CSR_PERI,Tx2 CSR Register"
|
|
bitfld.word 0x02 15. " AUTOSET ,TxPktRdy autoset when data of the maximum packet size is loaded into the TxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " ISO ,Enable Tx endpoint for Isochronous transfer and clear it to enable Tx endpoint for bulk or interrupt transfer" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " DMAREQEN ,Enable DMA request for the Tx endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " FRCDATATOG ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 10. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " SETTXPKTRDY_TWICE ,TxPktRdy had been set while it is 1'b1 already" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " INCOMPTX ,Incomplete data transmitted" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x02 5. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x02 4. " SENDSTALL ,Issue a STALL handshake to an IN token" "Not issued,Issued"
|
|
bitfld.word 0x02 3. " FLUSHFIFO ,Flush the latest packet from the endpoint TxFIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x02 2. " UNDERRUN ,In token received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.word 0x02 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x02 0. " TXPKTRDY ,Data packet loaded loaded into FIFO" "Not loaded,Loaded"
|
|
line.word 0x04 "RX2MAP,RX2MAP Register"
|
|
bitfld.word 0x04 11.--12. " M_1 ,Maximum payload size for indexed RX endpoint" "0,1,2,3"
|
|
hexmask.word 0x04 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x06 "RX2CSR_PERI,RX2 CSR Register"
|
|
bitfld.word 0x06 15. " AUTOCLEAR ,RxPktRdy autoclear when a packet of RxMaxP bytes has been unloaded from the RxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " ISO ,Enable Rx endpoint for isochronous transfer" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DMAREQEN ,Enable the DMA request for RX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x06 12. " DISNYET_PIDERR ,Disable the sending of NYET handshakes" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x06 11. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x06 9. " KEEPERRSTATUS ,Keep isochronous error, PIDERROR, INCOMPRX and DATAERROR" "Not kept,Kept"
|
|
bitfld.word 0x06 8. " INCOMPRX ,Incomplete data received error" "No error,Error"
|
|
bitfld.word 0x06 7. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x06 6. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x06 5. " SENDSTALL ,Issue a STALL handshake" "Not issued,Issued"
|
|
bitfld.word 0x06 4. " FLUSHFIFO ,Flush the next packet to be read from the endpoint RxFIFO" "Not flushed,Flushed"
|
|
rbitfld.word 0x06 3. " DATAERR ,Data packet CRC/bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x06 2. " OVERRUN ,OUT packet cannot be loaded into RxFIFO" "Not occurred,Occurred"
|
|
rbitfld.word 0x06 1. " FIFOFULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x06 0. " RXPKTRDY ,Data packet has been received" "Not received,Received"
|
|
if (((per.word(ad:0xA0900000+0x16)&0x01)==0x01))
|
|
rgroup.word (0x120+0x08)++0x01
|
|
line.word 0x00 "RX2COUNT,Rx2 Count Register"
|
|
hexmask.word 0x00 0.--13. 1. " RXCOUNT ,Number of received data bytes in the packet in RxFIFO"
|
|
else
|
|
hgroup.word (0x120+0x08)++0x01
|
|
hide.word 0x00 "RX2COUNT,Rx2 Count Register"
|
|
endif
|
|
group.byte (0x120+0x0A)++0x00
|
|
line.byte 0x00 "TX2TYPE,Tx2Type Register"
|
|
bitfld.byte 0x00 6.--7. " TX_SPEED ,Tx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " TX_PROTOCOL ,Tx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TX_TARGET_EP_NUMBER ,Tx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte (0x120+0x0B)++0x00
|
|
line.byte 0x00 "TX2INTERVAL,Tx2Interval Register"
|
|
else
|
|
hgroup.byte (0x120+0x0B)++0x00
|
|
hide.byte 0x00 "TX2INTERVAL,Tx2Interval Register"
|
|
endif
|
|
group.byte (0x120+0x0C)++0x01
|
|
line.byte 0x00 "RX2TYPE,Rx2Type Register"
|
|
bitfld.byte 0x00 6.--7. " RXSPEED ,Rx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " RX_PROTOCOL ,Rx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " RX_TARGET_EP_NUMBER ,Rx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "RX2INTERVAL,Rx2Interval Register"
|
|
rgroup.byte (0x120+0x0F)++0x00
|
|
line.byte 0x00 "FIFOSIZE2,EP2 Configured FIFO Size Register"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSIZE ,Indicates the RxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSIZE ,Indicates the TxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x130++0x07
|
|
line.word 0x00 "TX3MAP,TX3MAP Register"
|
|
bitfld.word 0x00 11.--12. " M_1 ,Maximum payload size for indexed TX endpoint" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x02 "TX3CSR_PERI,Tx3 CSR Register"
|
|
bitfld.word 0x02 15. " AUTOSET ,TxPktRdy autoset when data of the maximum packet size is loaded into the TxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " ISO ,Enable Tx endpoint for Isochronous transfer and clear it to enable Tx endpoint for bulk or interrupt transfer" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " DMAREQEN ,Enable DMA request for the Tx endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " FRCDATATOG ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 10. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " SETTXPKTRDY_TWICE ,TxPktRdy had been set while it is 1'b1 already" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " INCOMPTX ,Incomplete data transmitted" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x02 5. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x02 4. " SENDSTALL ,Issue a STALL handshake to an IN token" "Not issued,Issued"
|
|
bitfld.word 0x02 3. " FLUSHFIFO ,Flush the latest packet from the endpoint TxFIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x02 2. " UNDERRUN ,In token received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.word 0x02 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x02 0. " TXPKTRDY ,Data packet loaded loaded into FIFO" "Not loaded,Loaded"
|
|
line.word 0x04 "RX3MAP,RX3MAP Register"
|
|
bitfld.word 0x04 11.--12. " M_1 ,Maximum payload size for indexed RX endpoint" "0,1,2,3"
|
|
hexmask.word 0x04 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x06 "RX3CSR_PERI,RX3 CSR Register"
|
|
bitfld.word 0x06 15. " AUTOCLEAR ,RxPktRdy autoclear when a packet of RxMaxP bytes has been unloaded from the RxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " ISO ,Enable Rx endpoint for isochronous transfer" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DMAREQEN ,Enable the DMA request for RX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x06 12. " DISNYET_PIDERR ,Disable the sending of NYET handshakes" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x06 11. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x06 9. " KEEPERRSTATUS ,Keep isochronous error, PIDERROR, INCOMPRX and DATAERROR" "Not kept,Kept"
|
|
bitfld.word 0x06 8. " INCOMPRX ,Incomplete data received error" "No error,Error"
|
|
bitfld.word 0x06 7. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x06 6. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x06 5. " SENDSTALL ,Issue a STALL handshake" "Not issued,Issued"
|
|
bitfld.word 0x06 4. " FLUSHFIFO ,Flush the next packet to be read from the endpoint RxFIFO" "Not flushed,Flushed"
|
|
rbitfld.word 0x06 3. " DATAERR ,Data packet CRC/bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x06 2. " OVERRUN ,OUT packet cannot be loaded into RxFIFO" "Not occurred,Occurred"
|
|
rbitfld.word 0x06 1. " FIFOFULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x06 0. " RXPKTRDY ,Data packet has been received" "Not received,Received"
|
|
if (((per.word(ad:0xA0900000+0x16)&0x01)==0x01))
|
|
rgroup.word (0x130+0x08)++0x01
|
|
line.word 0x00 "RX3COUNT,Rx3 Count Register"
|
|
hexmask.word 0x00 0.--13. 1. " RXCOUNT ,Number of received data bytes in the packet in RxFIFO"
|
|
else
|
|
hgroup.word (0x130+0x08)++0x01
|
|
hide.word 0x00 "RX3COUNT,Rx3 Count Register"
|
|
endif
|
|
group.byte (0x130+0x0A)++0x00
|
|
line.byte 0x00 "TX3TYPE,Tx3Type Register"
|
|
bitfld.byte 0x00 6.--7. " TX_SPEED ,Tx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " TX_PROTOCOL ,Tx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TX_TARGET_EP_NUMBER ,Tx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte (0x130+0x0B)++0x00
|
|
line.byte 0x00 "TX3INTERVAL,Tx3Interval Register"
|
|
else
|
|
hgroup.byte (0x130+0x0B)++0x00
|
|
hide.byte 0x00 "TX3INTERVAL,Tx3Interval Register"
|
|
endif
|
|
group.byte (0x130+0x0C)++0x01
|
|
line.byte 0x00 "RX3TYPE,Rx3Type Register"
|
|
bitfld.byte 0x00 6.--7. " RXSPEED ,Rx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " RX_PROTOCOL ,Rx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " RX_TARGET_EP_NUMBER ,Rx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "RX3INTERVAL,Rx3Interval Register"
|
|
rgroup.byte (0x130+0x0F)++0x00
|
|
line.byte 0x00 "FIFOSIZE3,EP3 Configured FIFO Size Register"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSIZE ,Indicates the RxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSIZE ,Indicates the TxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x140++0x07
|
|
line.word 0x00 "TX4MAP,TX4MAP Register"
|
|
bitfld.word 0x00 11.--12. " M_1 ,Maximum payload size for indexed TX endpoint" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x02 "TX4CSR_PERI,Tx4 CSR Register"
|
|
bitfld.word 0x02 15. " AUTOSET ,TxPktRdy autoset when data of the maximum packet size is loaded into the TxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " ISO ,Enable Tx endpoint for Isochronous transfer and clear it to enable Tx endpoint for bulk or interrupt transfer" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " DMAREQEN ,Enable DMA request for the Tx endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " FRCDATATOG ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 10. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " SETTXPKTRDY_TWICE ,TxPktRdy had been set while it is 1'b1 already" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " INCOMPTX ,Incomplete data transmitted" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x02 5. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x02 4. " SENDSTALL ,Issue a STALL handshake to an IN token" "Not issued,Issued"
|
|
bitfld.word 0x02 3. " FLUSHFIFO ,Flush the latest packet from the endpoint TxFIFO" "Not flushed,Flushed"
|
|
bitfld.word 0x02 2. " UNDERRUN ,In token received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.word 0x02 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x02 0. " TXPKTRDY ,Data packet loaded loaded into FIFO" "Not loaded,Loaded"
|
|
line.word 0x04 "RX4MAP,RX4MAP Register"
|
|
bitfld.word 0x04 11.--12. " M_1 ,Maximum payload size for indexed RX endpoint" "0,1,2,3"
|
|
hexmask.word 0x04 0.--10. 1. " MAXIMUM_PAYLOAD_TRANSACTION ,Maximum payload transmitted in a single transaction"
|
|
line.word 0x06 "RX4CSR_PERI,RX4 CSR Register"
|
|
bitfld.word 0x06 15. " AUTOCLEAR ,RxPktRdy autoclear when a packet of RxMaxP bytes has been unloaded from the RxFIFO" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " ISO ,Enable Rx endpoint for isochronous transfer" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DMAREQEN ,Enable the DMA request for RX endpoint" "Disabled,Enabled"
|
|
bitfld.word 0x06 12. " DISNYET_PIDERR ,Disable the sending of NYET handshakes" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x06 11. " DMAREQMODE ,Select and clear DMA request mode 1 enable to DMA request mode 0" "Disabled,Enabled"
|
|
bitfld.word 0x06 9. " KEEPERRSTATUS ,Keep isochronous error, PIDERROR, INCOMPRX and DATAERROR" "Not kept,Kept"
|
|
bitfld.word 0x06 8. " INCOMPRX ,Incomplete data received error" "No error,Error"
|
|
bitfld.word 0x06 7. " CLRDATATOG ,Reset the endpoint data toggle to 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x06 6. " SENTSTALL ,STALL handshake is transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x06 5. " SENDSTALL ,Issue a STALL handshake" "Not issued,Issued"
|
|
bitfld.word 0x06 4. " FLUSHFIFO ,Flush the next packet to be read from the endpoint RxFIFO" "Not flushed,Flushed"
|
|
rbitfld.word 0x06 3. " DATAERR ,Data packet CRC/bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x06 2. " OVERRUN ,OUT packet cannot be loaded into RxFIFO" "Not occurred,Occurred"
|
|
rbitfld.word 0x06 1. " FIFOFULL ,FIFO is full" "Not full,Full"
|
|
bitfld.word 0x06 0. " RXPKTRDY ,Data packet has been received" "Not received,Received"
|
|
if (((per.word(ad:0xA0900000+0x16)&0x01)==0x01))
|
|
rgroup.word (0x140+0x08)++0x01
|
|
line.word 0x00 "RX4COUNT,Rx4 Count Register"
|
|
hexmask.word 0x00 0.--13. 1. " RXCOUNT ,Number of received data bytes in the packet in RxFIFO"
|
|
else
|
|
hgroup.word (0x140+0x08)++0x01
|
|
hide.word 0x00 "RX4COUNT,Rx4 Count Register"
|
|
endif
|
|
group.byte (0x140+0x0A)++0x00
|
|
line.byte 0x00 "TX4TYPE,Tx4Type Register"
|
|
bitfld.byte 0x00 6.--7. " TX_SPEED ,Tx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " TX_PROTOCOL ,Tx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TX_TARGET_EP_NUMBER ,Tx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
group.byte (0x140+0x0B)++0x00
|
|
line.byte 0x00 "TX4INTERVAL,Tx4Interval Register"
|
|
else
|
|
hgroup.byte (0x140+0x0B)++0x00
|
|
hide.byte 0x00 "TX4INTERVAL,Tx4Interval Register"
|
|
endif
|
|
group.byte (0x140+0x0C)++0x01
|
|
line.byte 0x00 "RX4TYPE,Rx4Type Register"
|
|
bitfld.byte 0x00 6.--7. " RXSPEED ,Rx speed" ",High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " RX_PROTOCOL ,Rx protocol" ",Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " RX_TARGET_EP_NUMBER ,Rx target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "RX4INTERVAL,Rx4Interval Register"
|
|
rgroup.byte (0x140+0x0F)++0x00
|
|
line.byte 0x00 "FIFOSIZE4,EP4 Configured FIFO Size Register"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSIZE ,Indicates the RxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSIZE ,Indicates the TxFIFO size of 2^n bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 10.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DMA_INTR,DMA Interrupt Status Register"
|
|
setclrfld.long 0x00 15. 0x00 31. 0x00 23. " DMA_INTR_UNMASK[7]_SET/CLR ,Unmask DMA interrupts bit [7]" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x00 30. 0x00 22. " [6]_SET/CLR ,Unmask DMA interrupts bit [6]" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. 0x00 29. 0x00 21. " [5]_SET/CLR ,Unmask DMA interrupts bit [5]" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x00 28. 0x00 20. " [4]_SET/CLR ,Unmask DMA interrupts bit [4]" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 27. 0x00 19. " [3]_SET/CLR ,Unmask DMA interrupts bit [3]" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. 0x00 26. 0x00 18. " [2]_SET/CLR ,Unmask DMA interrupts bit [2]" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. 0x00 25. 0x00 17. " [1]_SET/CLR ,Unmask DMA interrupts bit [1]" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x00 24. 0x00 16. " [0]_SET/CLR ,Unmask DMA interrupts bit [0]" "Masked,Unmasked"
|
|
textline " "
|
|
eventfld.long 0x00 7. " DMA_INTR_STATUS[7] ,DMA channel 7 complete interrupt status" "Not completed,Completed"
|
|
eventfld.long 0x00 6. " [6] ,DMA channel 6 complete interrupt status" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " [5] ,DMA channel 5 complete interrupt status" "Not completed,Completed"
|
|
eventfld.long 0x00 4. " [4] ,DMA channel 4 complete interrupt status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,DMA channel 3 complete interrupt status" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " [2] ,DMA channel 2 complete interrupt status" "Not completed,Completed"
|
|
eventfld.long 0x00 1. " [1] ,DMA channel 1 complete interrupt status" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " [0] ,DMA channel 0 complete interrupt status" "Not completed,Completed"
|
|
textline " "
|
|
width 13.
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "DMA_CNTL_0,DMA Channel 0 Control Register"
|
|
bitfld.word 0x00 13. " DMAABORT ,Abort current DMA transfer" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " DMACHEN ,DMA channel enable monitor bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " BURST_MODE ,Burst mode" "Bursts,INCR4,INCR8 INCR4,INCR16 INCR8 INCR4"
|
|
rbitfld.word 0x00 8. " BUSERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " ENDPNT ,Endpoint which DMA will transfer with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMAMODE ,DMA mode" "Single packet op,Multi packets op"
|
|
bitfld.word 0x00 1. " DMADIR ,Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x200+0x08)++0x07
|
|
line.long 0x00 "DMA_ADDR_0,DMA Channel 0 Address Register"
|
|
line.long 0x04 "DMA_COUNT_0,DMA Channel 0 Byte Count Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DMA_COUNT_0 ,24-bit DMA transfer count with byte unit"
|
|
group.word 0x214++0x01
|
|
line.word 0x00 "DMA_CNTL_1,DMA Channel 1 Control Register"
|
|
bitfld.word 0x00 13. " DMAABORT ,Abort current DMA transfer" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " DMACHEN ,DMA channel enable monitor bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " BURST_MODE ,Burst mode" "Bursts,INCR4,INCR8 INCR4,INCR16 INCR8 INCR4"
|
|
rbitfld.word 0x00 8. " BUSERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " ENDPNT ,Endpoint which DMA will transfer with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMAMODE ,DMA mode" "Single packet op,Multi packets op"
|
|
bitfld.word 0x00 1. " DMADIR ,Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x214+0x08)++0x07
|
|
line.long 0x00 "DMA_ADDR_1,DMA Channel 1 Address Register"
|
|
line.long 0x04 "DMA_COUNT_1,DMA Channel 1 Byte Count Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DMA_COUNT_1 ,24-bit DMA transfer count with byte unit"
|
|
group.word 0x228++0x01
|
|
line.word 0x00 "DMA_CNTL_2,DMA Channel 2 Control Register"
|
|
bitfld.word 0x00 13. " DMAABORT ,Abort current DMA transfer" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " DMACHEN ,DMA channel enable monitor bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " BURST_MODE ,Burst mode" "Bursts,INCR4,INCR8 INCR4,INCR16 INCR8 INCR4"
|
|
rbitfld.word 0x00 8. " BUSERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " ENDPNT ,Endpoint which DMA will transfer with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMAMODE ,DMA mode" "Single packet op,Multi packets op"
|
|
bitfld.word 0x00 1. " DMADIR ,Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x228+0x08)++0x07
|
|
line.long 0x00 "DMA_ADDR_2,DMA Channel 2 Address Register"
|
|
line.long 0x04 "DMA_COUNT_2,DMA Channel 2 Byte Count Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DMA_COUNT_2 ,24-bit DMA transfer count with byte unit"
|
|
group.word 0x23C++0x01
|
|
line.word 0x00 "DMA_CNTL_3,DMA Channel 3 Control Register"
|
|
bitfld.word 0x00 13. " DMAABORT ,Abort current DMA transfer" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " DMACHEN ,DMA channel enable monitor bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " BURST_MODE ,Burst mode" "Bursts,INCR4,INCR8 INCR4,INCR16 INCR8 INCR4"
|
|
rbitfld.word 0x00 8. " BUSERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " ENDPNT ,Endpoint which DMA will transfer with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DMAMODE ,DMA mode" "Single packet op,Multi packets op"
|
|
bitfld.word 0x00 1. " DMADIR ,Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x23C+0x08)++0x07
|
|
line.long 0x00 "DMA_ADDR_3,DMA Channel 3 Address Register"
|
|
line.long 0x04 "DMA_COUNT_3,DMA Channel 3 Byte Count Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DMA_COUNT_3 ,24-bit DMA transfer count with byte unit"
|
|
textline " "
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DMA_LIMITER,DMA Limiter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DMA_LIMITER ,Bus utilization of the DMA channels limit"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "DMA_CONFIG,DMA Configuration Register"
|
|
bitfld.long 0x00 10.--11. " DMA_ACTIVE_EN ,Usb_active control" "Depends on all DMAEN of DMA,Ties to 1,Ties to 0,Depends on ep_active dma_active and all DMAEN of DMA"
|
|
bitfld.long 0x00 8.--9. " AHB_HPROT_2_EN ,AHB master interface HPROT2 function operating control" "Bufferable except last burst transfer,Non-bufferable,Bufferable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DMAQ_CHAN_SEL ,DMA channel select used by USB_DMAQ" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AHBWAIT_SEL ,AHBWAIT behavior select" "No wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BOUNDARY_1K_CROSS_EN ,1k boundary page crossing enable" "Disabled,Enabled"
|
|
textline " "
|
|
width 15.
|
|
if ((per.byte(ad:0xA0900000+0x60)&0x04)==0x04)
|
|
if ((per.w(ad:0xA0900000+0x16)&0x8000)==0x8000)
|
|
group.word 0x304++0x01
|
|
line.word 0x00 "EP1RXPKTCOUNT,EP1 RxPktCount Register"
|
|
group.word 0x308++0x01
|
|
line.word 0x00 "EP2RXPKTCOUNT,EP2 RxPktCount Register"
|
|
else
|
|
hgroup.word 0x304++0x01
|
|
hide.word 0x00 "EP1RXPKTCOUNT,EP1 RxPktCount Register"
|
|
hgroup.word 0x308++0x01
|
|
hide.word 0x00 "EP2RXPKTCOUNT,EP2 RxPktCount Register"
|
|
endif
|
|
else
|
|
hgroup.word 0x304++0x01
|
|
hide.word 0x00 "EP1RXPKTCOUNT,EP1 RxPktCount Register"
|
|
hgroup.word 0x308++0x01
|
|
hide.word 0x00 "EP2RXPKTCOUNT,EP2 RxPktCount Register"
|
|
endif
|
|
group.word 0x604++0x01
|
|
line.word 0x00 "TM1,Test Mode 1 Register"
|
|
bitfld.word 0x00 0. " TM1 ,USB IP internal TM1" "0,1"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "HWVER_DATE,HW Version Control Register"
|
|
if (((per.l(ad:0xA0900000+0x684)&0x10000)==0x10000))
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SRAMA,SRAM Address Register"
|
|
bitfld.long 0x00 17. " EP0_STARTAD_TM6_EN ,Change EP0 FIFO star address for test mode 6 FIFO loopback test by DMA/PIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SRAMDBG ,SRAM debug mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SRAMA ,SRAM address"
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "SRAMD,SRAM Data Register"
|
|
endif
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "RISC_SIZE,RISC Size Register"
|
|
bitfld.long 0x00 0.--1. " RISC_SIZE ,RISC wrapper access size" "8bit,16bit,32bit,?..."
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "RESREG,Reserved Register"
|
|
bitfld.long 0x00 19. " MAC_CG_DIS ,Disable USB MAC clock gate" "No,Yes"
|
|
bitfld.long 0x00 18. " USB_CG_DIS ,Disable USB clock gate" "No,Yes"
|
|
bitfld.long 0x00 17. " DMA_CG_DIS ,Disable DMA clock gate" "No,Yes"
|
|
bitfld.long 0x00 16. " MCU_CG_DIS ,Disable MCU clock gate" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HSTPWRDWN_OPT ,Host mode device connection detection option" "Disabled,Enabled"
|
|
group.byte 0x730++0x01
|
|
line.byte 0x00 "OTG20_CSRL,OTG20 Related Control Register L"
|
|
bitfld.byte 0x00 7. " DIS_HSUS ,Disable host mode entering C_OPM_HSUS state before entering suspend" "No,Yes"
|
|
bitfld.byte 0x00 6. " EN_A_HFS_WHNP ,Transfer FS idle of A device to HFS_HSUS state first" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DIS_B_WTDIS ,Disable B device entering C_OPM_B_WTDIS states before switching to host mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " EN_HHS_SUSP_DIS ,Enable host-hs-suspend entering OPM_FS_WTCON state first while receiving disconnect signal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DIS_CHARGE_VBUS ,Disable B device charging VBUS function for OTG2.0 feature" "No,Yes"
|
|
bitfld.byte 0x00 2. " EN_HSUS_RESUME_INT ,Enable hsus mode of host initializing resuming interrupt while receiving resume K as waiting for HNP" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EN_HSUS_RESUME ,Enable hnpsus-mode of host entering host-normal mode as receiving resume K while waiting for HNP" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " OTG20_EN ,Enables OTG 2.0 feature" "Disabled,Enabled"
|
|
line.byte 0x01 "OTG20_CSRH,OTG20 Related Control Register H"
|
|
bitfld.byte 0x01 1. " DIS_AUTORST ,Disable autoreset" "No,Yes"
|
|
bitfld.byte 0x01 0. " EN_CON_DEB_SHORT ,Decrease A device connection denounce waiting timing enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPT (General Purpose Timer)"
|
|
base ad:0xA2140000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "GPT_IRQSTA,GPT IRQ Status"
|
|
bitfld.long 0x00 5. " IRQSTA[5] ,Interrupt status of GPT[5]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt status of GPT[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt status of GPT[3]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt status of GPT[2]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Interrupt status of GPT[1]" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt status of GPT[0]" "No interrupt,Interrupt"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "GPT_IRQMASK0,ARM IRQMASK Register"
|
|
bitfld.long 0x00 5. " IRQ_MSK0[5] ,ARM GPT5 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,ARM GPT4 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,ARM GPT3 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,ARM GPT2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,ARM GPT1 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,ARM GPT0 interrupt mask" "Not masked,Masked"
|
|
line.long 0x04 "GPT_IRQMASK1,CM4 IRQMASK Register"
|
|
bitfld.long 0x04 5. " IRQ_MSK1[5] ,CM4 GPT5 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,CM4 GPT4 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [3] ,CM4 GPT3 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [2] ,CM4 GPT2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [1] ,CM4 GPT1 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,CM4 GPT0 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
group.long 0x10++0x0B "GPT1 Registers"
|
|
line.long 0x00 "GPT1_CON,GPT1 Control"
|
|
bitfld.long 0x00 6. " SW_CG1 ,GPT1 clock stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MODE1 ,GPT1 operation mode" "One-shot,Repeat,Keep-go,Freerun"
|
|
bitfld.long 0x00 1. " CLR1 ,GPT1 counter clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " EN1 ,GPT1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPT1_CLK,GPT1 Clock Setting"
|
|
bitfld.long 0x04 4. " CLK1 ,GPT1 clock source" "System clock,RTC clock"
|
|
bitfld.long 0x04 0.--3. " CLKDIV1 ,GPT1 input clock frequency divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/16,/32,/64"
|
|
line.long 0x08 "GPT1_IRQ_EN,GPT1 IRQ Enabling"
|
|
bitfld.long 0x08 0. " IRQEN ,Enable interrupt of GPT1" "Disabled,Enabled"
|
|
rgroup.long (0x10+0x0C)++0x03
|
|
line.long 0x00 "GPT1_IRQ_STA,GPT1 IRQ Status"
|
|
bitfld.long 0x00 0. " IRQSTA ,Interrupt status of GPT1" "No interrupt,Interrupt"
|
|
wgroup.long (0x10+0x10)++0x03
|
|
line.long 0x00 "GPT1_IRQ_ACK,GPT1 IRQ Acknowledgement"
|
|
bitfld.long 0x00 0. " IRQACK ,Interrupt acknowledgement for GPT1" "No effect,Acknowledge"
|
|
rgroup.long (0x10+0x14)++0x03
|
|
line.long 0x00 "GPT1_COUNT,GPT1 Counter"
|
|
group.long (0x10+0x18)++0x03
|
|
line.long 0x00 "GPT1_COMPARE,GPT1 Compare Value"
|
|
textline " "
|
|
group.long 0x40++0x0B "GPT2 Registers"
|
|
line.long 0x00 "GPT2_CON,GPT2 Control"
|
|
bitfld.long 0x00 6. " SW_CG2 ,GPT2 clock stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MODE2 ,GPT2 operation mode" "One-shot,Repeat,Keep-go,Freerun"
|
|
bitfld.long 0x00 1. " CLR2 ,GPT2 counter clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " EN2 ,GPT2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPT2_CLK,GPT2 Clock Setting"
|
|
bitfld.long 0x04 4. " CLK2 ,GPT2 clock source" "System clock,RTC clock"
|
|
bitfld.long 0x04 0.--3. " CLKDIV2 ,GPT2 input clock frequency divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/16,/32,/64"
|
|
line.long 0x08 "GPT2_IRQ_EN,GPT2 IRQ Enabling"
|
|
bitfld.long 0x08 0. " IRQEN ,Enable interrupt of GPT2" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "GPT2_IRQ_STA,GPT2 IRQ Status"
|
|
bitfld.long 0x00 0. " IRQSTA ,Interrupt status of GPT2" "No interrupt,Interrupt"
|
|
wgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "GPT2_IRQ_ACK,GPT2 IRQ Acknowledgement"
|
|
bitfld.long 0x00 0. " IRQACK ,Interrupt acknowledgement for GPT2" "No effect,Acknowledge"
|
|
rgroup.long (0x40+0x14)++0x03
|
|
line.long 0x00 "GPT2_COUNT,GPT2 Counter"
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "GPT2_COMPARE,GPT2 Compare Value"
|
|
textline " "
|
|
group.long 0x70++0x0B "GPT3 Registers"
|
|
line.long 0x00 "GPT3_CON,GPT3 Control"
|
|
bitfld.long 0x00 6. " SW_CG3 ,GPT3 clock stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MODE3 ,GPT3 operation mode" "One-shot,Repeat,Keep-go,Freerun"
|
|
bitfld.long 0x00 1. " CLR3 ,GPT3 counter clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " EN3 ,GPT3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPT3_CLK,GPT3 Clock Setting"
|
|
bitfld.long 0x04 4. " CLK3 ,GPT3 clock source" "System clock,RTC clock"
|
|
bitfld.long 0x04 0.--3. " CLKDIV3 ,GPT3 input clock frequency divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/16,/32,/64"
|
|
line.long 0x08 "GPT3_IRQ_EN,GPT3 IRQ Enabling"
|
|
bitfld.long 0x08 0. " IRQEN ,Enable interrupt of GPT3" "Disabled,Enabled"
|
|
rgroup.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "GPT3_IRQ_STA,GPT3 IRQ Status"
|
|
bitfld.long 0x00 0. " IRQSTA ,Interrupt status of GPT3" "No interrupt,Interrupt"
|
|
wgroup.long (0x70+0x10)++0x03
|
|
line.long 0x00 "GPT3_IRQ_ACK,GPT3 IRQ Acknowledgement"
|
|
bitfld.long 0x00 0. " IRQACK ,Interrupt acknowledgement for GPT3" "No effect,Acknowledge"
|
|
rgroup.long (0x70+0x14)++0x03
|
|
line.long 0x00 "GPT3_COUNT,GPT3 Counter"
|
|
group.long (0x70+0x18)++0x03
|
|
line.long 0x00 "GPT3_COMPARE,GPT3 Compare Value"
|
|
textline " "
|
|
group.long 0xA0++0x0B "GPT4 Registers"
|
|
line.long 0x00 "GPT4_CON,GPT4 Control"
|
|
bitfld.long 0x00 6. " SW_CG4 ,GPT4 clock stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MODE4 ,GPT4 operation mode" "One-shot,Repeat,Keep-go,Freerun"
|
|
bitfld.long 0x00 1. " CLR4 ,GPT4 counter clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " EN4 ,GPT4 enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPT4_CLK,GPT4 Clock Setting"
|
|
bitfld.long 0x04 4. " CLK4 ,GPT4 clock source" "System clock,RTC clock"
|
|
bitfld.long 0x04 0.--3. " CLKDIV4 ,GPT4 input clock frequency divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/16,/32,/64"
|
|
line.long 0x08 "GPT4_IRQ_EN,GPT4 IRQ Enabling"
|
|
bitfld.long 0x08 0. " IRQEN ,Enable interrupt of GPT4" "Disabled,Enabled"
|
|
rgroup.long (0xA0+0x0C)++0x03
|
|
line.long 0x00 "GPT4_IRQ_STA,GPT4 IRQ Status"
|
|
bitfld.long 0x00 0. " IRQSTA ,Interrupt status of GPT4" "No interrupt,Interrupt"
|
|
wgroup.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "GPT4_IRQ_ACK,GPT4 IRQ Acknowledgement"
|
|
bitfld.long 0x00 0. " IRQACK ,Interrupt acknowledgement for GPT4" "No effect,Acknowledge"
|
|
rgroup.long (0xA0+0x14)++0x03
|
|
line.long 0x00 "GPT4_COUNT,GPT4 Counter"
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "GPT4_COMPARE,GPT4 Compare Value"
|
|
textline " "
|
|
group.long 0xD0++0x0B "GPT5 Registers"
|
|
line.long 0x00 "GPT5_CON,GPT5 Control"
|
|
bitfld.long 0x00 6. " SW_CG5 ,GPT5 clock stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MODE5 ,GPT5 operation mode" "One-shot,Repeat,Keep-go,Freerun"
|
|
bitfld.long 0x00 1. " CLR5 ,GPT5 counter clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " EN5 ,GPT5 enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPT5_CLK,GPT5 Clock Setting"
|
|
bitfld.long 0x04 4. " CLK5 ,GPT5 clock source" "System clock,RTC clock"
|
|
bitfld.long 0x04 0.--3. " CLKDIV5 ,GPT5 input clock frequency divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/16,/32,/64"
|
|
line.long 0x08 "GPT5_IRQ_EN,GPT5 IRQ Enabling"
|
|
bitfld.long 0x08 0. " IRQEN ,Enable interrupt of GPT5" "Disabled,Enabled"
|
|
rgroup.long (0xD0+0x0C)++0x03
|
|
line.long 0x00 "GPT5_IRQ_STA,GPT5 IRQ Status"
|
|
bitfld.long 0x00 0. " IRQSTA ,Interrupt status of GPT5" "No interrupt,Interrupt"
|
|
wgroup.long (0xD0+0x10)++0x03
|
|
line.long 0x00 "GPT5_IRQ_ACK,GPT5 IRQ Acknowledgement"
|
|
bitfld.long 0x00 0. " IRQACK ,Interrupt acknowledgement for GPT5" "No effect,Acknowledge"
|
|
rgroup.long (0xD0+0x14)++0x03
|
|
line.long 0x00 "GPT5_COUNT,GPT5 Counter"
|
|
group.long (0xD0+0x18)++0x03
|
|
line.long 0x00 "GPT5_COMPARE,GPT5 Compare Value"
|
|
textline " "
|
|
group.long 0x100++0x0B "GPT6 Registers"
|
|
line.long 0x00 "GPT6_CON,GPT6 Control"
|
|
bitfld.long 0x00 6. " SW_CG6 ,GPT6 clock stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MODE6 ,GPT6 operation mode" "One-shot,Repeat,Keep-go,Freerun"
|
|
bitfld.long 0x00 1. " CLR6 ,GPT6 counter clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " EN6 ,GPT6 enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPT6_CLK,GPT6 Clock Setting"
|
|
bitfld.long 0x04 4. " CLK6 ,GPT6 clock source" "System clock,RTC clock"
|
|
bitfld.long 0x04 0.--3. " CLKDIV6 ,GPT6 input clock frequency divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/16,/32,/64"
|
|
line.long 0x08 "GPT6_IRQ_EN,GPT6 IRQ Enabling"
|
|
bitfld.long 0x08 0. " IRQEN ,Enable interrupt of GPT6" "Disabled,Enabled"
|
|
rgroup.long (0x100+0x0C)++0x03
|
|
line.long 0x00 "GPT6_IRQ_STA,GPT6 IRQ Status"
|
|
bitfld.long 0x00 0. " IRQSTA ,Interrupt status of GPT6" "No interrupt,Interrupt"
|
|
wgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "GPT6_IRQ_ACK,GPT6 IRQ Acknowledgement"
|
|
bitfld.long 0x00 0. " IRQACK ,Interrupt acknowledgement for GPT6" "No effect,Acknowledge"
|
|
rgroup.long (0x100+0x14)++0x03
|
|
line.long 0x00 "GPT6_COUNT,GPT6 Counter"
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "GPT6_COMPARE,GPT6 Compare Value"
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "PWM (Pulse Width Modulation)"
|
|
tree "PWM0"
|
|
base ad:0xA2160000
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PWM_0CH_CTRL_ADDR,PWM Control Register"
|
|
bitfld.word 0x00 2. " PWM_0CH_CLK_SEL ,Source clock frequency of PWM" "13MHz,32kHz"
|
|
bitfld.word 0x00 0.--1. " PWM_0CH_CLK_SEL ,Clock prescaler scale of PWM" "fclk,fclk/2,fclk/4,fclk/8"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PWM_0CH_COUNT_ADDR,PWM Max Counter Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_0CH_COUNT ,PWM max. counter value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "PWM_0CH_THRESH_ADDR,PWM Threshold Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_0CH_THRES ,PWM threshold value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM1"
|
|
base ad:0xA2170000
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PWM_1CH_CTRL_ADDR,PWM Control Register"
|
|
bitfld.word 0x00 2. " PWM_1CH_CLK_SEL ,Source clock frequency of PWM" "13MHz,32kHz"
|
|
bitfld.word 0x00 0.--1. " PWM_1CH_CLK_SEL ,Clock prescaler scale of PWM" "fclk,fclk/2,fclk/4,fclk/8"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PWM_1CH_COUNT_ADDR,PWM Max Counter Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_1CH_COUNT ,PWM max. counter value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "PWM_1CH_THRESH_ADDR,PWM Threshold Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_1CH_THRES ,PWM threshold value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM2"
|
|
base ad:0xA0160000
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PWM_2CH_CTRL_ADDR,PWM Control Register"
|
|
bitfld.word 0x00 2. " PWM_2CH_CLK_SEL ,Source clock frequency of PWM" "13MHz,32kHz"
|
|
bitfld.word 0x00 0.--1. " PWM_2CH_CLK_SEL ,Clock prescaler scale of PWM" "fclk,fclk/2,fclk/4,fclk/8"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PWM_2CH_COUNT_ADDR,PWM Max Counter Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_2CH_COUNT ,PWM max. counter value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "PWM_2CH_THRESH_ADDR,PWM Threshold Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_2CH_THRES ,PWM threshold value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM3"
|
|
base ad:0xA0170000
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PWM_3CH_CTRL_ADDR,PWM Control Register"
|
|
bitfld.word 0x00 2. " PWM_3CH_CLK_SEL ,Source clock frequency of PWM" "13MHz,32kHz"
|
|
bitfld.word 0x00 0.--1. " PWM_3CH_CLK_SEL ,Clock prescaler scale of PWM" "fclk,fclk/2,fclk/4,fclk/8"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PWM_3CH_COUNT_ADDR,PWM Max Counter Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_3CH_COUNT ,PWM max. counter value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "PWM_3CH_THRESH_ADDR,PWM Threshold Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_3CH_THRES ,PWM threshold value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM4"
|
|
base ad:0xA0180000
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PWM_4CH_CTRL_ADDR,PWM Control Register"
|
|
bitfld.word 0x00 2. " PWM_4CH_CLK_SEL ,Source clock frequency of PWM" "13MHz,32kHz"
|
|
bitfld.word 0x00 0.--1. " PWM_4CH_CLK_SEL ,Clock prescaler scale of PWM" "fclk,fclk/2,fclk/4,fclk/8"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PWM_4CH_COUNT_ADDR,PWM Max Counter Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_4CH_COUNT ,PWM max. counter value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "PWM_4CH_THRESH_ADDR,PWM Threshold Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_4CH_THRES ,PWM threshold value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM5"
|
|
base ad:0xA0190000
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PWM_5CH_CTRL_ADDR,PWM Control Register"
|
|
bitfld.word 0x00 2. " PWM_5CH_CLK_SEL ,Source clock frequency of PWM" "13MHz,32kHz"
|
|
bitfld.word 0x00 0.--1. " PWM_5CH_CLK_SEL ,Clock prescaler scale of PWM" "fclk,fclk/2,fclk/4,fclk/8"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PWM_5CH_COUNT_ADDR,PWM Max Counter Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_5CH_COUNT ,PWM max. counter value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "PWM_5CH_THRESH_ADDR,PWM Threshold Value Register"
|
|
hexmask.word 0x00 0.--12. 1. " PWM_5CH_THRES ,PWM threshold value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "KS (Keypad Scanner)"
|
|
base ad:0xA20D0000
|
|
width 16.
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "KP_STA,Keypad Status"
|
|
bitfld.word 0x00 0. " STA ,Keypad status" "No key pressed,Key pressed"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "KP_MEM1,Keypad Scanning Output Register"
|
|
bitfld.word 0x00 15. " KEY15 ,Key 15" "Not pressed,Pressed"
|
|
bitfld.word 0x00 14. " KEY14 ,Key 14" "Not pressed,Pressed"
|
|
bitfld.word 0x00 13. " KEY13 ,Key 13" "Not pressed,Pressed"
|
|
bitfld.word 0x00 11. " KEY11 ,Key 11" "Not pressed,Pressed"
|
|
textline " "
|
|
bitfld.word 0x00 10. " KEY10 ,Key 10" "Not pressed,Pressed"
|
|
bitfld.word 0x00 9. " KEY9 ,Key 9" "Not pressed,Pressed"
|
|
bitfld.word 0x00 5. " KEY5 ,Key 5" "Not pressed,Pressed"
|
|
bitfld.word 0x00 4. " KEY4 ,Key 4" "Not pressed,Pressed"
|
|
textline " "
|
|
bitfld.word 0x00 3. " KEY3 ,Key 3" "Not pressed,Pressed"
|
|
bitfld.word 0x00 2. " KEY2 ,Key 2" "Not pressed,Pressed"
|
|
bitfld.word 0x00 1. " KEY1 ,Key 1" "Not pressed,Pressed"
|
|
bitfld.word 0x00 0. " KEY0 ,Key 0" "Not pressed,Pressed"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "KP_MEM2,Keypad Scanning Output Register"
|
|
bitfld.word 0x00 15. " KEY31 ,Key 31" "Not pressed,Pressed"
|
|
bitfld.word 0x00 14. " KEY30 ,Key 30" "Not pressed,Pressed"
|
|
bitfld.word 0x00 13. " KEY29 ,Key 29" "Not pressed,Pressed"
|
|
bitfld.word 0x00 12. " KEY28 ,Key 28" "Not pressed,Pressed"
|
|
textline " "
|
|
bitfld.word 0x00 11. " KEY27 ,Key 27" "Not pressed,Pressed"
|
|
bitfld.word 0x00 10. " KEY26 ,Key 26" "Not pressed,Pressed"
|
|
bitfld.word 0x00 4. " KEY20 ,Key 20" "Not pressed,Pressed"
|
|
bitfld.word 0x00 3. " KEY19 ,Key 19" "Not pressed,Pressed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " KEY18 ,Key 18" "Not pressed,Pressed"
|
|
bitfld.word 0x00 1. " KEY17 ,Key 17" "Not pressed,Pressed"
|
|
bitfld.word 0x00 0. " KEY16 ,Key 16" "Not pressed,Pressed"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "KP_DEBOUNCE,De-bounce Period Setting"
|
|
hexmask.word 0x00 0.--13. 1. " DEBOUNCE ,De-bounce time"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "KP_SCAN_TIMING,Keypad Scan Timing Adjustment Register"
|
|
bitfld.word 0x00 12.--15. " COL_HIGH_PULSE ,COL SCAN high pulse cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.word 0x00 8.--11. " ROW_HIGH_PULSE ,ROW SCAN high pulse cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.word 0x00 4.--7. " COL_SCAN_DIV ,COL SCAN cycle included COL_INTERVAL_DIV and the high pulse period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.word 0x00 0.--3. " ROW_SCAN_DIV ,ROW SCAN cycle included ROW_INTERVAL_DIV and the high pulse period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
if (((per.word(ad:0xA20D0000+0x20)&0x01)==0x01))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "KP_SEL,Keypad Selection Register"
|
|
bitfld.word 0x00 12. " KP1_COL_SEL[2] ,Column 2 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " [1] ,Column 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " [0] ,Column 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " KP1_ROW_SEL[2] ,Row 2 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " [1] ,Row 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " [0] ,Row 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--3. " DUMMY2 ,DUMMY2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0. " KP_SEL ,Keypad select" "Single,Double"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "KP_SEL,Keypad Selection Register"
|
|
bitfld.word 0x00 1.--3. " DUMMY2 ,DUMMY2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0. " KP_SEL ,Keypad select" "Single,Double"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "KP_EN,Keypad Enable Register"
|
|
bitfld.word 0x00 0. " KP_EN ,Keypad enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPC (General Purpose Counter)"
|
|
base ad:0xA21E0000
|
|
width 25.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPCOUNTER_CON_SET/CLR,GPCOUNTER Control Register"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GPC_EN ,GPC status" "Disabled,Enabled"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "GPCOUNTER_MISC,GPCOUNTER MISC Setting"
|
|
bitfld.long 0x00 24. " GPC_INV_EN ,Rising/Falling edge detect" "Rising,Falling"
|
|
bitfld.long 0x00 16. " GPC_INT_EN ,GPC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GPC_BCLK_SEL ,GPC clock select" "26MHz,32kHz"
|
|
line.long 0x04 "GPCOUNTER_DEBOUNCE,GPCOUNTER De-bounce Period Setting"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPC_PAD_DEB ,De-bounce time"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "GPCOUNTER_DATA,GPCOUNTER Counter for Clear"
|
|
in
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPCOUNTER_THRESHOLD,GPCOUNTER Threshold"
|
|
hexmask.long 0x00 0.--30. 1. " GPC_THRESHOLD ,GPC threshold"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "GPCOUNTER_INTERRUPT_STA,GPCOUNTER Interrupt Status"
|
|
bitfld.long 0x00 0. " GPC_INT_STA ,GPC interrupt status" "Interrupt,No interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AUXADC (Auxiliary ADC Unit)"
|
|
base ad:0xA0240000
|
|
width 14.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "AUXADC_CON1,Auxiliary ADC Control Register 1"
|
|
bitfld.word 0x00 15. " IMM_[15] ,Channel 15 immediate mode" "Not selected,Selected"
|
|
bitfld.word 0x00 14. " [14] ,Channel 14 immediate mode" "Not selected,Selected"
|
|
bitfld.word 0x00 13. " [13] ,Channel 13 immediate mode" "Not selected,Selected"
|
|
bitfld.word 0x00 12. " [12] ,Channel 12 immediate mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 11. " [11] ,Channel 11 immediate mode" "Not selected,Selected"
|
|
bitfld.word 0x00 8. " [8] ,Channel 8 immediate mode" "Not selected,Selected"
|
|
bitfld.word 0x00 7. " [7] ,Channel 7 immediate mode" "Not selected,Selected"
|
|
bitfld.word 0x00 6. " [6] ,Channel 6 immediate mode" "Not selected,Selected"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "AUXADC_CON3,Auxiliary ADC Control Register 3"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto-sample mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " SOFT_RST ,Software reset AUXADC state machine" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " AUXADC_STA ,AUXADC state" "Idle,Busy"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "AUXADC_DAT6,Auxiliary ADC Channel 6 Register (GPDAC)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT6 ,Sampled data for channel 6"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "AUXADC_DAT7,Auxiliary ADC Channel 7 Register (Audio DL_HPL)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT7 ,Sampled data for channel 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "AUXADC_DAT8,Auxiliary ADC Channel 8 Register (Audio DL_HPR)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT8 ,Sampled data for channel 8"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "AUXADC_DAT11,Auxiliary ADC Channel 11 Register (External)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT11 ,Sampled data for channel 11"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "AUXADC_DAT12,Auxiliary ADC Channel 12 Register (External)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT12 ,Sampled data for channel 12"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "AUXADC_DAT13,Auxiliary ADC Channel 13 Register (External)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT13 ,Sampled data for channel 13"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "AUXADC_DAT14,Auxiliary ADC Channel 14 Register (External)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT14 ,Sampled data for channel 14"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "AUXADC_DAT15,Auxiliary ADC Channel 15 Register (External)"
|
|
hexmask.word 0x00 0.--11. 1. " DAT15 ,Sampled data for channel 15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPDAC (General Purpose DAC)"
|
|
base ad:0xA21B0000
|
|
width 16.
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SWRST,Soft Reset Register"
|
|
bitfld.word 0x00 0. " SWRST ,Reset all register" "No reset,Reset"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "OUTPUT_COMMAND,Output Command Register"
|
|
bitfld.word 0x00 4. " REPEAT_EN ,Repeat mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " OUTPUT_EN ,Output data enable" "Disabled,Enabled"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "OUTPUT_REGION,Range Of Output Register"
|
|
hexmask.word.byte 0x00 8.--14. 0x01 " OUTPUT_END_ADDR ,Range of output (end of address)"
|
|
hexmask.word.byte 0x00 0.--6. 0x01 " OUTPUT_START_ADDR ,Range of output (start of address)"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "WRITE_COMMAND,Write Command Register"
|
|
hexmask.long.word 0x00 8.--17. 1. " SRAM_DATA ,Write in SRAM.SRAM_data"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SRAM_ADDR ,Write in SRAM.SRAM address"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "GPDAC_SRAM_PWR,SRAM Power Control Register"
|
|
bitfld.word 0x00 3. " GPDAC_SLEEPB ,SRAM sleep control" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " GPDAC_PD ,SRAM power down control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " GPDAC_ISOINTB ,SRAM ISO control" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " GPDAC_RET ,SRAM retention control" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACCDET (Accessory Detector)"
|
|
base ad:0xA21F0000
|
|
width 25.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "ACCDET_RSTB,ACCDET Software Reset Register"
|
|
bitfld.long 0x00 0. " RSTB ,Reset ACCDET unit" "No reset,Reset"
|
|
line.long 0x04 "ACCDET_CTRL,ACCDET Control Register"
|
|
bitfld.long 0x04 0. " ACCDET_EN ,Enable ACCDET unit" "Disabled,Enabled"
|
|
line.long 0x08 "ACCDET_STATE_SWCTRL,ACCDET State Switch Control Register"
|
|
bitfld.long 0x08 4. " MBIAS_PWM_EN ,Enable PWM of ACCDET MBIAS unit" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " VTH_PWM_EN ,Enable PWM of ACCDET voltage threshold unit" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CMP_PWM_EN ,Enable PWM of ACCDET comparator" "Disabled,Enabled"
|
|
line.long 0x0C "ACCDET_PWM_WIDTH,ACCDET PWM Width Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PWM_WIDTH ,ACCDET PWM width"
|
|
line.long 0x10 "ACCDET_PWM_THRESH,ACCDET PWM Threshold Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " PWM_THRESH ,ACCDET PWM threshold"
|
|
group.long 0x24++0x0F
|
|
line.long 0x00 "ACCDET_EN_DELAY_NUM,ACCDET Enable Delay Number Register"
|
|
bitfld.long 0x00 15. " FALL_DELAY_NUM ,Falling delay cycle compared to CMP PWM waveform" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " RISE_DELAY_NUM ,Rising delay cycle compared to PWM waveform"
|
|
line.long 0x04 "ACCDET_PWM_IDLE_VALUE,ACCDET PWM IDLE Value Register"
|
|
bitfld.long 0x04 2. " MBIAS ,IDLE value of MBIAS PWM" "Busy,Idle"
|
|
bitfld.long 0x04 1. " VTH ,IDLE value of VTH PWM" "Busy,Idle"
|
|
bitfld.long 0x04 0. " CMP ,IDLE value of CMP PWM" "Busy,Idle"
|
|
line.long 0x08 "ACCDET_DEBOUNCE0,ACCDET Debounce0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DEBOUNCE0 ,De-bounce time for hook key press event"
|
|
line.long 0x0C "ACCDET_DEBOUNCE1,ACCDET Debounce1 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DEBOUNCE1 ,De-bounce time for plug-in event"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "ACCDET_DEBOUNCE3,ACCDET Debounce3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DEBOUNCE3 ,De-bounce time for plug-out event"
|
|
line.long 0x04 "ACCDET_IRQ_STS,ACCDET Interrupt Status Register"
|
|
bitfld.long 0x04 8. " IRQ_CLR ,Clear interrupt status of ACCDET unit" "No effect,Cleared"
|
|
rbitfld.long 0x04 0. " IRQ ,Interrupt status of ACCDET unit" "No interrupt,Interrupt"
|
|
rgroup.long 0x40++0x1B
|
|
line.long 0x00 "ACCDET_CURR_IN,ACCDET Current Input Status Register"
|
|
bitfld.long 0x00 0.--1. " CURR_IN ,Current input status of ACCDET unit" "0,1,2,3"
|
|
line.long 0x04 "ACCDET_SAMPLE_IN,ACCDET Current Sampled Status Register"
|
|
bitfld.long 0x04 0.--1. " SAMPLE_IN ,Samples input status of ACCDET unit" "0,1,2,3"
|
|
line.long 0x08 "ACCDET_MEMOIZED_IN,ACCDET Current Memorized Status Register"
|
|
bitfld.long 0x08 0.--1. " MEMORIZED_IN ,Memorized input status of ACCDET unit" "0,1,2,3"
|
|
line.long 0x0C "ACCDET_LAST_MEMOIZED_IN,ACCDET Last Memorized Input Status Register"
|
|
bitfld.long 0x0C 0.--1. " LAST_MEMORIZED_IN ,Last memorized input status of ACCDET unit" "0,1,2,3"
|
|
line.long 0x10 "ACCDET_FSM_STATE,ACCDET FSM Status Register Register"
|
|
bitfld.long 0x10 0.--2. " FSM_SATE ,State of ACCDET unit finite-state-machine" "Idle,Sample,Debounce,Check,Memorized,IRQ,?..."
|
|
line.long 0x14 "ACCDET_CURR_DEBOUNCE,ACCDET Current De-bounce Status Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " CURR_DEBOUNCE ,Currently used de-bounce time setting"
|
|
line.long 0x18 "ACCDET_VERSION,ACCDET Version Code Register"
|
|
bitfld.long 0x18 0.--1. " ACCDET_VERSION ,Version code for ACCDET" "0,1,2,3"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ACCDET_IN_DEFAULT,Default Value Of Accdet_in Register"
|
|
bitfld.long 0x00 4. " ACCDET_IN_DEFAULT_REFRESH_EN ,Enable signal for whether to load accdet_in_default" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " ACCDET_IN_DEFAULT ,Default value of accdet_in set by software" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xA0010000
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TRNG_CTRL,TRNG Control Register"
|
|
rbitfld.long 0x00 31. " TRNG_RDY ,Random data ready status" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " TRNF_FREERUN ,Enable free run (interference) mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TRNG_START ,Start/terminate random number generation" "Stopped,Started"
|
|
line.long 0x04 "TRNG_TIME,TRNG Time Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " SAMPLE_CNT ,TRNG data sampling time"
|
|
hexmask.long.byte 0x04 16.--23. 1. " UNGATE_CNT ,TRNG inverter ungating time interval"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LATCH_CNT ,TRNG inverter latching time interval"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SYSCLK_CNT ,TRNG SYSCLK frequency"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TRNG_DATA,TRNG Data Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRNG_CONF,TRNG Configure Register"
|
|
bitfld.long 0x00 31. " FR_IRQ_EN ,Enable IRQ during free run mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 6.--17. 1. " TIMEOUT_LIMIT ,Sampling times limit"
|
|
bitfld.long 0x00 5. " VON_EN ,Enable Von-Neumann extractor" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " RO_EN ,Enable ring oscillator" ",H-FIRO,H-RO,,H-GARO,?..."
|
|
bitfld.long 0x00 0.--1. " RO_OUT_SEL ,Select RO to connect to debug out" "H-FIRO,H-RO,H-GARO,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRNG_INT_SET,Interrupt Setting Register"
|
|
bitfld.long 0x00 1. " INT_[1] ,Successful random number generation interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Timeout error interrupt" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRNG_INT_CLR,Interrupt Clean Register"
|
|
bitfld.long 0x00 1. " CLR_[1] ,Successful random number generation interrupt clear" "No clear,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Timeout error interrupt clear" "No clear,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AFE (Audio Front End)"
|
|
base ad:0x82CD0000
|
|
width 20.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "AFE_VMCU_CON0,AFE Voice MCU Control Register"
|
|
bitfld.word 0x00 0. " VIRQON ,Turn on 8k interrupt" "Turned off,Turned on"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "AFE_VMCU_CON1,AFE Voice MCU Control Register 1"
|
|
bitfld.word 0x00 12. " DUAL_MIC ,Dual mic control" "Signal,Dual"
|
|
bitfld.word 0x00 10. " VMODE32K ,Configure up-link 32K recording" "VMODE4K RG,32K sample rate"
|
|
bitfld.word 0x00 9. " VMODE4K ,Select DSP data mode" "8K in-band,4K in-band"
|
|
bitfld.word 0x00 7. " VRSDON ,SDM level for VBITX (up-link)" "2 levels,3 levels"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "AFE_VMCU_CON2,AFE Voice MCU Control Register 2"
|
|
bitfld.word 0x00 15. " VDC_COMP_EN ,Enable DC offset compensation" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " VTX_CK_PHASE ,Select phase selection for clock to analog" "Falling edge,Rising edge"
|
|
bitfld.word 0x00 0.--5. " VSDM_GAIN ,Gain settings at voice SDM input" "0/64,1/64,2/64,3/64,4/64,5/64,6/64,7/64,8/64,9/64,10/64,11/64,12/64,13/64,14/64,15/64,16/64,17/64,18/64,19/64,20/64,21/64,22/64,23/64,24/64,25/64,26/64,27/64,28/64,29/64,30/64,31/64,32/64,33/64,34/64,35/64,36/64,37/64,38/64,39/64,40/64,41/64,42/64,43/64,44/64,45/64,46/64,47/64,48/64,49/64,50/64,51/64,52/64,53/64,54/64,55/64,56/64,57/64,58/64,59/64,60/64,61/64,62/64,63/64"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "AFE_VDB_CON,AFE Voice DAI Bluetooth Control Register"
|
|
bitfld.word 0x00 14.--15. " PCM_CK_MODE ,Pcm clock (dai_clk) rate mode" "256kHz,512kHz,1024kHz,2048kHz"
|
|
bitfld.word 0x00 12. " VBT_LOOP_BACK ,Loop back test for DAI/BT interface" "No loopback,Loopback"
|
|
bitfld.word 0x00 10. " VBT_LOOP ,Loop test for DAI/BT interface" "No loopback,Loopback"
|
|
bitfld.word 0x00 5. " VDAION ,Turn on DAI function" "Turned off,Turned on"
|
|
textline " "
|
|
bitfld.word 0x00 4. " VBTON ,Turn on Bluetooth PCM function" "Turned off,Turned on"
|
|
bitfld.word 0x00 3. " VBTSYNC ,Bluetooth PCM frame sync type" "Short sync,Long sync"
|
|
bitfld.word 0x00 0.--2. " VBTSLEN ,Bluetooth PCM long frame sync length" "0,1,2,3,4,5,6,7"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "AFE_VLB_CON,AFE Voice Loopback Mode Control Register"
|
|
bitfld.word 0x00 7. " ENGEN_OPT ,Engen generator option" "Origin engen,New engen"
|
|
bitfld.word 0x00 6. " VINTINSEL ,Select DL data" "1st voice,2st voice"
|
|
bitfld.word 0x00 5. " ENGEN_OPT ,Bypass DSP loopback mode" "Normal,Bypassed"
|
|
bitfld.word 0x00 4. " VDSPCSMODE ,DSP COSIM mode" "Normal,Cosim"
|
|
textline " "
|
|
bitfld.word 0x00 3. " VDAPIN_CH_[1] ,MODEMSIM voice loopback channel 1 control" "Normal,Loopback"
|
|
bitfld.word 0x00 2. " [0] ,MODEMSIM voice loopback channel 0 control" "Normal,Loopback"
|
|
bitfld.word 0x00 1. " VINTINMODE ,Downlink data = uplink data" "Normal,Loopback"
|
|
bitfld.word 0x00 0. " VDECINMODE ,Decimator input mode control" "Normal,Loopback"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "AFE_VMCU_CON3,AFE Voice MCU Control Register 3"
|
|
bitfld.word 0x00 8. " SDMLP_ULTODL ,UL sigma delta data loopback to DL sigma delta data enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VSDM_DATA_MONO ,Rch output data = Lch output data enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " SDMLP_DLTOUL ,DL sigma delta data loopback to UL sigma delta data enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SDM_CK_PHASE ,Select phase of SDM clock" "Falling edge,Rising edge"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "AFE_AMCU_CON0,AFE Audio MCU Control Register 0"
|
|
bitfld.word 0x00 0. " AIRQON ,Turn on audio interrupt operation" "Turned off,Turned on"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "AFE_AMCU_CON1,AFE Audio MCU Control Register 1"
|
|
bitfld.word 0x00 14. " MONO_SEL ,Select mono mode" "Normal,Mono"
|
|
bitfld.word 0x00 12. " I2S_1XOUT_SEL ,Select audio 1x data to I2S mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--9. " AFS ,Sampling frequency setting" "8kHz,11.025kHz,12kHz,,16kHz,22.05kHz,24kHz,,32kHz,44.1kHz,48kHz,?..."
|
|
bitfld.word 0x00 4.--5. " ARAMPSP ,Select ramp up/down speed" "8,16,24,32"
|
|
textline " "
|
|
bitfld.word 0x00 3. " AMUTER ,Mute audio R-channel with soft ramp up/down" "Not muted,Muted"
|
|
bitfld.word 0x00 2. " AMUTEL ,Mute audio L-channel with soft ramp up/down" "Not muted,Muted"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "AFE_EDI_CON,AFE EDI Control Register"
|
|
bitfld.word 0x00 15. " EN2 ,Enable EDI PAD output" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " UL_TOI2SDSP ,Force UL data to dsp_i2s port" "Not forced,Forced"
|
|
bitfld.word 0x00 12.--13. " I2S_OUT_MODE ,I2S output mode" "1X,2X,4X,?..."
|
|
bitfld.word 0x00 10. " ULTOEDI ,Up-link data to I2S enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " EDI_LPBK_MODE ,Control loopback mode: EDI_RX = EDI_TX" "Normal,Loopback"
|
|
bitfld.word 0x00 8. " DIR ,Serial data bit direction" "Only output,Both"
|
|
bitfld.word 0x00 2.--6. " WCYCLE ,Clock cycle count in a word" ",,,,,,,,,,,,,,,15,,,,,,,,,,,,,,,,31"
|
|
bitfld.word 0x00 1. " FMT ,EDI format selection" "EIAJ,I2S"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,Enable EDI" "Disabled,Enabled"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "AFE_AMCU_CON2,AFE Audio Control Register 2"
|
|
bitfld.word 0x00 15. " ADC_COMP_EN ,Enable DC offset compensation" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " EDI_WS_OPTION ,Optional setting for I2S" "0,1"
|
|
bitfld.word 0x00 10. " PREDIT_EN ,Enable pre-distortion function" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " EDI_SEL ,EDI input data selection" "From DSP,From EDI"
|
|
textline " "
|
|
bitfld.word 0x00 0.--5. " ASDM_GAIN ,Gain settings at audio SDM input" "0/64,1/64,2/64,3/64,4/64,5/64,6/64,7/64,8/64,9/64,10/64,11/64,12/64,13/64,14/64,15/64,16/64,17/64,18/64,19/64,20/64,21/64,22/64,23/64,24/64,25/64,26/64,27/64,28/64,29/64,30/64,31/64,32/64,33/64,34/64,35/64,36/64,37/64,38/64,39/64,40/64,41/64,42/64,43/64,44/64,45/64,46/64,47/64,48/64,49/64,50/64,51/64,52/64,53/64,54/64,55/64,56/64,57/64,58/64,59/64,60/64,61/64,62/64,63/64"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "AFE_DAC_TEST,Audio/Voice DAC SineWave Generator Register"
|
|
bitfld.word 0x00 15. " VON ,Voice DAC input" "Voice samples,Sine waves"
|
|
bitfld.word 0x00 14. " AON ,Audio DAC input" "Voice samples,Sine waves"
|
|
bitfld.word 0x00 13. " MUTE ,Mute switch" "Not muted,Muted"
|
|
bitfld.word 0x00 8.--10. " AMP_DIV ,Amplitude setting" "1/128,1/64,1/32,1/16,1/8,1/4,1/2,Full scale"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " FREQ_DIV ,Frequency setting"
|
|
textline " "
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "AFE_VAM_SET,Audio/Voice Interactive Mode Setting Register"
|
|
bitfld.word 0x00 15. " A2V ,Redirect audio interrupt to voice interrupt" "Voice interrupt/audio interrupt,Audio interrupt/no interrupt"
|
|
bitfld.word 0x00 0.--2. " PER_VAL ,Counter reset value for audio interrupt generation period setting" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "AFE_AMCU_CON3,AFE Audio Control Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " PRE_A2 ,A2 parameter for pre-distortion"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "AFE_AMCU_CON4,AFE Audio Control Register 4"
|
|
hexmask.word 0x00 0.--11. 1. " PRE_A3 ,A3 parameter for pre-distortion"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "AFE_DC_DBG_1,AFE DC Compensation Debug Register 1"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "AFE_DC_DBG_2,AFE DC Compensation Debug Register 2"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "AFE_DC_DBG_3,AFE DC Compensation Debug Register 3"
|
|
bitfld.word 0x00 15. " DBG_DC_SEL ,DBG_DC_SEL" "DC compensation,Stage output"
|
|
bitfld.word 0x00 4.--7. " AFE_DC_DBG_2_1 ,AFE right channel 8X dc compensation/gain output value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " AFE_DC_DBG_1_1 ,AFE left channel 8X dc compensation/gain output value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x140++0x01
|
|
line.word 0x00 "AFE_ACHECK_SUM_R,AFE Checksum Register 0"
|
|
rgroup.word 0x144++0x01
|
|
line.word 0x00 "AFE_ACHECK_SUM_L,AFE Checksum Register 1"
|
|
rgroup.word 0x148++0x01
|
|
line.word 0x00 "AFE_MUTE_STA,AFE Mute Status Register"
|
|
bitfld.word 0x00 3. " UNMUTE_DONE_L ,UNMUTE done L status" "Not done,Done"
|
|
bitfld.word 0x00 2. " UNMUTE_DONE_R ,UNMUTE done R status" "Not done,Done"
|
|
bitfld.word 0x00 1. " MUTE_DONE_L ,MUTE done L status" "Not muted,Muted"
|
|
bitfld.word 0x00 0. " MUTE_DONE_R ,MUTE done R status" "Not muted,Muted"
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "AFE_AMCU_CON5,AFE Audio MCU Control Register 5"
|
|
bitfld.word 0x00 8. " SDMLP_ULTODL ,UL sigma delta data loopback to DL sigma delta data enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VSDM_DATA_MONO ,Rch output data = Lch output data enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " SDMLP_DLTOUL ,DL sigma delta data loopback to UL sigma delta data enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SDM_CK_PHASE ,Select phase of SDM clock" "Falling edge,Rising edge"
|
|
group.word 0x184++0x01
|
|
line.word 0x00 "AFE_AMCU_CON6,AFE Audio MCU Control Register 6"
|
|
group.word 0x188++0x01
|
|
line.word 0x00 "AFE_AMCU_CON7,AFE Audio MCU Control Register 7"
|
|
group.word 0x190++0x01
|
|
line.word 0x00 "AFE_DBG_RD_PRE,AFE MCU Debug Mode Reading SRAM Out Register"
|
|
bitfld.word 0x00 10.--11. " MEM ,Memory" ",Data,Coefficient,DSP co-processor"
|
|
hexmask.word 0x00 0.--9. 0x01 " AFE_DBG_RD_PRE ,Read address"
|
|
group.word 0x194++0x01
|
|
line.word 0x00 "AFE_DBG_MD_CON0,AFE Debug Mode Control Register"
|
|
rbitfld.word 0x00 1. " DBG_DONE ,Debug done signal" "Not done,Done"
|
|
bitfld.word 0x00 0. " DBG_TRIG ,Start running debug mode" "Not started,Started"
|
|
group.word 0x198++0x01
|
|
line.word 0x00 "AFE_DBG_MD_CON1,AFE Debug Mode Control Register 1"
|
|
bitfld.word 0x00 15. " DBG_MD ,Enable debug mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--14. " MODE_SEL ,Select debug mode" "Step 1,Next n cycle,Run to break point,Run 1X,,Run to n 1X,?..."
|
|
hexmask.word 0x00 0.--11. 1. " DBG_MD_VAL ,Corresponding value for different debug mode"
|
|
rgroup.word 0x19C++0x01
|
|
line.word 0x00 "AFE_DBG_APB_STATUS,AFE MCU Status Register"
|
|
bitfld.word 0x00 2. " DBGR_OK ,Status for debug mode reading SRAM" "Not done,Done"
|
|
bitfld.word 0x00 1. " APBR_OK ,Status for read SRAM data" "Not done,Done"
|
|
bitfld.word 0x00 0. " APBW_ACK ,Status for writing data into SRAM" "Not done,Done"
|
|
group.word 0x1A0++0x01
|
|
line.word 0x00 "AFE_VMCU_CON4,AFE Voice MCU Control Register 4"
|
|
group.word 0x1CC++0x01
|
|
line.word 0x00 "AFE_CMPR_CNTR,AFE Compare Counter Control Register"
|
|
bitfld.word 0x00 15. " AVCNTR_ERR_SIGNAL ,Compare counter for 1X enable error flag" "No error,Error"
|
|
hexmask.word 0x00 0.--11. 1. " CMPR_CNTR ,Compare counter"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "AFE_DBG_RD_DAT,AFE Debug Mode - Reading SRAM Data Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " DBG_RD_DAT ,Debug SRAM data"
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "AFE_APBMEM_RD_DAT,AFE MCU Reading SRAM Data Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AFE_APBMEM_RD_DAT ,AFE MCU SRAM data"
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "AFE_APBMEM_RD,AFE MCU Read SRAM Request Register"
|
|
bitfld.word 0x00 10.--11. " MEM ,Memory" ",Data,Coefficient,DSP co-processor"
|
|
hexmask.word 0x00 0.--9. 0x01 " AFE_APBMEM_RD ,Read address"
|
|
group.word 0x1EC++0x01
|
|
line.word 0x00 "AFE_PC_1X_IDX,AFE Program 1X IDX Register"
|
|
hexmask.word 0x00 0.--11. 0x01 " AFE_PC_1X_IDX ,DSP co-processor idle address"
|
|
group.word 0x1F0++0x01
|
|
line.word 0x00 "AFE_DBG_SIG,AFE 8X/Buffer/Mux Debug Register"
|
|
bitfld.word 0x00 15. " DBG_1XDAT_EN ,Enable 1X sample data for debug input" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " V8X_LPBK ,Force voice down-link 8x output loopback to up-link 8x" "Not forced,Forced"
|
|
bitfld.word 0x00 6. " DMIC_SWAP ,Swap digital mic input source" "Not swapped,Swapped"
|
|
rbitfld.word 0x00 5. " AAFE_ALN ,AAFE_ON align 1x enable signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " VAFE_ALN ,VAFE_ON align 1x enable signal" "Disabled,Enabled"
|
|
rbitfld.word 0x00 3. " VDL ,VDL debug signal" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " VUL ,VLL debug signal" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " ADL ,ADL debug signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " I2S ,I2S debug signal" "Disabled,Enabled"
|
|
rgroup.word 0x1F4++0x01
|
|
line.word 0x00 "AFE_PC_OUT_DBG,AFE Program PC Address Register"
|
|
hexmask.word 0x00 0.--11. 1. " PC_OUT ,Current DSP co-processor programming counter output for debugging"
|
|
group.word 0x1F8++0x01
|
|
line.word 0x00 "AFE_DBG_1XDAT,DBG_1XDAT Register"
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "AFE_COSIM_RG,AFE COSIM RG Test Register"
|
|
bitfld.word 0x00 1. " FPGA_DL2UL_LPBK ,FPGA loopback mode" "Normal,Loopback"
|
|
bitfld.word 0x00 0. " UL_SINE_OUT ,Sine table output for up-link data enable" "Disabled,Enabled"
|
|
group.word 0x210++0x01
|
|
line.word 0x00 "AFE_MCU_CON0,AFE MCU CON0 Register"
|
|
bitfld.word 0x00 0. " AFE_ON ,Turn on the audio front end" "Turned off,Turned on"
|
|
group.word 0x214++0x01
|
|
line.word 0x00 "AFE_MCU_CON1,AFE MCU CON1 Register"
|
|
bitfld.word 0x00 3. " UDSP_DL_ON ,Turn on UDSP DL function" "Turned off,Turned on"
|
|
bitfld.word 0x00 2. " A_IF_DL_ON ,Turn on a_interface DL function" "Turned off,Turned on"
|
|
bitfld.word 0x00 1. " UDSP_UL_ON ,Turn on UDSP UL function" "Turned off,Turned on"
|
|
bitfld.word 0x00 0. " A_IF_UL_ON ,Turn on a_interface UL function" "Turned off,Turned on"
|
|
group.word 0x1AC++0x01
|
|
line.word 0x00 "AFE_VMCU_CON5,AFE Voice MCU Control Register 5"
|
|
bitfld.word 0x00 13.--15. " LCH_PHASE ,Select digital mic LCH data phase from phase 0~phase 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " RCH_PHASE ,Select digital mic RCH data phase from phase 0~phase 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 9. " CK_PHASE ,Select digital mic clock latch phase" "L,R"
|
|
bitfld.word 0x00 4. " DIG_MIC_EN ,Enable digital mic" "Analog mic,Digital mic"
|
|
textline " "
|
|
bitfld.word 0x00 0. " D3P25M_SEL ,Select digital mic sample rate" "1.625M,3.25M"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "AFE_SLV_I2S_CON,AFE Slave I2S Control Register"
|
|
bitfld.long 0x00 31. " SLV_I2S_EN ,Enable slave I2S" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AFE_FOC_EN ,Enable SRC function in slave I2S" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SLV_I2S_BIT_SWAP ,Swap MSB 16 bits and LSB 16 bits" "Not swapped,Swapped"
|
|
bitfld.long 0x00 17. " SLV_I2S_BYPASS_SRC ,Bypassed SRC function in slave I2S" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_I2S_2CH_SEL ,Slave I2S mono or stereo mode" "Speech,Stereo"
|
|
bitfld.long 0x00 12.--15. " SLV_I2S_MODE ,Sampling frequency setting" "8kHz,11.025kHz,12kHz,,16kHz,22.05kHz,24kHz,,32kHz,44.1kHz,48kHz,?..."
|
|
bitfld.long 0x00 1. " SLV_I2S_FMT ,EDI format" "EIAJ,I2S"
|
|
bitfld.long 0x00 0. " SLV_I2S_PCM_SEL ,Select PCM or slave I2S" "PCM,Slave I2S"
|
|
group.word 0x310++0x0B "Slave I2S TX"
|
|
line.word 0x00 "AFE_FOC_TX_CON0,AFE Slave I2S TX FOC Control Register 0"
|
|
bitfld.word 0x00 15. " FREQ_EST_MODE ,Frequency offset estimation mode" "512 cycles,1024 cycles"
|
|
bitfld.word 0x00 14. " N_STEP_MODE ,Control the reference for step_change" "Step,Step_target"
|
|
bitfld.word 0x00 8.--13. " STEP_EST_UPDATE_LV ,Control step update threshold for frequency tracking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 4.--7. " MON ,Select data monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STEP_LIM_MODE ,Control maximum tracking frequency offset" "270 ppm,540 ppm"
|
|
bitfld.word 0x00 2. " PTR_TRACK_EN ,Enable signal to tracking frequency" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " FT_EN ,Enable signals for frequency tracking" "Disabled,Enabled"
|
|
line.word 0x02 "AFE_FOC_TX_CON1,AFE Slave I2S TX FOC Control Register 1"
|
|
bitfld.word 0x02 15. " MANUAL ,Control frequency tracking mode" "Auto,Manual"
|
|
hexmask.word 0x02 0.--12. 1. " STEP_MANUAL ,Step manual"
|
|
line.word 0x04 "AFE_FOC_TX_CON2,AFE Slave I2S TX FOC Control Register 2"
|
|
bitfld.word 0x04 12.--15. " N_STEP_JUMP_CON_[3] ,Control input samples to change step when step change is larger than power (2, step_change_con3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x04 8.--11. " [2] ,Control input samples to change step when step change is smaller than power (2, step_change_con2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x04 4.--7. " [1] ,Control input samples to change step when step change is smaller than power (2, step_change_con1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x04 0.--3. " [0] ,Control input samples to change step when step change is smaller than power (2, step_change_con0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x06 "AFE_FOC_TX_CON3,AFE Slave I2S TX FOC Control Register 3"
|
|
hexmask.word 0x06 0.--10. 1. " STEP_CHANGE_CON0 ,Control boundary between N_STEP_JUMP0 and N_STEP_JUMP1"
|
|
line.word 0x08 "AFE_FOC_TX_CON4,AFE Slave I2S TX FOC Control Register 4"
|
|
hexmask.word 0x08 0.--10. 1. " STEP_CHANGE_CON1 ,Control boundary between N_STEP_JUMP1 and N_STEP_JUMP2"
|
|
line.word 0x0A "AFE_FOC_TX_CON5,AFE Slave I2S TX FOC Control Register 5"
|
|
hexmask.word 0x0A 0.--10. 1. " STEP_CHANGE_CON2 ,Control boundary between N_STEP_JUMP2 and N_STEP_JUMP3"
|
|
group.word 0x330++0x0B "Slave I2S RX"
|
|
line.word 0x00 "AFE_FOC_RX_CON0,AFE Slave I2S RX FOC Control Register 0"
|
|
bitfld.word 0x00 15. " FREQ_EST_MODE ,Frequency offset estimation mode" "512 cycles,1024 cycles"
|
|
bitfld.word 0x00 14. " N_STEP_MODE ,Control the reference for step_change" "Step,Step_target"
|
|
bitfld.word 0x00 8.--13. " STEP_EST_UPDATE_LV ,Control step update threshold for frequency tracking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 4.--7. " MON ,Select data monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STEP_LIM_MODE ,Control maximum tracking frequency offset" "270 ppm,540 ppm"
|
|
bitfld.word 0x00 2. " PTR_TRACK_EN ,Enable signal to tracking frequency" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " FT_EN ,Enable signals for frequency tracking" "Disabled,Enabled"
|
|
line.word 0x02 "AFE_FOC_RX_CON1,AFE Slave I2S RX FOC Control Register 1"
|
|
bitfld.word 0x02 15. " MANUAL ,Control frequency tracking mode" "Auto,Manual"
|
|
hexmask.word 0x02 0.--12. 1. " STEP_MANUAL ,Step manual"
|
|
line.word 0x04 "AFE_FOC_RX_CON2,AFE Slave I2S RX FOC Control Register 2"
|
|
bitfld.word 0x04 12.--15. " N_STEP_JUMP_CON_[3] ,Control input samples to change step when step change is larger than power (2, step_change_con3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x04 8.--11. " [2] ,Control input samples to change step when step change is smaller than power (2, step_change_con2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x04 4.--7. " [1] ,Control input samples to change step when step change is smaller than power (2, step_change_con1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x04 0.--3. " [0] ,Control input samples to change step when step change is smaller than power (2, step_change_con0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x06 "AFE_FOC_RX_CON3,AFE Slave I2S RX FOC Control Register 3"
|
|
hexmask.word 0x06 0.--10. 1. " STEP_CHANGE_CON0 ,Control boundary between N_STEP_JUMP0 and N_STEP_JUMP1"
|
|
line.word 0x08 "AFE_FOC_RX_CON4,AFE Slave I2S RX FOC Control Register 4"
|
|
hexmask.word 0x08 0.--10. 1. " STEP_CHANGE_CON1 ,Control boundary between N_STEP_JUMP1 and N_STEP_JUMP2"
|
|
line.word 0x0A "AFE_FOC_RX_CON5,AFE Slave I2S RX FOC Control Register 5"
|
|
hexmask.word 0x0A 0.--10. 1. " STEP_CHANGE_CON2 ,Control boundary between N_STEP_JUMP2 and N_STEP_JUMP3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "2D Acceleration"
|
|
base ad:0xA0440000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "G2D_START,G2D Start Register"
|
|
bitfld.word 0x00 0. " START ,Start G2D engine" "Not started,Started"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "G2D_MODE_CON,G2D Mode Control Register"
|
|
bitfld.long 0x00 0.--2. " ENG_MODE ,2D engine function mode" ",Bitblt,?..."
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "G2D_RESET,G2D Reset Register"
|
|
bitfld.word 0x00 1. " HRST ,G2D hard reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " WRST ,G2D warm reset" "No reset,Reset"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "G2D_STATUS,G2D Status Register"
|
|
bitfld.word 0x00 1. " TBUSY ,2D engine busy status" "Idle,Busy"
|
|
bitfld.word 0x00 0. " BUSY ,Transaction busy status" "Idle,Busy"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "G2D_IRQ,G2D Interrupt Register"
|
|
bitfld.long 0x00 16. " FLAG0 ,2D interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FLAG0_IRQ_EN ,2D engine interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "G2D_SLOW_DOWN,G2D Slow Down Control Register"
|
|
bitfld.long 0x04 31. " EN ,Enable slow down mechanism to slower 2D engine read/write memory speed" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--26. " RD_BTYP ,Read request maximum burst type" "Burst-8,Burst-4,,Single,?..."
|
|
bitfld.long 0x04 20.--22. " WR_BTYP ,Write request maximum burst type" "Single,,Burst-4,Burst-8,Burst-16,?..."
|
|
hexmask.long.byte 0x04 0.--7. 1. " SLOW_CNT ,Read/write request slow counter"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "G2D_ROI_CON,G2D ROI Control Register"
|
|
bitfld.long 0x00 31. " EN_[0] ,Enable 0th layer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [1] ,Enable 1th layer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [2] ,Enable 2th layer" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [3] ,Enable 3th layer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CLR_REP_EN ,Color replacement enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DIS_BG ,Disable background color" "No,Yes"
|
|
bitfld.long 0x00 18. " TILE_SIZE ,ROI scan tile size for bitblt/linear transform" "4x4/8x8,8x8/16x8"
|
|
bitfld.long 0x00 17. " FORCE_TS ,Force tile size" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CLP_EN ,Clipping window enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OUT_ALPHA ,Replaced alpha channel value"
|
|
bitfld.long 0x00 7. " OUT_ALP_EN ,Output alpha channel replacement enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLRFMT ,Write to memory color format" ",RGB565,,RGB888,,,,,ARGB8888,ARGB8565,ARGB6666,,PARGB8888,PARGB8565,PARGB6666,,,,,BGR888,?..."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "G2D_W2M_ADDR,G2D W2M Address Register"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "G2D_W2M_PITCH,G2D W2M Pitch Register"
|
|
hexmask.word 0x00 0.--13. 1. " PITCH ,Pitch in unit of byte"
|
|
group.long 0x4C++0x1F
|
|
line.long 0x00 "G2D_ROI_OFS,G2D ROI Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " OFS_X ,ROI x offset in unit of pixel"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFS_Y ,ROI y offset in unit of pixel"
|
|
line.long 0x04 "G2D_ROI_SIZE,G2D ROI Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WIDTH ,Width of ROI window in unit of pixel"
|
|
hexmask.long.word 0x04 0.--11. 1. " HEIGHT ,Height of ROI window in unit of pixel"
|
|
line.long 0x08 "G2D_ROI_BGCLR,G2D ROI Background Color Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " ALPHA ,Alpha component of ROI background color"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RED ,Red component of ROI background color"
|
|
hexmask.long.byte 0x08 8.--15. 1. " GREEN ,Green component of ROI background color"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BLUE ,Blue component of ROI background color"
|
|
line.long 0x0C "G2D_CLP_MIN,G2D Clipping Minimum Register"
|
|
hexmask.long.word 0x0C 16.--27. 1. " CLP_MIN_X ,Minimum value of x coordinate in clipping window"
|
|
hexmask.long.word 0x0C 0.--11. 1. " CLP_MIN_Y ,Minimum value of y coordinate in clipping window"
|
|
line.long 0x10 "G2D_CLP_MAX,G2D Clipping Maximum Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " CLP_MAX_X ,Maximum value of x coordinate in clipping window"
|
|
hexmask.long.word 0x10 0.--11. 1. " CLP_MAX_Y ,Maximum value of y coordinate in clipping window"
|
|
line.long 0x14 "G2D_AVO_CLR,G2D Avoid Write Color Register"
|
|
line.long 0x18 "G2D_REP_CLR,G2D Replaced Color Register"
|
|
line.long 0x1C "G2D_W2M_MOFS,G2D Write To Memory Offset Register"
|
|
hexmask.long.word 0x1C 16.--27. 0x01 " W2M_MOFS_X ,ROI memory x-offset"
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " W2M_MOFS_Y ,ROI memory y-offset"
|
|
textline " "
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "G2D_MW_INIT,G2D MW Initial Value Register"
|
|
line.long 0x04 "G2D_MZ_INIT,G2D MZ Initial Value Register"
|
|
group.word 0x78++0x01
|
|
line.word 0x00 "G2D_DI_CON,G2D Dithering Control Register"
|
|
bitfld.word 0x00 12.--13. " DI_R ,Dithering bit selection" "0 bit,1 bit,2 bit,3 bit"
|
|
bitfld.word 0x00 8.--9. " DI_G ,Dithering bit selection" "0 bit,1 bit,2 bit,3 bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " DI_B ,Dithering bit selection" "0 bit,1 bit,2 bit,3 bit"
|
|
bitfld.word 0x00 0.--1. " DI_MODE ,Dither mode selection" "Disabled,Random number algorithm,Fixed-pattern,?..."
|
|
group.long 0x80++0x07 "Layer 0"
|
|
line.long 0x00 "G2D_L0_CON,G2D Layer 0 Control Register"
|
|
bitfld.long 0x00 30. " FONT_EN ,Enable font drawing" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " IDX ,Bit-per-pixel for font drawing" "1 bit,2 bit,4 bit,8 bit"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SKEY_EN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RECT_EN ,Enable RECT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " ROT ,Rotation configuration" "No rotation,Horizontal flip then 90 degree,Horizontal flip,90 degree,Horizontal flip then 180 degree,270 degree,180 degree,Horizontal flip then 270 degree"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Constant alpha value for alpha-blending and AA-font"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ALP_EN ,Enable alpha-blending" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLRFMT ,Layer color format" ",RGB565,UY0VY1,RGB888,,,,,ARGB8888,ARGB8565,ARGB6666,,PARGB8888,PARGB8565,PARGB6666,,,,,BGR888,?..."
|
|
line.long 0x04 "G2D_L0_ADDR,G2D Layer 0 Address Register"
|
|
group.word (0x80+0x08)++0x01
|
|
line.word 0x00 "G2D_L0_PITCH,G2D Layer 0 Pitch Register"
|
|
group.long (0x80+0x0C)++0x0B
|
|
line.long 0x00 "G2D_L0_OFS,G2D Layer 0 Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 0x01 " OFS_X ,ROI x offset in unit of pixel"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " OFS_Y ,ROI y offset in unit of pixel"
|
|
line.long 0x04 "G2D_L0_SIZE,G2D Layer 0 Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WIDTH ,Width of layer 0 window in unit of pixel"
|
|
hexmask.long.word 0x04 0.--11. 1. " HEIGHT ,Height of layer 0 window in unit of pixel"
|
|
line.long 0x08 "G2D_L0_SRCKEY,G2D Layer 0 Source Key Register"
|
|
group.long 0xC0++0x07 "Layer 1"
|
|
line.long 0x00 "G2D_L1_CON,G2D Layer 1 Control Register"
|
|
bitfld.long 0x00 30. " FONT_EN ,Enable font drawing" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " IDX ,Bit-per-pixel for font drawing" "1 bit,2 bit,4 bit,8 bit"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SKEY_EN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RECT_EN ,Enable RECT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " ROT ,Rotation configuration" "No rotation,Horizontal flip then 90 degree,Horizontal flip,90 degree,Horizontal flip then 180 degree,270 degree,180 degree,Horizontal flip then 270 degree"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Constant alpha value for alpha-blending and AA-font"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ALP_EN ,Enable alpha-blending" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLRFMT ,Layer color format" ",RGB565,UY0VY1,RGB888,,,,,ARGB8888,ARGB8565,ARGB6666,,PARGB8888,PARGB8565,PARGB6666,,,,,BGR888,?..."
|
|
line.long 0x04 "G2D_L1_ADDR,G2D Layer 1 Address Register"
|
|
group.word (0xC0+0x08)++0x01
|
|
line.word 0x00 "G2D_L1_PITCH,G2D Layer 1 Pitch Register"
|
|
group.long (0xC0+0x0C)++0x0B
|
|
line.long 0x00 "G2D_L1_OFS,G2D Layer 1 Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 0x01 " OFS_X ,ROI x offset in unit of pixel"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " OFS_Y ,ROI y offset in unit of pixel"
|
|
line.long 0x04 "G2D_L1_SIZE,G2D Layer 1 Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WIDTH ,Width of layer 1 window in unit of pixel"
|
|
hexmask.long.word 0x04 0.--11. 1. " HEIGHT ,Height of layer 1 window in unit of pixel"
|
|
line.long 0x08 "G2D_L1_SRCKEY,G2D Layer 1 Source Key Register"
|
|
group.long 0x100++0x07 "Layer 2"
|
|
line.long 0x00 "G2D_L2_CON,G2D Layer 2 Control Register"
|
|
bitfld.long 0x00 30. " FONT_EN ,Enable font drawing" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " IDX ,Bit-per-pixel for font drawing" "1 bit,2 bit,4 bit,8 bit"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SKEY_EN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RECT_EN ,Enable RECT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " ROT ,Rotation configuration" "No rotation,Horizontal flip then 90 degree,Horizontal flip,90 degree,Horizontal flip then 180 degree,270 degree,180 degree,Horizontal flip then 270 degree"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Constant alpha value for alpha-blending and AA-font"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ALP_EN ,Enable alpha-blending" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLRFMT ,Layer color format" ",RGB565,UY0VY1,RGB888,,,,,ARGB8888,ARGB8565,ARGB6666,,PARGB8888,PARGB8565,PARGB6666,,,,,BGR888,?..."
|
|
line.long 0x04 "G2D_L2_ADDR,G2D Layer 2 Address Register"
|
|
group.word (0x100+0x08)++0x01
|
|
line.word 0x00 "G2D_L2_PITCH,G2D Layer 2 Pitch Register"
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "G2D_L2_OFS,G2D Layer 2 Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 0x01 " OFS_X ,ROI x offset in unit of pixel"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " OFS_Y ,ROI y offset in unit of pixel"
|
|
line.long 0x04 "G2D_L2_SIZE,G2D Layer 2 Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WIDTH ,Width of layer 2 window in unit of pixel"
|
|
hexmask.long.word 0x04 0.--11. 1. " HEIGHT ,Height of layer 2 window in unit of pixel"
|
|
line.long 0x08 "G2D_L2_SRCKEY,G2D Layer 2 Source Key Register"
|
|
group.long 0x140++0x07 "Layer 3"
|
|
line.long 0x00 "G2D_L3_CON,G2D Layer 3 Control Register"
|
|
bitfld.long 0x00 30. " FONT_EN ,Enable font drawing" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " IDX ,Bit-per-pixel for font drawing" "1 bit,2 bit,4 bit,8 bit"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SKEY_EN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RECT_EN ,Enable RECT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " ROT ,Rotation configuration" "No rotation,Horizontal flip then 90 degree,Horizontal flip,90 degree,Horizontal flip then 180 degree,270 degree,180 degree,Horizontal flip then 270 degree"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Constant alpha value for alpha-blending and AA-font"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ALP_EN ,Enable alpha-blending" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLRFMT ,Layer color format" ",RGB565,UY0VY1,RGB888,,,,,ARGB8888,ARGB8565,ARGB6666,,PARGB8888,PARGB8565,PARGB6666,,,,,BGR888,?..."
|
|
line.long 0x04 "G2D_L3_ADDR,G2D Layer 3 Address Register"
|
|
group.word (0x140+0x08)++0x01
|
|
line.word 0x00 "G2D_L3_PITCH,G2D Layer 3 Pitch Register"
|
|
group.long (0x140+0x0C)++0x0B
|
|
line.long 0x00 "G2D_L3_OFS,G2D Layer 3 Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 0x01 " OFS_X ,ROI x offset in unit of pixel"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " OFS_Y ,ROI y offset in unit of pixel"
|
|
line.long 0x04 "G2D_L3_SIZE,G2D Layer 3 Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WIDTH ,Width of layer 3 window in unit of pixel"
|
|
hexmask.long.word 0x04 0.--11. 1. " HEIGHT ,Height of layer 3 window in unit of pixel"
|
|
line.long 0x08 "G2D_L3_SRCKEY,G2D Layer 3 Source Key Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Multimedia Subsystem Configuration"
|
|
base ad:0xA0480000
|
|
width 24.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "RESIZER_PATH_SEL,MDP Resizer In/Out Selection Register"
|
|
bitfld.long 0x00 0.--1. " RESIZER_OUT_SEL ,Resizer output selection" "Rotator,Color,?..."
|
|
line.long 0x04 "COLOR_PATH_SEL,MDP Color In/Out Selection Register"
|
|
bitfld.long 0x04 4.--5. " COLOR_IN_SEL ,Color input selection" "Resizer,LCD,?..."
|
|
bitfld.long 0x04 0.--1. " COLOR_OUT_SEL ,Color output selection" "Rotator,LCD,?..."
|
|
line.long 0x08 "ROTDMA_PATH_SEL,MDP Rotator In/Out Selection Register"
|
|
bitfld.long 0x08 4.--5. " ROTATOR_IN_SEL ,Rotator input selection" "Resizer,Color,?..."
|
|
line.long 0x0C "APB_OPT_SEL,APB Buffer Enable Selection Register"
|
|
bitfld.long 0x0C 0. " APB_BUFFER_EN ,APB buffer enable selection" "Disabled,Enabled"
|
|
line.long 0x10 "DSI0_SEL,DSI/ DBI Interface Selection Register"
|
|
bitfld.long 0x10 0. " DSI0_SEL ,Interface output selection" "DBI,DSI"
|
|
line.long 0x14 "CG_1ST_CON0_SET/CLR,CG_1ST_CON0 Register"
|
|
setclrfld.long 0x14 31. 0x18 31. 0x1C 31. " CG_1ST_CON0_[31] ,Hardware cg 1st configuration bit 31" "Not gated,Gated"
|
|
setclrfld.long 0x14 30. 0x18 30. 0x1C 30. " [30] ,Hardware cg 1st configuration bit 30" "Not gated,Gated"
|
|
setclrfld.long 0x14 29. 0x18 29. 0x1C 29. " [29] ,Hardware cg 1st configuration bit 29" "Not gated,Gated"
|
|
setclrfld.long 0x14 28. 0x18 28. 0x1C 28. " [28] ,Hardware cg 1st configuration bit 28" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 27. 0x18 27. 0x1C 27. " [27] ,Hardware cg 1st configuration bit 27" "Not gated,Gated"
|
|
setclrfld.long 0x14 26. 0x18 26. 0x1C 26. " [26] ,Hardware cg 1st configuration bit 26" "Not gated,Gated"
|
|
setclrfld.long 0x14 25. 0x18 25. 0x1C 25. " [25] ,Hardware cg 1st configuration bit 25" "Not gated,Gated"
|
|
setclrfld.long 0x14 24. 0x18 24. 0x1C 24. " [24] ,Hardware cg 1st configuration bit 24" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 23. 0x18 23. 0x1C 23. " [23] ,Hardware cg 1st configuration bit 23" "Not gated,Gated"
|
|
setclrfld.long 0x14 22. 0x18 22. 0x1C 22. " [22] ,Hardware cg 1st configuration bit 22" "Not gated,Gated"
|
|
setclrfld.long 0x14 21. 0x18 21. 0x1C 21. " [21] ,Hardware cg 1st configuration bit 21" "Not gated,Gated"
|
|
setclrfld.long 0x14 20. 0x18 20. 0x1C 20. " [20] ,Hardware cg 1st configuration bit 20" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x18 19. 0x1C 19. " [19] ,Hardware cg 1st configuration bit 19" "Not gated,Gated"
|
|
setclrfld.long 0x14 18. 0x18 18. 0x1C 18. " [18] ,Hardware cg 1st configuration bit 18" "Not gated,Gated"
|
|
setclrfld.long 0x14 17. 0x18 17. 0x1C 17. " [17] ,Hardware cg 1st configuration bit 17" "Not gated,Gated"
|
|
setclrfld.long 0x14 16. 0x18 16. 0x1C 16. " [16] ,Hardware cg 1st configuration bit 16" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 15. 0x18 15. 0x1C 15. " [15] ,Hardware cg 1st configuration bit 15" "Not gated,Gated"
|
|
setclrfld.long 0x14 14. 0x18 14. 0x1C 14. " [14] ,Hardware cg 1st configuration bit 14" "Not gated,Gated"
|
|
setclrfld.long 0x14 13. 0x18 13. 0x1C 13. " [13] ,Hardware cg 1st configuration bit 13" "Not gated,Gated"
|
|
setclrfld.long 0x14 12. 0x18 12. 0x1C 12. " [12] ,Hardware cg 1st configuration bit 12" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 11. 0x18 11. 0x1C 11. " [11] ,Hardware cg 1st configuration bit 11" "Not gated,Gated"
|
|
setclrfld.long 0x14 10. 0x18 10. 0x1C 10. " [10] ,Hardware cg 1st configuration bit 10" "Not gated,Gated"
|
|
setclrfld.long 0x14 9. 0x18 9. 0x1C 9. " [9] ,Hardware cg 1st configuration bit 9" "Not gated,Gated"
|
|
setclrfld.long 0x14 8. 0x18 8. 0x1C 8. " [8] ,Hardware cg 1st configuration bit 8" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x18 7. 0x1C 7. " [7] ,Hardware cg 1st configuration bit 7" "Not gated,Gated"
|
|
setclrfld.long 0x14 6. 0x18 6. 0x1C 6. " [6] ,Hardware cg 1st configuration bit 6" "Not gated,Gated"
|
|
setclrfld.long 0x14 5. 0x18 5. 0x1C 5. " [5] ,Hardware cg 1st configuration bit 5" "Not gated,Gated"
|
|
setclrfld.long 0x14 4. 0x18 4. 0x1C 4. " [4] ,Hardware cg 1st configuration bit 4" "Not gated,Gated"
|
|
textline " "
|
|
setclrfld.long 0x14 3. 0x18 3. 0x1C 3. " [3] ,Hardware cg 1st configuration bit 3" "Not gated,Gated"
|
|
setclrfld.long 0x14 2. 0x18 2. 0x1C 2. " [2] ,Hardware cg 1st configuration bit 2" "Not gated,Gated"
|
|
setclrfld.long 0x14 1. 0x18 1. 0x1C 1. " [1] ,Hardware cg 1st configuration bit 1" "Not gated,Gated"
|
|
setclrfld.long 0x14 0. 0x18 0. 0x1C 0. " [0] ,Hardware cg 1st configuration bit 0" "Not gated,Gated"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "HW_CG_DIS_CON0_SET/CLR,HW_CG_DIS_CON0 Register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " HW_CG_DIS_CON0_[10] ,DSI interface clock enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GMC enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,DSI engine clock enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,AAL enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,MM_COLOR enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,G2D enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,PAD2CAM enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,CAMINF enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,ROTDMA enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Resizer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,LCD engine clock enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LCD (LCD display)"
|
|
base ad:0xA0450000
|
|
width 26.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "LCD_STA,LCD Interface Status Register"
|
|
bitfld.long 0x00 8. " MAIN_IDLE ,Maincon idle status" "Busy,Idle"
|
|
bitfld.long 0x00 6. " GMC ,Sending a read/write GMC request" "Not sent,Sent"
|
|
bitfld.long 0x00 5. " BUSY ,LCD interface busy status" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WAIT_SYNC ,Wait for LCM tearing-free sync signal" "Not waiting,Waiting"
|
|
bitfld.long 0x00 0. " RUN ,LCD interface transfer status" "Not run,Run"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "LCD_INTEN,LCD Interface Interrupt Enable Register"
|
|
bitfld.word 0x00 6. " APB_TIMEOUT ,CPU accessing LCD time out interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " SYNC ,TE sync interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CPL ,Frame complete interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "LCD_INTSTA,LCD Interface Interrupt Status Register"
|
|
bitfld.word 0x00 6. " APB_TIMEOUT ,CPU accessing LCD time out interrupt" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " SYNC ,TE sync interrupt" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " CPL ,Frame complete interrupt" "No interrupt,Interrupt"
|
|
group.word 0x0C++0x03
|
|
line.word 0x00 "LCD_START,LCD Interface Frame Transfer Register"
|
|
bitfld.word 0x00 15. " START ,LCD interface start" "No effect,Started"
|
|
bitfld.word 0x00 0. " INT_RESET ,LCD interface software reset" "No effect,Reset"
|
|
line.word 0x02 "LCD_RSTB,LCD Parallel/Serial Interface Reset Register"
|
|
bitfld.word 0x02 0. " RSTB ,LCD-B/LCD-C reset signal" "No effect,Reset"
|
|
if (((per.l(ad:0xA0450000+0x28)&0x808)==0x808))
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "LCD_SIF_PIX_CON,LCD Serial Interface Pixel Data Configuration Register"
|
|
bitfld.long 0x00 15. " SIF1_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SIF1_SINGLE_A0 ,Enable the Single A0 mode for frame pixel data transmission in 1-data-pin or 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SIF1_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SIF1_PIX_2PIN ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SIF1_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
bitfld.long 0x00 7. " SIF0_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SIF0_SINGLE_A0 ,Enable the Single A0 mode for frame pixel data transmission in 1-data-pin or 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SIF0_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SIF0_2PIN_SIZE ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SIF0_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
elif (((per.l(ad:0xA0450000+0x28)&0x808)==0x800))
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "LCD_SIF_PIX_CON,LCD Serial Interface Pixel Data Configuration Register"
|
|
bitfld.long 0x00 15. " SIF1_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SIF1_SINGLE_A0 ,Enable the Single A0 mode for frame pixel data transmission in 1-data-pin or 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SIF1_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SIF1_PIX_2PIN ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SIF1_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
bitfld.long 0x00 7. " SIF0_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIF0_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SIF0_2PIN_SIZE ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " SIF0_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
elif (((per.l(ad:0xA0450000+0x28)&0x808)==0x08))
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "LCD_SIF_PIX_CON,LCD Serial Interface Pixel Data Configuration Register"
|
|
bitfld.long 0x00 15. " SIF1_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SIF1_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SIF1_PIX_2PIN ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SIF1_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
bitfld.long 0x00 7. " SIF0_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SIF0_SINGLE_A0 ,Enable the Single A0 mode for frame pixel data transmission in 1-data-pin or 2-data-pin protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIF0_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SIF0_2PIN_SIZE ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " SIF0_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
else
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "LCD_SIF_PIX_CON,LCD Serial Interface Pixel Data Configuration Register"
|
|
bitfld.long 0x00 15. " SIF1_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SIF1_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SIF1_PIX_2PIN ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SIF1_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
bitfld.long 0x00 7. " SIF0_CS_STAY_LOW ,Enable the CS_Stay_Low mode for frame pixel data transmission in both 1-data-pin and 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SIF0_PARA_2PIN ,Enable 2-data-pin parameter protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SIF0_2PIN_SIZE ,Enable 2-data-pin protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " SIF0_2PIN_SIZE ,Interface size of Serial interface 0 in 2-data-pin protocol" ",,16 bits,18 bits,24 bits,,12 bits,?..."
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "LCD_SIF_TIMING0,LCD Serial Interface 0 Timing Register"
|
|
bitfld.long 0x00 20.--23. " CSS ,Chip select setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CSH ,Chip select hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " RD1ST ,The first phase timing of LSCK when read transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " RD2ND ,The second phase timing of LSCK when read transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WR1ST ,The first phase timing of LSCK when write transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " WR2ND ,The second phase timing of LSCK when write transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "LCD_SIF_TIMING1,LCD Serial Interface 1 Timing Register"
|
|
bitfld.long 0x04 20.--23. " CSS ,Chip select setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " CSH ,Chip select hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 12.--15. " RD1ST ,The first phase timing of LSCK when read transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " RD2ND ,The second phase timing of LSCK when read transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " WR1ST ,The first phase timing of LSCK when write transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " WR2ND ,The second phase timing of LSCK when write transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "LCD_SCNF,LCD Serial Interface Configuration Register"
|
|
bitfld.long 0x00 24. " SIF_HW_CS ,Hardware control serial interface chip select" "Software,Hardware"
|
|
bitfld.long 0x00 15. " SIF1_DIV2 ,Slow down the serial interface 1 timing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SIF1_SCK_DEF ,The default value of LSCK for serial interface 1 when not transfer data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SIF1_1ST_POL ,The first phase polarity of LSCK for serial interface 1" "Low,High"
|
|
bitfld.long 0x00 12. " SIF1_SDI ,Read data from LSDI pin" "Not read,Read"
|
|
bitfld.long 0x00 11. " SIF1_3WIRE ,Enable 3 wire mode of serial interface 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SIF1_SIZE ,Interface size of serial interface 1" "8 bits,9 bits,16 bits,18 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x00 7. " SIF0_DIV2 ,Slow down the serial interface 0 timing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SIF0_SCK_DEF ,The default value of LSCK for serial interface 0 when not transfer data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIF0_1ST_POL ,The first phase polarity of LSCK for serial interface 0" "Low,High"
|
|
bitfld.long 0x00 4. " SIF0_SDI ,Read data from LSDI pin" "Not read,Read"
|
|
bitfld.long 0x00 3. " SIF0_3WIRE ,Enable 3 wire mode of serial interface 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SIF0_SIZE ,Interface size of serial interface 0" "8 bits,9 bits,16 bits,18 bits,24 bits,32 bits,?..."
|
|
if (((per.l(ad:0xA0450000+0x28))&0x1000000)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "LCD_SCNF_CS,LCD Serial Interface Chip Select Register"
|
|
bitfld.long 0x00 1. " CS1 ,Directly control the value of the Chip Select pin LSCE1" "Low,High"
|
|
bitfld.long 0x00 0. " CS0 ,Directly control the value of the Chip Select pin LSCE0" "Low,High"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "LCD_SCNF_CS,LCD Serial Interface Chip Select Register"
|
|
endif
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "LCD_SYNC_LCM_SIZE,LCD Sync LCM Size Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " VTT ,Vertical timing"
|
|
hexmask.long.word 0x00 0.--9. 1. " HTT ,Horizontal timing"
|
|
line.long 0x04 "LCD_SYNC_CNT,LCD Sync Counter Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " SCANLINE ,Current TE counter value"
|
|
hexmask.long.word 0x04 0.--11. 1. " WAITLINE ,TE delay"
|
|
if (((per.l(ad:0xA0450000+0x50))&0x04)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "LCD_TECON,LCD Tearing Control Register"
|
|
bitfld.long 0x00 15. " SW_TE ,Receive TE signal" "Not received,Received"
|
|
bitfld.long 0x00 10. " TE_COUNTER_EN ,TE counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSI_END_CTL ,DSI produce EOF" "DSI vde falling,DSI frame done"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DSI_START_CTL ,DSI produce SOF" "Vsync falling,TE event"
|
|
bitfld.long 0x00 3. " TE_REPEAT ,Repeat mode" "Every TE,After TE"
|
|
bitfld.long 0x00 2. " SYNC_MODE ,Select TE sync mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TE_EDGE_SEL ,TE edge select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0. " SYNC_MODE ,Sync enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "LCD_TECON,LCD Tearing Control Register"
|
|
bitfld.long 0x00 10. " TE_COUNTER_EN ,TE counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSI_END_CTL ,DSI produce EOF" "DSI vde falling,DSI frame done"
|
|
bitfld.long 0x00 8. " DSI_START_CTL ,DSI produce SOF" "Vsync falling,TE event"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE_REPEAT ,Repeat mode" "Every TE,After TE"
|
|
bitfld.long 0x00 2. " SYNC_MODE ,Select TE sync mode" "0,1"
|
|
bitfld.long 0x00 1. " TE_EDGE_SEL ,TE edge select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC_MODE ,Sync enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x13
|
|
line.long 0x00 "LCD_ROICON,LCD Region of Interest Control Register"
|
|
bitfld.long 0x00 31. " EN_[0] ,Layer 0 window enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [1] ,Layer 1 window enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [2] ,Layer 2 window enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [3] ,Layer 3 window enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " COLOR_EN ,Enable the data path through mm_color" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IF24 ,24 bit data bus enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEND_RES_MOD ,Send residual odd pixel control" "Extra byte,First pixel"
|
|
bitfld.long 0x00 15. " ENC ,Command transfer enable control" "Only pixel data,Both"
|
|
bitfld.long 0x00 8.--13. " COMMAND ,Number of commands to be sent to LCD module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " FMT_[7:6] ,Interface size" "8 bit,16 bit,9 bit,18 bit"
|
|
bitfld.long 0x00 3.--5. " [5:3] ,Color format" ",,RGB565,RGB666,RGB888,?..."
|
|
bitfld.long 0x00 2. " [2] ,Padding" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Significance" "LSB,MSB"
|
|
bitfld.long 0x00 0. " [0] ,Sequence" "BGR,RGB"
|
|
line.long 0x04 "LCD_WROIOFS,LCD Region of Interest Window Offset Register"
|
|
hexmask.long.word 0x04 16.--26. 0x01 " Y_OFFSET ,ROI window column offset"
|
|
hexmask.long.word 0x04 0.--10. 0x01 " X_OFFSET ,ROI window ROW offset"
|
|
line.long 0x08 "LCD_WROICADD,LCD Region of Interest Command Address Register"
|
|
bitfld.long 0x08 4.--7. " ADDR ,LCM address" "LCD-B LCM CS0 and A0 bit,,LCD-B LCM CS1 and A0 bit,,CD-B LCM CS2 and A0 bit,,,,LCD-C LCM CS0 and A0 bit,,LCD-C LCM CS1 and A0 bit,?..."
|
|
line.long 0x0C "LCD_WROIDADD,LCD Region of Interest Data Address Register"
|
|
bitfld.long 0x0C 4.--7. " ADDR ,LCM address" ",LCD-B LCM CS0 and A0 bit,,LCD-B LCM CS1 and A0 bit,,CD-B LCM CS2 and A0 bit,,,,LCD-C LCM CS0 and A0 bit,,LCD-C LCM CS1 and A0 bit,?..."
|
|
line.long 0x10 "LCD_WROISIZE,LCD Region of Interest Size Register"
|
|
hexmask.long.word 0x10 16.--26. 1. " ROW ,ROI window row size"
|
|
hexmask.long.word 0x10 0.--10. 1. " COL ,ROI window column size"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "LCD_WROI_BGCLR,LCD Region of Interest Background Color Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha component of ROI window's background color"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red component of ROI window's background color"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green component of ROI window's background color"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue component of ROI window's background color"
|
|
textline " "
|
|
if (((per.l(ad:0xA0450000+0xB0))&0xF00000)==0x200000)
|
|
group.long 0xB0++0x03 "LCD Layer 0"
|
|
line.long 0x00 "LCD_L0WINCON,LCD Layer 0 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
else
|
|
if (((per.l(ad:0xA0450000+0xB0)&0x1004000)==0x4000))
|
|
group.long 0xB0++0x03 "LCD Layer 0"
|
|
line.long 0x00 "LCD_L0WINCON,LCD Layer 0 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
elif (((per.l(ad:0xA0450000+0xB0)&0x1004000)==0x1000000))
|
|
group.long 0xB0++0x03 "LCD Layer 0"
|
|
line.long 0x00 "LCD_L0WINCON,LCD Layer 0 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
else
|
|
group.long 0xB0++0x03 "LCD Layer 0"
|
|
line.long 0x00 "LCD_L0WINCON,LCD Layer 0 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
endif
|
|
endif
|
|
group.long 0xB4++0x0F
|
|
line.long 0x00 "LCD_L0WINKEY,LCD Layer 0 Color Key Register"
|
|
line.long 0x04 "LCD_L0WINOFS,LCD Layer 0 Window Display Offset Register"
|
|
hexmask.long.word 0x04 16.--26. 0x01 " Y_OFFSET ,Layer 0 window column offset"
|
|
hexmask.long.word 0x04 0.--10. 0x01 " X_OFFSET ,Layer 0 window ROW offset"
|
|
line.long 0x08 "LCD_L0WINADD,LCD Layer 0 Window Display Start Address Register"
|
|
line.long 0x0C "LCD_L0WINSIZE,LCD Layer 0 Window Size Register"
|
|
hexmask.long.word 0x0C 16.--26. 1. " ROW ,Layer 0 window row size in unit of pixel"
|
|
hexmask.long.word 0x0C 0.--10. 1. " COLUMN ,Layer 0 window column size in unit of pixel"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "LCD_L0WINMOFS,LCD Layer 0 Memory Offset Register"
|
|
hexmask.long.word 0x00 16.--26. 0x01 " Y_OFFSET ,Layer 0 window column offset"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " X_OFFSET ,Layer 0 window ROW offset"
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "LCD_L0WINPITCH,LCD Layer 0 Memory Pitch Register"
|
|
textline " "
|
|
if (((per.l(ad:0xA0450000+0xE0)&0x1004000)==0x4000))
|
|
group.long 0xE0++0x03 "LCD Layer 1"
|
|
line.long 0x00 "LCD_L1WINCON,LCD Layer 1 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
elif (((per.l(ad:0xA0450000+0xE0)&0x1004000)==0x1000000))
|
|
group.long 0xE0++0x03 "LCD Layer 1"
|
|
line.long 0x00 "LCD_L1WINCON,LCD Layer 1 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
else
|
|
group.long 0xE0++0x03 "LCD Layer 1"
|
|
line.long 0x00 "LCD_L1WINCON,LCD Layer 1 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
endif
|
|
group.long (0xE0+0x04)++0x0F
|
|
line.long 0x00 "LCD_L1WINKEY,LCD Layer 1 Color Key Register"
|
|
line.long 0x04 "LCD_L1WINOFS,LCD Layer 1 Window Display Offset Register"
|
|
hexmask.long.word 0x04 16.--26. 0x01 " Y_OFFSET ,Layer 1 window column offset"
|
|
hexmask.long.word 0x04 0.--10. 0x01 " X_OFFSET ,Layer 1 window ROW offset"
|
|
line.long 0x08 "LCD_L1WINADD,LCD Layer 1 Window Display Start Address Register"
|
|
line.long 0x0C "LCD_L1WINSIZE,LCD Layer 1 Window Size Register"
|
|
hexmask.long.word 0x0C 16.--26. 1. " ROW ,Layer 1 window row size in unit of pixel"
|
|
hexmask.long.word 0x0C 0.--10. 1. " COLUMN ,Layer 1 window column size in unit of pixel"
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "LCD_L1WINMOFS,LCD Layer 1 Memory Offset Register"
|
|
hexmask.long.word 0x00 16.--26. 0x01 " Y_OFFSET ,Layer 1 window column offset"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " X_OFFSET ,Layer 1 window ROW offset"
|
|
group.word (0xE0+0x1C)++0x01
|
|
line.word 0x00 "LCD_L1WINPITCH,LCD Layer 1 Memory Pitch Register"
|
|
if (((per.l(ad:0xA0450000+0x110)&0x1004000)==0x4000))
|
|
group.long 0x110++0x03 "LCD Layer 2"
|
|
line.long 0x00 "LCD_L2WINCON,LCD Layer 2 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
elif (((per.l(ad:0xA0450000+0x110)&0x1004000)==0x1000000))
|
|
group.long 0x110++0x03 "LCD Layer 2"
|
|
line.long 0x00 "LCD_L2WINCON,LCD Layer 2 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
else
|
|
group.long 0x110++0x03 "LCD Layer 2"
|
|
line.long 0x00 "LCD_L2WINCON,LCD Layer 2 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
endif
|
|
group.long (0x110+0x04)++0x0F
|
|
line.long 0x00 "LCD_L2WINKEY,LCD Layer 2 Color Key Register"
|
|
line.long 0x04 "LCD_L2WINOFS,LCD Layer 2 Window Display Offset Register"
|
|
hexmask.long.word 0x04 16.--26. 0x01 " Y_OFFSET ,Layer 2 window column offset"
|
|
hexmask.long.word 0x04 0.--10. 0x01 " X_OFFSET ,Layer 2 window ROW offset"
|
|
line.long 0x08 "LCD_L2WINADD,LCD Layer 2 Window Display Start Address Register"
|
|
line.long 0x0C "LCD_L2WINSIZE,LCD Layer 2 Window Size Register"
|
|
hexmask.long.word 0x0C 16.--26. 1. " ROW ,Layer 2 window row size in unit of pixel"
|
|
hexmask.long.word 0x0C 0.--10. 1. " COLUMN ,Layer 2 window column size in unit of pixel"
|
|
group.long (0x110+0x18)++0x03
|
|
line.long 0x00 "LCD_L2WINMOFS,LCD Layer 2 Memory Offset Register"
|
|
hexmask.long.word 0x00 16.--26. 0x01 " Y_OFFSET ,Layer 2 window column offset"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " X_OFFSET ,Layer 2 window ROW offset"
|
|
group.word (0x110+0x1C)++0x01
|
|
line.word 0x00 "LCD_L2WINPITCH,LCD Layer 2 Memory Pitch Register"
|
|
if (((per.l(ad:0xA0450000+0x140)&0x1004000)==0x4000))
|
|
group.long 0x140++0x03 "LCD Layer 3"
|
|
line.long 0x00 "LCD_L3WINCON,LCD Layer 3 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
elif (((per.l(ad:0xA0450000+0x140)&0x1004000)==0x1000000))
|
|
group.long 0x140++0x03 "LCD Layer 3"
|
|
line.long 0x00 "LCD_L3WINCON,LCD Layer 3 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
else
|
|
group.long 0x140++0x03 "LCD Layer 3"
|
|
line.long 0x00 "LCD_L3WINCON,LCD Layer 3 Window Control Register"
|
|
bitfld.long 0x00 26. " RGB_SWAP ,Swap RGB order of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " DST_KEYEN ,Enable destination color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CLRFMT ,Color format" "8bpp indexed color,RGB565,YUYV422,RGB888,ARGB8888,PARGB8888,XRGB,ARGB6666,PARGB6666,4bpp index color,2bpp index color,1bpp index color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " DITHER_EN ,Enable dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BYTE_SWAP ,Swap high byte and low byte of pixel data read from memory" "Not swapped,Swapped"
|
|
bitfld.long 0x00 15. " SRC ,Disable auto-increment of the source pixel address" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRC_KEYEN ,Enable source color key" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--13. " ROTATE ,Rotation configuration" "No rotation,90 degree,180 degree,270 degree,Horizontal flip,Horizontal flip then 90 degree,Horizontal flip then 180 degree,Horizontal flip then 270 degree"
|
|
bitfld.long 0x00 8. " ALPHA_EN ,Enable alpha blending" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALPHA ,Constant alpha value"
|
|
endif
|
|
group.long (0x140+0x04)++0x0F
|
|
line.long 0x00 "LCD_L3WINKEY,LCD Layer 3 Color Key Register"
|
|
line.long 0x04 "LCD_L3WINOFS,LCD Layer 3 Window Display Offset Register"
|
|
hexmask.long.word 0x04 16.--26. 0x01 " Y_OFFSET ,Layer 3 window column offset"
|
|
hexmask.long.word 0x04 0.--10. 0x01 " X_OFFSET ,Layer 3 window ROW offset"
|
|
line.long 0x08 "LCD_L3WINADD,LCD Layer 3 Window Display Start Address Register"
|
|
line.long 0x0C "LCD_L3WINSIZE,LCD Layer 3 Window Size Register"
|
|
hexmask.long.word 0x0C 16.--26. 1. " ROW ,Layer 3 window row size in unit of pixel"
|
|
hexmask.long.word 0x0C 0.--10. 1. " COLUMN ,Layer 3 window column size in unit of pixel"
|
|
group.long (0x140+0x18)++0x03
|
|
line.long 0x00 "LCD_L3WINMOFS,LCD Layer 3 Memory Offset Register"
|
|
hexmask.long.word 0x00 16.--26. 0x01 " Y_OFFSET ,Layer 3 window column offset"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " X_OFFSET ,Layer 3 window ROW offset"
|
|
group.word (0x140+0x1C)++0x01
|
|
line.word 0x00 "LCD_L3WINPITCH,LCD Layer 3 Memory Pitch Register"
|
|
textline " "
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "LCD_SIF_STR_BYTE_CON,LCD SIF Start Byte Configuration Register"
|
|
bitfld.long 0x00 15. " SIF1_STR_BYTE_MOD ,Start byte mode of serial interface 1" "Off,On"
|
|
bitfld.long 0x00 14. " SIF1_STR_BYTE_SWITCH ,Start byte mod2 switch of serial interface 1" "Off,On"
|
|
bitfld.long 0x00 8.--10. " SIF1_STR_DATA_SIZE ,Interface size of the data part of serial interface 1" "8 bits,9 bits,16 bits,18 bits,24 bits,32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SIF0_STR_BYTE_MOD ,Start byte mode of serial interface 0" "Off,On"
|
|
bitfld.long 0x00 6. " SIF0_STR_BYTE_SWITCH ,Start byte mod2 switch of serial interface 0" "Off,On"
|
|
bitfld.long 0x00 0.--2. " SIF0_STR_DATA_SIZE ,Interface size of the data part of serial interface 0" "8 bits,9 bits,16 bits,18 bits,24 bits,32 bits,?..."
|
|
group.long 0x278++0x07
|
|
line.long 0x00 "LCD_SIF_WR_STR_BYTE,LCD SIF Write Start Byte Value Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " SIF1_WR_STR_BYTE2 ,Value of the write start byte2 of serial interface 1"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " SIF0_WR_STR_BYTE2 ,Value of the write start byte2 of serial interface 0"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " SIF1_WR_STR_BYTE ,Value of the write start byte of serial interface 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " SIF0_WR_STR_BYTE ,Value of the write start byte of serial interface 0"
|
|
line.long 0x04 "LCD_SIF_RD_STR_BYTE,LCD SIF Read Start Byte Value Register"
|
|
hexmask.long.byte 0x04 8.--15. 0x01 " SIF1_RD_STR_BYTE ,Value of the read start byte of serial interface 1"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " SIF0_RD_STR_BYTE ,Value of the read start byte of serial interface 0"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "LCD_SIF_PAD_INPUT_SELECT,LCD Serial Pad Selection Register"
|
|
bitfld.long 0x00 16.--18. " LSDA_SEL ,Input selection of lsda from slcd_pad_macro" "Input 0,Input 1,?..."
|
|
bitfld.long 0x00 0.--2. " LSDI_SEL ,Input selection of lsdi from slcd_pad_macro" "Input 0,Input 1,?..."
|
|
textline " "
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_0_1,LCD INDEX Mode 0_1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEX1_RGB565 ,Index 1 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEX0_RGB565 ,Index 0 RGB565"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_2_3,LCD INDEX Mode 2_3 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEX3_RGB565 ,Index 3 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEX2_RGB565 ,Index 2 RGB565"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_4_5,LCD INDEX Mode 4_5 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEX5_RGB565 ,Index 5 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEX4_RGB565 ,Index 4 RGB565"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_6_7,LCD INDEX Mode 6_7 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEX7_RGB565 ,Index 7 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEX6_RGB565 ,Index 6 RGB565"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_8_9,LCD INDEX Mode 8_9 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEX9_RGB565 ,Index 9 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEX8_RGB565 ,Index 8 RGB565"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_A_B,LCD INDEX Mode A_B Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEXB_RGB565 ,Index 11 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEXA_RGB565 ,Index 10 RGB565"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_C_D,LCD INDEX Mode C_D Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEXD_RGB565 ,Index 13 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEXC_RGB565 ,Index 12 RGB565"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "LCD_TABLE_INDEX_E_F,LCD INDEX Mode E_F Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDEXF_RGB565 ,Index 15 RGB565"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDEXE_RGB565 ,Index 14 RGB565"
|
|
group.long 0xF80++0x03
|
|
line.long 0x00 "LCD_SCMD0,LCD Serial Interface Command Port0 Register"
|
|
group.long 0xF90++0x03
|
|
line.long 0x00 "LCD_SDAT0,LCD Serial Interface Data Port0 Register"
|
|
group.long 0xFA0++0x03
|
|
line.long 0x00 "LCD_SCMD1,LCD Serial Interface Command Port1 Register"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "LCD_SDAT1,LCD Serial Interface Data Port1 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DISP_DSI (Display Serial Interface)"
|
|
base ad:0xA04A0000
|
|
width 18.
|
|
if (((per.l(ad:0xA04A0000+0x14))&0x100000)==0x100000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DSI_START,DSI Start Register"
|
|
bitfld.long 0x00 2. " SLEEPOUT_START ,DSI sleep-out operation" "No effect,Started"
|
|
bitfld.long 0x00 0. " DSI_START ,Start DSI controller operation" "No effect,Started"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DSI_START,DSI Start Register"
|
|
bitfld.long 0x00 0. " DSI_START ,Start DSI controller operation" "No effect,Started"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DSI_INTEN,DSI Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " TE_TIMEOUT_INT_EN ,Enable TE timeout interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SLEEPOUT_DONE_INT_EN ,Enable ULPS sleep-out interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FRAME_DONE_INT_EN ,Enable frame done interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TE_RDY_INT_EN ,Enable DSI TE ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CMD_DONE_INT_EN ,Enable DSI command mode finished interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LPRX_RD_RDY_INT_EN ,Enable RX data-ready interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DSI_INTSTA,DSI Interrupt Status Register"
|
|
bitfld.long 0x00 31. " DSI_BUSY ,DSI busy status" "Idle,Busy"
|
|
bitfld.long 0x00 7. " TE_TIMEOUT_INT_FLAG ,TE time-out interrupt status" "Cleared,No effect"
|
|
bitfld.long 0x00 6. " SLEEPOUT_DONE_INT_FLAG ,ULPS sleep-out done interrupt status" "Cleared,No effect"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FRAME_DONE_INT_FLAG ,Frame done interrupt status" "Cleared,No effect"
|
|
bitfld.long 0x00 2. " TE_RDY_INT_FLAG ,DSI TE ready interrupt status" "Cleared,No effect"
|
|
bitfld.long 0x00 1. " CMD_DONE_INT_FLAG ,DSI command mode finish interrupt status" "Cleared,No effect"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPRX_RD_RDY_INT_FLAG ,RX data-ready interrupt status" "Cleared,No effect"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "DSI_COM_CON,DSI Common Control Register"
|
|
bitfld.long 0x00 2. " DPHY_RESET ,DIG_MIPI_TX software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DSI_RESET ,DSI module software reset" "No reset,Reset"
|
|
line.long 0x04 "DSI_MODE_CON,DSI Mode Control Register"
|
|
bitfld.long 0x04 20. " SLEEP_MODE ,DSI sleep mode for ULPS wake-up operation" "Disabled,Enabled"
|
|
line.long 0x08 "DSI_TXRX_CON,DSI TX RX Control Register"
|
|
bitfld.long 0x08 19. " TE_TIMEOUT_CHK_EN ,Enable TE time-out check mechanism" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " TE_WITH_CMD_EN ,Enable combine the TE bit and other commands" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " TYPE1_BTA_SEL ,Select TYPE1 BTA mechanism" "Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x08 16. " HSTX_CKLP_EN ,Enable non-continuous clock lane" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--15. " MAX_RTN_SIZE ,Maximum return packet size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 10. " EXT_TE_EDGE_SEL ,Select trigger edge type of external TE" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x08 9. " EXT_TE_EN ,Enable external TE signal" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HSTX_DIS_EOT ,Disable end of transmission packet" "No,Yes"
|
|
bitfld.long 0x08 2.--5. " LANE_NUM ,Lane number" "Disabled all,Enabled 1 data+1 clock,?..."
|
|
line.long 0x0C "DSI_PSCON,DSI Pixel Stream Control Register"
|
|
bitfld.long 0x0C 25. " BYTE_SWAP ,Select byte order" "Normal,Byte"
|
|
bitfld.long 0x0C 24. " RGB_SWAP ,Select order of RGB" "Normal,R/B"
|
|
bitfld.long 0x0C 16.--17. " DSI_PS_SEL ,Select pixel stream type" "16-bit RGB 5-6-5 format,,24-bit RGB 6-6-6 format,24-bit RGB 8-8-8 format"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--13. 1. " DSI_PS_WC ,Word count of long packet in valid pixel data duration"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DSI_VACT_NL,DSI Vertical Active Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VACT_NL ,Vertical active duration"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DSI_CMDQ_CON,DSI Command Queue Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMDQ_SIZE ,Number of commands in command queue"
|
|
if (((per.l(ad:0xA04A0000+0x18))&0x10000)==0x10000)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DSI_HSTX_CKLP_WC,DSI HSTX Clock Low-power Mode Word Count Register"
|
|
bitfld.long 0x00 16. " HSTX_CKLP_WC_AUTO ,Automatic calculation for HSTX_CKLP_WC enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 2.--15. 1. " HSTX_CKLP_WC ,Word count of non-continuous clock lane counter"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DSI_HSTX_CKLP_WC,DSI HSTX Clock Low-power Mode Word Count Register"
|
|
bitfld.long 0x00 16. " HSTX_CKLP_WC_AUTO ,Automatic calculation for HSTX_CKLP_WC enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x74++0x0F
|
|
line.long 0x00 "DSI_RX_DATA03,DSI Receive Packet Data Byte 0 ~ 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE_[3] ,RX read data buffer byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " [2] ,RX read data buffer byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " [1] ,RX read data buffer byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " [0] ,RX read data buffer byte 0"
|
|
line.long 0x04 "DSI_RX_DATA47,DSI Receive Packet Data Byte 4 ~ 7 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BYTE_[7] ,RX read data buffer byte 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [6] ,RX read data buffer byte 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [5] ,RX read data buffer byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " [4] ,RX read data buffer byte 4"
|
|
line.long 0x08 "DSI_RX_DATA8B,DSI Receive Packet Data Byte 8 ~ 11 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " BYTE_[11] ,RX read data buffer byte B"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [10] ,RX read data buffer byte A"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [9] ,RX read data buffer byte 9"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " [8] ,RX read data buffer byte 8"
|
|
line.long 0x0C "DSI_RX_DATAC,DSI Receive Packet Data Byte 12 ~ 15 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BYTE_[15] ,RX read data buffer byte F"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " [14] ,RX read data buffer byte E"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " [13] ,RX read data buffer byte D"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " [12] ,RX read data buffer byte C"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "DSI_RX_RACK,DSI Read Data Acknowledge Register"
|
|
bitfld.long 0x00 1. " RACK_BYPASS ,Enable RX read acknowledge bypass" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " RACK ,Acknowledges RX read" "No effect,Acknowledged"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "DSI_RX_TRIG_STA,DSI Receiver Status Register"
|
|
bitfld.long 0x00 5. " DIRECTION ,Escape turnaround direction" "Forward,Reverse"
|
|
bitfld.long 0x00 4. " RX_ULPS ,RX ULPS (Ultra-low power state)" "0,1"
|
|
bitfld.long 0x00 2. " RX_TRIG_[2] ,Acknowledge" "No effect,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,TE" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Remote application reset" "No reset,Reset"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "DSI_MEM_CONTI,DSI Memory Continue Command Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DSI_RWMEM_CONTI ,Read/Write memory continue command"
|
|
line.long 0x04 "DSI_FRM_BC,DSI Frame Byte Count Register"
|
|
hexmask.long.tbyte 0x04 0.--20. 1. " DSI_FRM_BC ,Frame buffer byte count"
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "DSI_TIME_CON0,DSI Timing Control 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ULPS_WAKEUP_PRD ,ULPS wakeup period"
|
|
line.long 0x04 "DSI_TIME_CON1,DSI Timing Control 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_TIMEOUT_PRD ,TE time-out check period"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "DSI_PHY_LCCON,DSI PHY Lane Clock Control Register"
|
|
bitfld.long 0x00 2. " LC_WAKEUP_EN ,Enable clock lane wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LC_ULPM_EN ,Enable clock lane ULPS" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LC_HSTX_EN ,Enable clock lane HS mode" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_PHY_LD0CON,DSI PHY Lane 0 Control Register"
|
|
bitfld.long 0x04 2. " L0_WAKEUP_EN ,Enable clock lane 0 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " L0_ULPM_EN ,Enable clock lane 0 ULPS" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " L0_RM_TRIG_EN ,Enable clock lane 0 HS mode" "Disabled,Enabled"
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "DSI_PHY_TIMCON0,DSI PHY Timing Control 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DA_HS_TRAIL ,Control for timing parameter: T_HS-Trail"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DA_HS_ZERO ,Control for timing parameter: T_HS-Zero"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DA_HS_PREP ,Control for timing parameter: T_HS-Prepare"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LPX ,Control for timing parameter: T_LPX"
|
|
line.long 0x04 "DSI_PHY_TIMCON0,DSI PHY Timing Control 0 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CLK_HS_EXIT ,Control for timing parameter: T_HS-Exit for clock lane"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TA_GET ,Control for timing parameter: T_TA-Get"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TA_SURE ,Control for timing parameter: T_TA-Sure"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TA_GO ,Control for timing parameter: T_TA-Go"
|
|
line.long 0x08 "DSI_PHY_TIMCON2,DSI PHY Timing Control 2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CLK_HS_TRAIL ,Control for timing parameter: T_CLK-Trail"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CLK_HS_ZERO ,Control for timing parameter: T_CLK-Zero"
|
|
line.long 0x0C "DSI_PHY_TIMCON3,DSI PHY Timing Control 3 Register"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DA_HS_EXIT ,Control for timing parameter: T_HS-Exit for data lane"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CLK_HS_POST ,Control for timing parameter: T_CLK-Post"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CLK_HS_PREP ,Control for timing parameter: T_CLK-Prepare"
|
|
width 14.
|
|
tree "DSI Commands Queue"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DSI_CMDQ_0,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DSI_CMDQ_1,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DSI_CMDQ_2,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DSI_CMDQ_3,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DSI_CMDQ_4,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DSI_CMDQ_5,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "DSI_CMDQ_6,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "DSI_CMDQ_7,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "DSI_CMDQ_8,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "DSI_CMDQ_9,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "DSI_CMDQ_10,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "DSI_CMDQ_11,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "DSI_CMDQ_12,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "DSI_CMDQ_13,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "DSI_CMDQ_14,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "DSI_CMDQ_15,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DSI_CMDQ_16,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DSI_CMDQ_17,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "DSI_CMDQ_18,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "DSI_CMDQ_19,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "DSI_CMDQ_20,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DSI_CMDQ_21,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "DSI_CMDQ_22,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "DSI_CMDQ_23,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DSI_CMDQ_24,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "DSI_CMDQ_25,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "DSI_CMDQ_26,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "DSI_CMDQ_27,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "DSI_CMDQ_28,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "DSI_CMDQ_29,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "DSI_CMDQ_30,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "DSI_CMDQ_31,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DSI_CMDQ_32,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "DSI_CMDQ_33,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "DSI_CMDQ_34,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "DSI_CMDQ_35,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "DSI_CMDQ_36,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DSI_CMDQ_37,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "DSI_CMDQ_38,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "DSI_CMDQ_39,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "DSI_CMDQ_40,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "DSI_CMDQ_41,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "DSI_CMDQ_42,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "DSI_CMDQ_43,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "DSI_CMDQ_44,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "DSI_CMDQ_45,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "DSI_CMDQ_46,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "DSI_CMDQ_47,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "DSI_CMDQ_48,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "DSI_CMDQ_49,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "DSI_CMDQ_50,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "DSI_CMDQ_51,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "DSI_CMDQ_52,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DSI_CMDQ_53,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "DSI_CMDQ_54,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "DSI_CMDQ_55,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "DSI_CMDQ_56,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "DSI_CMDQ_57,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "DSI_CMDQ_58,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "DSI_CMDQ_59,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "DSI_CMDQ_60,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "DSI_CMDQ_61,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "DSI_CMDQ_62,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "DSI_CMDQ_63,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DSI_CMDQ_64,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DSI_CMDQ_65,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DSI_CMDQ_66,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DSI_CMDQ_67,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DSI_CMDQ_68,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DSI_CMDQ_69,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DSI_CMDQ_70,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "DSI_CMDQ_71,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DSI_CMDQ_72,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "DSI_CMDQ_73,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "DSI_CMDQ_74,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "DSI_CMDQ_75,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "DSI_CMDQ_76,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "DSI_CMDQ_77,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "DSI_CMDQ_78,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "DSI_CMDQ_79,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "DSI_CMDQ_80,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "DSI_CMDQ_81,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "DSI_CMDQ_82,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "DSI_CMDQ_83,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "DSI_CMDQ_84,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DSI_CMDQ_85,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "DSI_CMDQ_86,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "DSI_CMDQ_87,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "DSI_CMDQ_88,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "DSI_CMDQ_89,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "DSI_CMDQ_90,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "DSI_CMDQ_91,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "DSI_CMDQ_92,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "DSI_CMDQ_93,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "DSI_CMDQ_94,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "DSI_CMDQ_95,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DSI_CMDQ_96,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "DSI_CMDQ_97,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "DSI_CMDQ_98,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "DSI_CMDQ_99,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DSI_CMDQ_100,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DSI_CMDQ_101,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "DSI_CMDQ_102,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "DSI_CMDQ_103,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "DSI_CMDQ_104,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "DSI_CMDQ_105,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "DSI_CMDQ_106,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "DSI_CMDQ_107,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "DSI_CMDQ_108,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "DSI_CMDQ_109,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "DSI_CMDQ_110,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "DSI_CMDQ_111,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "DSI_CMDQ_112,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "DSI_CMDQ_113,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "DSI_CMDQ_114,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "DSI_CMDQ_115,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "DSI_CMDQ_116,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DSI_CMDQ_117,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "DSI_CMDQ_118,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "DSI_CMDQ_119,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "DSI_CMDQ_120,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "DSI_CMDQ_121,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "DSI_CMDQ_122,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "DSI_CMDQ_123,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "DSI_CMDQ_124,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "DSI_CMDQ_125,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "DSI_CMDQ_126,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "DSI_CMDQ_127,DSI Command Queue Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_1 ,Data byte 1 of command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_0 ,Data byte 0 of command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ID ,Data ID of command"
|
|
bitfld.long 0x00 5. " TE ,Enable internal or external TE" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL ,Select DCS byte" "1-byte,2-byte"
|
|
bitfld.long 0x00 3. " HS ,Enable high-speed transmission" "LPTX,HSTX"
|
|
bitfld.long 0x00 2. " BTA ,Enable BTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Command type" "Type-0,Type-1,Type-2,Type-3"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "Image Resizer"
|
|
base ad:0xA0410000
|
|
width 25.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "RESZ_CFG,Image Resizer Configuration Register"
|
|
bitfld.long 0x00 16. " MODE1 ,Mode selection of 1st pass of resizer" "Frame,Tile"
|
|
bitfld.long 0x00 8. " VSRSTEN_[2] ,Resizer auto reset when SRC1 is camera and pixel drop is detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [1] ,Resizer auto reset when SRC1 is camera and new frame comes and previous input is complete but output not complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [0] ,Resizer auto reset when SRC1 is camera and new frame comes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DCM_DIS ,DCM disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PCON ,Run for pixel-based resizing selection" "Single,Continuous"
|
|
bitfld.long 0x00 0.--1. " SRC1 ,Input source of 1st pass of resizer" "Camera,Memory (Packet UYVY),Memory (Planar YUV420),Memory (Planar YUV422)"
|
|
line.long 0x04 "RESZ_CON,Image Resizer Control Register"
|
|
bitfld.long 0x04 16. " RST ,Reset resizer" "No reset,Reset"
|
|
bitfld.long 0x04 0. " ENA ,Enable resizer" "Disabled,Enabled"
|
|
line.long 0x08 "RESZ_STA,Image Resizer Status Register"
|
|
rbitfld.long 0x08 16. " DCM_STATUS ,DCM status" "0,1"
|
|
eventfld.long 0x08 14. " ERR_[5] ,Input pixel is not enough when crop is enabled" "No error,Error"
|
|
eventfld.long 0x08 13. " [4] ,Drop frame due to LOCK is changed between start point of original image and start point of cropped image" "No error,Error"
|
|
eventfld.long 0x08 12. " [3] ,Drop frame due to LOCK when vsync comes" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 10. " [2] ,Input complete but output not complete when new frame comes" "No error,Error"
|
|
eventfld.long 0x08 9. " [1] ,Input pixel is not enough" "No error,Error"
|
|
eventfld.long 0x08 8. " [0] ,Pixel over run" "No error,Error"
|
|
rbitfld.long 0x08 4. " CROPBUSY ,Cropping busy status" "Idle,Busy"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " INBUSY ,Input busy status" "Idle,Busy"
|
|
rbitfld.long 0x08 1. " MEMINBUSY ,Memory input busy status" "Idle,Busy"
|
|
rbitfld.long 0x08 0. " OUTBUSY ,Output busy status" "Idle,Busy"
|
|
textline " "
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "RESZ_INT,Image Resizer Interrupt Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "RESZ_SRCSZ1,Image Resizer Source Image Size Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " HS ,Height of source image"
|
|
hexmask.long.word 0x00 0.--10. 1. " WS ,Width of source image"
|
|
line.long 0x04 "RESZ_TARSZ1,Image Resizer Target Image Size Register 1"
|
|
hexmask.long.word 0x04 16.--26. 1. " HT ,Height of target image"
|
|
hexmask.long.word 0x04 0.--10. 1. " WT ,Width of target image"
|
|
line.long 0x08 "RESZ_HRATIO1,Image Resizer Horizontal Ratio Register 1"
|
|
line.long 0x0C "RESZ_VRATIO1,Image Resizer Vertical Ratio Register 1"
|
|
line.long 0x10 "RESZ_HRES1,Image Resizer Horizontal Residual Register 1"
|
|
hexmask.long.word 0x10 0.--11. 1. " RESIDUAL ,Residual"
|
|
line.long 0x14 "RESZ_VRES1,Image Resizer Vertical Residual Register 1"
|
|
hexmask.long.word 0x14 0.--11. 1. " RESIDUAL ,Residual"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RESZ_LOCK,Image Resizer LOCK Register"
|
|
bitfld.long 0x00 0. " LOCK ,Lock image resizer" "Not locked,Locked"
|
|
if (((per.l(ad:0xA0410000+0x34))&0x80000000)==0x00)
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RESZ_ORIGSZ1,Image Resizer Crop Original Size Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " ORIGSZ_HS ,Resizer input image height before cropping for pass 1"
|
|
hexmask.long.word 0x00 0.--10. 1. " ORIGSZ_WS ,Resizer input image width before cropping for pass 1"
|
|
line.long 0x04 "RESZ_CROPLR1,Image Resizer Crop Left Right Register 1"
|
|
bitfld.long 0x04 31. " CROP_EN ,Crop enable for pass 1" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 16.--26. 1. " CROP_L ,Horizontal cropping start/left position index for pass 1"
|
|
hexmask.long.word 0x04 0.--10. 1. " CROP_R ,Horizontal cropping end/right position index for pass 1"
|
|
line.long 0x08 "RESZ_CROPTB1,Image Resizer Crop Top Bottom Register 1"
|
|
hexmask.long.word 0x08 16.--26. 1. " CROP_T ,Vertical cropping start/top position index for pass 1"
|
|
hexmask.long.word 0x08 0.--10. 1. " CROP_B ,Vertical cropping end/bottom position index for pass 1"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RESZ_ORIGSZ1,Image Resizer Crop Original Size Register 1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RESZ_CROPLR1,Image Resizer Crop Left Right Register 1"
|
|
bitfld.long 0x00 31. " CROP_EN ,Crop enable for pass 1" "Disabled,Enabled"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "RESZ_CROPTB1,Image Resizer Crop Top Bottom Register 1"
|
|
endif
|
|
textline " "
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RESZ_FRCFG,Image Resizer Fine Resizing Configuration Register"
|
|
bitfld.long 0x00 16.--21. " WMSZ1 ,The number of lines which can be filled into working memory after horizontal resizing" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
bitfld.long 0x00 15. " LCKINTEN ,Drop frame due to lock interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MININTEN ,Memory input interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PXDINTEN ,Pixel drop interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSTART1INTEN ,Frame start of 1st pass interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FENDINTEN ,Frame end interrupt enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RESZ_DBGCFG,Image Resizer Debug Configuration Register"
|
|
bitfld.long 0x00 11. " NODB ,Force register not double buffered" "Double buffered,No double buffered"
|
|
bitfld.long 0x00 10. " PHR1 ,Force horizontal resizing to execute" "Normal,Executed"
|
|
bitfld.long 0x00 9. " PVR1 ,Force vertical resizing to execute" "Normal,Executed"
|
|
textline " "
|
|
rgroup.long 0xB0++0x07
|
|
line.long 0x00 "RESZ_INFO0,Image Resizer Information Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " IN_VERT_CNT ,Input vertical counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " IN_HORZ_CNT ,Input horizontal counter"
|
|
line.long 0x04 "RESZ_INFO1,Image Resizer Information Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OUT_VERT_CNT ,Output vertical counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " OUT_HORZ_CNT ,Output horizontal counter"
|
|
group.long 0xDC++0x0B
|
|
line.long 0x00 "RESZ_SMBASE_Y,Image Resizer Y-Component Source Memory Base Address Register"
|
|
line.long 0x04 "RESZ_SMBASE_U,Image Resizer U-Component Source Memory Base Address Register"
|
|
line.long 0x08 "RESZ_SMBASE_V,Image Resizer V-Component Source Memory Base Address Register"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RESZ_GMCCON,Image Resizer GMC Control Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " RD_MIN_REQ_INTERVAL ,The value of AHB bus cycles between two GMC requests for read port"
|
|
bitfld.long 0x00 4. " RD_MAX_BL ,Maximum burst length of GMC request for read port" "16 bytes,4 bytes"
|
|
bitfld.long 0x00 0. " RD_MIN_REQ_EN ,Enable GMC port minimum request control for read port" "Disabled,Enabled"
|
|
if (((per.l(ad:0xA0410000))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "RESZ_CLIP,Image Resizer CLIP Register"
|
|
bitfld.long 0x00 31. " CLIP_EN ,Enable clip function of memory in mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " MEM_WD ,Width of background image in pixels"
|
|
else
|
|
hgroup.long 0xFC++0x03
|
|
hide.long 0x00 "RESZ_CLIP,Image Resizer CLIP Register"
|
|
endif
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "RESZ_TILE_CFG,Image Resizer Tile Configuration Register"
|
|
bitfld.long 0x00 1. " SA_EN_Y1 ,Vertical source accumulation enable signal of 1st pass of resizer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SA_EN_X1 ,Horizontal source accumulation enable signal of 1st pass of resizer" "Disabled,Enabled"
|
|
line.long 0x04 "RESZ_TILE_START_POS_X1,Image Resizer Tile Start Position X Register 1"
|
|
hexmask.long 0x04 0.--30. 1. " TILE_START_POS_X ,Horizontal start position/weight of bilinear interpolation/source accumulation"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RESZ_TILE_START_POS_Y1,Image Resizer Tile Start Position Y Register 1"
|
|
hexmask.long 0x00 0.--30. 1. " TILE_START_POS_Y ,Vertical start position/weight of bilinear interpolation/source accumulation"
|
|
group.long 0x114++0x07
|
|
line.long 0x00 "RESZ_BI_TRUNC_ERR_COMP1,Image Resizer Bilinear Truncation Error Compensation Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " BI_TRUNC_ERR_COMP_Y ,Vertical condition of truncation error compensation by accumulated residual"
|
|
hexmask.long.word 0x00 0.--11. 1. " BI_TRUNC_ERR_COMP_X ,Horizontal condition of truncation error compensation by accumulated residual"
|
|
line.long 0x04 "RESZ_BI_INIT_RESID1,Image Resizer Bilinear Initial Residual Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " BI_INIT_RESID_Y ,Vertical initial residual for truncation error compensation"
|
|
hexmask.long.word 0x04 0.--12. 1. " BI_INIT_RESID_X ,Horizontal initial residual for truncation error compensation"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ROT_DMA (Image Rotator DMA)"
|
|
base ad:0xA0400000
|
|
width 24.
|
|
if (((per.l(ad:0xA0400000+0x30))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ROT_DMA_IRQ_FLAG,Rotator DMA Interrupt Flag Register"
|
|
bitfld.long 0x00 16. " FLAG0_IRQ_EN ,Flag 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLAG0 ,Engine finished the descriptor" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "ROT_DMA_IRQ_FLAG,Rotator DMA Interrupt Flag Register"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "ROT_DMA_IRQ_FLAG_CLR,Rotator DMA Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 0. " FLAG0_CLR ,Clear interrupt flag 0" "No effect,Clear"
|
|
if (((per.l(ad:0xA0400000+0x30))&0x01)==0x00)&&(((per.l(ad:0xA0400000+0x368))&0x07)==0x07)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ROT_DMA_CFG,Rotator DMA Configuration Register"
|
|
bitfld.long 0x00 31. " FRAME_SYNC_EN ,Enable frame sync signal from camera" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " YUV_PITCH_EN ,Enable pitch mechanism for generic YUV output format" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DROP ,Drop previous engine input data" "Not dropped,Dropped"
|
|
bitfld.long 0x00 0. " AUTO_LOOP ,Auto loop enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xA0400000+0x30))&0x01)==0x00)&&(((per.l(ad:0xA0400000+0x368))&0x07)!=0x07)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ROT_DMA_CFG,Rotator DMA Configuration Register"
|
|
bitfld.long 0x00 31. " FRAME_SYNC_EN ,Enable frame sync signal from camera" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DROP ,Drop previous engine input data" "Not dropped,Dropped"
|
|
bitfld.long 0x00 0. " AUTO_LOOP ,Auto loop enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xA0400000+0x30))&0x01)==0x01)&&(((per.l(ad:0xA0400000+0x368))&0x07)==0x07)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ROT_DMA_CFG,Rotator DMA Configuration Register"
|
|
bitfld.long 0x00 31. " FRAME_SYNC_EN ,Enable frame sync signal from camera" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " YUV_PITCH_EN ,Enable pitch mechanism for generic YUV output format" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTO_LOOP ,Auto loop enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ROT_DMA_CFG,Rotator DMA Configuration Register"
|
|
bitfld.long 0x00 31. " FRAME_SYNC_EN ,Enable frame sync signal from camera" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTO_LOOP ,Auto loop enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ROT_DMA_STOP,Rotator DMA Stop Register"
|
|
bitfld.long 0x00 0. " STOP ,Stop (disable) the DMA engine" "Not stopped,Stopped"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ROT_DMA_EN,Rotator DMA Enable Status Register"
|
|
bitfld.long 0x00 0. " EN ,Enable engine" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ROT_DMA_RESET,Rotator DMA Reset Register"
|
|
bitfld.long 0x00 1. " WARM_RST ,Warm reset DMA descriptor queue and control register settings" "No reset,Reset"
|
|
bitfld.long 0x00 0. " HARD_RST ,Hard reset DMA descriptor queue and control register settings" "No reset,Reset"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "ROT_DMA_SLOW_DOWN,Image Rotator DMA SLOW DOWN Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SLOW_CNT ,Slow down count"
|
|
bitfld.long 0x00 0. " SLOW_EN ,Slow down enable" "Disabled,Enabled"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "ROT_DMA_Y_DST_STR_ADDR,Image Rotator DMA Y Destination Start Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " Y_DST_STR_ADDR ,Destination Y start address"
|
|
if (((per.l(ad:0xA0400000+0x368))&0x07)==0x07)
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "ROT_DMA_U_DST_STR_ADDR,Image Rotator DMA U Destination Start Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " U_DST_STR_ADDR ,Destination U start address"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "ROT_DMA_V_DST_STR_ADDR,Image Rotator DMA V Destination Start Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " V_DST_STR_ADDR ,Destination V start address"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "ROT_DMA_U_DST_STR_ADDR,Image Rotator DMA U Destination Start Address Register"
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "ROT_DMA_V_DST_STR_ADDR,Image Rotator DMA V Destination Start Address Register"
|
|
endif
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "ROT_DMA_SRC_SIZE,Image Rotator DMA Source Image Size Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " SRC_H ,Source height"
|
|
hexmask.long.word 0x00 0.--10. 1. " SRC_W ,Source width"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "ROT_DMA_DST_SIZE,Image Rotator DMA Destination Image Size Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DST_W_IN_BYTE ,Destination width in bytes"
|
|
if (((per.l(ad:0xA0400000+0x368))&0x07)==0x04)
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "ROT_DMA_CON,Image Rotator DMA Control Register"
|
|
bitfld.long 0x00 31. " INT_EN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NOP ,No operation command" "NOP,Effective"
|
|
bitfld.long 0x00 27. " ROT_EN ,90 degree rotation with flip enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " V_SUBSAMPLE ,Vertical sub-sampling" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " THRESHOLD ,Bus control threshold" "4 bytes,,,16 bytes,,,,32 bytes"
|
|
bitfld.long 0x00 7. " ULTRA_EN ,Enable of bus ultra signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PROT_EN ,Enable of bus protect signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " OUTPUT_FORMAT ,Output format selection" ",,,,UYVY (YUYV422),,,Generic YUV"
|
|
else
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "ROT_DMA_CON,Image Rotator DMA Control Register"
|
|
bitfld.long 0x00 31. " INT_EN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NOP ,No operation command" "NOP,Effective"
|
|
bitfld.long 0x00 24. " V_SUBSAMPLE ,Vertical sub-sampling" "YUV422,YUV420"
|
|
bitfld.long 0x00 8.--10. " THRESHOLD ,Bus control threshold" "4 bytes,,,16 bytes,,,,32 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULTRA_EN ,Enable of bus ultra signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PROT_EN ,Enable of bus protect signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " OUTPUT_FORMAT ,Output format selection" ",,,,UYVY (YUYV422),,,Generic YUV"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose Inputs/Outputs)"
|
|
base ad:0xA2020000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_DIR0_SET/CLR,GPIO Direction Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,GPIO31 direction control" "Input,Output"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 direction control" "Input,Output"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 direction control" "Input,Output"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 direction control" "Input,Output"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 direction control" "Input,Output"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 direction control" "Input,Output"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 direction control" "Input,Output"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 direction control" "Input,Output"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 direction control" "Input,Output"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 direction control" "Input,Output"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 direction control" "Input,Output"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 direction control" "Input,Output"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 direction control" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 direction control" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 direction control" "Input,Output"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 direction control" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,GPIO10 direction control" "Input,Output"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 direction control" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 direction control" "Input,Output"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 direction control" "Input,Output"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 direction control" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 direction control" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 direction control" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 direction control" "Input,Output"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 direction control" "Input,Output"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPIO_DIR1_SET/CLR,GPI0 Direction Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,GPIO48 direction control" "Input,Output"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 direction control" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 direction control" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 direction control" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 direction control" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 direction control" "Input,Output"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 direction control" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 direction control" "Input,Output"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 direction control" "Input,Output"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 direction control" "Input,Output"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 direction control" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 direction control" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 direction control" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 direction control" "Input,Output"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_PULLEN0_SET/CLR,GPIO Pull-up/down Enable Control Register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " GPIO_[10] ,GPIO10 pull enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 pull enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 pull enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 pull enable" "Disabled,Enabled"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "GPIO_DINV0_SET/CLR,GPIO Data Inversion Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " INV_[31] ,GPIO31 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,GPIO10 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 inversion control" "Not inverted,Inverted"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "GPIO_DINV1_SET/CLR,GPIO Data Inversion Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " INV_[48] ,GPIO48 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 inversion control" "Not inverted,Inverted"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 inversion control" "Not inverted,Inverted"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 inversion control" "Not inverted,Inverted"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "GPIO_DOUT0_SET/CLR,GPIO Output Data Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,GPIO31 data output value" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 data output value" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 data output value" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 data output value" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 data output value" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 data output value" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 data output value" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 data output value" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 data output value" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 data output value" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 data output value" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 data output value" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 data output value" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 data output value" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 data output value" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 data output value" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,GPIO10 data output value" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 data output value" "Low,High"
|
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setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 data output value" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 data output value" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 data output value" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 data output value" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 data output value" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 data output value" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 data output value" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 data output value" "Low,High"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "GPIO_DOUT1_SET/CLR,GPIO Output Data Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,GPIO48 data output value" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 data output value" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 data output value" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 data output value" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 data output value" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 data output value" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 data output value" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 data output value" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 data output value" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 data output value" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 data output value" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 data output value" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 data output value" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 data output value" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 data output value" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 data output value" "Low,High"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "GPIO_DIN0,GPIO Input Data Value Register"
|
|
bitfld.long 0x00 31. " GPIO_[31] ,GPIO31 data input value" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,GPIO30 data input value" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,GPIO29 data input value" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,GPIO28 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,GPIO27 data input value" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,GPIO26 data input value" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,GPIO25 data input value" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,GPIO24 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,GPIO23 data input value" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,GPIO22 data input value" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,GPIO21 data input value" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,GPIO20 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,GPIO19 data input value" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,GPIO18 data input value" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,GPIO17 data input value" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,GPIO16 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,GPIO15 data input value" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,GPIO14 data input value" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,GPIO13 data input value" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,GPIO12 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,GPIO11 data input value" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,GPIO10 data input value" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,GPIO9 data input value" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,GPIO8 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,GPIO7 data input value" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,GPIO6 data input value" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,GPIO5 data input value" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,GPIO4 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,GPIO3 data input value" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,GPIO2 data input value" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,GPIO1 data input value" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,GPIO0 data input value" "Low,High"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "GPIO_DIN1,GPIO Input Data Value Register"
|
|
bitfld.long 0x00 16. " GPIO_[48] ,GPIO48 data input value" "Low,High"
|
|
bitfld.long 0x00 15. " [47] ,GPIO47 data input value" "Low,High"
|
|
bitfld.long 0x00 14. " [46] ,GPIO46 data input value" "Low,High"
|
|
bitfld.long 0x00 13. " [45] ,GPIO45 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [44] ,GPIO44 data input value" "Low,High"
|
|
bitfld.long 0x00 11. " [43] ,GPIO43 data input value" "Low,High"
|
|
bitfld.long 0x00 10. " [42] ,GPIO42 data input value" "Low,High"
|
|
bitfld.long 0x00 9. " [41] ,GPIO41 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [40] ,GPIO40 data input value" "Low,High"
|
|
bitfld.long 0x00 7. " [39] ,GPIO39 data input value" "Low,High"
|
|
bitfld.long 0x00 6. " [38] ,GPIO38 data input value" "Low,High"
|
|
bitfld.long 0x00 5. " [37] ,GPIO37 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [36] ,GPIO36 data input value" "Low,High"
|
|
bitfld.long 0x00 3. " [35] ,GPIO35 data input value" "Low,High"
|
|
bitfld.long 0x00 2. " [34] ,GPIO34 data input value" "Low,High"
|
|
bitfld.long 0x00 1. " [33] ,GPIO33 data input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [32] ,GPIO32 data input value" "Low,High"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "GPIO_PULLSEL0_SET/CLR,GPIO Pullsel Control Register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " GPIO_[10] ,GPIO10 pull selection" "Pull down,Pull up"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 pull selection" "Pull down,Pull up"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 pull selection" "Pull down,Pull up"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 pull selection" "Pull down,Pull up"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 pull selection" "Pull down,Pull up"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "GPIO_SMT0_SET/CLR,GPIO SMT Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,GPIO31 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,GPIO10 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 Schmitt trigger enable" "Disabled,Enabled"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "GPIO_SMT1_SET/CLR,GPIO SMT Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,GPIO16 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 Schmitt trigger enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 Schmitt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 Schmitt trigger enable" "Disabled,Enabled"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "GPIO_SR0_SET/CLR,GPIO SR Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,GPIO31 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,GPIO10 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 slew rate enable" "Disabled,Enabled"
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "GPIO_SR1_SET/CLR,GPIO SR Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,GPIO48 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 slew rate enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 slew rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 slew rate enable" "Disabled,Enabled"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "GPIO_DRV0,GPIO DRV Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[15] ,GPIO15 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " [14] ,GPIO14 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " [13] ,GPIO13 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " [12] ,GPIO12 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [11] ,GPIO11 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " [10] ,GPIO10 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " [9] ,GPIO9 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " [8] ,GPIO8 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [7] ,GPIO7 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " [6] ,GPIO6 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " [5] ,GPIO5 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " [4] ,GPIO4 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [3] ,GPIO3 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " [2] ,GPIO2 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " [1] ,GPIO1 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " [0] ,GPIO0 driving control" "0,1,2,3"
|
|
wgroup.long 0x804++0x07
|
|
line.long 0x00 "GPIO_DRV0_SET,GPIO DRV Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[15] ,Bitwise SET operation of GPIO15_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 28.--29. " [14] ,Bitwise SET operation of GPIO14_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 26.--27. " [13] ,Bitwise SET operation of GPIO13_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 24.--25. " [12] ,Bitwise SET operation of GPIO12_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [11] ,Bitwise SET operation of GPIO11_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 20.--21. " [10] ,Bitwise SET operation of GPIO10_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 18.--19. " [9] ,Bitwise SET operation of GPIO9_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 16.--17. " [8] ,Bitwise SET operation of GPIO8_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [7] ,Bitwise SET operation of GPIO7_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 12.--13. " [6] ,Bitwise SET operation of GPIO6_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 10.--11. " [5] ,Bitwise SET operation of GPIO5_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 8.--9. " [4] ,Bitwise SET operation of GPIO4_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [3] ,Bitwise SET operation of GPIO3_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 4.--5. " [2] ,Bitwise SET operation of GPIO2_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 2.--3. " [1] ,Bitwise SET operation of GPIO1_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 0.--1. " [0] ,Bitwise SET operation of GPIO0_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_DRV0_CLR,GPIO DRV Control Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[15] ,Bitwise CLR operation of GPIO15_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 28.--29. " [14] ,Bitwise CLR operation of GPIO14_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 26.--27. " [13] ,Bitwise CLR operation of GPIO13_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 24.--25. " [12] ,Bitwise CLR operation of GPIO12_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [11] ,Bitwise CLR operation of GPIO11_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 20.--21. " [10] ,Bitwise CLR operation of GPIO10_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 18.--19. " [9] ,Bitwise CLR operation of GPIO9_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 16.--17. " [8] ,Bitwise CLR operation of GPIO8_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [7] ,Bitwise CLR operation of GPIO7_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 12.--13. " [6] ,Bitwise CLR operation of GPIO6_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 10.--11. " [5] ,Bitwise CLR operation of GPIO5_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 8.--9. " [4] ,Bitwise CLR operation of GPIO4_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [3] ,Bitwise CLR operation of GPIO3_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 4.--5. " [2] ,Bitwise CLR operation of GPIO2_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 2.--3. " [1] ,Bitwise CLR operation of GPIO1_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 0.--1. " [0] ,Bitwise CLR operation of GPIO0_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "GPIO_DRV0,GPIO DRV Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[31] ,GPIO31 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " [30] ,GPIO30 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " [29] ,GPIO29 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " [28] ,GPIO28 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [27] ,GPIO27 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " [26] ,GPIO26 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " [25] ,GPIO25 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " [24] ,GPIO24 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [23] ,GPIO23 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " [22] ,GPIO22 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " [21] ,GPIO21 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " [20] ,GPIO20 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [19] ,GPIO19 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " [18] ,GPIO18 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " [17] ,GPIO17 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " [16] ,GPIO16 driving control" "0,1,2,3"
|
|
wgroup.long 0x814++0x07
|
|
line.long 0x00 "GPIO_DRV1_SET,GPIO DRV Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[31] ,Bitwise SET operation of GPIO31_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 28.--29. " [30] ,Bitwise SET operation of GPIO30_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 26.--27. " [29] ,Bitwise SET operation of GPIO29_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 24.--25. " [28] ,Bitwise SET operation of GPIO28_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [27] ,Bitwise SET operation of GPIO27_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 20.--21. " [26] ,Bitwise SET operation of GPIO26_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 18.--19. " [25] ,Bitwise SET operation of GPIO25_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 16.--17. " [24] ,Bitwise SET operation of GPIO24_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [23] ,Bitwise SET operation of GPIO23_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 12.--13. " [22] ,Bitwise SET operation of GPIO22_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 10.--11. " [21] ,Bitwise SET operation of GPIO21_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 8.--9. " [20] ,Bitwise SET operation of GPIO20_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [19] ,Bitwise SET operation of GPIO19_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 4.--5. " [18] ,Bitwise SET operation of GPIO18_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 2.--3. " [17] ,Bitwise SET operation of GPIO17_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 0.--1. " [16] ,Bitwise SET operation of GPIO16_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_DRV1_CLR,GPIO DRV Control Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[31] ,Bitwise CLR operation of GPIO31_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 28.--29. " [30] ,Bitwise CLR operation of GPIO30_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 26.--27. " [29] ,Bitwise CLR operation of GPIO29_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 24.--25. " [28] ,Bitwise CLR operation of GPIO28_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [27] ,Bitwise CLR operation of GPIO27_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 20.--21. " [26] ,Bitwise CLR operation of GPIO26_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 18.--19. " [25] ,Bitwise CLR operation of GPIO25_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 16.--17. " [24] ,Bitwise CLR operation of GPIO24_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [23] ,Bitwise CLR operation of GPIO23_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 12.--13. " [22] ,Bitwise CLR operation of GPIO22_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 10.--11. " [21] ,Bitwise CLR operation of GPIO21_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 8.--9. " [20] ,Bitwise CLR operation of GPIO20_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [19] ,Bitwise CLR operation of GPIO19_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 4.--5. " [18] ,Bitwise CLR operation of GPIO18_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 2.--3. " [17] ,Bitwise CLR operation of GPIO17_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 0.--1. " [16] ,Bitwise CLR operation of GPIO16_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "GPIO_DRV2,GPIO DRV Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[47] ,GPIO47 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " [46] ,GPIO46 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " [45] ,GPIO45 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " [44] ,GPIO44 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [43] ,GPIO43 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " [42] ,GPIO42 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " [41] ,GPIO41 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " [40] ,GPIO40 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [39] ,GPIO39 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " [38] ,GPIO38 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " [37] ,GPIO37 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " [36] ,GPIO36 driving control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [35] ,GPIO35 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " [34] ,GPIO34 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " [33] ,GPIO33 driving control" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " [32] ,GPIO32 driving control" "0,1,2,3"
|
|
wgroup.long 0x824++0x07
|
|
line.long 0x00 "GPIO_DRV2_SET,GPIO DRV Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[47] ,Bitwise SET operation of GPIO47_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 28.--29. " [46] ,Bitwise SET operation of GPIO46_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 26.--27. " [45] ,Bitwise SET operation of GPIO45_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 24.--25. " [44] ,Bitwise SET operation of GPIO44_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [43] ,Bitwise SET operation of GPIO43_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 20.--21. " [42] ,Bitwise SET operation of GPIO42_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 18.--19. " [41] ,Bitwise SET operation of GPIO41_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 16.--17. " [40] ,Bitwise SET operation of GPIO40_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [39] ,Bitwise SET operation of GPIO39_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 12.--13. " [38] ,Bitwise SET operation of GPIO38_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 10.--11. " [37] ,Bitwise SET operation of GPIO37_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 8.--9. " [36] ,Bitwise SET operation of GPIO36_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [35] ,Bitwise SET operation of GPIO35_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 4.--5. " [34] ,Bitwise SET operation of GPIO34_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 2.--3. " [33] ,Bitwise SET operation of GPIO33_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 0.--1. " [32] ,Bitwise SET operation of GPIO32_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_DRV2_CLR,GPIO DRV Control Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[47] ,Bitwise CLR operation of GPIO47_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 28.--29. " [46] ,Bitwise CLR operation of GPIO46_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 26.--27. " [45] ,Bitwise CLR operation of GPIO45_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 24.--25. " [44] ,Bitwise CLR operation of GPIO44_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [43] ,Bitwise CLR operation of GPIO43_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 20.--21. " [42] ,Bitwise CLR operation of GPIO42_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 18.--19. " [41] ,Bitwise CLR operation of GPIO41_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 16.--17. " [40] ,Bitwise CLR operation of GPIO40_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [39] ,Bitwise CLR operation of GPIO39_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 12.--13. " [38] ,Bitwise CLR operation of GPIO38_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 10.--11. " [37] ,Bitwise CLR operation of GPIO37_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 8.--9. " [36] ,Bitwise CLR operation of GPIO36_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [35] ,Bitwise CLR operation of GPIO35_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 4.--5. " [34] ,Bitwise CLR operation of GPIO34_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 2.--3. " [33] ,Bitwise CLR operation of GPIO33_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 0.--1. " [32] ,Bitwise CLR operation of GPIO32_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "GPIO_DRV3,GPIO DRV Control Register"
|
|
bitfld.long 0x00 0.--1. " GPIO_[48] ,GPIO48 driving control" "0,1,2,3"
|
|
wgroup.long 0x834++0x07
|
|
line.long 0x00 "GPIO_DRV3_SET,GPIO DRV Control Register"
|
|
bitfld.long 0x00 0.--1. " GPIO_[48] ,Bitwise SET operation of GPIO48_DRV" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_DRV3_CLR,GPIO DRV Control Register"
|
|
bitfld.long 0x04 0.--1. " GPIO_[48] ,Bitwise CLR operation of GPIO48_DRV" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "GPIO_IES0_SET/CLR,GPIO IES Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,GPIO31 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,GPIO10 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GPIO3 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GPIO2 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GPIO1 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GPIO0 input buffer enable" "Disabled,Enabled"
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "GPIO_IES1_SET/CLR,GPIO IES Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,GPIO48 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 input buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 input buffer enable" "Disabled,Enabled"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "GPIO_PUPD0_SET/CLR,GPIO PUPD Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,GPIO31 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,GPIO30 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,GPIO29 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,GPIO28 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,GPIO27 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,GPIO26 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,GPIO25 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,GPIO24 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,GPIO23 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,GPIO22 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,GPIO21 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,GPIO20 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,GPIO19 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,GPIO18 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,GPIO17 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,GPIO16 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,GPIO15 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,GPIO14 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,GPIO13 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,GPIO12 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,GPIO11 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,GPIO9 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,GPIO8 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,GPIO7 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GPIO6 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GPIO5 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GPIO4 PUPD enable" "Disabled,Enabled"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "GPIO_PUPD1_SET/CLR,GPIO PUPD Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,GPIO48 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,GPIO47 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,GPIO46 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,GPIO45 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,GPIO44 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,GPIO43 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,GPIO42 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,GPIO41 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,GPIO40 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,GPIO39 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,GPIO38 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,GPIO37 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,GPIO36 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,GPIO35 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,GPIO34 PUPD enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,GPIO33 PUPD enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,GPIO32 PUPD enable" "Disabled,Enabled"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "GPIO_RESEN0_0_SET/CLR,GPIO R0 Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,R0 enable for GPIO31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,R0 enable for GPIO30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,R0 enable for GPIO29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,R0 enable for GPIO28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,R0 enable for GPIO27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,R0 enable for GPIO26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,R0 enable for GPIO25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,R0 enable for GPIO24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,R0 enable for GPIO23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,R0 enable for GPIO22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,R0 enable for GPIO21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,R0 enable for GPIO20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,R0 enable for GPIO19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,R0 enable for GPIO18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,R0 enable for GPIO17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,R0 enable for GPIO16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,R0 enable for GPIO15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,R0 enable for GPIO14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,R0 enable for GPIO13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,R0 enable for GPIO12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,R0 enable for GPIO11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,R0 enable for GPIO9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,R0 enable for GPIO8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,R0 enable for GPIO7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,R0 enable for GPIO6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,R0 enable for GPIO5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,R0 enable for GPIO4" "Disabled,Enabled"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "GPIO_RESEN0_1_SET/CLR,GPIO R0 Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,R0 enable for GPIO48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,R0 enable for GPIO47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,R0 enable for GPIO46" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,R0 enable for GPIO45" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,R0 enable for GPIO44" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,R0 enable for GPIO43" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,R0 enable for GPIO42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,R0 enable for GPIO41" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,R0 enable for GPIO40" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,R0 enable for GPIO39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,R0 enable for GPIO38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,R0 enable for GPIO37" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,R0 enable for GPIO36" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,R0 enable for GPIO35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,R0 enable for GPIO34" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,R0 enable for GPIO33" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,R0 enable for GPIO32" "Disabled,Enabled"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "GPIO_RESEN1_0_SET/CLR,GPIO R1 Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO_[31] ,R1 enable for GPIO31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,R1 enable for GPIO30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,R1 enable for GPIO29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,R1 enable for GPIO28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,R1 enable for GPIO27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,R1 enable for GPIO26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,R1 enable for GPIO25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,R1 enable for GPIO24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,R1 enable for GPIO23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,R1 enable for GPIO22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,R1 enable for GPIO21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,R1 enable for GPIO20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,R1 enable for GPIO19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,R1 enable for GPIO18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,R1 enable for GPIO17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,R1 enable for GPIO16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,R1 enable for GPIO15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,R1 enable for GPIO14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,R1 enable for GPIO13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,R1 enable for GPIO12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,R1 enable for GPIO11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,R1 enable for GPIO9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,R1 enable for GPIO8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,R1 enable for GPIO7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,R1 enable for GPIO6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,R1 enable for GPIO5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,R1 enable for GPIO4" "Disabled,Enabled"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "GPIO_RESEN1_0_SET/CLR,GPIO R1 Control Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO_[48] ,R1 enable for GPIO48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [47] ,R1 enable for GPIO47" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [46] ,R1 enable for GPIO46" "Disabled,Enabled"
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setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [45] ,R1 enable for GPIO45" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [44] ,R1 enable for GPIO44" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [43] ,R1 enable for GPIO43" "Disabled,Enabled"
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setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [42] ,R1 enable for GPIO42" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [41] ,R1 enable for GPIO41" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [40] ,R1 enable for GPIO40" "Disabled,Enabled"
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [39] ,R1 enable for GPIO39" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [38] ,R1 enable for GPIO38" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [37] ,R1 enable for GPIO37" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [36] ,R1 enable for GPIO36" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [35] ,R1 enable for GPIO35" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [34] ,R1 enable for GPIO34" "Disabled,Enabled"
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setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [33] ,R1 enable for GPIO33" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [32] ,R1 enable for GPIO32" "Disabled,Enabled"
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textline " "
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group.long 0xC00++0x03
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line.long 0x00 "GPIO_MODE0,GPIO Mode Control Register"
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bitfld.long 0x00 28.--30. " GPIO_[7] ,Aux. mode of GPIO_7" "GPIO7 (IO),EINT6 (I),MC1_A_DA1 (IO),SLA_EDICK (I),U2TXD (O),,BT_BUCK_EN_HW (O),MA_SPI0_B_MISO (I)"
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bitfld.long 0x00 24.--26. " [6] ,Aux. mode of GPIO_6" "GPIO6 (IO),EINT5 (I),MC1_A_DA0 (IO),SLA_EDIWS (I),U2RXD (I),,,MA_SPI0_B_MOSI (O)"
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bitfld.long 0x00 20.--22. " [5] ,Aux. mode of GPIO_5" "GPIO5 (IO),EINT4 (I),MC1_A_CM0 (IO),SLA_EDIDI (I),,,U1TXD (O),MA_SPI0_B_SCK (O)"
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bitfld.long 0x00 16.--18. " [4] ,Aux. mode of GPIO_4" "GPIO4 (IO),EINT3 (I),MC1_A_CK (IO),SLA_EDIDO (O),,,U1RXD (I),MA_SPI0_B_CS (O)"
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textline " "
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bitfld.long 0x00 12.--15. " [3] ,Aux. mode of GPIO_3" "GPIO3 (IO),EINT14 (I),AUXADCIN_3 (AIO),U3TXD (I),U0RTS (O),MA_SPI1_A_MISO (I),MA_EDICK (O),MA_SPI0_A_MISO (I),DEBUGMON14 (IO),BTPRI (IO),?..."
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bitfld.long 0x00 8.--11. " [2] ,Aux. mode of GPIO_2" "GPIO2 (IO),EINT2 (I),AUXADCIN_2 (AIO),U3RXD (I),U0CTS (I),MA_SPI1_A_MOSI (O),MA_EDIWS (O),MA_SPI0_A_MOSI (O),DEBUGMON13 (IO),BT_BUCK_EN_HW (O),?..."
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bitfld.long 0x00 4.--7. " [1] ,Aux. mode of GPIO_1" "GPIO1 (IO),EINT1 (I),AUXADCIN_1 (AIO),U2TXD (O),PWM1 (O),MA_SPI1_A_SCK (O),MA_EDIDI (I),MA_SPI0_A_SCK (O),DEBUGMON12 (IO),BTDBGACKN (I),?..."
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bitfld.long 0x00 0.--3. " [0] ,Aux. mode of GPIO_0" "GPIO0 (IO),EINT0 (I),AUXADCIN_0 (AIO),U2RXD (I),PWM0 (O),MA_SPI1_A_CS (O),MA_EDIDO (O),MA_SPI0_A_CS (O),DEBUGMON11 (IO),BTJTDI (O),?..."
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wgroup.long 0xC04++0x07
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line.long 0x00 "GPIO_MODE0_SET,GPIO Mode Set Register"
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bitfld.long 0x00 28.--30. " GPIO_[7] ,GPIO_7 aux. mode set" "GPIO7 (IO),EINT6 (I),MC1_A_DA1 (IO),SLA_EDICK (I),U2TXD (O),,BT_BUCK_EN_HW (O),MA_SPI0_B_MISO (I)"
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bitfld.long 0x00 24.--26. " [6] ,GPIO_6 aux. mode set" "GPIO6 (IO),EINT5 (I),MC1_A_DA0 (IO),SLA_EDIWS (I),U2RXD (I),,,MA_SPI0_B_MOSI (O)"
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bitfld.long 0x00 20.--22. " [5] ,GPIO_5 aux. mode set" "GPIO5 (IO),EINT4 (I),MC1_A_CM0 (IO),SLA_EDIDI (I),,,U1TXD (O),MA_SPI0_B_SCK (O)"
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bitfld.long 0x00 16.--18. " [4] ,GPIO_4 aux. mode set" "GPIO4 (IO),EINT3 (I),MC1_A_CK (IO),SLA_EDIDO (O),,,U1RXD (I),MA_SPI0_B_CS (O)"
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textline " "
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bitfld.long 0x00 12.--15. " [3] ,GPIO_3 aux. mode set" "GPIO3 (IO),EINT14 (I),AUXADCIN_3 (AIO),U3TXD (I),U0RTS (O),MA_SPI1_A_MISO (I),MA_EDICK (O),MA_SPI0_A_MISO (I),DEBUGMON14 (IO),BTPRI (IO),?..."
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bitfld.long 0x00 8.--11. " [2] ,GPIO_2 aux. mode set" "GPIO2 (IO),EINT2 (I),AUXADCIN_2 (AIO),U3RXD (I),U0CTS (I),MA_SPI1_A_MOSI (O),MA_EDIWS (O),MA_SPI0_A_MOSI (O),DEBUGMON13 (IO),BT_BUCK_EN_HW (O),?..."
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bitfld.long 0x00 4.--7. " [1] ,GPIO_1 aux. mode set" "GPIO1 (IO),EINT1 (I),AUXADCIN_1 (AIO),U2TXD (O),PWM1 (O),MA_SPI1_A_SCK (O),MA_EDIDI (I),MA_SPI0_A_SCK (O),DEBUGMON12 (IO),BTDBGACKN (I),?..."
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bitfld.long 0x00 0.--3. " [0] ,GPIO_0 aux. mode set" "GPIO0 (IO),EINT0 (I),AUXADCIN_0 (AIO),U2RXD (I),PWM0 (O),MA_SPI1_A_CS (O),MA_EDIDO (O),MA_SPI0_A_CS (O),DEBUGMON11 (IO),BTJTDI (O),?..."
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line.long 0x04 "GPIO_MODE0_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 28.--30. " GPIO_[7] ,GPIO_7 aux. mode clear" "GPIO7 (IO),EINT6 (I),MC1_A_DA1 (IO),SLA_EDICK (I),U2TXD (O),,BT_BUCK_EN_HW (O),MA_SPI0_B_MISO (I)"
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bitfld.long 0x04 24.--26. " [6] ,GPIO_6 aux. mode clear" "GPIO6 (IO),EINT5 (I),MC1_A_DA0 (IO),SLA_EDIWS (I),U2RXD (I),,,MA_SPI0_B_MOSI (O)"
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bitfld.long 0x04 20.--22. " [5] ,GPIO_5 aux. mode clear" "GPIO5 (IO),EINT4 (I),MC1_A_CM0 (IO),SLA_EDIDI (I),,,U1TXD (O),MA_SPI0_B_SCK (O)"
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bitfld.long 0x04 16.--18. " [4] ,GPIO_4 aux. mode clear" "GPIO4 (IO),EINT3 (I),MC1_A_CK (IO),SLA_EDIDO (O),,,U1RXD (I),MA_SPI0_B_CS (O)"
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textline " "
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bitfld.long 0x04 12.--15. " [3] ,GPIO_3 aux. mode clear" "GPIO3 (IO),EINT14 (I),AUXADCIN_3 (AIO),U3TXD (I),U0RTS (O),MA_SPI1_A_MISO (I),MA_EDICK (O),MA_SPI0_A_MISO (I),DEBUGMON14 (IO),BTPRI (IO),?..."
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bitfld.long 0x04 8.--11. " [2] ,GPIO_2 aux. mode clear" "GPIO2 (IO),EINT2 (I),AUXADCIN_2 (AIO),U3RXD (I),U0CTS (I),MA_SPI1_A_MOSI (O),MA_EDIWS (O),MA_SPI0_A_MOSI (O),DEBUGMON13 (IO),BT_BUCK_EN_HW (O),?..."
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bitfld.long 0x04 4.--7. " [1] ,GPIO_1 aux. mode clear" "GPIO1 (IO),EINT1 (I),AUXADCIN_1 (AIO),U2TXD (O),PWM1 (O),MA_SPI1_A_SCK (O),MA_EDIDI (I),MA_SPI0_A_SCK (O),DEBUGMON12 (IO),BTDBGACKN (I),?..."
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bitfld.long 0x04 0.--3. " [0] ,GPIO_0 aux. mode clear" "GPIO0 (IO),EINT0 (I),AUXADCIN_0 (AIO),U2RXD (I),PWM0 (O),MA_SPI1_A_CS (O),MA_EDIDO (O),MA_SPI0_A_CS (O),DEBUGMON11 (IO),BTJTDI (O),?..."
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group.long 0xC10++0x03
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line.long 0x00 "GPIO_MODE1,GPIO Mode Control Register"
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bitfld.long 0x00 28.--30. " GPIO_[15] ,Aux. mode of GPIO_15" "GPIO15 (IO),EINT13 (I),,,,PWM4 (O),?..."
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bitfld.long 0x00 24.--26. " [14] ,Aux. mode of GPIO_14" "GPIO14 (IO),EINT12 (I),CLKO4 (O),MA_EDICK (O),MA_SPI1_B_MISO (O),PWM3 (O),SLA_EDICK (I),?..."
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bitfld.long 0x00 20.--22. " [13] ,Aux. mode of GPIO_13" "GPIO13 (IO),EINT11 (I),CLKO3 (O),MA_EDIWS (O),MA_SPI1_B_MOSI (O),PWM2 (O),SLA_EDIWS (I),?..."
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bitfld.long 0x00 16.--18. " [12] ,Aux. mode of GPIO_12" "GPIO12 (IO),EINT10 (I),,MA_EDIDI (I),MA_SPI1_B_SCK (O),PWM1 (O),SLA_EDIDI (I),?..."
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textline " "
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bitfld.long 0x00 12.--14. " [11] ,Aux. mode of GPIO_11" "GPIO11 (IO),EINT9 (I),BT_BUCK_EN_HW (O),MA_EDIDO (O),MA_SPI1_B_CS (O),PWM0 (O),SLA_EDIDO (O),?..."
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bitfld.long 0x00 8.--11. " [10] ,Aux. mode of GPIO_10" "GPIO10 (IO),EINT15 (I),AUXADCIN_4(AIO),,,,,,DEBUGMON15(IO),BTPRI(IO),?..."
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bitfld.long 0x00 4.--6. " [9] ,Aux. mode of GPIO_9" "GPIO9 (IO),EINT8 (I),MC1_A_DA3 (IO),,,,SDA2 (IO),?..."
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bitfld.long 0x00 0.--2. " [8] ,Aux. mode of GPIO_8" "GPIO8 (IO),EINT7 (I),MC1_A_DA2 (IO),,,,SCL2 (IO),?..."
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wgroup.long 0xC14++0x07
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line.long 0x00 "GPIO_MODE1_SET,GPIO Mode Set Register"
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bitfld.long 0x00 28.--30. " GPIO_[15] ,GPIO_15 aux. mode set" "GPIO15 (IO),EINT13 (I),,,,PWM4 (O),?..."
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bitfld.long 0x00 24.--26. " [14] ,GPIO_14 aux. mode set" "GPIO14 (IO),EINT12 (I),CLKO4 (O),MA_EDICK (O),MA_SPI1_B_MISO (O),PWM3 (O),SLA_EDICK (I),?..."
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bitfld.long 0x00 20.--22. " [13] ,GPIO_13 aux. mode set" "GPIO13 (IO),EINT11 (I),CLKO3 (O),MA_EDIWS (O),MA_SPI1_B_MOSI (O),PWM2 (O),SLA_EDIWS (I),?..."
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bitfld.long 0x00 16.--18. " [12] ,GPIO_12 aux. mode set" "GPIO12 (IO),EINT10 (I),,MA_EDIDI (I),MA_SPI1_B_SCK (O),PWM1 (O),SLA_EDIDI (I),?..."
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textline " "
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bitfld.long 0x00 12.--14. " [11] ,GPIO_11 aux. mode set" "GPIO11 (IO),EINT9 (I),BT_BUCK_EN_HW (O),MA_EDIDO (O),MA_SPI1_B_CS (O),PWM0 (O),SLA_EDIDO (O),?..."
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bitfld.long 0x00 8.--11. " [10] ,GPIO_10 aux. mode set" "GPIO10 (IO),EINT15 (I),AUXADCIN_4(AIO),,,,,,DEBUGMON15(IO),BTPRI(IO),?..."
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bitfld.long 0x00 4.--6. " [9] ,GPIO_9 aux. mode set" "GPIO9 (IO),EINT8 (I),MC1_A_DA3 (IO),,,,SDA2 (IO),?..."
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bitfld.long 0x00 0.--2. " [8] ,GPIO_8 aux. mode set" "GPIO8 (IO),EINT7 (I),MC1_A_DA2 (IO),,,,SCL2 (IO),?..."
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line.long 0x04 "GPIO_MODE1_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 28.--30. " GPIO_[15] ,GPIO_15 aux. mode clear" "GPIO15 (IO),EINT13 (I),,,,PWM4 (O),?..."
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bitfld.long 0x04 24.--26. " [14] ,GPIO_14 aux. mode clear" "GPIO14 (IO),EINT12 (I),CLKO4 (O),MA_EDICK (O),MA_SPI1_B_MISO (O),PWM3 (O),SLA_EDICK (I),?..."
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bitfld.long 0x04 20.--22. " [13] ,GPIO_13 aux. mode clear" "GPIO13 (IO),EINT11 (I),CLKO3 (O),MA_EDIWS (O),MA_SPI1_B_MOSI (O),PWM2 (O),SLA_EDIWS (I),?..."
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bitfld.long 0x04 16.--18. " [12] ,GPIO_12 aux. mode clear" "GPIO12 (IO),EINT10 (I),,MA_EDIDI (I),MA_SPI1_B_SCK (O),PWM1 (O),SLA_EDIDI (I),?..."
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textline " "
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bitfld.long 0x04 12.--14. " [11] ,GPIO_11 aux. mode clear" "GPIO11 (IO),EINT9 (I),BT_BUCK_EN_HW (O),MA_EDIDO (O),MA_SPI1_B_CS (O),PWM0 (O),SLA_EDIDO (O),?..."
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bitfld.long 0x04 8.--11. " [10] ,GPIO_10 aux. mode clear" "GPIO10 (IO),EINT15 (I),AUXADCIN_4(AIO),,,,,,DEBUGMON15(IO),BTPRI(IO),?..."
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bitfld.long 0x04 4.--6. " [9] ,GPIO_9 aux. mode clear" "GPIO9 (IO),EINT8 (I),MC1_A_DA3 (IO),,,,SDA2 (IO),?..."
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bitfld.long 0x04 0.--2. " [8] ,GPIO_8 aux. mode clear" "GPIO8 (IO),EINT7 (I),MC1_A_DA2 (IO),,,,SCL2 (IO),?..."
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group.long 0xC20++0x03
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line.long 0x00 "GPIO_MODE2,GPIO Mode Control Register"
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bitfld.long 0x00 28.--31. " GPIO_[23] ,Aux. mode of GPIO_23" "GPIO23 (IO),KROW0 (IO),EINT19 (I),CLKO0 (O),U1CTS(I),TRACEDATA3 (O),MC_RST (O),DEBUGMON9 (IO),JTRST_B (I),BTJTRSTB (I),?..."
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bitfld.long 0x00 24.--27. " [22] ,Aux. mode of GPIO_22" "GPIO22 (IO),KROW1 (IO),U1TXD (O),U3TXD (O),,TRACEDATA2 (O),TRACE_SWV (O),DEBUGMON5 (IO),JTDO (O),BTDBGIN (I),?..."
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bitfld.long 0x00 20.--23. " [21] ,Aux. mode of GPIO_21" "GPIO21 (IO),KROW2 (IO),,GPCOUNTER_0 (I),U1RTS (O),TRACECLK (O),,DEBUGMON4 (IO),JTCK (I),BTJTCK (I),?..."
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bitfld.long 0x00 16.--18. " [20] ,Aux. mode of GPIO_20" "GPIO20 (IO),KCOL0 (IO),GPSFSYNC (O),U0CTS (I),SDA2 (IO),,MA_SPI2_CS1(O),DEBUGMON7 (IO)"
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textline " "
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bitfld.long 0x00 12.--15. " [19] ,Aux. mode of GPIO_19" "GPIO19 (IO),KCOL1 (IO),EINT18 (I),U0RTS (O),SCL2 (IO),TRACEDATA1 (O),,DEBUGMON2 (IO),JTMS (IO),BTJTMS (IO),?..."
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bitfld.long 0x00 8.--11. " [18] ,Aux. mode of GPIO_18" "GPIO18 (IO),KCOL2 (IO),U1RXD (I),U3RXD (I),,TRACEDATA0 (O),LSCE1_B1 (O),DEBUGMON6 (IO),JTDI (I),BTJTDI (IO),?..."
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bitfld.long 0x00 4.--6. " [17] ,Aux. mode of GPIO_17" "GPIO17 (IO),U0TXD (O),,EINT17 (I),,,DEBUGMIN_CK (I),?..."
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bitfld.long 0x00 0.--2. " [16] ,Aux. mode of GPIO_16" "GPIO16 (IO),U0RXD (I),,EINT16 (I),,,DEBUGMIN0 (I),DEBUGMON0 (IO)"
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wgroup.long 0xC24++0x07
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line.long 0x00 "GPIO_MODE2_SET,GPIO Mode Set Register"
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bitfld.long 0x00 28.--31. " GPIO_[23] ,GPIO_23 aux. mode set" "GPIO23 (IO),KROW0 (IO),EINT19 (I),CLKO0 (O),U1CTS(I),TRACEDATA3 (O),MC_RST (O),DEBUGMON9 (IO),JTRST_B (I),BTJTRSTB (I),?..."
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bitfld.long 0x00 24.--27. " [22] ,GPIO_22 aux. mode set" "GPIO22 (IO),KROW1 (IO),U1TXD (O),U3TXD (O),,TRACEDATA2 (O),TRACE_SWV (O),DEBUGMON5 (IO),JTDO (O),BTDBGIN (I),?..."
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bitfld.long 0x00 20.--23. " [21] ,GPIO_21 aux. mode set" "GPIO21 (IO),KROW2 (IO),,GPCOUNTER_0 (I),U1RTS (O),TRACECLK (O),,DEBUGMON4 (IO),JTCK (I),BTJTCK (I),?..."
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bitfld.long 0x00 16.--18. " [20] ,GPIO_20 aux. mode set" "GPIO20 (IO),KCOL0 (IO),GPSFSYNC (O),U0CTS (I),SDA2 (IO),,MA_SPI2_CS1(O),DEBUGMON7 (IO)"
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textline " "
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bitfld.long 0x00 12.--15. " [19] ,GPIO_19 aux. mode set" "GPIO19 (IO),KCOL1 (IO),EINT18 (I),U0RTS (O),SCL2 (IO),TRACEDATA1 (O),,DEBUGMON2 (IO),JTMS (IO),BTJTMS (IO),?..."
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bitfld.long 0x00 8.--11. " [18] ,GPIO_18 aux. mode set" "GPIO18 (IO),KCOL2 (IO),U1RXD (I),U3RXD (I),,TRACEDATA0 (O),LSCE1_B1 (O),DEBUGMON6 (IO),JTDI (I),BTJTDI (IO),?..."
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bitfld.long 0x00 4.--6. " [17] ,GPIO_17 aux. mode set" "GPIO17 (IO),U0TXD (O),,EINT17 (I),,,DEBUGMIN_CK (I),?..."
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bitfld.long 0x00 0.--2. " [16] ,GPIO_16 aux. mode set" "GPIO16 (IO),U0RXD (I),,EINT16 (I),,,DEBUGMIN0 (I),DEBUGMON0 (IO)"
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line.long 0x04 "GPIO_MODE2_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 28.--31. " GPIO_[23] ,GPIO_23 aux. mode clear" "GPIO23 (IO),KROW0 (IO),EINT19 (I),CLKO0 (O),U1CTS(I),TRACEDATA3 (O),MC_RST (O),DEBUGMON9 (IO),JTRST_B (I),BTJTRSTB (I),?..."
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bitfld.long 0x04 24.--27. " [22] ,GPIO_22 aux. mode clear" "GPIO22 (IO),KROW1 (IO),U1TXD (O),U3TXD (O),,TRACEDATA2 (O),TRACE_SWV (O),DEBUGMON5 (IO),JTDO (O),BTDBGIN (I),?..."
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bitfld.long 0x04 20.--23. " [21] ,GPIO_21 aux. mode clear" "GPIO21 (IO),KROW2 (IO),,GPCOUNTER_0 (I),U1RTS (O),TRACECLK (O),,DEBUGMON4 (IO),JTCK (I),BTJTCK (I),?..."
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bitfld.long 0x04 16.--18. " [20] ,GPIO_20 aux. mode clear" "GPIO20 (IO),KCOL0 (IO),GPSFSYNC (O),U0CTS (I),SDA2 (IO),,MA_SPI2_CS1(O),DEBUGMON7 (IO)"
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textline " "
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bitfld.long 0x04 12.--15. " [19] ,GPIO_19 aux. mode clear" "GPIO19 (IO),KCOL1 (IO),EINT18 (I),U0RTS (O),SCL2 (IO),TRACEDATA1 (O),,DEBUGMON2 (IO),JTMS (IO),BTJTMS (IO),?..."
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bitfld.long 0x04 8.--11. " [18] ,GPIO_18 aux. mode clear" "GPIO18 (IO),KCOL2 (IO),U1RXD (I),U3RXD (I),,TRACEDATA0 (O),LSCE1_B1 (O),DEBUGMON6 (IO),JTDI (I),BTJTDI (IO),?..."
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bitfld.long 0x04 4.--6. " [17] ,GPIO_17 aux. mode clear" "GPIO17 (IO),U0TXD (O),,EINT17 (I),,,DEBUGMIN_CK (I),?..."
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bitfld.long 0x04 0.--2. " [16] ,GPIO_16 aux. mode clear" "GPIO16 (IO),U0RXD (I),,EINT16 (I),,,DEBUGMIN0 (I),DEBUGMON0 (IO)"
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group.long 0xC30++0x03
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line.long 0x00 "GPIO_MODE3,GPIO Mode Control Register"
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bitfld.long 0x00 28.--31. " GPIO_[31] ,Aux. mode of GPIO_31" "GPIO31 (IO),SDA0 (IO),EINT12 (I),PWM1 (O),U1TXD (I),MC0_CM0 (IO),DEBUGMIN1 (I),DEBUGMON1 (IO),BT_RGPIO1 (IO),SDA2 (IO),?..."
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bitfld.long 0x00 24.--27. " [30] ,Aux. mode of GPIO_30" "GPIO30 (IO),SCL0 (IO),EINT11 (I),PWM0 (O),U1RXD (I),MC0_CK (IO),BT_RGPIO0 (IO),DEBUGMON0 (IO),,SCL2 (IO),?..."
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bitfld.long 0x00 20.--23. " [29] ,Aux. mode of GPIO_29" "GPIO29 (IO),CMCSK (I),LPTE (I),,CMCSD2 (I),EINT10 (I),,DEBUGMON15 (IO),MC1_B_DA1(IO),BT_RGPIO2 (IO),?..."
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bitfld.long 0x00 16.--19. " [28] ,Aux. mode of GPIO_28" "GPIO28 (IO),CMMCLK (O),LSA0DA1 (O),DAISYNC (O),MA_SPI2_A_MISO (I),MA_SPI3_A_MISO (I),JTDO (O),DEBUGMON14 (IO),MC1_B_DA0(IO),SLV_SPI0_MISO (O),?..."
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textline " "
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bitfld.long 0x00 12.--15. " [27] ,Aux. mode of GPIO_27" "GPIO27 (IO),CMCSD1 (O),LSDA1 (IO),DAIPCMOUT (I),MA_SPI2_A_MOSI (O),MA_SPI3_A_MOSI (O),JTRST_B (I),DEBUGMON13 (IO),MC1_B_CK(IO),SLV_SPI0_MOSI (I),?..."
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bitfld.long 0x00 8.--11. " [26] ,Aux. mode of GPIO_26" "GPIO26 (IO),CMCSD0 (O),LSCE_B1 (O),DAIPCMIN (I),MA_SPI2_A_SCK (O),MA_SPI3_A_SCK (O),JTCK (I),DEBUGMON12 (IO),MC1_B_CM0 (IO),SLV_SPI0_SCK (I),?..."
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bitfld.long 0x00 4.--7. " [25] ,Aux. mode of GPIO_25" "GPIO25 (IO),CMPDN (O),LSCK1 (O),DAICLK (O),MA_SPI2_A_CS (O),MA_SPI3_A_CS (O),JTMS (IO),DEBUGMON11 (IO),MC1_B_DA2 (IO),SLV_SPI0_CS (I),?..."
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bitfld.long 0x00 0.--3. " [24] ,Aux. mode of GPIO_24" "GPIO24 (IO),CMRST (O),LSRSTB (O),CLKO1 (O),EINT9 (I),GPCOUNTER_0 (I),JTDI (I),DEBUGMON10 (IO),MC1_B_DA3 (IO),?..."
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wgroup.long 0xC34++0x07
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line.long 0x00 "GPIO_MODE3_SET,GPIO Mode Set Register"
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bitfld.long 0x00 28.--31. " GPIO_[31] ,GPIO_31 aux. mode set" "GPIO31 (IO),SDA0 (IO),EINT12 (I),PWM1 (O),U1TXD (I),MC0_CM0 (IO),DEBUGMIN1 (I),DEBUGMON1 (IO),BT_RGPIO1 (IO),SDA2 (IO),?..."
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bitfld.long 0x00 24.--27. " [30] ,GPIO_30 aux. mode set" "GPIO30 (IO),SCL0 (IO),EINT11 (I),PWM0 (O),U1RXD (I),MC0_CK (IO),BT_RGPIO0 (IO),DEBUGMON0 (IO),,SCL2 (IO),?..."
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bitfld.long 0x00 20.--23. " [29] ,GPIO_29 aux. mode set" "GPIO29 (IO),CMCSK (I),LPTE (I),,CMCSD2 (I),EINT10 (I),,DEBUGMON15 (IO),MC1_B_DA1(IO),BT_RGPIO2 (IO),?..."
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bitfld.long 0x00 16.--19. " [28] ,GPIO_28 aux. mode set" "GPIO28 (IO),CMMCLK (O),LSA0DA1 (O),DAISYNC (O),MA_SPI2_A_MISO (I),MA_SPI3_A_MISO (I),JTDO (O),DEBUGMON14 (IO),MC1_B_DA0(IO),SLV_SPI0_MISO (O),?..."
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textline " "
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bitfld.long 0x00 12.--15. " [27] ,GPIO_27 aux. mode set" "GPIO27 (IO),CMCSD1 (O),LSDA1 (IO),DAIPCMOUT (I),MA_SPI2_A_MOSI (O),MA_SPI3_A_MOSI (O),JTRST_B (I),DEBUGMON13 (IO),MC1_B_CK(IO),SLV_SPI0_MOSI (I),?..."
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bitfld.long 0x00 8.--11. " [26] ,GPIO_26 aux. mode set" "GPIO26 (IO),CMCSD0 (O),LSCE_B1 (O),DAIPCMIN (I),MA_SPI2_A_SCK (O),MA_SPI3_A_SCK (O),JTCK (I),DEBUGMON12 (IO),MC1_B_CM0 (IO),SLV_SPI0_SCK (I),?..."
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bitfld.long 0x00 4.--7. " [25] ,GPIO_25 aux. mode set" "GPIO25 (IO),CMPDN (O),LSCK1 (O),DAICLK (O),MA_SPI2_A_CS (O),MA_SPI3_A_CS (O),JTMS (IO),DEBUGMON11 (IO),MC1_B_DA2 (IO),SLV_SPI0_CS (I),?..."
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bitfld.long 0x00 0.--3. " [24] ,GPIO_24 aux. mode set" "GPIO24 (IO),CMRST (O),LSRSTB (O),CLKO1 (O),EINT9 (I),GPCOUNTER_0 (I),JTDI (I),DEBUGMON10 (IO),MC1_B_DA3 (IO),?..."
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line.long 0x04 "GPIO_MODE3_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 28.--31. " GPIO_[31] ,GPIO_31 aux. mode clear" "GPIO31 (IO),SDA0 (IO),EINT12 (I),PWM1 (O),U1TXD (I),MC0_CM0 (IO),DEBUGMIN1 (I),DEBUGMON1 (IO),BT_RGPIO1 (IO),SDA2 (IO),?..."
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bitfld.long 0x04 24.--27. " [30] ,GPIO_30 aux. mode clear" "GPIO30 (IO),SCL0 (IO),EINT11 (I),PWM0 (O),U1RXD (I),MC0_CK (IO),BT_RGPIO0 (IO),DEBUGMON0 (IO),,SCL2 (IO),?..."
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bitfld.long 0x04 20.--23. " [29] ,GPIO_29 aux. mode clear" "GPIO29 (IO),CMCSK (I),LPTE (I),,CMCSD2 (I),EINT10 (I),,DEBUGMON15 (IO),MC1_B_DA1(IO),BT_RGPIO2 (IO),?..."
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bitfld.long 0x04 16.--19. " [28] ,GPIO_28 aux. mode clear" "GPIO28 (IO),CMMCLK (O),LSA0DA1 (O),DAISYNC (O),MA_SPI2_A_MISO (I),MA_SPI3_A_MISO (I),JTDO (O),DEBUGMON14 (IO),MC1_B_DA0(IO),SLV_SPI0_MISO (O),?..."
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textline " "
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bitfld.long 0x04 12.--15. " [27] ,GPIO_27 aux. mode clear" "GPIO27 (IO),CMCSD1 (O),LSDA1 (IO),DAIPCMOUT (I),MA_SPI2_A_MOSI (O),MA_SPI3_A_MOSI (O),JTRST_B (I),DEBUGMON13 (IO),MC1_B_CK(IO),SLV_SPI0_MOSI (I),?..."
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bitfld.long 0x04 8.--11. " [26] ,GPIO_26 aux. mode clear" "GPIO26 (IO),CMCSD0 (O),LSCE_B1 (O),DAIPCMIN (I),MA_SPI2_A_SCK (O),MA_SPI3_A_SCK (O),JTCK (I),DEBUGMON12 (IO),MC1_B_CM0 (IO),SLV_SPI0_SCK (I),?..."
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bitfld.long 0x04 4.--7. " [25] ,GPIO_25 aux. mode clear" "GPIO25 (IO),CMPDN (O),LSCK1 (O),DAICLK (O),MA_SPI2_A_CS (O),MA_SPI3_A_CS (O),JTMS (IO),DEBUGMON11 (IO),MC1_B_DA2 (IO),SLV_SPI0_CS (I),?..."
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bitfld.long 0x04 0.--3. " [24] ,GPIO_24 aux. mode clear" "GPIO24 (IO),CMRST (O),LSRSTB (O),CLKO1 (O),EINT9 (I),GPCOUNTER_0 (I),JTDI (I),DEBUGMON10 (IO),MC1_B_DA3 (IO),?..."
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group.long 0xC40++0x03
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line.long 0x00 "GPIO_MODE4,GPIO Mode Control Register"
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bitfld.long 0x00 28.--31. " GPIO_[39] ,Aux. mode of GPIO_39" "GPIO39 (IO),LSCE_B0 (O),EINT4 (I),CMCSD0 (I),CLKO4 (O),SFSCS0 (O),DEBUGMIN5 (I),DEBUGMON5 (IO),SCL1 (IO),MA_SPI2_B_CS (O),?..."
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bitfld.long 0x00 24.--27. " [38] ,Aux. mode of GPIO_38" "GPIO38 (IO),LSRSTB (O),,CMRST (O),CLKO3 (O),SFSWP (O),,DEBUGMON9 (IO),,SCL1(IO),?..."
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bitfld.long 0x00 20.--22. " [37] ,Aux. mode of GPIO_37" "GPIO37 (IO),SDA0 (IO),SDA1 (IO),,,,DEBUGMIN4 (I),DEBUGMON4 (IO)"
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bitfld.long 0x00 16.--18. " [36] ,Aux. mode of GPIO_36" "GPIO36 (IO),SCL0 (IO),SCL1 (IO),,,,DEBUGMIN3 (I),DEBUGMON3 (IO)"
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textline " "
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bitfld.long 0x00 12.--15. " [35] ,Aux. mode of GPIO_35" "GPIO35 (IO),SLV_SPI0_MISO (I),EINT3 (I),PWM5 (O),DAIPCMOUT (I),MC0_DA3 (IO),CLKO2 (O),BT_RGPIO5 (IO),,MA_SPI3_B_MISO (I),?..."
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bitfld.long 0x00 8.--11. " [34] ,Aux. mode of GPIO_34" "GPIO34 (IO),SLV_SPI0_MOSI (I),EINT15 (I),PWM4 (O),DAICLK (I),MC0_DA2 (IO),BT_RGPIO4 (IO),DEBUGMON4 (IO),,MA_SPI3_B_MOSI (O),?..."
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bitfld.long 0x00 4.--7. " [33] ,Aux. mode of GPIO_33" "GPIO33 (IO),SLV_SPI0_SCK (I),EINT14 (I),PWM3 (O),DAIPCMIN (I),MC0_DA1 (IO),BT_RGPIO3 (IO),DEBUGMON3 (IO),,MA_SPI3_B_SCK (O),?..."
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bitfld.long 0x00 0.--3. " [32] ,Aux. mode of GPIO_32" "GPIO32 (IO),SLV_SPI0_CS (I),EINT13 (I),PWM2 (O),DAISYNC (O),MC0_DA0 (IO),DEBUGMIN2 (I),DEBUGMON2 (IO),,MA_SPI3_B_CS (O),?..."
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wgroup.long 0xC44++0x07
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line.long 0x00 "GPIO_MODE4_SET,GPIO Mode Set Register"
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bitfld.long 0x00 28.--31. " GPIO_[39] ,GPIO_39 aux. mode set" "GPIO39 (IO),LSCE_B0 (O),EINT4 (I),CMCSD0 (I),CLKO4 (O),SFSCS0 (O),DEBUGMIN5 (I),DEBUGMON5 (IO),SCL1 (IO),MA_SPI2_B_CS (O),?..."
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bitfld.long 0x00 24.--27. " [38] ,GPIO_38 aux. mode set" "GPIO38 (IO),LSRSTB (O),,CMRST (O),CLKO3 (O),SFSWP (O),,DEBUGMON9 (IO),,SCL1(IO),?..."
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bitfld.long 0x00 20.--22. " [37] ,GPIO_37 aux. mode set" "GPIO37 (IO),SDA0 (IO),SDA1 (IO),,,,DEBUGMIN4 (I),DEBUGMON4 (IO)"
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bitfld.long 0x00 16.--18. " [36] ,GPIO_36 aux. mode set" "GPIO36 (IO),SCL0 (IO),SCL1 (IO),,,,DEBUGMIN3 (I),DEBUGMON3 (IO)"
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textline " "
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bitfld.long 0x00 12.--15. " [35] ,GPIO_35 aux. mode set" "GPIO35 (IO),SLV_SPI0_MISO (I),EINT3 (I),PWM5 (O),DAIPCMOUT (I),MC0_DA3 (IO),CLKO2 (O),BT_RGPIO5 (IO),,MA_SPI3_B_MISO (I),?..."
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bitfld.long 0x00 8.--11. " [34] ,GPIO_34 aux. mode set" "GPIO34 (IO),SLV_SPI0_MOSI (I),EINT15 (I),PWM4 (O),DAICLK (I),MC0_DA2 (IO),BT_RGPIO4 (IO),DEBUGMON4 (IO),,MA_SPI3_B_MOSI (O),?..."
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bitfld.long 0x00 4.--7. " [33] ,GPIO_33 aux. mode set" "GPIO33 (IO),SLV_SPI0_SCK (I),EINT14 (I),PWM3 (O),DAIPCMIN (I),MC0_DA1 (IO),BT_RGPIO3 (IO),DEBUGMON3 (IO),,MA_SPI3_B_SCK (O),?..."
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bitfld.long 0x00 0.--3. " [32] ,GPIO_32 aux. mode set" "GPIO32 (IO),SLV_SPI0_CS (I),EINT13 (I),PWM2 (O),DAISYNC (O),MC0_DA0 (IO),DEBUGMIN2 (I),DEBUGMON2 (IO),,MA_SPI3_B_CS (O),?..."
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line.long 0x04 "GPIO_MODE4_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 28.--31. " GPIO_[39] ,GPIO_39 aux. mode clear" "GPIO39 (IO),LSCE_B0 (O),EINT4 (I),CMCSD0 (I),CLKO4 (O),SFSCS0 (O),DEBUGMIN5 (I),DEBUGMON5 (IO),SCL1 (IO),MA_SPI2_B_CS (O),?..."
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bitfld.long 0x04 24.--27. " [38] ,GPIO_38 aux. mode clear" "GPIO38 (IO),LSRSTB (O),,CMRST (O),CLKO3 (O),SFSWP (O),,DEBUGMON9 (IO),,SCL1(IO),?..."
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bitfld.long 0x04 20.--22. " [37] ,GPIO_37 aux. mode clear" "GPIO37 (IO),SDA0 (IO),SDA1 (IO),,,,DEBUGMIN4 (I),DEBUGMON4 (IO)"
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bitfld.long 0x04 16.--18. " [36] ,GPIO_36 aux. mode clear" "GPIO36 (IO),SCL0 (IO),SCL1 (IO),,,,DEBUGMIN3 (I),DEBUGMON3 (IO)"
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textline " "
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bitfld.long 0x04 12.--15. " [35] ,GPIO_35 aux. mode clear" "GPIO35 (IO),SLV_SPI0_MISO (I),EINT3 (I),PWM5 (O),DAIPCMOUT (I),MC0_DA3 (IO),CLKO2 (O),BT_RGPIO5 (IO),,MA_SPI3_B_MISO (I),?..."
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bitfld.long 0x04 8.--11. " [34] ,GPIO_34 aux. mode clear" "GPIO34 (IO),SLV_SPI0_MOSI (I),EINT15 (I),PWM4 (O),DAICLK (I),MC0_DA2 (IO),BT_RGPIO4 (IO),DEBUGMON4 (IO),,MA_SPI3_B_MOSI (O),?..."
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bitfld.long 0x04 4.--7. " [33] ,GPIO_33 aux. mode clear" "GPIO33 (IO),SLV_SPI0_SCK (I),EINT14 (I),PWM3 (O),DAIPCMIN (I),MC0_DA1 (IO),BT_RGPIO3 (IO),DEBUGMON3 (IO),,MA_SPI3_B_SCK (O),?..."
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bitfld.long 0x04 0.--3. " [32] ,GPIO_32 aux. mode clear" "GPIO32 (IO),SLV_SPI0_CS (I),EINT13 (I),PWM2 (O),DAISYNC (O),MC0_DA0 (IO),DEBUGMIN2 (I),DEBUGMON2 (IO),,MA_SPI3_B_CS (O),?..."
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group.long 0xC50++0x03
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line.long 0x00 "GPIO_MODE5,GPIO Mode Control Register"
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bitfld.long 0x00 28.--30. " GPIO_[47] ,Aux. mode of GPIO_47" "GPIO47 (IO),MA_SPI1_CS1 (O),,,,,,DEBUGMON2 (IO)"
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bitfld.long 0x00 24.--26. " [46] ,Aux. mode of GPIO_46" "GPIO46 (IO),MA_SPI0_CS1 (O),,,,,,DEBUGMON1 (IO)"
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bitfld.long 0x00 20.--22. " [45] ,Aux. mode of GPIO_45" "GPIO45 (IO),SRCLKENAI (I),?..."
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bitfld.long 0x00 16.--19. " [44] ,Aux. mode of GPIO_44" "GPIO44 (IO),LSCE1_B1 (O),DISP_PWM (O),,,,,DEBUGMON0 (IO),DEBUGMON6 (IO),?..."
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textline " "
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bitfld.long 0x00 12.--15. " [43] ,Aux. mode of GPIO_43" "GPIO43 (IO),LPTE (I),EINT6 (I),CMCSK (I),CMCSD2 (I),SFSIN (O),,DEBUGMON7 (IO),DEBUGMIN7 (I),SDA1 (IO),?..."
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bitfld.long 0x00 8.--11. " [42] ,Aux. mode of GPIO_42" "GPIO42 (IO),LSA0DA0 (O),LSCE1_B0 (O),CMMCLK (O),,SFSOUT (O),,DEBUGMON8 (IO),CLKO5 (O),MA_SPI2_B_MISO (O),?..."
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bitfld.long 0x00 4.--7. " [41] ,Aux. mode of GPIO_41" "GPIO41 (IO),LSDA0 (IO),EINT5 (I),CMCSD1 (I),WIFITOBT (I),SFSCK (O),DEBUGMIN6 (I),DEBUGMON6 (IO),SDA1 (IO),MA_SPI2_B_MOSI (O),?..."
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bitfld.long 0x00 0.--3. " [40] ,Aux. mode of GPIO_40" "GPIO40 (IO),LSCK0 (O),,CMPDN (O),,SFSHOLD (O),,DEBUGMON10 (IO),,MA_SPI2_B_SCK (O),?..."
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wgroup.long 0xC54++0x07
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line.long 0x00 "GPIO_MODE5_SET,GPIO Mode Set Register"
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bitfld.long 0x00 28.--30. " GPIO_[47] ,GPIO_47 aux. mode set" "GPIO47 (IO),MA_SPI1_CS1 (O),,,,,,DEBUGMON2 (IO)"
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bitfld.long 0x00 24.--26. " [46] ,GPIO_46 aux. mode set" "GPIO46 (IO),MA_SPI0_CS1 (O),,,,,,DEBUGMON1 (IO)"
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bitfld.long 0x00 20.--22. " [45] ,GPIO_45 aux. mode set" "GPIO45 (IO),SRCLKENAI (I),?..."
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bitfld.long 0x00 16.--19. " [44] ,GPIO_44 aux. mode set" "GPIO44 (IO),LSCE1_B1 (O),DISP_PWM (O),,,,,DEBUGMON0 (IO),DEBUGMON6 (IO),?..."
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textline " "
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bitfld.long 0x00 12.--15. " [43] ,GPIO_43 aux. mode set" "GPIO43 (IO),LPTE (I),EINT6 (I),CMCSK (I),CMCSD2 (I),SFSIN (O),,DEBUGMON7 (IO),DEBUGMIN7 (I),SDA1 (IO),?..."
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bitfld.long 0x00 8.--11. " [42] ,GPIO_42 aux. mode set" "GPIO42 (IO),LSA0DA0 (O),LSCE1_B0 (O),CMMCLK (O),,SFSOUT (O),,DEBUGMON8 (IO),CLKO5 (O),MA_SPI2_B_MISO (O),?..."
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bitfld.long 0x00 4.--7. " [41] ,GPIO_41 aux. mode set" "GPIO41 (IO),LSDA0 (IO),EINT5 (I),CMCSD1 (I),WIFITOBT (I),SFSCK (O),DEBUGMIN6 (I),DEBUGMON6 (IO),SDA1 (IO),MA_SPI2_B_MOSI (O),?..."
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bitfld.long 0x00 0.--3. " [40] ,GPIO_40 aux. mode set" "GPIO40 (IO),LSCK0 (O),,CMPDN (O),,SFSHOLD (O),,DEBUGMON10 (IO),,MA_SPI2_B_SCK (O),?..."
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line.long 0x04 "GPIO_MODE5_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 28.--30. " GPIO_[47] ,GPIO_47 aux. mode clear" "GPIO47 (IO),MA_SPI1_CS1 (O),,,,,,DEBUGMON2 (IO)"
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bitfld.long 0x04 24.--26. " [46] ,GPIO_46 aux. mode clear" "GPIO46 (IO),MA_SPI0_CS1 (O),,,,,,DEBUGMON1 (IO)"
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bitfld.long 0x04 20.--22. " [45] ,GPIO_45 aux. mode clear" "GPIO45 (IO),SRCLKENAI (I),?..."
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bitfld.long 0x04 16.--19. " [44] ,GPIO_44 aux. mode clear" "GPIO44 (IO),LSCE1_B1 (O),DISP_PWM (O),,,,,DEBUGMON0 (IO),DEBUGMON6 (IO),?..."
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textline " "
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bitfld.long 0x04 12.--15. " [43] ,GPIO_43 aux. mode clear" "GPIO43 (IO),LPTE (I),EINT6 (I),CMCSK (I),CMCSD2 (I),SFSIN (O),,DEBUGMON7 (IO),DEBUGMIN7 (I),SDA1 (IO),?..."
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bitfld.long 0x04 8.--11. " [42] ,GPIO_42 aux. mode clear" "GPIO42 (IO),LSA0DA0 (O),LSCE1_B0 (O),CMMCLK (O),,SFSOUT (O),,DEBUGMON8 (IO),CLKO5 (O),MA_SPI2_B_MISO (O),?..."
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bitfld.long 0x04 4.--7. " [41] ,GPIO_41 aux. mode clear" "GPIO41 (IO),LSDA0 (IO),EINT5 (I),CMCSD1 (I),WIFITOBT (I),SFSCK (O),DEBUGMIN6 (I),DEBUGMON6 (IO),SDA1 (IO),MA_SPI2_B_MOSI (O),?..."
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bitfld.long 0x04 0.--3. " [40] ,GPIO_40 aux. mode clear" "GPIO40 (IO),LSCK0 (O),,CMPDN (O),,SFSHOLD (O),,DEBUGMON10 (IO),,MA_SPI2_B_SCK (O),?..."
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group.long 0xC60++0x03
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line.long 0x00 "GPIO_MODE6,GPIO Mode Control Register"
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bitfld.long 0x00 0.--2. " GPIO_[48] ,Aux. mode of GPIO_48" "GPIO48 (IO),MA_SPI3_CS1 (O),,,,,,DEBUGMON5 (IO)"
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wgroup.long 0xC64++0x07
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line.long 0x00 "GPIO_MODE6_SET,GPIO Mode Set Register"
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bitfld.long 0x00 0.--2. " GPIO_[48] ,GPIO_48 aux. mode set" "GPIO48 (IO),MA_SPI3_CS1 (O),,,,,,DEBUGMON5 (IO)"
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line.long 0x04 "GPIO_MODE5_CLR,GPIO Mode Clear Register"
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bitfld.long 0x04 0.--2. " GPIO_[48] ,GPIO_48 aux. mode clear" "GPIO48 (IO),MA_SPI3_CS1 (O),,,,,,DEBUGMON5 (IO)"
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textline " "
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group.long 0xD00++0x03
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line.long 0x00 "GPIO_TDSEL0,GPIO TDSEL Control Register"
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bitfld.long 0x00 30.--31. " GPIO_[15] ,GPIO15 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 28.--29. " [14] ,GPIO14 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 26.--27. " [13] ,GPIO13 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 24.--25. " [12] ,GPIO12 Tx duty control" "0,1,2,3"
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textline " "
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bitfld.long 0x00 22.--23. " [11] ,GPIO11 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 20.--21. " [10] ,GPIO10 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 18.--19. " [9] ,GPIO9 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 16.--17. " [8] ,GPIO8 Tx duty control" "0,1,2,3"
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textline " "
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bitfld.long 0x00 14.--15. " [7] ,GPIO7 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 12.--13. " [6] ,GPIO6 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 10.--11. " [5] ,GPIO5 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 8.--9. " [4] ,GPIO4 Tx duty control" "0,1,2,3"
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textline " "
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bitfld.long 0x00 6.--7. " [3] ,GPIO3 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 4.--5. " [2] ,GPIO2 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 2.--3. " [1] ,GPIO1 Tx duty control" "0,1,2,3"
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bitfld.long 0x00 0.--1. " [0] ,GPIO0 Tx duty control" "0,1,2,3"
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wgroup.long 0xD04++0x07
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line.long 0x00 "GPIO_TDSEL0_SET,GPIO TDSEL Control Register"
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bitfld.long 0x00 30.--31. " GPIO_[15] ,Bitwise SET operation of GPIO15_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 28.--29. " [14] ,Bitwise SET operation of GPIO14_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 26.--27. " [13] ,Bitwise SET operation of GPIO13_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 24.--25. " [12] ,Bitwise SET operation of GPIO12_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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textline " "
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bitfld.long 0x00 22.--23. " [11] ,Bitwise SET operation of GPIO11_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 20.--21. " [10] ,Bitwise SET operation of GPIO10_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 18.--19. " [9] ,Bitwise SET operation of GPIO9_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 16.--17. " [8] ,Bitwise SET operation of GPIO8_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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textline " "
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bitfld.long 0x00 14.--15. " [7] ,Bitwise SET operation of GPIO7_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
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bitfld.long 0x00 12.--13. " [6] ,Bitwise SET operation of GPIO6_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 10.--11. " [5] ,Bitwise SET operation of GPIO5_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 8.--9. " [4] ,Bitwise SET operation of GPIO4_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [3] ,Bitwise SET operation of GPIO3_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 4.--5. " [2] ,Bitwise SET operation of GPIO2_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 2.--3. " [1] ,Bitwise SET operation of GPIO1_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 0.--1. " [0] ,Bitwise SET operation of GPIO0_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_TDSEL0_CLR,GPIO TDSEL Control Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[15] ,Bitwise CLR operation of GPIO15_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 28.--29. " [14] ,Bitwise CLR operation of GPIO14_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 26.--27. " [13] ,Bitwise CLR operation of GPIO13_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 24.--25. " [12] ,Bitwise CLR operation of GPIO12_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [11] ,Bitwise CLR operation of GPIO11_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 20.--21. " [10] ,Bitwise CLR operation of GPIO10_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 18.--19. " [9] ,Bitwise CLR operation of GPIO9_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 16.--17. " [8] ,Bitwise CLR operation of GPIO8_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [7] ,Bitwise CLR operation of GPIO7_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 12.--13. " [6] ,Bitwise CLR operation of GPIO6_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 10.--11. " [5] ,Bitwise CLR operation of GPIO5_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 8.--9. " [4] ,Bitwise CLR operation of GPIO4_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [3] ,Bitwise CLR operation of GPIO3_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 4.--5. " [2] ,Bitwise CLR operation of GPIO2_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 2.--3. " [1] ,Bitwise CLR operation of GPIO1_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 0.--1. " [0] ,Bitwise CLR operation of GPIO0_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "GPIO_TDSEL1,GPIO TDSEL Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[31] ,GPIO31 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " [30] ,GPIO30 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " [29] ,GPIO29 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " [28] ,GPIO28 Tx duty control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [27] ,GPIO27 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " [26] ,GPIO26 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " [25] ,GPIO25 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " [24] ,GPIO24 Tx duty control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [23] ,GPIO23 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " [22] ,GPIO22 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " [21] ,GPIO21 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " [20] ,GPIO20 Tx duty control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [19] ,GPIO19 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " [18] ,GPIO18 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " [17] ,GPIO17 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " [16] ,GPIO16 Tx duty control" "0,1,2,3"
|
|
wgroup.long 0xD14++0x07
|
|
line.long 0x00 "GPIO_TDSEL1_SET,GPIO TDSEL Set Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[31] ,Bitwise SET operation of GPIO31_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 28.--29. " [30] ,Bitwise SET operation of GPIO30_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 26.--27. " [29] ,Bitwise SET operation of GPIO29_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 24.--25. " [28] ,Bitwise SET operation of GPIO28_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [27] ,Bitwise SET operation of GPIO27_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 20.--21. " [26] ,Bitwise SET operation of GPIO26_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 18.--19. " [25] ,Bitwise SET operation of GPIO25_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 16.--17. " [24] ,Bitwise SET operation of GPIO24_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [23] ,Bitwise SET operation of GPIO23_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 12.--13. " [22] ,Bitwise SET operation of GPIO22_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 10.--11. " [21] ,Bitwise SET operation of GPIO21_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 8.--9. " [20] ,Bitwise SET operation of GPIO20_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [19] ,Bitwise SET operation of GPIO19_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 4.--5. " [18] ,Bitwise SET operation of GPIO18_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 2.--3. " [17] ,Bitwise SET operation of GPIO17_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 0.--1. " [16] ,Bitwise SET operation of GPIO16_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_TDSEL1_CLR,GPIO TDSEL Clear Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[31] ,Bitwise CLR operation of GPIO31_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 28.--29. " [30] ,Bitwise CLR operation of GPIO30_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 26.--27. " [29] ,Bitwise CLR operation of GPIO29_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 24.--25. " [28] ,Bitwise CLR operation of GPIO28_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [27] ,Bitwise CLR operation of GPIO27_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 20.--21. " [26] ,Bitwise CLR operation of GPIO26_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 18.--19. " [25] ,Bitwise CLR operation of GPIO25_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 16.--17. " [24] ,Bitwise CLR operation of GPIO24_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [23] ,Bitwise CLR operation of GPIO23_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 12.--13. " [22] ,Bitwise CLR operation of GPIO22_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 10.--11. " [21] ,Bitwise CLR operation of GPIO21_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 8.--9. " [20] ,Bitwise CLR operation of GPIO20_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [19] ,Bitwise CLR operation of GPIO19_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 4.--5. " [18] ,Bitwise CLR operation of GPIO18_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 2.--3. " [17] ,Bitwise CLR operation of GPIO17_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 0.--1. " [16] ,Bitwise CLR operation of GPIO16_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "GPIO_TDSEL2,GPIO TDSEL Control Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[47] ,GPIO47 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " [46] ,GPIO46 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " [45] ,GPIO45 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " [44] ,GPIO44 Tx duty control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [43] ,GPIO43 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " [42] ,GPIO42 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " [41] ,GPIO41 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " [40] ,GPIO40 Tx duty control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [39] ,GPIO39 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " [38] ,GPIO38 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " [37] ,GPIO37 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " [36] ,GPIO36 Tx duty control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [35] ,GPIO35 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " [34] ,GPIO34 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " [33] ,GPIO33 Tx duty control" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " [32] ,GPIO32 Tx duty control" "0,1,2,3"
|
|
wgroup.long 0xD24++0x07
|
|
line.long 0x00 "GPIO_TDSEL2_SET,GPIO TDSEL Set Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[31] ,Bitwise SET operation of GPIO47_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 28.--29. " [46] ,Bitwise SET operation of GPIO46_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 26.--27. " [45] ,Bitwise SET operation of GPIO45_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 24.--25. " [44] ,Bitwise SET operation of GPIO44_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [43] ,Bitwise SET operation of GPIO43_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 20.--21. " [42] ,Bitwise SET operation of GPIO42_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 18.--19. " [41] ,Bitwise SET operation of GPIO41_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 16.--17. " [40] ,Bitwise SET operation of GPIO40_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [39] ,Bitwise SET operation of GPIO39_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 12.--13. " [38] ,Bitwise SET operation of GPIO38_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 10.--11. " [37] ,Bitwise SET operation of GPIO37_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 8.--9. " [36] ,Bitwise SET operation of GPIO36_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [35] ,Bitwise SET operation of GPIO35_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 4.--5. " [34] ,Bitwise SET operation of GPIO34_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 2.--3. " [33] ,Bitwise SET operation of GPIO33_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
bitfld.long 0x00 0.--1. " [32] ,Bitwise SET operation of GPIO32_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_TDSEL2_CLR,GPIO TDSEL Clear Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[47] ,Bitwise CLR operation of GPIO47_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 28.--29. " [46] ,Bitwise CLR operation of GPIO46_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 26.--27. " [45] ,Bitwise CLR operation of GPIO45_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 24.--25. " [44] ,Bitwise CLR operation of GPIO44_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [43] ,Bitwise CLR operation of GPIO43_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 20.--21. " [42] ,Bitwise CLR operation of GPIO42_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 18.--19. " [41] ,Bitwise CLR operation of GPIO41_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 16.--17. " [40] ,Bitwise CLR operation of GPIO40_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [39] ,Bitwise CLR operation of GPIO39_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 12.--13. " [38] ,Bitwise CLR operation of GPIO38_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 10.--11. " [37] ,Bitwise CLR operation of GPIO37_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 8.--9. " [36] ,Bitwise CLR operation of GPIO36_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [35] ,Bitwise CLR operation of GPIO35_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 4.--5. " [34] ,Bitwise CLR operation of GPIO34_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 2.--3. " [33] ,Bitwise CLR operation of GPIO33_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
bitfld.long 0x04 0.--1. " [32] ,Bitwise CLR operation of GPIO32_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
textline " "
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "GPIO_TDSEL3,GPIO TDSEL Control Register"
|
|
bitfld.long 0x00 0.--1. " GPIO_[48] ,GPIO48 Tx duty control" "0,1,2,3"
|
|
wgroup.long 0xD34++0x07
|
|
line.long 0x00 "GPIO_TDSEL3_SET,GPIO TDSEL Set Register"
|
|
bitfld.long 0x00 30.--31. " GPIO_[48] ,Bitwise SET operation of GPIO48_TDSEL Tx duty control" "No effect,Set LSB,Set MSB,Set both"
|
|
line.long 0x04 "GPIO_TDSEL3_CLR,GPIO TDSEL Clear Register"
|
|
bitfld.long 0x04 30.--31. " GPIO_[48] ,Bitwise CLR operation of GPIO48_TDSEL Tx duty control" "No effect,Clear LSB,Clear MSB,Clear both"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "CLK_OUT0,CLK Out 0 Selection Control Register"
|
|
bitfld.long 0x00 0.--3. " CLK_OUT0 ,Select clock output for CLKO_0" ",f26m_mcusys_ck,,,f32k_mcusys_ck,?..."
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "CLK_OUT1,CLK Out 1 Selection Control Register"
|
|
bitfld.long 0x00 0.--3. " CLK_OUT1 ,Select clock output for CLKO_1" ",f26m_mcusys_ck,,,f32k_mcusys_ck,?..."
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "CLK_OUT2,CLK Out 2 Selection Control Register"
|
|
bitfld.long 0x00 0.--3. " CLK_OUT2 ,Select clock output for CLKO_2" ",f26m_mcusys_ck,,,f32k_mcusys_ck,?..."
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "CLK_OUT3,CLK Out 3 Selection Control Register"
|
|
bitfld.long 0x00 0.--3. " CLK_OUT3 ,Select clock output for CLKO_3" ",f26m_mcusys_ck,,,f32k_mcusys_ck,?..."
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "CLK_OUT4,CLK Out 4 Selection Control Register"
|
|
bitfld.long 0x00 0.--3. " CLK_OUT4 ,Select clock output for CLKO_4" ",f26m_mcusys_ck,,,f32k_mcusys_ck,?..."
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "CLK_OUT5,CLK Out 5 Selection Control Register"
|
|
bitfld.long 0x00 0.--3. " CLK_OUT5 ,Select clock output for CLKO_5" ",f26m_mcusys_ck,,,f32k_mcusys_ck,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMU (Power Management Unit)"
|
|
base ad:0xA21A0000
|
|
width 20.
|
|
rgroup.byte 0x1D++0x0F
|
|
line.byte 0x00 "RSTCFG3,Reset Config 3 Register"
|
|
bitfld.byte 0x00 2. " WDTRSTB_STATUS ,WDTRSTB reset" "No reset,Reset"
|
|
group.byte 0x1E++0x0E
|
|
line.byte 0x00 "INTSTS0,Interrupt Status/Clear 0"
|
|
eventfld.byte 0x00 7. " INTS_DLDO_PG_F ,DLDO_PG_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " INTS_DLDO_PG_R ,DLDO_PG_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " INTS_DLDO_OC_F ,DLDO_OC_F interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " INTS_DLDO_OC_R ,DLDO_OC_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " INTS_ALDO_PG_F ,ALDO_PG_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " INTS_ALDO_PG_R ,ALDO_PG_R interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " INTS_ALDO_OC_F ,ALDO_OC_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " INTS_ALDO_OC_R ,ALDO_OC_R interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x01 "INTSTS1,Interrupt Status/Clear 1 Register"
|
|
eventfld.byte 0x01 7. " INTS_PKEYLP_F ,PKEYLP_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 6. " INTS_PKEYLP_R ,PKEYLP_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 5. " INTS_VC_LDO_OC_F ,VC_LDO_OC_F interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x01 4. " INTS_VC_LDO_OC_R ,VC_LDO_OC_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 3. " INTS_VCORE_PG_F ,VCORE_PG_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 2. " INTS_VCORE_PG_R ,VCORE_PG_R interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x01 1. " INTS_VC_BUCK_OC_F ,VC_BUCK_OC_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 0. " INTS_VC_BUCK_OC_R ,VC_BUCK_OC_R interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x02 "INTSTS2,Interrupt Status/Clear 2 Register"
|
|
eventfld.byte 0x02 7. " INTS_PWRKEY_F ,PWRKEY_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " INTS_PWRKEY_R ,PWRKEY_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " INTS_AXPKEY_F ,AXPKEY_F interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x02 4. " INTS_AXPKEY_R ,AXPKEY_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 3. " INTS_THM2_F ,THM2_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " INTS_THM2_R ,THM2_R interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " INTS_THM1_F ,THM1_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 0. " INTS_THM1_R ,THM1_R interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x03 "INTSTS3,Interrupt Status/Clear 3"
|
|
eventfld.byte 0x03 7. " INTS_THR_L_F ,THR_L_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x03 6. " INTS_THR_L_R ,THR_L_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x03 5. " INTS_THR_H_F ,THR_H_F interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x03 4. " INTS_THR_H_R ,THR_H_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x03 3. " INTS_CHRDET_F ,CHRDET_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x03 2. " INTS_CHRDET_R ,CHRDET_R interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x03 1. " INTS_CHGOV_F ,CHGOV_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x03 0. " INTS_CHGOV_R ,CHGOV_R interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x04 "INTSTS4,Interrupt Status/Clear 4 Register"
|
|
eventfld.byte 0x04 5. " INTS_PSW_PG_F ,PSW_PG_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x04 4. " INTS_PSW_PG_R ,PSW_PG_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x04 3. " INTS_OVER40_F ,OVER40_F interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x04 2. " INTS_OVER40_R ,OVER40_R interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x04 1. " INTS_OVER110_F ,OVER110_F interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x04 0. " INTS_OVER110_R ,OVER110_R interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x05 "INTSTS5,Interrupt Status/Clear 5 Register"
|
|
eventfld.byte 0x05 7. " INTS_WARM_LV ,WARM_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x05 6. " INTS_HOT_LV ,HOT_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x05 5. " INTS_CHRWDT_LV ,CHRWDT_LV interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x05 4. " INTS_BVALID_DET_LV ,BVALID_DET_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x05 3. " INTS_VBAT_UNDET_LV ,VBAT_UNDET_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x05 2. " INTS_VBATON_HV_LV ,VBATON_HV_LV interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x05 1. " INTS_BAT_L_LV ,BAT_L_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x05 0. " INTS_BAT_H_LV ,BAT_H_LV interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x06 "INTSTS6,Interrupt Status/Clear 6 Register"
|
|
eventfld.byte 0x06 4. " INTS_AD_LBAT_LV ,AD_LBAT_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x06 3. " INTS_NAG_C_LV ,NAG_C_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x06 2. " INTS_IMP_LV ,IMP_LV interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x06 1. " INTS_COLD_LV ,COLD_LV interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x06 0. " INTS_COOL_LV ,COOL_LV interrupt" "No interrupt,Interrupt"
|
|
line.byte 0x07 "INTEN0,Interrupt Enable 0 Register"
|
|
bitfld.byte 0x07 7. " INTE_DLDO_PG_F ,DLDO_PG_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 6. " INTE_DLDO_PG_R ,DLDO_PG_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 5. " INTE_DLDO_OC_F ,DLDO_OC_F interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x07 4. " INTE_DLDO_OC_R ,DLDO_OC_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 3. " INTE_ALDO_PG_F ,ALDO_PG_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 2. " INTE_ALDO_PG_R ,ALDO_PG_R interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x07 1. " INTE_ALDO_OC_F ,ALDO_OC_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 0. " INTE_ALDO_OC_R ,ALDO_OC_R interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x08 "INTEN1,Interrupt Enable 1 Register"
|
|
bitfld.byte 0x08 7. " INTE_PKEYLP_F ,PKEYLP_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 6. " INTE_PKEYLP_R ,PKEYLP_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " INTE_VC_LDO_OC_F ,VC_LDO_OC_F interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x08 4. " INTE_VC_LDO_OC_R ,VC_LDO_OC_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " INTE_VCORE_PG_F ,VCORE_PG_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 2. " INTE_VCORE_PG_R ,VCORE_PG_R interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x08 1. " INTE_VC_BUCK_OC_F ,VC_BUCK_OC_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 0. " INTE_VC_BUCK_OC_R ,VC_BUCK_OC_R interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "INTEN2,Interrupt Enable 2 Register"
|
|
bitfld.byte 0x09 7. " INTE_PWRKEY_F ,PWRKEY_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x09 6. " INTE_PWRKEY_R ,PWRKEY_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x09 5. " INTE_AXPKEY_F ,AXPKEY_F interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x09 4. " INTE_AXPKEY_R ,AXPKEY_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x09 3. " INTE_THM2_F ,THM2_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x09 2. " INTE_THM2_R ,THM2_R interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x09 1. " INTE_THM1_F ,THM1_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x09 0. " INTE_THM1_R ,THM1_R interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x0A "INTEN3,Interrupt Enable 3 Register"
|
|
bitfld.byte 0x0A 7. " INTE_THR_L_F ,THR_L_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0A 6. " INTE_THR_L_R ,THR_L_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0A 5. " INTE_THR_H_F ,THR_H_F interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0A 4. " INTE_THR_H_R ,THR_H_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0A 3. " INTE_CHRDET_F ,CHRDET_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0A 2. " INTE_CHRDET_R ,CHRDET_R interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0A 1. " INTE_CHGOV_F ,CHGOV_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0A 0. " INTE_CHGOV_R ,CHGOV_R interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x0B "INTEN4,Interrupt Enable 4 Register"
|
|
bitfld.byte 0x0B 5. " INTE_PSW_PG_F ,PSW_PG_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0B 4. " INTE_PSW_PG_R ,PSW_PG_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0B 3. " INTE_OVER40_F ,OVER40_F interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0B 2. " INTE_OVER40_R ,OVER40_R interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0B 1. " INTE_OVER110_F ,OVER110_F interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0B 0. " INTE_OVER110_R ,OVER110_R interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x0C "INTEN5,Interrupt Enable 5 Register"
|
|
bitfld.byte 0x0C 7. " INTE_WARM_LV ,WARM_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 6. " INTE_HOT_LV ,HOT_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 5. " INTE_CHRWDT_LV ,CHRWDT_LV interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0C 4. " INTE_BVALID_DET_LV ,BVALID_DET_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 3. " INTE_VBAT_UNDET_LV ,VBAT_UNDET_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 2. " INTE_VBATON_HV_LV ,VBATON_HV_LV interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0C 1. " INTE_BAT_L_LV ,BAT_L_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 0. " INTE_BAT_H_LV ,BAT_H_LV interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x0D "INTEN6,Interrupt Enable 6 Register"
|
|
bitfld.byte 0x0D 4. " INTE_AD_LBAT_LV ,AD_LBAT_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0D 3. " INTE_NAG_C_LV ,NAG_C_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0D 2. " INTE_IMP_LV ,IMP_LV interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0D 1. " INTE_COLD_LV ,COLD_LV interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0D 0. " INTE_COOL_LV ,COOL_LV interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x0E "INTMISC,Interrupt Misc Register"
|
|
bitfld.byte 0x0E 1. " RG_INTR_MODE_SEL ,RG interrupt mode selection" "0,1"
|
|
bitfld.byte 0x0E 0. " POLARITY ,Polarity" "0,1"
|
|
rgroup.byte 0x2D++0x0F
|
|
line.byte 0x00 "PONSTS,Power On Source Record Register"
|
|
bitfld.byte 0x00 4. " STS_RBOOT ,Power on for cold reset" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STS_SPAR ,Power on for SPAR event" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " STS_CHRIN ,Power on for charger insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STS_RTCA ,Power on for RTC alarm" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " STS_PWRKEY ,Power on for PWREKY press" "Disabled,Enabled"
|
|
line.byte 0x01 "POFFSTS,Power Off Source Record Register"
|
|
bitfld.byte 0x01 7. " STS_NORMOFF ,Power off for PWRHOLD clear" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " STS_PKEYLP ,Power off for power key(s) long press" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " STS_CRST ,Power off for cold reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " STS_WRST ,Power off for warm reset" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " STS_THRDN ,Power off for thermal shutdown" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " STS_PSOC ,Power off for SOC WDT reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " STS_PGFAIL ,Power off for PWRGOOD failure" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " STS_UVLO ,Power off for UVLO event" "Disabled,Enabled"
|
|
line.byte 0x02 "PDNSTS0,Power Exception Shutdown Status 0 Register"
|
|
bitfld.byte 0x02 6. " STS_PDN_VSF_PG ,PDN_VSF_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " STS_PDN_VIO18_PG ,PDN_VIO18_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " STS_PDN_VCORE_PG ,PDN_VCORE_PG shutdown status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " STS_PDN_VA18_PG ,PDN_VA18_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " STS_PDN_VCAMA_PG ,PDN_VCAMA_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " STS_PDN_VA_PG ,PDN_VA_PG shutdown status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 0. " STS_PDN_VBT_PG ,PDN_VBT_PG shutdown status" "Disabled,Enabled"
|
|
line.byte 0x03 "PDNSTS1,Power Exception Shutdown Status 1 Register"
|
|
bitfld.byte 0x03 7. " STS_PDN_SWBAT_PG ,PDN_SWBAT_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " STS_PDN_VIBR_PG ,PDN_VIBR_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " STS_PDN_VUSB_PG ,PDN_VUSB_PG shutdown status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " STS_PDN_VMC_PG ,PDN_VMC_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " STS_PDN_SWMP_PG ,PDN_SWMP_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " STS_PDN_VIO28_PG ,PDN_VIO28_PG shutdown status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " STS_PDN_SWDP_PG ,PDN_SWDP_PG shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " STS_PDN_SWXM_PG ,PDN_SWXM_PG shutdown status" "Disabled,Enabled"
|
|
line.byte 0x04 "PDNSTS2,Power Exception Shutdown Status 2 Register"
|
|
bitfld.byte 0x04 5. " STS_PDN_VIO18_OC ,PDN_VIO18_OC shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x04 4. " STS_PDN_VCORE_LDO_OC ,PDN_VCORE_LDO_OC shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x04 3. " STS_PDN_VCORE_BUCK_OC ,PDN_VCORE_BUCK_OC shutdown status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 2. " STS_PDN_VIO28_OC ,PDN_VIO28_OC shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x04 1. " STS_PDN_VA_OC ,PDN_VA_OC shutdown status" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " STS_PDN_VMC_OC ,PDN_VMC_OC shutdown status" "Disabled,Enabled"
|
|
line.byte 0x05 "PSSTS0,Power Supply Status 0 Register"
|
|
bitfld.byte 0x05 6. " STS_VA18_ENA ,VA18 supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x05 5. " STS_VA_ENA ,VA supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x05 4. " STS_VBT_ENA ,VBT supply status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x05 3. " STS_VCAMA_ENA ,VCAMA supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x05 2. " STS_VUSB_ENA ,VUSB supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x05 1. " STS_OSC_EN ,OSC supply status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x05 0. " STS_IVGEN_EN ,IVGEN supply status" "Disabled,Enabled"
|
|
line.byte 0x06 "PSSTS1,Power Supply Status 1 Register"
|
|
bitfld.byte 0x06 6. " STS_VIBR_ENA ,VIBR supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x06 5. " STS_VMC_ENA ,VMC supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x06 4. " STS_VIO28_ENA ,VIO28 supply status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x06 3. " STS_VSF_ENA ,VSF supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x06 2. " STS_VIO18_ENA ,VIO18 supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x06 1. " STS_VC_LDO_ENA ,VC_LDO supply status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x06 0. " STS_VC_BUCK_ENA ,VC_BUCK supply status" "Disabled,Enabled"
|
|
line.byte 0x07 "PSSTS2,Power Supply Status 2 Register"
|
|
bitfld.byte 0x07 6. " PKEYLP_VAL ,PKEYLP_VAL" "0,1"
|
|
bitfld.byte 0x07 5. " AXPKEY_VAL ,AXPKEY_VAL" "0,1"
|
|
bitfld.byte 0x07 4. " PWRKEY_VAL ,PWRKEY_VAL" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x07 3. " STS_SWMP_ENA ,SWMP supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x07 2. " STS_SWDP_ENA ,SWDP supply status" "Disabled,Enabled"
|
|
bitfld.byte 0x07 1. " STS_SWXM_ENA ,SWXM supply status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x07 0. " STS_SWBAT_ENA ,SWBAT supply status" "Disabled,Enabled"
|
|
line.byte 0x08 "PSOCSTS0,Power Supply Overcurrent Status 0 Register"
|
|
bitfld.byte 0x08 6. " STS_VSF_OC ,VSF overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x08 5. " STS_VIO18_OC ,VIO18 overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x08 4. " STS_VC_LDO_OC ,VC_LDO overcurrent status" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.byte 0x08 3. " STS_VC_BUCK_OC ,VC_BUCK overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x08 2. " STS_VA18_OC ,VA18 overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x08 1. " STS_VA_OC ,VA overcurrent status" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.byte 0x08 0. " STS_VBT_OC ,VBT overcurrent status" "No overcurrent,Overcurrent"
|
|
line.byte 0x09 "PSOCSTS1,Power Supply Overcurrent Status 1 Register"
|
|
bitfld.byte 0x09 4. " STS_VIBR_OC ,VIBR overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x09 3. " STS_VCAMA_OC ,VCAMA overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x09 2. " STS_VUSB_OC ,VUSB overcurrent status" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.byte 0x09 1. " STS_VMC_OC ,VMC overcurrent status" "No overcurrent,Overcurrent"
|
|
bitfld.byte 0x09 0. " STS_VIO28_OC ,VIO28 overcurrent status" "No overcurrent,Overcurrent"
|
|
line.byte 0x0A "PSPGSTS0,Power Supply PWRGOOD Status 0 Register"
|
|
bitfld.byte 0x0A 6. " STS_VSF_PG ,VSF_PG status" "0,1"
|
|
bitfld.byte 0x0A 5. " STS_VIO18_PG ,VIO18_PG status" "0,1"
|
|
bitfld.byte 0x0A 4. " STS_VCORE_PG ,VCORE_PG status" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x0A 3. " STS_VA18_PG ,VA18_PG status" "0,1"
|
|
bitfld.byte 0x0A 2. " STS_VCAMA_PG ,VCAMA_PG status" "0,1"
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|
bitfld.byte 0x0A 1. " STS_VA_PG ,VA_PG status" "0,1"
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|
textline " "
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|
bitfld.byte 0x0A 0. " STS_VBT_PG ,VBT_PG status" "0,1"
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|
line.byte 0x0B "PSPGSTS1,Power Supply PWRGOOD Status 1 Register"
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|
bitfld.byte 0x0B 7. " STS_SWBAT_PG ,SWBAT_PG status" "0,1"
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|
bitfld.byte 0x0B 6. " STS_VIBR_PG ,VIBR_PG status" "0,1"
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|
bitfld.byte 0x0B 5. " STS_VUSB_PG ,VUSB_PG status" "0,1"
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textline " "
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bitfld.byte 0x0B 4. " STS_VMC_PG ,VMC_PG status" "0,1"
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bitfld.byte 0x0B 3. " STS_SWMP_PG ,SWMP_PG status" "0,1"
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bitfld.byte 0x0B 2. " STS_VIO28_PG ,VIO28_PG status" "0,1"
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textline " "
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bitfld.byte 0x0B 1. " STS_SWDP_PG ,SWDP_PG status" "0,1"
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bitfld.byte 0x0B 0. " STS_SWXM_PG ,SWXM_PG status" "0,1"
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line.byte 0x0C "PSOMSTS0,Power Supply Operational Mode Status 0 Register"
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bitfld.byte 0x0C 6. " STS_VA18_OPMOD ,VA18_OPMOD status" "0,1"
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bitfld.byte 0x0C 4.--5. " STS_VCAMA_OPMOD ,VCAMA_OPMOD status" "0,1,2,3"
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|
bitfld.byte 0x0C 2.--3. " STS_VA_OPMOD ,VA_OPMOD status" "0,1,2,3"
|
|
textline " "
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bitfld.byte 0x0C 0.--1. " STS_VBT_OPMOD ,VBT_OPMOD status" "0,1,2,3"
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line.byte 0x0D "PSOMSTS1,Power Supply Operational Mode Status 1 Register"
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bitfld.byte 0x0D 6.--7. " STS_VSF_OPMOD ,VSF_OPMOD status" "0,1,2,3"
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bitfld.byte 0x0D 4.--5. " STS_VIO18_OPMOD ,VIO18_OPMOD status" "0,1,2,3"
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bitfld.byte 0x0D 2.--3. " STS_VC_LDO_OPMOD ,VC_LDO_OPMOD status" "0,1,2,3"
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|
textline " "
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bitfld.byte 0x0D 0.--1. " STS_VDIG18_OPMOD ,VDIG18_OPMOD status" "0,1,2,3"
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line.byte 0x0E "PSOMSTS2,Power Supply Operational Mode Status 2 Register"
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|
bitfld.byte 0x0E 6.--7. " STS_VIBR_OPMOD ,VIBR_OPMOD status" "0,1,2,3"
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bitfld.byte 0x0E 4.--5. " STS_VUSB_OPMOD ,VUSB_OPMOD status" "0,1,2,3"
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bitfld.byte 0x0E 2.--3. " STS_VMC_OPMOD ,VMC_OPMOD status" "0,1,2,3"
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|
textline " "
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bitfld.byte 0x0E 0.--1. " STS_VIO28_OPMOD ,VIO28_OPMOD status" "0,1,2,3"
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line.byte 0x0F "THMSTS,Thermal Status Register"
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|
bitfld.byte 0x0F 5. " STS_THM_DEB_STS ,THM_DEB status" "0,1"
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bitfld.byte 0x0F 4. " STS_THM_RAW_STS ,THM_RAW status" "0,1"
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bitfld.byte 0x0F 3. " STS_THM_OVER125 ,THM_OVER125 status" "0,1"
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textline " "
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bitfld.byte 0x0F 2. " STS_THM_OVER110 ,THM_OVER110 status" "0,1"
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bitfld.byte 0x0F 1. " STS_THM_OVER55 ,THM_OVER55 status" "0,1"
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bitfld.byte 0x0F 0. " STS_THM_OVER40 ,THM_OVER40 status" "0,1"
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group.byte 0x3D++0x00
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|
line.byte 0x00 "WKFG_STS,Wake Up Fuel Gauge Status Register"
|
|
eventfld.byte 0x00 0. " STS_WKUP_FG_DONE ,STS_WKUP_FG done status" "Not done,Done"
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group.byte 0x40++0x00
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|
line.byte 0x00 "PSICTL,PSI Control Register"
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|
bitfld.byte 0x00 2.--3. " RG_HNDOVR_LEN ,VR handover time interval selection" "2T*32K,3T*32K,4T*32K,5T*32K"
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|
bitfld.byte 0x00 0. " RG_PSIOVR ,PSI overwrite enable" "Disabled,Enabled"
|
|
rgroup.byte 0x41++0x00
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line.byte 0x00 "PSISTS,PSI Status Register"
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|
bitfld.byte 0x00 6.--7. " RGS_PSI_STS ,PSI bus status" "0,1,2,3"
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group.byte 0x48++0x00
|
|
line.byte 0x00 "PPCCFG0,PPC Configuration 0 Register"
|
|
bitfld.byte 0x00 2.--3. " RG_WDTRST_ACT ,Reset mode" "PMIC reg,Warm,Cold,?..."
|
|
group.byte 0x4A++0x01
|
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line.byte 0x00 "PPCCFG2,PPC Configuration 2 Register"
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|
bitfld.byte 0x00 2. " RG_XRST_ACT ,Response for EXTRSTB assertion during active modes" "Warm reset,Cold reset"
|
|
line.byte 0x01 "PPCCTL0,PPC Control 0 Register"
|
|
bitfld.byte 0x01 5. " RG_CRST ,Cold reset" "No reset,Reset"
|
|
bitfld.byte 0x01 4. " RG_WRST ,Warm reset" "No reset,Reset"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "SHDNCFG1,Shutdown Configuration 1 Register"
|
|
bitfld.byte 0x00 2.--3. " RG_PKEY_LTIME ,PWRKEY long press shutdown timing selection" "5 sec,7 sec,8 sec,11 sec"
|
|
group.byte 0x87++0x04
|
|
line.byte 0x00 "CHR_CON0,Charger Control Register 0"
|
|
rbitfld.byte 0x00 7. " RGS_VCDT_HV_DET ,Charger-in high voltage detection" "Not detected,Detected"
|
|
rbitfld.byte 0x00 6. " RGS_VCDT_LV_DET ,Charger-in low voltage detection" "Not detected,Detected"
|
|
rbitfld.byte 0x00 5. " RGS_CHRDET ,Charger-in detection" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RG_NORM_CHR_EN ,Charger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " RG_CSDAC_EN ,CS DAC enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 1. " RGS_CHR_LDO_DE ,Charger LDO detection" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RG_VCDT_HV_EN ,ChargerIn HV detection function enable" "Disabled,Enabled"
|
|
line.byte 0x01 "CHR_CON1,Charger Control Register 1"
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bitfld.byte 0x01 4.--7. " RG_VCDT_HV_VTH ,ChargerIn HV detection threshold" "4.20V,4.25V,4.30V,4.35V,4.40V,4.45V,4.50V,4.55V,4.60V,6.0V,6.5V,7.0V,7.5V,8.5V,9.5V,10.5V"
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|
bitfld.byte 0x01 0.--3. " RG_VCDT_LV_VTH ,ChargerIn LV detection threshold" "4.20V,4.25V,4.30V,4.35V,4.40V,4.45V,4.50V,4.55V,4.60V,6.0V,6.5V,7.0V,7.5V,8.5V,9.5V,10.5V"
|
|
line.byte 0x02 "CHR_CON2,Charger Control Register 2"
|
|
rbitfld.byte 0x02 7. " RGS_VBAT_CC_DET ,VBAT high voltage detection for CC" "Not detected,Detected"
|
|
rbitfld.byte 0x02 6. " RGS_VBAT_CV_DET ,VBAT high voltage detection for CV" "Not detected,Detected"
|
|
rbitfld.byte 0x02 5. " RGS_CS_DET ,Current sense high voltage detection" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " RG_CS_EN ,Current sense voltage detection comparator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " RG_VBAT_CC_EN ,Battery CC detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " RG_VBAT_CV_EN ,Battery CV detection enable" "Disabled,Enabled"
|
|
line.byte 0x03 "CHR_CON3,Charger Control Register 3"
|
|
bitfld.byte 0x03 6.--7. " RG_VBAT_CC_VTH ,Battery CC detection threshold" "3.3V,3.35V,3.4V,3.45V"
|
|
bitfld.byte 0x03 0.--5. " RG_VBAT_NORM_CV_VTH ,Battery CV detection threshold trimming option" "3.5V,3.6V,3.7V,3.8V,3.85V,3.9V,4V,4.05V,4.1V,4.125V,4.1375V,4.15V,4.1625V,4.175V,4.1875V,4.2V,4.2125V,4.225V,4.2375V,4.25V,4.2625V,4.275V,4.2875V,4.3V,4.3125V,4.325V,4.3375V,4.35V,4.3625V,4.375V,4.3875V,4.4V,4.4125V,4.425V,4.4375V,4.45V,4.4625V,4.475V,4.4875V,4.5V,4.6V,,,,,,,,,,,,,,,,,,,,,,,2.2V"
|
|
line.byte 0x04 "CHR_CON4,Charger Control Register 4"
|
|
bitfld.byte 0x04 0.--3. " RG_NORM_CS_VTH ,Current sense voltage detection threshold" "2000mA,1600mA,1500mA,1350mA,1200mA,1100mA,1000mA,900mA,800mA,700mA,650mA,550mA,450mA,300mA,200mA,70mA"
|
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group.byte 0x8D++0x01
|
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line.byte 0x00 "CHR_CON6,Charger Control Register 6"
|
|
rbitfld.byte 0x00 6. " RGS_VBAT_OV_DET ,VBAT_OV high voltage detection" "Not detected,Detected"
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bitfld.byte 0x00 5. " RG_VBAT_OV_DEG ,VBAT OV voltage detection deglitch enable" "Disabled,Enabled"
|
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bitfld.byte 0x00 1.--4. " RG_VBAT_OV_VTH ,Battery over-voltage detection threshold" "3.900V,4.200V,4.300V,4.400V,4.450V,4.500V,4.600V,4.700V,3.800V,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RG_VBAT_OV_EN ,Battery over-voltage for driving protection enable" "Disabled,Enabled"
|
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line.byte 0x01 "CHR_CON7,Charger Control Register 7"
|
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bitfld.byte 0x01 2. " BATON_TDET_EN ,Enable BATON temperature detection" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " RG_BATON_HT_EN_RSV0 ,Battery-On HW high temperature detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " RG_BATON_EN ,BATON battery detection comparator enable" "Disabled,Enabled"
|
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group.byte 0x92++0x01
|
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line.byte 0x00 "CHR_CON9,Charger Control Register 9"
|
|
bitfld.byte 0x00 0. " RG_FRC_CSVTH_USBDL ,Force CS DAC detection threshold to maximum in USB download mode" "CS_VTH=450mA,CS_VTH=1600mA"
|
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line.byte 0x01 "CHR_CON10,Charger Control Register 10"
|
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rbitfld.byte 0x01 6. " RGS_OTG_BVALID_DET ,Session for B-peripheral validation" "Vbus<0.8V,Vbus > 4V"
|
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bitfld.byte 0x01 5. " RG_OTG_BVALID_EN ,OTG BValid detection enable" "Disabled,Enabled"
|
|
group.byte 0x96++0x01
|
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line.byte 0x00 "CHR_CON13,Charger Control Register 13"
|
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bitfld.byte 0x00 4. " RG_CHRWDT_EN ,Enable setting for charger watch-dog timer" "Disabled,Enabled"
|
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bitfld.byte 0x00 0.--3. " RG_CHRWDT_TD ,Time constant setting for charger watch-dog timer" "4 sec,8 sec,16 sec,32 sec,128 sec,256 sec,512 sec,1024 sec,3000 sec,3000 sec,3000 sec,3000 sec,3000 sec,3000 sec,3000 sec,3000 sec"
|
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line.byte 0x01 "CHR_CON13_H,Charger Control Register 13_H"
|
|
eventfld.byte 0x01 0. " RG_CHRWDT_WR ,Reset charger watch-dog timer and update CHRWDT_TD" "No reset,Reset"
|
|
group.byte 0x99++0x08
|
|
line.byte 0x00 "CHR_CON15,Charger Control Register 15"
|
|
rbitfld.byte 0x00 2. " RGS_CHRWDT_OUT ,Time-out flag for charger watch-dog timer" "Not occurred,Occurred"
|
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eventfld.byte 0x00 1. " RG_CHRWDT_FLAG_WR ,Clear time-out flag for charger watch-dog timer" "Not cleared,Cleared"
|
|
line.byte 0x01 "CHR_CON16,Charger Control Register 16"
|
|
bitfld.byte 0x01 3. " RG_USBDL_SET ,USBDL_MODE software set control" "No effect,Set"
|
|
bitfld.byte 0x01 2. " RG_USBDL_RST ,USBDL_MODE software reset control" "No effect,Reset"
|
|
line.byte 0x02 "CHR_CON16_H,Charger Control Register 16_H"
|
|
bitfld.byte 0x02 4. " RG_ADCIN_CHR_EN ,AUXADC input source enable for CHR" "Disabled,Enabled"
|
|
bitfld.byte 0x02 3. " RG_ADCIN_VSEN_EN ,AUXADC input source enable for VSEN" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " RG_ADCIN_VBAT_EN ,AUXADC input source enable for VBAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " RG_ADCIN_VSEN_EXT_BATON_EN ,AUXADC input source enable for external source to be switched to AUXADC's Ch3" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " RG_ADCIN_VSEN_MUX_EN ,AUXADC input source enable for VSEN to be switched to VBAT's" "Disabled,Enabled"
|
|
line.byte 0x03 "CHR_CON17,Charger Control Register 17"
|
|
bitfld.byte 0x03 0.--4. " RG_UVLO_VTHL ,UVLO low threshold selection" "2.5V,2.55V,2.6V,2.65V,2.7V,2.75V,2.8V,2.85V,2.9V,?..."
|
|
line.byte 0x04 "CHR_CON18,Charger Control Register 18"
|
|
bitfld.byte 0x04 0.--4. " RG_LBAT_INT_VTH ,LBAT_INT threshold voltage" "2.5V,2.55V,2.6V,2.65V,2.7V,2.75V,2.8V,2.85V,2.9V,2.95V,3.0V,3.05V,3.1V,3.15V,3.2V,3.25V,,,,,,,,,3.3V,3.35V,3.4V,?..."
|
|
line.byte 0x05 "CHR_CON19,Charger Control Register 19"
|
|
bitfld.byte 0x05 0.--2. " RG_BGR_RSEL ,BGR resistor selection" "780K,820K,860K,900K,620K,660K,700K,740K"
|
|
textline " "
|
|
line.byte 0x06 "CHR_CON20,Charger Control Register 20"
|
|
rbitfld.byte 0x06 7. " RGS_BC11_CMP_OUT ,Comparison result of BC11 charger detection" "DP or DM < BC11_VREF_VTH,DP or DM > BC11_VREF_VTH"
|
|
bitfld.byte 0x06 2.--3. " RG_BC11_VSRC_EN ,BC11 voltage source" "Disabled,DM,DP,?..."
|
|
bitfld.byte 0x06 1. " RG_BC11_RST ,Reset BC11 detection mechanism in PCHR_DIG" "No effect,Reset"
|
|
bitfld.byte 0x06 0. " RG_BC11_BB_CTRL ,Force BC11 charger detection controlled by baseband" "PCHR_DIG,Baseband"
|
|
textline " "
|
|
line.byte 0x07 "CHR_CON21,Charger Control Register 21"
|
|
bitfld.byte 0x07 6.--7. " RG_BC11_IPU_EN ,BC11 7~15uA pull up current enable" "Disabled,DM,DP,?..."
|
|
bitfld.byte 0x07 4.--5. " RG_BC11_IPD_EN ,BC11 50~150uA pull down current enable" "Disabled,DM,DP,?..."
|
|
bitfld.byte 0x07 2.--3. " RG_BC11_CMP_EN ,BC11 comparator connection enable" "Disabled,DM,DP,?..."
|
|
textline " "
|
|
bitfld.byte 0x07 0.--1. " RG_BC11_VREF_VTH ,VREF threshold voltage for comparator" "0.325V,1.2V,2.6V,2.6V"
|
|
line.byte 0x08 "CHR_CON21_H,Charger Control Register 21_H"
|
|
bitfld.byte 0x08 0. " RG_BC11_BIAS_EN ,Enable BC11 detection bias circuit" "Disabled,Enabled"
|
|
group.byte 0xA3++0x02
|
|
line.byte 0x00 "CHR_CON23,Charger Control Register 23"
|
|
bitfld.byte 0x00 4.--6. " RG_CSDAC_STP ,Current DAC output step timer" "1,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. " RG_CSDAC_DLY ,Current DAC output detection delay control" "16us,32us,64us,128us,256us,512us,1024us,2048us"
|
|
line.byte 0x01 "CHR_CON24,Charger Control Register 24"
|
|
bitfld.byte 0x01 7. " RG_CHRIND_DIMMING ,Enable pre-charge indicator dimming" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " RG_CHRIND_ON ,Pre-charge enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--5. " RG_LOW_ICH_DB ,Plug out HW detection debounce time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "CHR_CON25,Charger Control Register 25"
|
|
bitfld.byte 0x02 7. " RG_ULC_DET_EN ,Enable charger plug out auto detection" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " RG_HWCV_EN ,Enable hardware CV current tracking" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " RG_TRACKING_EN ,Enable tracking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 2. " RG_CSDAC_MODE ,Enable charging AUTO mode" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " RG_VCDT_MODE ,Charger detection mode selection" "Off state,Both"
|
|
bitfld.byte 0x02 0. " RG_CV_MODE ,Battery CV detection mode selection" "Off state,Both"
|
|
group.byte 0xAA++0x01
|
|
line.byte 0x00 "CHR_CON30,Charger Control Register 30"
|
|
line.byte 0x01 "CHR_CON30_H,Charger Control Register 30_H"
|
|
bitfld.byte 0x01 0.--1. " RG_DAC_USBDL_MAX1 ,USBDL maximum current setting" "0,1,2,3"
|
|
group.byte 0xAD++0x01
|
|
line.byte 0x00 "CHR_CON42,Charger Control Register 42"
|
|
eventfld.byte 0x00 1. " RG_ENVTEM_EN ,Block CHR_DET signal to start_up" ",Enabled"
|
|
bitfld.byte 0x00 0. " RG_ENVTEM_D ,Block CHR_DET signal to start_up" "Not blocked,Blocked"
|
|
line.byte 0x01 "BATON_CON0,BATON Control Register 0"
|
|
bitfld.byte 0x01 0. " RG_BATON_HT_EN ,Battery-On HW high temperature detection enable" "Disabled,Enabled"
|
|
group.byte 0xB0++0x05
|
|
line.byte 0x00 "CHR_CON44,Charger Control Register 44"
|
|
rbitfld.byte 0x00 1. " RGS_BATON_UNDET ,Battery-On undetected" "Detected,Not detected"
|
|
bitfld.byte 0x00 0. " RG_QI_BATON_LT_EN ,RG_QI_BATON_LT_EN" "Disabled,Enabled"
|
|
line.byte 0x01 "CHR_CON45,Charger Control Register 45"
|
|
bitfld.byte 0x01 0.--3. " RG_JW_CS_VTH ,Current sense voltage detection threshold" "2000mA,1600mA,1500mA,1350mA,1200mA,1100mA,1000mA,900mA,800mA,700mA,650mA,550mA,450mA,300mA,200mA,70mA"
|
|
line.byte 0x02 "CHR_CON45_H,Charger Control Register 45_H"
|
|
bitfld.byte 0x02 0.--5. " RG_JW_CV_VTH ,Battery CV dection threshold trimming option" "3.5V,3.6V,3.7V,3.8V,3.85V,3.9V,4V,4.05V,4.1V,4.125V,4.1375V,4.15V,4.1625V,4.175V,4.1875V,4.2V,4.2125V,4.225V,4.2375V,4.25V,4.2625V,4.275V,4.2875V,4.3V,4.3125V,4.325V,4.3375V,4.35V,4.3625V,4.375V,4.3875V,4.4V,4.4125V,4.425V,4.4375V,4.45V,4.4625V,4.475V,4.4875V,4.5V,4.6V,,,,,,,,,,,,,,,,,,,,,,,2.2V"
|
|
line.byte 0x03 "CHR_CON46,Charger Control Register 46"
|
|
bitfld.byte 0x03 0.--3. " RG_JC_CS_VTH ,Current sense voltage detection threshold" "2000mA,1600mA,1500mA,1350mA,1200mA,1100mA,1000mA,900mA,800mA,700mA,650mA,550mA,450mA,300mA,200mA,70mA"
|
|
line.byte 0x04 "CHR_CON46_H,Charger Control Register 46_H"
|
|
bitfld.byte 0x04 0.--5. " RG_JC_CV_VTH ,Battery CV dection threshold trimming option" "3.5V,3.6V,3.7V,3.8V,3.85V,3.9V,4V,4.05V,4.1V,4.125V,4.1375V,4.15V,4.1625V,4.175V,4.1875V,4.2V,4.2125V,4.225V,4.2375V,4.25V,4.2625V,4.275V,4.2875V,4.3V,4.3125V,4.325V,4.3375V,4.35V,4.3625V,4.375V,4.3875V,4.4V,4.4125V,4.425V,4.4375V,4.45V,4.4625V,4.475V,4.4875V,4.5V,4.6V,,,,,,,,,,,,,,,,,,,,,,,2.2V"
|
|
line.byte 0x05 "CHR_CON47,Charger Control Register 47"
|
|
bitfld.byte 0x05 1. " RG_JEITA_EN ,Enable JEITA" "Disabled,Enabled"
|
|
group.byte 0xDA++0x01
|
|
line.byte 0x00 "VA18CTL0,VA18 Control Register 0"
|
|
bitfld.byte 0x00 2. " RG_OVR_VA18_PMOD ,Low power mode enabled" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RG_VA18_EN ,RG_VA18_EN" "Disabled,Enabled"
|
|
line.byte 0x01 "VA18CTL1,VA18 Control Register 1"
|
|
bitfld.byte 0x01 2. " RG_OFF_VA18_PMOD ,VA18 operational mode for system OFF mode" "Normal,Low power"
|
|
group.byte 0xE2++0x04
|
|
line.byte 0x00 "VA18PSI0,VA18 LDO PSI Register 0"
|
|
bitfld.byte 0x00 5. " RG_LP_VA18_PMOD ,RG_LP_VA18_PMOD" "0,1"
|
|
bitfld.byte 0x00 1. " RG_HP_VA18_PMOD ,RG_HP_VA18_PMOD" "0,1"
|
|
line.byte 0x01 "VA18PSI1,VA18 LDO PSI Register 1"
|
|
bitfld.byte 0x01 5. " RG_S1_VA18_PMOD ,RG_S1_VA18_PMOD" "0,1"
|
|
bitfld.byte 0x01 4. " RG_S1_VA18_ON ,RG_S1_VA18_ON" "0,1"
|
|
bitfld.byte 0x01 1. " RG_S0_VA18_PMOD ,RG_S0_VA18_PMOD" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " RG_S0_VA18_ON ,RG_S0_VA18_ON" "0,1"
|
|
line.byte 0x02 "VBTCTL0,VBT Control Register 0"
|
|
bitfld.byte 0x02 2.--3. " RG_OVR_VBT_PMOD ,VBT LDO operation mode" "Normal,Lite,LP,ULP"
|
|
bitfld.byte 0x02 1. " RG_VBT_OCFB_EN ,RG_VBT_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " RG_VBT_EN ,VBT LDO enable" "Disabled,Enabled"
|
|
line.byte 0x03 "VACTL0,VA Control Register 0"
|
|
bitfld.byte 0x03 2.--3. " RG_OVR_VA_PMOD ,RG_OVR_VA_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x03 1. " RG_VA_OCFB_EN ,RG_VA_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " RG_VA_EN ,RG_VA_EN" "Disabled,Enabled"
|
|
line.byte 0x04 "VCLDOCTL0,LDO Control Register 0"
|
|
bitfld.byte 0x04 2.--3. " RG_OVR_VC_LDO_PMOD ,RG_OVR_VC_LDO_PMOD" "Normal,Lite,LP,ULP"
|
|
bitfld.byte 0x04 1. " RG_VC_LDO_OCFB_EN ,RG_VC_LDO_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " RG_VC_LDO_EN ,RG_VC_LDO_EN" "Disabled,Enabled"
|
|
group.byte 0xE8++0x05
|
|
line.byte 0x00 "PSWCTL1,PSW Control Register 1"
|
|
bitfld.byte 0x00 1. " RG_SWDP_ENA ,Optional SWDP enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RG_SWXM_ENA ,Optional SWXM enable" "Disabled,Enabled"
|
|
line.byte 0x01 "VIO18CTL0,VIO18 Control Register 0"
|
|
bitfld.byte 0x01 2.--3. " RG_OVR_VIO18_PMOD ,RG_OVR_VIO18_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x01 1. " RG_VIO18_OCFB_EN ,RG_VIO18_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " RG_VIO18_EN ,RG_VIO18_EN" "Disabled,Enabled"
|
|
line.byte 0x02 "VSFCTL0,VSF Control Register 0"
|
|
bitfld.byte 0x02 2.--3. " RG_OVR_VSF_PMOD ,RG_OVR_VSF_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x02 1. " RG_VSF_OCFB_EN ,RG_VSF_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " RG_VSF_EN ,RG_VSF_EN" "Disabled,Enabled"
|
|
line.byte 0x03 "VIO28CTL0,VIO28 Control Register 0"
|
|
bitfld.byte 0x03 2.--3. " RG_OVR_VIO28_PMOD ,RG_OVR_VIO28_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x03 1. " RG_VIO28_OCFB_EN ,RG_VIO28_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " RG_VIO28_EN ,RG_VIO28_EN" "Disabled,Enabled"
|
|
line.byte 0x04 "VMCCTL0,VMC Control Register 0"
|
|
bitfld.byte 0x04 2.--3. " RG_OVR_VMC_PMOD ,RG_OVR_VMC_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x04 1. " RG_VMC_OCFB_EN ,RG_VMC_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " RG_VMC_EN ,RG_VMC_EN" "Disabled,Enabled"
|
|
line.byte 0x05 "VUSBCTL0,VUSB Control Register 0"
|
|
bitfld.byte 0x05 2.--3. " RG_OVR_VUSB_PMOD ,RG_OVR_VUSB_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x05 1. " RG_VUSB_OCFB_EN ,RG_VUSB_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x05 0. " RG_VUSB_EN ,RG_VUSB_EN" "Disabled,Enabled"
|
|
group.byte 0xEF++0x00
|
|
line.byte 0x00 "VUSBLDO0,VUSBLDO0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VUSB_CAL ,RG_VUSB_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0xF3++0x00
|
|
line.byte 0x00 "VUSBLDOBF0,VUSBLDOBF0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VUSB_BUF_CAL ,RG_VUSB_BUF_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0xF5++0x02
|
|
line.byte 0x00 "VUSBPSI0,VUSB LDO PSI Register 0"
|
|
bitfld.byte 0x00 5.--6. " RG_LP_VUSB_PMOD ,RG_LP_VUSB_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x00 1.--2. " RG_HP_VUSB_PMOD ,RG_HP_VUSB_PMOD" "0,1,2,3"
|
|
line.byte 0x01 "VUSBPSI1,VUSB LDO PSI Register 1"
|
|
bitfld.byte 0x01 5.--6. " RG_S1_VUSB_PMOD ,RG_S1_VUSB_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x01 4. " RGS_S1_VUSB_ON ,RGS_S1_VUSB_ON" "0,1"
|
|
bitfld.byte 0x01 1.--2. " RG_S0_VUSB_PMOD ,RG_S0_VUSB_PMOD" "0,1,2,3"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " RGS_S0_VUSB_ON ,RGS_S0_VUSB_ON" "0,1"
|
|
line.byte 0x02 "VDIG18LDO0,VDIG1 8LDO0 Register"
|
|
bitfld.byte 0x02 0.--3. " RG_OVR_VDIG18_CAL ,VDIG18 calibration" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0xFB++0x00
|
|
line.byte 0x00 "VDIG18LDOBF0,VDIG1 8LDOB F0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_OVR_VDIG18_BUF_CAL ,VDIG18 buffer calibration" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0xFD++0x01
|
|
line.byte 0x00 "VCLDO0,VCORE LDO Register 0"
|
|
bitfld.byte 0x00 0.--4. " RG_OVR_VC_LDO_CAL ,VC LDO calibration" "0 mV,-5 mV,-10 mV,-15 mV,-20 mV,-25 mV,-30 mV,-35 mV,-40 mV,-45 mV,-50 mV,-55 mV,-60 mV,-65 mV,-70 mV,-75 mV,+80 mV,+75 mV,+70 mV,+65 mV,+60 mV,+55 mV,+50 mV,+45 mV,+40 mV,+35 mV,+30 mV,+25 mV,+20 mV,+15 mV,+10 mV,+5 mV"
|
|
line.byte 0x01 "VCLDO1,VCORE LDO Register 1"
|
|
bitfld.byte 0x01 0.--3. " RG_OVR_VC_LDO_VOSEL ,VC LDO output voltage" "0.7V,0.75V,0.8 V,0.85 V,0.9 V,0.95 V,1 V,1.05 V,1.1V,1.15 V,1.2 V,1.25 V,1.3 V,1.3 V,1.3 V,1.3 V"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "VCLDOBF0,VCORE LDO Buffer Register 0"
|
|
bitfld.byte 0x00 0.--4. " RG_OVR_VC_LDO_BUF_CAL ,VC LDO buffer calibration" "0 mV,-5 mV,-10 mV,-15 mV,-20 mV,-25 mV,-30 mV,-35 mV,-40 mV,-45 mV,-50 mV,-55 mV,-60 mV,-65 mV,-70 mV,-75 mV,+80 mV,+75 mV,+70 mV,+65 mV,+60 mV,+55 mV,+50 mV,+45 mV,+40 mV,+35 mV,+30 mV,+25 mV,+20 mV,+15 mV,+10 mV,+5 mV"
|
|
group.byte 0x103++0x05
|
|
line.byte 0x00 "VCLDOPSI0,VCORE LDO PSI Register 0"
|
|
bitfld.byte 0x00 4.--7. " RG_HP_VC_LDO_VOSEL ,RG_HP_VC_LDO_VOSEL" "0.7V,0.75V,0.8 V,0.85 V,0.9 V,0.95 V,1 V,1.05 V,1.1V,1.15 V,1.2 V,1.25 V,1.3 V,1.3 V,1.3 V,1.3 V"
|
|
bitfld.byte 0x00 1.--2. " RG_HP_VC_LDO_PMOD ,RG_HP_VC_LDO_PMOD" "Normal,Lite,LP,ULP"
|
|
bitfld.byte 0x00 0. " RG_HP_VC_LDO_ON ,RG_HP_VC_LDO_ON" "0,1"
|
|
line.byte 0x01 "VCLDOPSI1,VCORE LDO PSI Register 1"
|
|
bitfld.byte 0x01 0.--4. " RG_HP_VC_LDO_CAL ,RG_HP_VC_LDO_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x02 "VCLDOPSI2,VCORE LDO PSI Register 2"
|
|
bitfld.byte 0x02 4.--7. " RG_LP_VC_LDO_VOSEL ,RG_LP_VC_LDO_V" "0.7V,0.75V,0.8 V,0.85 V,0.9 V,0.95 V,1 V,1.05 V,1.1V,1.15 V,1.2 V,1.25 V,1.3 V,1.3 V,1.3 V,1.3 V"
|
|
line.byte 0x03 "VCLDOPSI3,VCORE LDO PSI Register 3"
|
|
bitfld.byte 0x03 0.--4. " RG_LP_VC_LDO_CAL ,RG_HP_VC_LDO_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x04 "VCLDOPSI4,VCORE LDO PSI Register 4"
|
|
bitfld.byte 0x04 1.--2. " RG_S0_VC_LDO_PMOD ,RG_S0_VC_LDO_PMOD" "0,1,2,3"
|
|
line.byte 0x05 "VCLDOPSI5,VCORE LDO PSI Register 5"
|
|
bitfld.byte 0x05 4.--7. " RG_S1_VC_LDO_VOSEL ,RG_HP_VC_LDO_VOSEL" "0.7V,0.75V,0.8 V,0.85 V,0.9 V,0.95 V,1 V,1.05 V,1.1V,1.15 V,1.2 V,1.25 V,1.3 V,1.3 V,1.3 V,1.3 V"
|
|
bitfld.byte 0x05 1.--2. " RG_S1_VC_LDO_PMOD ,RG_HP_VC_LDO_PMOD" "0,1,2,3"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "VIO18LDO0,VIO18LDO0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VIO18_CAL ,RG_HP_VC_LDO_PMOD" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "VIO18LDOBF0,VIO18LDOBF0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VIO18_BUF_CAL ,RG_VIO18_BUF_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0x110++0x01
|
|
line.byte 0x00 "VIO18PSI0,LDO PSI Register 0"
|
|
bitfld.byte 0x00 5.--6. " RG_LP_VIO18_PMOD ,RG_LP_VIO18_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x00 1.--2. " RG_HP_VIO18_PMOD ,RG_HP_VIO18_PMOD" "0,1,2,3"
|
|
line.byte 0x01 "VIO18PSI1,LDO PSI Register 1"
|
|
bitfld.byte 0x01 5.--6. " RG_S1_VIO18_PMOD ,RG_S1_VIO18_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x01 1.--2. " RG_S0_VIO18_PMOD ,RG_S0_VIO18_PMOD" "0,1,2,3"
|
|
group.byte 0x113++0x01
|
|
line.byte 0x00 "VSFLDO0,VSFLDO0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VSF_CAL ,RG_VSF_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
line.byte 0x01 "VSFLDO1,VSFLDO1 Register"
|
|
bitfld.byte 0x01 0.--1. " RG_VSF_VOSEL_[1:0] ,VSF output voltage select" "1.86V,3 V,3.3 V,Null"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "VSFLDOBF0,VSFLDOBF0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VSF_BUF_CAL ,RG_VSF_BUF_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0x119++0x01
|
|
line.byte 0x00 "VSFPSI0,VSF LDO PSI Register 0"
|
|
bitfld.byte 0x00 5.--6. " RG_LP_VSF_PMOD ,RG_LP_VSF_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x00 1.--2. " RG_LP_VSF_PMOD ,RG_LP_VSF_PMOD" "0,1,2,3"
|
|
line.byte 0x01 "VSFPSI1,VSF LDO PSI Register 1"
|
|
bitfld.byte 0x01 5.--6. " RG_S1_VSF_PMOD ,RG_S1_VSF_PMOD" "0,1,2,3"
|
|
rbitfld.byte 0x01 4. " RGS_S1_VSF_ON ,RGS_S1_VSF_ON" "0,1"
|
|
bitfld.byte 0x01 1.--2. " RG_S0_VSF_PMOD ,RG_S0_VSF_PMOD" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " RGS_S0_VSF_ON ,RGS_S0_VSF_ON" "0,1"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "SMPSCTL0,SMPS Control Register 0"
|
|
bitfld.byte 0x00 6.--7. " RG_VCORE_BUCK_SCHG_TSTEP ,VCORE DVS soft change time step" "0.6us,1.3us,2.6us,4.6us"
|
|
bitfld.byte 0x00 4. " RG_VCORE_BUCK_SCHG_EN ,VCORE DVS soft change enable" "Disabled,Enabled"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "SMPSANA3,SMPS Analog Control Register 3"
|
|
bitfld.byte 0x00 3. " RG_VOUTDET_EN ,VOUT tied to VBAT detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " RG_VCORE_VSLEEP_SEL ,Sleep mode voltage selection" "0.7V,0.75V,0.6V,0.65V"
|
|
rgroup.byte 0x135++0x00
|
|
line.byte 0x00 "VCBUCK19,VCORE BUCK Register 19"
|
|
bitfld.byte 0x00 1. " RGS_QI_VCORE_OC_STATUS ,OC status" "0,1"
|
|
group.byte 0x13E++0x02
|
|
line.byte 0x00 "VCBUCKPSI0,VCORE BUCK PSI Register 0"
|
|
bitfld.byte 0x00 4.--7. " RG_HP_VC_BUCK_VOVAL ,VCORE BUCK output voltage value for HP state" "0.6V,0.65V,0.7V,,0.8V,,0.9V,,1V,,1.1V,,1.2V,,1.3V,1.35V"
|
|
bitfld.byte 0x00 1.--3. " RG_HP_VC_BUCK_VOADJ ,VCORE BUCK voltage adjust value for HP state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. " RG_HP_VC_BUCK_ON ,VCORE BUCK on/off control for HP state" "Off,On"
|
|
line.byte 0x01 "VCBUCKPSI1,VCORE BUCK PSI Register 1"
|
|
bitfld.byte 0x01 4.--7. " RG_LP_VC_BUCK_VOVAL ,VCORE BUCK output voltage value for LP state" "0.6V,0.65V,0.7V,,0.8V,,0.9V,,1V,,1.1V,,1.2V,,1.3V,1.35V"
|
|
bitfld.byte 0x01 1.--3. " RG_LP_VC_BUCK_VOADJ ,VCORE BUCK voltage adjust value for LP state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x01 0. " RG_LP_VC_BUCK_ON ,VCORE BUCK on/off control for LP state" "Off,On"
|
|
line.byte 0x02 "VCBUCKPSI2,VCORE BUCK PSI Register 2"
|
|
bitfld.byte 0x02 4.--7. " RG_S1_VC_BUCK_VOVAL ,VCORE BUCK output voltage value for LP state" "0.6V,0.65V,0.7V,,0.8V,,0.9V,,1V,,1.1V,,1.2V,,1.3V,1.35V"
|
|
bitfld.byte 0x02 1.--3. " RG_S1_VC_BUCK_VOADJ ,VCORE BUCK voltage adjust value for LP state" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
rgroup.byte 0x200++0x01
|
|
line.byte 0x00 "AUXADC_ADC0,AUXADC ADC Register 0"
|
|
line.byte 0x01 "AUXADC_ADC0_H,AUXADC ADC Register 0_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH0 ,AUXADC channel 0 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH0_H ,AUXADC channel 0 output data bit [14:8]"
|
|
rgroup.byte 0x202++0x01
|
|
line.byte 0x00 "AUXADC_ADC1,AUXADC ADC Register 1"
|
|
line.byte 0x01 "AUXADC_ADC1_H,AUXADC ADC Register 1_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH1 ,AUXADC channel 1 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH1_H ,AUXADC channel 1 output data bit [14:8]"
|
|
rgroup.byte 0x204++0x01
|
|
line.byte 0x00 "AUXADC_ADC2,AUXADC ADC Register 2"
|
|
line.byte 0x01 "AUXADC_ADC2_H,AUXADC ADC Register 2_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH2 ,AUXADC channel 2 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH2_H ,AUXADC channel 2 output data bit [14:8]"
|
|
rgroup.byte 0x206++0x01
|
|
line.byte 0x00 "AUXADC_ADC3,AUXADC ADC Register 3"
|
|
line.byte 0x01 "AUXADC_ADC3_H,AUXADC ADC Register 3_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH3 ,AUXADC channel 3 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH3_H ,AUXADC channel 3 output data bit [14:8]"
|
|
rgroup.byte 0x208++0x01
|
|
line.byte 0x00 "AUXADC_ADC4,AUXADC ADC Register 4"
|
|
line.byte 0x01 "AUXADC_ADC4_H,AUXADC ADC Register 4_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH4 ,AUXADC channel 4 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH4_H ,AUXADC channel 4 output data bit [14:8]"
|
|
textline " "
|
|
rgroup.byte 0x21A++0x01
|
|
line.byte 0x00 "AUXADC_ADC13,AUXADC ADC Register 13"
|
|
line.byte 0x01 "AUXADC_ADC13_H,AUXADC ADC Register 13_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_THR_HW ,AUXADC channel 13 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_ADC_OUT_THR_HW_H ,AUXADC channel 13 output data bit [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x21C++0x01
|
|
line.byte 0x00 "AUXADC_ADC14,AUXADC ADC Register 14"
|
|
line.byte 0x01 "AUXADC_ADC14_H,AUXADC ADC Register 14_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_LBAT ,AUXADC channel 14 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_ADC_OUT_LBAT_H ,AUXADC channel 14 output data bit [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x21E++0x01
|
|
line.byte 0x00 "AUXADC_ADC15,AUXADC ADC Register 15"
|
|
line.byte 0x01 "AUXADC_ADC15_H,AUXADC ADC Register 15_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_LBAT2 ,AUXADC channel 15 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_ADC_OUT_LBAT2_H ,AUXADC channel 15 output data bit [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rgroup.byte 0x226++0x01
|
|
line.byte 0x00 "AUXADC_ADC19,AUXADC ADC Register 19"
|
|
line.byte 0x01 "AUXADC_ADC19_H,AUXADC ADC Register 19_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH4_BY_MD ,AUXADC channel 19 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_ADC_OUT_CH4_BY_MD_H ,AUXADC channel 19 output data bit [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rgroup.byte 0x228++0x01
|
|
line.byte 0x00 "AUXADC_ADC20,AUXADC ADC Register 20"
|
|
line.byte 0x01 "AUXADC_ADC20_H,AUXADC ADC Register 20_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_WAKEUP_PCHR ,AUXADC channel 20 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_WAKEUP_PCHR_H ,AUXADC channel 20 output data bit [14:8]"
|
|
rgroup.byte 0x22A++0x01
|
|
line.byte 0x00 "AUXADC_ADC21,AUXADC ADC Register 21"
|
|
line.byte 0x01 "AUXADC_ADC21_H,AUXADC ADC Register 21_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_WAKEUP_SWCHR ,AUXADC channel 21 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_WAKEUP_SWCHR_H ,AUXADC channel 21 output data bit [14:8]"
|
|
textline " "
|
|
rgroup.byte 0x22C++0x01
|
|
line.byte 0x00 "AUXADC_ADC22,AUXADC ADC Register 22"
|
|
line.byte 0x01 "AUXADC_ADC22_H,AUXADC ADC Register 22_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH0_BY_MD ,AUXADC channel 22 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH0_BY_MD_H ,AUXADC channel 22 output data bit [14:8]"
|
|
rgroup.byte 0x22E++0x01
|
|
line.byte 0x00 "AUXADC_ADC23,AUXADC ADC Register 23"
|
|
line.byte 0x01 "AUXADC_ADC23_H,AUXADC ADC Register 23_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH0_BY_AP ,AUXADC channel 23 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH0_BY_AP_H ,AUXADC channel 23 output data bit [14:8]"
|
|
rgroup.byte 0x230++0x01
|
|
line.byte 0x00 "AUXADC_ADC24,AUXADC ADC Register 24"
|
|
line.byte 0x01 "AUXADC_ADC24_H,AUXADC ADC Register 24_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH1_BY_MD ,AUXADC channel 24 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH1_BY_MD_H ,AUXADC channel 24 output data bit [14:8]"
|
|
rgroup.byte 0x232++0x01
|
|
line.byte 0x00 "AUXADC_ADC25,AUXADC ADC Register 25"
|
|
line.byte 0x01 "AUXADC_ADC25_H,AUXADC ADC Register 25_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_CH1_BY_AP ,AUXADC channel 25 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_CH1_BY_AP_H ,AUXADC channel 25 output data bit [14:8]"
|
|
textline " "
|
|
rgroup.byte 0x234++0x01
|
|
line.byte 0x00 "AUXADC_ADC26,AUXADC ADC Register 26"
|
|
line.byte 0x01 "AUXADC_ADC26_H,AUXADC ADC Register 26_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_VISMPS0 ,AUXADC channel 26 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_ADC_OUT_VISMPS0_H ,AUXADC channel 26 output data bit [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rgroup.byte 0x236++0x01
|
|
line.byte 0x00 "AUXADC_ADC27,AUXADC ADC Register 27"
|
|
line.byte 0x01 "AUXADC_ADC27_H,AUXADC ADC Register 27_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_FGADC1 ,AUXADC channel 27 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_DDDDDD_FGADC1 ,AUXADC channel 27 output data bit [14:8]"
|
|
rgroup.byte 0x238++0x01
|
|
line.byte 0x00 "AUXADC_ADC28,AUXADC ADC Register 28"
|
|
line.byte 0x01 "AUXADC_ADC28_H,AUXADC ADC Register 28_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_FGADC2 ,AUXADC channel 28 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_DDDDDD_FGADC2 ,AUXADC channel 28 output data bit [14:8]"
|
|
rgroup.byte 0x23A++0x01
|
|
line.byte 0x00 "AUXADC_ADC29,AUXADC ADC Register 29"
|
|
line.byte 0x01 "AUXADC_ADC29_H,AUXADC ADC Register 29_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_RDY_IMP ,AUXADC channel 29 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_DDDDDD_IMP ,AUXADC channel 29 output data bit [14:8]"
|
|
textline " "
|
|
rgroup.byte 0x23C++0x15
|
|
line.byte 0x00 "AUXADC_ADC30,AUXADC ADC Register 30"
|
|
line.byte 0x01 "AUXADC_ADC30_H,AUXADC1 ADC Register 0_H"
|
|
bitfld.byte 0x01 7. " AUXADC_ADC_IMP_AVG ,AUXADC channel 30 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x01 0.--6. 1. " AUXADC_ADC_OUT_IMP_AVG_H ,AUXADC channel 30 output data bit [14:8]"
|
|
line.byte 0x02 "AUXADC_ADC31,AUXADC ADC Register 31"
|
|
line.byte 0x03 "AUXADC_ADC31_H,AUXADC1 ADC Register 1_H"
|
|
hexmask.byte 0x03 0.--6. 1. " AUXADC_ADC_OUT_RAW_H ,AUXADC channel 31 output data bit [14:8]"
|
|
line.byte 0x04 "AUXADC_ADC32,AUXADC ADC Register 32"
|
|
line.byte 0x05 "AUXADC_ADC32_H,AUXADC1 ADC Register 2_H"
|
|
bitfld.byte 0x05 7. " AUXADC_ADC_RDY_MDRT ,AUXADC channel 32 output data ready" "Not ready,Ready"
|
|
hexmask.byte 0x05 0.--6. 1. " AUXADC_ADC_OUT_MDRT_H ,AUXADC channel 32 output data bit [14:8]"
|
|
line.byte 0x06 "AUXADC_ADC33,AUXADC ADC Register 33"
|
|
line.byte 0x07 "AUXADC_ADC33_H,AUXADC1 ADC Register 3_H"
|
|
bitfld.byte 0x07 7. " AUXADC_ADC_RDY_JEITA ,AUXADC channel 33 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x07 0.--3. " AUXADC_ADC_OUT_JEITA_H ,AUXADC output data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x08 "AUXADC_ADC34,AUXADC ADC Register 34"
|
|
line.byte 0x09 "AUXADC_ADC34_H,AUXADC1 ADC Register 4_H"
|
|
bitfld.byte 0x09 7. " AUXADC_ADC_RDY_DCXO_BY_GPS ,AUXADC channel 4 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x09 0.--3. " AUXADC_ADC_OUT_DCXO_BY_GPS_H ,AUXADC channel 4 output data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x0A "AUXADC_ADC35,AUXADC ADC Register 35"
|
|
line.byte 0x0B "AUXADC_ADC35_H,AUXADC ADC Register 35_H"
|
|
bitfld.byte 0x0B 7. " AUXADC_ADC_RDY_DCXO_BY_MD ,AUXADC channel 4 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x0B 0.--3. " AUXADC_ADC_OUT_DCXO_BY_MD_H ,AUXADC channel 4 output data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x0C "AUXADC_ADC36,AUXADC ADC Register 36"
|
|
line.byte 0x0D "AUXADC_ADC36_H,AUXADC ADC Register _H"
|
|
bitfld.byte 0x0D 7. " AUXADC_ADC_RDY_DCXO_BY_AP ,AUXADC channel 4 output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x0D 0.--3. " AUXADC_ADC_OUT_DCXO_BY_AP_H ,AUXADC channel 4 output data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x0E "AUXADC_ADC37,AUXADC ADC Register 37"
|
|
line.byte 0x0F "AUXADC_ADC37_H,AUXADC1 ADC Register _H"
|
|
bitfld.byte 0x0F 7. " AUXADC_ADC_RDY_DCXO_MDRT ,AUXADC output data ready" "Not ready,Ready"
|
|
bitfld.byte 0x0F 0.--3. " AUXADC_ADC_OUT_DCXO_MDRT_H ,AUXADC output data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x10 "AUXADC_ADC38,AUXADC ADC Register 38"
|
|
line.byte 0x11 "AUXADC_ADC38_H,AUXADC1 ADC Register 34_H"
|
|
bitfld.byte 0x11 7. " AUXADC_ADC_RDY_NAG ,AUXADC_ADC_RDY_NAG" "Not ready,Ready"
|
|
hexmask.byte 0x11 0.--6. 1. " AUXADC_ADC_OUT_NAG_H ,AUXADC_ADC_OUT_NAG_H"
|
|
line.byte 0x12 "AUXADC_STA0,AUXADC_STA 0 Register"
|
|
line.byte 0x13 "AUXADC_STA0_H,AUXADC_STA0_H Register"
|
|
bitfld.byte 0x13 7. " AUXADC_ADC_BUSY_IN_WAKEUP ,ADC busy IN_WAKEUP status" "Idle,Busy"
|
|
bitfld.byte 0x13 6. " AUXADC_ADC_BUSY_IN_VISMPS0 ,ADC busy VISMPS0 status" "Idle,Busy"
|
|
bitfld.byte 0x13 5. " AUXADC_ADC_BUSY_IN_LBAT2 ,ADC busy LBAT2 status" "Idle,Busy"
|
|
textline " "
|
|
bitfld.byte 0x13 4. " AUXADC_ADC_BUSY_IN_LBAT ,ADC busy LBAT status" "Idle,Busy"
|
|
bitfld.byte 0x13 3. " AUXADC_ADC_BUSY_IN_H_[3] ,ADC channel 11 busy status" "Idle,Busy"
|
|
bitfld.byte 0x13 2. " [2] ,ADC channel 10 busy status" "Idle,Busy"
|
|
textline " "
|
|
bitfld.byte 0x13 1. " [1] ,ADC channel 9 busy status" "Idle,Busy"
|
|
bitfld.byte 0x13 0. " [0] ,ADC channel 8 busy status" "Idle,Busy"
|
|
line.byte 0x14 "AUXADC_STA1,AUXADC_STA1 Register"
|
|
bitfld.byte 0x14 7. " AUXADC_ADC_BUSY_IN_SHARE ,ADC busy IN_SHARE status" "Idle,Busy"
|
|
bitfld.byte 0x14 6. " AUXADC_ADC_BUSY_IN_MDRT ,ADC busy IN_MDRT status" "Idle,Busy"
|
|
bitfld.byte 0x14 5. " AUXADC_ADC_BUSY_IN_JEITA ,ADC busy IN_JEITA status" "Idle,Busy"
|
|
textline " "
|
|
bitfld.byte 0x14 4. " AUXADC_ADC_BUSY_IN_NAG ,ADC busy IN_NAG status" "Idle,Busy"
|
|
bitfld.byte 0x14 3. " AUXADC_ADC_BUSY_IN_DCXO_GPS ,ADC busy IN_DCXO_GPS status" "Idle,Busy"
|
|
bitfld.byte 0x14 2. " AUXADC_ADC_BUSY_IN_DCXO_GPS_MD ,ADC busy IN_DCXO_GPS_MD status" "Idle,Busy"
|
|
textline " "
|
|
bitfld.byte 0x14 1. " AUXADC_ADC_BUSY_IN_DCXO_GPS_AP ,ADC busy IN_DCXO_GPS_AP status" "Idle,Busy"
|
|
bitfld.byte 0x14 0. " AUXADC_ADC_BUSY_IN_DCXO_MDRT ,ADC busy IN_DCXO_MDRT status" "Idle,Busy"
|
|
line.byte 0x15 "AUXADC_STA1_H,AUXADC_STA1_H Register"
|
|
bitfld.byte 0x15 7. " AUXADC_ADC_BUSY_IN_THR_MD ,ADC busy IN_THR_MD status" "Idle,Busy"
|
|
bitfld.byte 0x15 6. " AUXADC_ADC_BUSY_IN_THR_HW ,ADC busy IN_THR_HW status" "Idle,Busy"
|
|
bitfld.byte 0x15 2. " AUXADC_ADC_BUSY_IN_FGADC2 ,ADC busy IN_FGADC2 status" "Idle,Busy"
|
|
textline " "
|
|
bitfld.byte 0x15 1. " AUXADC_ADC_BUSY_IN_FGADC1 ,ADC busy IN_FGADC1 status" "Idle,Busy"
|
|
bitfld.byte 0x15 0. " AUXADC_ADC_BUSY_IN_IMP ,ADC busy IN_IMP status" "Idle,Busy"
|
|
textline " "
|
|
group.byte 0x2BE++0x01
|
|
line.byte 0x00 "AUXADC_LBAT2_4,AUXADC_LBAT2_4 Register"
|
|
line.byte 0x01 "AUXADC_LBAT2_4_H,AUXADC_LBAT2_4_H Register"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_LBAT2_VOLT_MAXA ,LBAT2 detection voltage setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x2C0++0x01
|
|
line.byte 0x00 "AUXADC_LBAT2_5,AUXADC_LBAT2_5 Register"
|
|
line.byte 0x01 "AUXADC_LBAT2_5_H,AUXADC_LBAT2_5_H Register"
|
|
bitfld.byte 0x01 0.--3. " AUXADC_LBAT2_VOLT_MINA ,LBAT2 detection voltage setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.byte 0x2EF++0x00
|
|
line.byte 0x00 "VBTLDO0,VBT LDO Register 0"
|
|
bitfld.byte 0x00 0.--3. " RG_VBT_CAL ,RG_VBT_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x2F3++0x00
|
|
line.byte 0x00 "VBTLDOBF0,VBT LDO Buffer Register 0"
|
|
bitfld.byte 0x00 0.--3. " RG_VBT_BUF_CAL ,RG_VBT_BUF_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x2F5++0x01
|
|
line.byte 0x00 "VBTPSI0,VBTP LDO PSI Register 0"
|
|
bitfld.byte 0x00 5.--6. " RG_LP_VBT_PMOD ,RG_LP_VBT_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x00 1.--2. " RG_HP_VBT_PMOD ,RG_HP_VBT_PMOD" "0,1,2,3"
|
|
line.byte 0x01 "VBTPSI1,VBTP LDO PSI Register 1"
|
|
bitfld.byte 0x01 5.--6. " RG_S1_VBT_PMOD ,RG_S1_VBT_PMOD" "0,1,2,3"
|
|
rbitfld.byte 0x01 4. " RGS_S1_VBT_ON ,RGS_S1_VBT_ON" "0,1"
|
|
bitfld.byte 0x01 1.--2. " RG_S0_VBT_PMOD ,RG_S0_VBT_PMOD" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " RGS_S0_VBT_ON ,RGS_S0_VBT_ON" "0,1"
|
|
group.byte 0x2F8++0x00
|
|
line.byte 0x00 "VALDO0,VALDO Register 0"
|
|
bitfld.byte 0x00 0.--3. " RG_VA_CAL ,RG_VA_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x2FC++0x00
|
|
line.byte 0x00 "VALDOBF0,VALDO0 Buffer Register 0"
|
|
bitfld.byte 0x00 0.--3. " RG_VA_BUF_CAL ,RG_VA_BUF_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x2FE++0x02
|
|
line.byte 0x00 "VAPSI0,VALDO0 PSI Register 0"
|
|
bitfld.byte 0x00 5.--6. " RG_LP_VA_PMOD ,RG_LP_VA_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x00 1.--2. " RG_HP_VA_PMOD ,RG_HP_VA_PMOD" "0,1,2,3"
|
|
line.byte 0x01 "VAPSI1,VALDO PSI Register 1"
|
|
bitfld.byte 0x01 5.--6. " RG_S1_VA_PMOD ,RG_S1_VA_PMOD" "0,1,2,3"
|
|
rbitfld.byte 0x01 4. " RGS_S1_VA_ON ,RGS_S1_VA_ON" "0,1"
|
|
bitfld.byte 0x01 1.--2. " RG_S0_VA_PMOD ,RG_S0_VA_PMOD" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " RGS_S0_VA_ON ,RGS_S0_VA_ON" "0,1"
|
|
line.byte 0x02 "VCAMACTL0,VCAMA Control Register 0"
|
|
bitfld.byte 0x02 2.--3. " RG_OVR_VCAMA_PMOD ,RG_OVR_VCAMA_PMOD" "0,1,2,3"
|
|
bitfld.byte 0x02 1. " RG_VCAMA_OCFB_EN ,RG_VCAMA_OCFB_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " RG_VCAMA_EN ,RG_VCAMA_EN" "Disabled,Enabled"
|
|
group.byte 0x302++0x01
|
|
line.byte 0x00 "VCAMALDO0,VCAMA LDO Register 0"
|
|
bitfld.byte 0x00 0.--3. " RG_VCAMA_CAL ,RG_VCAMA_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "VCAMALDO1,VCAMA LDO Register 1"
|
|
bitfld.byte 0x01 0.--2. " RG_VCAMA_VOSEL ,RG_VCAMA_VOSEL" "1.5 V,1.8 V,2.5 V,2.8 V,?..."
|
|
group.byte 0x306++0x00
|
|
line.byte 0x00 "VCAMALDOBF0,VCAMA LDO Buffer Register 0"
|
|
bitfld.byte 0x00 4.--6. " RG_VCAMA_COIN_SS_TRIM_BIAS ,RG_VCAMA_COIN_SS_TRIM_BIAS" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--3. " RG_VCAMA_BUF_CAL ,RG_VCAMA_BUF_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x30A++0x00
|
|
line.byte 0x00 "PSWCTL0,PSW Control Register 0"
|
|
bitfld.byte 0x00 2. " RG_SWMP_EN ,RG_SWMP_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RG_SWDP_EN ,RG_SWDP_EN" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RG_SWXM_EN ,RG_SWXM_EN" "Disabled,Enabled"
|
|
rgroup.byte 0x30F++0x00
|
|
line.byte 0x00 "SWIO18PSI,SWIO18 LDO PSI Register"
|
|
bitfld.byte 0x00 3. " RGS_S1_SWDP_ON ,RGS_S1_SWDP_ON" "0,1"
|
|
bitfld.byte 0x00 2. " RGS_S0_SWDP_ON ,RGS_S0_SWDP_ON" "0,1"
|
|
bitfld.byte 0x00 1. " RGS_S1_SWXM_ON ,RGS_S1_SWXM_ON" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RGS_S0_SWXM_ON ,RGS_S0_SWXM_ON" "0,1"
|
|
group.byte 0x313++0x00
|
|
line.byte 0x00 "VIO28LDO0,VIO28LDO0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VIO28_CAL_E1 ,RG_VIO28_CAL_E1" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "VIO28LDOBF0,VIO28LDOBF0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VIO28_BUF_CAL_E1 ,RG_VIO28_BUF_CAL_E1" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
|
|
group.byte 0x319++0x01
|
|
line.byte 0x00 "VIO28PSI0,VIO28 LDO PSI Register 0"
|
|
bitfld.byte 0x00 5.--6. " RG_LP_VIO28_PMOD_E1 ,RG_LP_VIO28_PMOD_E1" "0,1,2,3"
|
|
bitfld.byte 0x00 1.--2. " RG_HP_VIO28_PMOD_E1 ,RG_HP_VIO28_PMOD_E1" "0,1,2,3"
|
|
line.byte 0x01 "VIO28PSI1,VIO28 LDO PSI Register 1"
|
|
bitfld.byte 0x01 5.--6. " RG_S1_VIO28_PMOD_E1 ,RG_S1_VIO28_PMOD_E1" "0,1,2,3"
|
|
rbitfld.byte 0x01 4. " RGS_S1_VIO28_ON_E1 ,RGS_S1_VIO28_ON_E1" "0,1"
|
|
bitfld.byte 0x01 1.--2. " RG_S0_VIO28_PMOD_E1 ,RG_S0_VIO28_PMOD_E1" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " RGS_S0_VIO28_ON_E1 ,RGS_S0_VIO28_ON_E1" "0,1"
|
|
group.byte 0x31C++0x01
|
|
line.byte 0x00 "VMCLDO0,VMCLDO0 Register"
|
|
bitfld.byte 0x00 0.--3. " RG_VMC_CAL ,RG_VMC_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "VMCLDO0,VMCLDO0 Register"
|
|
bitfld.byte 0x01 0.--1. " RG_VMC_VOSEL ,RG_VMC_VOSEL" "1.8V,2.8V,3V,3.3V"
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group.byte 0x320++0x00
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line.byte 0x00 "VMCLDOBF0,VMCLDOBF0 Register"
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bitfld.byte 0x00 0.--3. " RG_VMC_BUF_CAL ,RG_VMC_BUF_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.byte 0x322++0x02
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line.byte 0x00 "VMCPSI0,VMC LDO PSI Register 0"
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bitfld.byte 0x00 5.--6. " RG_LP_VMC_PMOD ,RG_LP_VMC_PMOD" "0,1,2,3"
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bitfld.byte 0x00 1.--2. " RG_HP_VMC_PMOD ,RG_HP_VIO28_PMOD_E1" "0,1,2,3"
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line.byte 0x01 "VMCPSI1,VMC LDO PSI Register 1"
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bitfld.byte 0x01 5.--6. " RG_S1_VMC_PMOD ,RG_S1_VMC_PMOD" "0,1,2,3"
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rbitfld.byte 0x01 4. " RGS_S1_VMC_ON ,RGS_S1_VMC_ON" "0,1"
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bitfld.byte 0x01 1.--2. " RG_S0_VMC_PMOD ,RG_S0_VMC_PMOD" "0,1,2,3"
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textline " "
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rbitfld.byte 0x01 0. " RGS_S0_VMC_ON ,RGS_S0_VMC_ON" "0,1"
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line.byte 0x02 "VIBRCTL0,VIBR Control Register 0"
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bitfld.byte 0x02 4.--5. " RG_VIBR_STBTD ,RG_VIBR_STBTD (Li-ion/coin)" "240us/1.6ms,2.4ms/15ms,90us/1.2ms,3ms/17ms"
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bitfld.byte 0x02 2.--3. " RG_OVR_VIBR_PMOD ,RG_OVR_VIBR_PMOD" "0,1,2,3"
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bitfld.byte 0x02 1. " RG_VIBR_OCFB_EN ,RG_VIBR_OCFB_EN" "Disabled,Enabled"
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textline " "
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bitfld.byte 0x02 0. " RG_VIBR_EN ,RG_VIBR_EN" "Disabled,Enabled"
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group.byte 0x326++0x01
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line.byte 0x00 "VIBRLDO0,VIBRLDO0 Register"
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bitfld.byte 0x00 0.--3. " RG_VIBR_CAL ,RG_VIBR_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
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line.byte 0x01 "VIBRLDO1,VIBRLDO1 Register"
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bitfld.byte 0x01 0.--2. " RG_VIBR_VOSEL ,RG_VIBR_VOSEL" "1.3V,1.5V,1.8V,2V,2.5 V,2.8V,3V,3.3V"
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group.byte 0x32A++0x00
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line.byte 0x00 "VIBRLDOBF0,VIBRLDOBF0 Register"
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bitfld.byte 0x00 0.--3. " RG_VIBR_BUF_CAL ,RG_VIBR_BUF_CAL" "0 mV,-20 mV,-40 mV,-60 mV,-80 mV,-100 mV,-120 mV,-140 mV,+160 mV,+140 mV,+120 mV,+100 mV,+80 mV,+60 mV,+40 mV,+20 mV"
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textline " "
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group.byte 0x32C++0x02
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line.byte 0x00 "ISINK0_CON0,ISINK0 Control Register 0"
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line.byte 0x01 "ISINK0_CON1,ISINK0 Control Register 1"
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line.byte 0x02 "ISINK0_CON2,ISINK0 Control Register 2"
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bitfld.byte 0x02 5.--7. " ISINK_CH0_STEP ,Coarse 6 step current level for ISINK CH0" "4mA,8mA,12mA,16mA,20mA,24mA,24mA,24mA"
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bitfld.byte 0x02 0.--4. " ISINK_DIM0_DUTY ,ISINK ON-duty of dimming 0 control" "1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32,32/32"
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group.byte (0x32C+0x04)++0x02
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line.byte 0x00 "ISINK0_CON4,ISINK0 Control Register 4"
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bitfld.byte 0x00 4.--7. " ISINK_BREATH0_TR1_SEL ,ISINK0 breath mode rising time selection for duty 0%~30%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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bitfld.byte 0x00 0.--3. " ISINK_BREATH0_TR2_SEL ,ISINK0 breath mode rising time selection for duty 31%~100%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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line.byte 0x01 "ISINK0_CON5,ISINK0 Control Register 5"
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bitfld.byte 0x01 4.--7. " ISINK_BREATH0_TF1_SEL ,ISINK0 breath mode falling time selection for duty 0%~30%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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bitfld.byte 0x01 0.--3. " ISINK_BREATH1_TF2_SEL ,ISINK0 breath mode falling time selection for duty 31%~100%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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line.byte 0x02 "ISINK0_CON6,ISINK0 Control Register 6"
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bitfld.byte 0x02 4.--7. " ISINK_BREATH0_TON_SEL ,ISINK0 breath mode Ton time selection" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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bitfld.byte 0x02 0.--3. " ISINK_BREATH0_TOFF_SEL ,ISINK0 breath mode Toff time selection" "0.246s,0.677s,1.046s,1.417s,1.845s,2.214s,2.583s,3.014s,3.383s,3.752s,4.183s,4.552s,4.921s,5.351s,5.720s,6.151s"
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group.byte 0x333++0x02
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line.byte 0x00 "ISINK1_CON0,ISINK1 Control Register 0"
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line.byte 0x01 "ISINK1_CON1,ISINK1 Control Register 1"
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line.byte 0x02 "ISINK1_CON2,ISINK1 Control Register 2"
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bitfld.byte 0x02 5.--7. " ISINK_CH1_STEP ,Coarse 6 step current level for ISINK CH1" "4mA,8mA,12mA,16mA,20mA,24mA,24mA,24mA"
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bitfld.byte 0x02 0.--4. " ISINK_DIM1_DUTY ,ISINK ON-duty of dimming 1 control" "1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32,32/32"
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group.byte (0x333+0x04)++0x02
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line.byte 0x00 "ISINK1_CON4,ISINK1 Control Register 4"
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bitfld.byte 0x00 4.--7. " ISINK_BREATH1_TR1_SEL ,ISINK1 breath mode rising time selection for duty 0%~30%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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bitfld.byte 0x00 0.--3. " ISINK_BREATH1_TR2_SEL ,ISINK1 breath mode rising time selection for duty 31%~100%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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line.byte 0x01 "ISINK1_CON5,ISINK1 Control Register 5"
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bitfld.byte 0x01 4.--7. " ISINK_BREATH1_TF1_SEL ,ISINK1 breath mode falling time selection for duty 0%~30%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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bitfld.byte 0x01 0.--3. " ISINK_BREATH1_TF2_SEL ,ISINK1 breath mode falling time selection for duty 31%~100%" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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line.byte 0x02 "ISINK1_CON6,ISINK1 Control Register 6"
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bitfld.byte 0x02 4.--7. " ISINK_BREATH1_TON_SEL ,ISINK1 breath mode Ton time selection" "0.123s,0.338s,0.523s,0.707s,0.926s,1.107s,1.291s,1.507s,1.691s,1.876s,2.091s,2.276s,2.460s,2.676s,2.860s,3.075s"
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bitfld.byte 0x02 0.--3. " ISINK_BREATH1_TOFF_SEL ,ISINK1 breath mode Toff time selection" "0.246s,0.677s,1.046s,1.417s,1.845s,2.214s,2.583s,3.014s,3.383s,3.752s,4.183s,4.552s,4.921s,5.351s,5.720s,6.151s"
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textline " "
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group.byte 0x33A++0x00
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line.byte 0x00 "ISINK2_CON1,ISINK2 Control Register 1"
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bitfld.byte 0x00 5.--7. " ISINK_CH2_STEP ,Coarse 6 step current level for ISINK CH2" "4mA,8mA,12mA,16mA,20mA,24mA,24mA,24mA"
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group.byte 0x33C++0x00
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line.byte 0x00 "ISINK3_CON1,ISINK3 Control Register 1"
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bitfld.byte 0x00 5.--7. " ISINK_CH3_STEP ,Coarse 6 step current level for ISINK CH3" "4mA,8mA,12mA,16mA,20mA,24mA,24mA,24mA"
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group.byte 0x33F++0x00
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line.byte 0x00 "ISINK_ANA0_H,ISINK_ANA0_H ACD Interface 0 High Register"
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bitfld.byte 0x00 1. " RG_ISINK1_DOUBLE ,Isink 1 surrent doubel enable" "Disabled,Enabled"
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bitfld.byte 0x00 0. " RG_ISINK0_DOUBLE ,Isink 0 surrent doubel enable" "Disabled,Enabled"
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group.byte 0x344++0x02
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line.byte 0x00 "ISINK_EN_CTRL_LOW,ISINK Enable Control Low Register"
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bitfld.byte 0x00 5. " RG_ISINK1_CHOP_EN ,ISINK Channel 1 CHOP CLK enable" "Disabled,Enabled"
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bitfld.byte 0x00 4. " RG_ISINK0_CHOP_EN ,ISINK Channel 0 CHOP CLK enable" "Disabled,Enabled"
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bitfld.byte 0x00 1. " ISINK_CH1_EN ,Turn on ISINK Channel 1 enable" "Disabled,Enabled"
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textline " "
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bitfld.byte 0x00 0. " ISINK_CH0_EN ,Turn on ISINK Channel 0 enable" "Disabled,Enabled"
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line.byte 0x01 "ISINK_EN_CTRL_HIGH,ISINK Enable Control High Register"
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bitfld.byte 0x01 1. " ISINK_CH1_BIAS_EN ,ISINK Channel 1 CHOP CLK enable" "Disabled,Enabled"
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bitfld.byte 0x01 0. " ISINK_CH0_BIAS_EN ,ISINK Channel 0 CHOP CLK enable" "Disabled,Enabled"
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line.byte 0x02 "ISINK_MODE_CTRL,ISINK Mode Control Register"
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bitfld.byte 0x02 6.--7. " ISINK_CH0_MODE ,ISINK Channel 0 enable mode select" "PWM,Breath,Register,Register"
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bitfld.byte 0x02 4.--5. " ISINK_CH1_MODE ,ISINK Channel 1 enable mode select" "PWM,Breath,Register,Register"
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width 0x0B
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tree.end
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textline ""
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