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d411edd9b47003e0a9ef98de9aef8259ddea419d
Gen4_R-Car_Trace32/2_Trunk/perlpc11exx.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: LPC11Exx On-Chip Peripherals
; @Props: Released
; @Author: DST, TOH, LUK
; @Changelog: 2019-02-05 TOH
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: ES_LPC11E1X.pdf (Rev. 2, 2013-02-01)
; ES_LPC11E3X.pdf (Rev. 1.2, 2014-09-17)
; LPC11E1x_DS.pdf (Rev. 1.1, 2013-09-24)
; LPC11E1x_LPC11E3x_UM10518.pdf (Rev. 3.5, 2016-12-21)
; LPC11E3x_DS.pdf (Rev. 2.3, 2014-09-11)
; LPC11E6x_DS.pdf (Rev. 1.3, 2016-09-09)
; LPC11E6x_UM10732.pdf (Rev. 1.8, 2016-09-19)
; @Core: Cortex-M0P, Cortex-M0
; @Chip:LPC11E11, LPC11E12, LPC11E13, LPC11E14, LPC11E35FHI33, LPC11E36, LPC11E37,
; LPC11E37H, LPC11E66JBD48, LPC11E67JBD100, LPC11E67JBD48, LPC11E67JBD64,
; LPC11E68JBD100, LPC11E68JBD48, LPC11E68JBD64
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perlpc11exx.per 10353 2019-03-22 12:14:53Z kwitkowski $
; Known problems
; Module Register Description
; --------------------------------------------------------------------------------
; DMA DMA TRIGMUX Two different base addresses (in memory map and in register description)
config 16. 8.
sif CORENAME()=="CORTEXM0"
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
elif CORENAME()=="CORTEXM0+"
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
tree "SYSCON (System Configuration)"
base ad:0x40048000
width 17.
group.long 0x00++0x03
line.long 0x00 "SYSMEMREMAP,System Memory Remap Register"
bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,?..."
sif cpuis("LPC11E*")
group.long 0x04++0x03
line.long 0x00 "PRESETCTRL,Peripheral Reset Control Register"
sif cpuis("LPC11E6*")
bitfld.long 0x00 10. " SCT1_RST_N ,SCT1 reset control" "Reset,No reset"
bitfld.long 0x00 9. " SCT0_RST_N ,SCT0 reset control" "Reset,No reset"
bitfld.long 0x00 8. " USART4_RST_N ,USART4 reset control" "Reset,No reset"
newline
bitfld.long 0x00 7. " USART3_RST_N ,USART3 reset control" "Reset,No reset"
bitfld.long 0x00 6. " USART2_RST_N ,USART2 reset control" "Reset,No reset"
bitfld.long 0x00 5. " USART1_RST_N ,USART1 reset control" "Reset,No reset"
newline
bitfld.long 0x00 4. " FRG_RST_N ,FRG reset control" "Reset,No reset"
bitfld.long 0x00 3. " I2C1_RST_N ,I2C1 reset control" "Reset,No reset"
bitfld.long 0x00 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset"
else
bitfld.long 0x00 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset"
endif
newline
bitfld.long 0x00 1. " I2C0_RST_N ,I2C0 reset control" "Reset,No reset"
bitfld.long 0x00 0. " SSP0_RST_N ,SSP0 reset control" "Reset,No reset"
endif
group.long 0x08++0x03
line.long 0x00 "SYSPLLCTRL,System PLL Control Register"
bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rgroup.long 0x0C++0x03
line.long 0x00 "SYSPLLSTAT,System PLL Status Register"
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
sif cpuis("LPC11E6*")
group.long 0x10++0x03
line.long 0x00 "USBPLLCTRL,USB PLL Control Register"
bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rgroup.long 0x14++0x03
line.long 0x00 "USBPLLSTAT,USB PLL Status Register"
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
group.long 0x1C++0x03
line.long 0x00 "RTCOSCCTRL,RTC Oscillator 32 kHz Output Control Register"
bitfld.long 0x00 0. " RTCOSCEN ,RTC 32 kHz output enable" "Disabled,Enabled"
endif
group.long 0x20++0x07
line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register"
bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz"
bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled"
line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register"
bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency" "0 MHz,0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz"
bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
sif cpuis("LPC11E*")
group.long 0x28++0x03
line.long 0x00 "IRCCTRL,Internal Resonant Crystal Control Register"
hexmask.long.byte 0x00 0.--7. 1. " TRIM ,Trim value"
group.long 0x30++0x03
line.long 0x00 "SYSRSTSTAT,System Reset Status Register"
eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset"
eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset"
eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset"
newline
eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset"
eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset"
else
group.long 0x28++0x03
line.long 0x00 "FROOSCCTRL, FRO Oscillator Control Register"
bitfld.long 0x00 17. " FRO_DIRECT ,FRO direct clock select" "fro_oscout /2 or /16,FRO oscillator"
group.long 0x30++0x03
line.long 0x00 "FRODIRECTCLKUEN, FRO Direct Clock Source Update Enable Register"
bitfld.long 0x00 0. " ENA ,FRO clock source update enable" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "SYSRSTSTAT,System Reset Status Register"
eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset"
eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset"
eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset"
newline
eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset"
eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset"
endif
group.long 0x40++0x07
line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register"
sif cpuis("LPC11E6*")
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,SYSOSC,,32kHz clock"
elif cpuis("LPC11E1*")||cpuis("LPC11E3*")
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,SYSOSC,?..."
else
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "FRO,External clock,Watchdog oscillator,FRO DIV"
endif
line.long 0x04 "SYSPLLCLKUEN,System PLL Clock Source Update Enable Register"
bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
sif cpuis("LPC11E6*")
group.long 0x48++0x07
line.long 0x00 "USBPLLCLKSEL,USB PLL Clock Source Select Register"
bitfld.long 0x00 0.--1. " SEL ,USB PLL clock source" "IRC oscillator,SYSOSC,?..."
line.long 0x04 "USBPLLCLKUEN,USB PLL Clock Source Update Enable Register"
bitfld.long 0x04 0. " ENA ,USB PLL clock source update enable" "Disabled,Enabled"
endif
group.long 0x70++0x0B
line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register"
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,PLL input,Watchdog oscillator,PLL output"
line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register"
bitfld.long 0x04 0. " ENA ,Main PLL clock source update enable" "Disabled,Enabled"
line.long 0x08 "SYSAHBCLKDIV,System Clock Divider Register"
hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values"
group.long 0x80++0x03
line.long 0x00 "SYSAHBCLKCTRL,System Clock Control Register"
sif cpuis("LPC11E6*")
bitfld.long 0x00 31. " SCT0_1 , SCT0 and SCT1 clock enable" "Disabled,Enabled"
bitfld.long 0x00 30. " RTC , RTC register interface clock enable" "Disabled,Enabled"
bitfld.long 0x00 29. " DMA ,DMA clock enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " CRC ,CRC clock enable" "Disabled,Enabled"
bitfld.long 0x00 27. " USBSRAM ,USB SRAM/SRAM2 block enable" "Disabled,Enabled"
bitfld.long 0x00 26. " RAM1 ,SRAM1 clock enable" "Disabled,Enabled"
else
bitfld.long 0x00 27. " USBSRAM ,USB SRAM/SRAM2 block enable" "Disabled,Enabled"
bitfld.long 0x00 26. " RAM1 ,SRAM1 clock enable" "Disabled,Enabled"
endif
newline
sif cpuis("LPC11E6*")
bitfld.long 0x00 25. " I2C1 ,I2C1 clock enable" "Disabled,Enabled"
bitfld.long 0x00 24. " GROUP1INT ,GPIO GROUP1 interrupt register clock enable" "Disabled,Enabled"
bitfld.long 0x00 23. " GROUP0INT ,GPIO GROUP0 interrupt register clock enable" "Disabled,Enabled"
else
bitfld.long 0x00 24. " GROUP1INT ,GPIO GROUP1 interrupt register clock enable" "Disabled,Enabled"
bitfld.long 0x00 23. " GROUP0INT ,GPIO GROUP0 interrupt register clock enable" "Disabled,Enabled"
endif
newline
sif cpuis("LPC11E6*")
bitfld.long 0x00 22. " USART3_4 ,USART3 and USART4 register interfaces clock enable" "Disabled,Enabled"
bitfld.long 0x00 21. " USART2 ,USART2 register interface clock enable" "Disabled,Enabled"
bitfld.long 0x00 20. " USART1 ,USART1 register interface clock enable" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 19. " PINT ,GPIO pin interrupt register interface clock enable" "Disabled,Enabled"
bitfld.long 0x00 18. " SSP1 ,SSP1 clock enable" "Disabled,Enabled"
bitfld.long 0x00 16. " IOCON ,I/O configuration block clock enable" "Disabled,Enabled"
newline
bitfld.long 0x00 15. " WWDT ,WWDT clock enable" "Disabled,Enabled"
sif cpuis("LPC11E6*")
bitfld.long 0x00 14. " USB ,USB register interface clock enable" "Disabled,Enabled"
bitfld.long 0x00 13. " ADC ,ADC clock enable" "Disabled,Enabled"
else
bitfld.long 0x00 13. " ADC ,ADC clock enable" "Disabled,Enabled"
endif
newline
bitfld.long 0x00 12. " USART0 ,USART0 clock enable" "Disabled,Enabled"
bitfld.long 0x00 11. " SSP0 ,SSP0 clock enable" "Disabled,Enabled"
bitfld.long 0x00 10. " CT32B1 ,32-bit counter/timer 1 clock enable" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " CT32B0 ,32-bit counter/timer 0 clock enable" "Disabled,Enabled"
bitfld.long 0x00 8. " CT16B1 ,16-bit counter/timer 1 clock enable" "Disabled,Enabled"
bitfld.long 0x00 7. " CT16B0 ,16-bit counter/timer 0 clock enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " GPIO ,GPIO port registers clock enable" "Disabled,Enabled"
bitfld.long 0x00 5. " I2C0 ,I2C0 clock enable" "Disabled,Enabled"
bitfld.long 0x00 4. " FLASHARRAY ,Flash access clock enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " FLASHREG ,Flash register interface clock enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RAM0 ,Main SRAM0 clock enable" "Disabled,Enabled"
bitfld.long 0x00 1. " ROM ,ROM clock enable" "Disabled,Enabled"
newline
rbitfld.long 0x00 0. " SYS ,Clock for AHB/APB bridge/Cortex-M0/SYSCON/Reset control/SRAM0/PMU enable" ",Enabled"
group.long 0x94++0x0B
line.long 0x00 "SSP0CLKDIV,SSP0 Clock Divider Register"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,SPI0_PCLK clock divider values"
line.long 0x04 "USART0CLKDIV,USART0 Clock Divider"
hexmask.long.byte 0x04 0.--7. 1. " DIV ,USART_PCLK clock divider values"
line.long 0x08 "SSP1CLKDIV,SSP1 Clock Divider"
hexmask.long.byte 0x08 0.--7. 1. " DIV ,SSP1_PCLK clock divider values"
sif cpuis("LPC11E6*")
group.long 0xA0++0x03
line.long 0x00 "FRGCLKDIV,UART Fractional Baud Rate Clock Divider Register"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,USART fractional baud rate generator clock divider values"
group.long 0xC0++0x0B
line.long 0x00 "USBCLKSEL,USB Clock Source Select Register"
bitfld.long 0x00 0.--1. " SEL ,USB clock source" "USB PLL out,Main clock,?..."
line.long 0x04 "USBCLKUEN,USB Clock Source Update Enable Register"
bitfld.long 0x04 0. " ENA ,USB clock source update enable" "Disabled,Enabled"
line.long 0x08 "USBCLKDIV,USB Clock Source Divider Register"
hexmask.long.byte 0x08 0.--7. 1. " DIV ,USB clock divider values"
endif
group.long 0xE0++0x0B
line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register"
bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,SYSOSC,Watchdog oscillator,Main clock"
line.long 0x04 "CLKOUTUEN,CLKOUT Clock Source Update Enable Register"
bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled"
line.long 0x08 "CLKOUTDIV,CLKOUT Clock Divider Register"
hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values"
sif cpuis("LPC11E6*")
group.long 0xF0++0x07
line.long 0x00 "UARTFRGDIV,USART Fractional Generator Divider Value Register"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider"
line.long 0x04 "UARTFRGMULT,USART Fractional Generator Multiplier Value Register"
hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider"
group.long 0xFC++0x03
line.long 0x00 "EXTTRACECMD,External Trace Buffer Command Register"
bitfld.long 0x00 1. " STOP ,Trace stop command" "No effect,Stopped"
bitfld.long 0x00 0. " START ,Trace start command" "No effect,Started"
endif
else
group.long 0x48++0x13
line.long 0x00 "MAINCLKPLLSEL,Main Clock Source Select Register"
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "main_clk_pre_pll,SYS PLL,?..."
line.long 0x04 "MAINCLKPLLUEN, Main Clock Source Update Enable Register"
bitfld.long 0x04 0. " ENA ,Main clock source update. enable" "Disabled,Enabled"
line.long 0x08 "MAINCLKSEL,Main Clock Source Select Register"
bitfld.long 0x08 0.--1. " SEL ,Clock source for main clock pre pll" "FRO,External clock,Watchdog oscillator,FRO DIV"
line.long 0x0C "MAINCLKUEN,Main Clock Source Update Enable Register"
bitfld.long 0x0C 0. " ENA ,Enable main clock source update" "Disabled,Enabled"
line.long 0x10 "SYSAHBCLKDIV,System AHB Clock Divider Register"
hexmask.long.byte 0x10 0.--7. 1. " DIV ,System AHB clock divider values"
group.long 0x60++0x17
line.long 0x00 "CAPTCLKSEL,CAPT Clock Source Select Register"
bitfld.long 0x00 0.--2. " SEL ,Clock source for CAPT clock" "FRO,main clock,SYS PLL,FRO_DIV,Watchdog oscillator,?..."
line.long 0x04 "ADCCLKSEL,ADC Clock Source Select Register"
bitfld.long 0x04 0.--1. " SEL ,Clock source for ADC clock" "FRO,SYS PLL,?..."
line.long 0x08 "ADCCLKDIV,ADC Clock Divider Register"
hexmask.long.byte 0x08 0.--7. 1. " DIV ,ADC clock divider values"
line.long 0x0C "SCTCLKSEL,SCT Clock Source Select Register"
bitfld.long 0x0C 0.--1. " SEL ,Clock source for SCT clock" "FRO,Main clock,SYS PLL,?..."
line.long 0x10 "SCTCLKDIV,SCT Clock Divider Register"
hexmask.long.byte 0x10 0.--7. 1. " DIV ,SCT clock divider values"
line.long 0x14 "EXTCLKSEL,External Clock Source Select Register"
bitfld.long 0x14 0. " SEL ,Clock source for external clock" "System oscillator,CLK_IN"
newline
group.long 0x80++0x3B
line.long 0x00 "SYSAHBCLKCTRL0,System Clock Control 0 Register"
bitfld.long 0x00 31. " UART4 ,Clock for UART4 enable" "Disabled,Enabled"
bitfld.long 0x00 30. " UART3 ,Clock for UART3 enable" "Disabled,Enabled"
bitfld.long 0x00 29. " DMA ,Clock for DMA enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " GPIO_INT ,Clock for GPIO pin interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 27. " DAC0 ,Clock for DAC0 enable" "Disabled,Enabled"
bitfld.long 0x00 26. " MTB ,Clock for MTB enable" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " CTIMER0 ,Clock for CTIMER0 enable" "Disabled,Enabled"
bitfld.long 0x00 24. " ADC ,Clock for ADC enable" "Disabled,Enabled"
bitfld.long 0x00 23. " I2C3 ,Clock for I2C3 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " I2C2 ,Clock for I2C2 enable" "Disabled,Enabled"
bitfld.long 0x00 21. " I2C1 ,Clock for I2C1 enable" "Disabled,Enabled"
bitfld.long 0x00 20. " GPIO1 ,Clock for GPIO1 port registers enable" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " ACMP ,Clock to analog comparator enable" "Disabled,Enabled"
bitfld.long 0x00 18. " IOCON ,Clock for IOCON block enable" "Disabled,Enabled"
bitfld.long 0x00 17. " WWDT ,Clock for WWDT enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " UART2 ,Clock for USART2 enable" "Disabled,Enabled"
bitfld.long 0x00 15. " UART1 ,Clock for USART1 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " UART0 ,Clock for USART0 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " CRC ,Clock for CRC enable" "Disabled,Enabled"
bitfld.long 0x00 12. " SPI1 ,Clock for SPI1 enable" "Disabled,Enabled"
bitfld.long 0x00 11. " SPI0 ,Clock for SPI0 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " MRT ,Clock for multi-rate timer enable" "Disabled,Enabled"
bitfld.long 0x00 9. " WKT ,Clock for self wake-up timer enable" "Disabled,Enabled"
bitfld.long 0x00 8. " SCT ,Clock for state configurable timer enable" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " SWM ,Clock for switch matrix enable" "Disabled,Enabled"
bitfld.long 0x00 6. " GPIO0 ,Clock for GPIO0 port registers enable" "Disabled,Enabled"
bitfld.long 0x00 5. " I2C0 ,Clock for I2C0 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " FLASH ,Clock for flash enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RAM0_1 ,Clock for SRAM0/SRAM1 enable" "Disabled,Enabled"
bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled"
newline
rbitfld.long 0x00 0. " SYS ,Clock for AHB to APB bridge enable" ",Enabled"
line.long 0x04 "SYSAHBCLKCTRL1,System Clock Control 1 Register"
bitfld.long 0x04 1. " CAPT ,Clock for CAPT enable" "Disabled,Enabled"
bitfld.long 0x04 0. " DAC1 ,Clock for DAC1 enable" "Disabled,Enabled"
line.long 0x08 "PRESETCTRL0,Peripheral Reset Control 0 Register"
bitfld.long 0x08 31. " UART4_RST_N ,UART4 reset control" "Assert,Clear"
bitfld.long 0x08 30. " UART3_RST_N ,UART3 reset control" "Assert,Clear"
bitfld.long 0x08 29. " DMA_RST_N ,DMA reset control" "Assert,Clear"
newline
bitfld.long 0x08 28. " GPIOINT_RST_N ,GPIOINT reset control" "Assert,Clear"
bitfld.long 0x08 27. " DAC0_RST_N ,DAC0 reset control" "Assert,Clear"
bitfld.long 0x08 25. " CTIMER0_RST_N ,CTIMER reset control" "Assert,Clear"
newline
bitfld.long 0x08 24. " ADC_RST_N ,ADC reset control" "Assert,Clear"
bitfld.long 0x08 23. " I2C3_RST_N ,I2C3 reset control" "Assert,Clear"
bitfld.long 0x08 22. " I2C2_RST_N ,I2C2 reset control" "Assert,Clear"
newline
bitfld.long 0x08 21. " I2C1_RST_N ,I2C1 reset control" "Assert,Clear"
bitfld.long 0x08 20. " GPIO1_RST_N ,GPIO1 reset control" "Assert,Clear"
bitfld.long 0x08 19. " ACMP_RST_N ,Analog comparator reset control" "Assert,Clear"
newline
bitfld.long 0x08 18. " IOCON_RST_N ,IOCON reset control" "Assert,Clear"
bitfld.long 0x08 16. " UART2_RST_N ,UART2 reset control" "Assert,Clear"
bitfld.long 0x08 15. " UART1_RST_N ,UART1 reset control" "Assert,Clear"
newline
bitfld.long 0x08 14. " UART0_RST_N ,UART0 reset control" "Assert,Clear"
bitfld.long 0x08 13. " CRC_RST_N ,CRC reset control" "Assert,Clear"
bitfld.long 0x08 12. " SPI1_RST_N ,SPI1 reset control" "Assert,Clear"
newline
bitfld.long 0x08 11. " SPI0_RST_N ,SPI0 reset control" "Assert,Clear"
bitfld.long 0x08 10. " MRT_RST_N ,Multi-rate timer reset control" "Assert,Clear"
bitfld.long 0x08 9. " WKT_RST_N ,Self-wake-up timer reset control" "Assert,Clear"
newline
bitfld.long 0x08 8. " SCT_RST_N ,SCT reset control" "Assert,Clear"
bitfld.long 0x08 7. " SWM_RST_N ,SWM reset control" "Assert,Clear"
bitfld.long 0x08 6. " GPIO0_RST_N ,GPIO0 reset control" "Assert,Clear"
newline
bitfld.long 0x08 5. " I2C0_RST_N ,I2C0 reset control" "Assert,Clear"
bitfld.long 0x08 4. " FLASH_RST_N ,Flash controller reset control" "Assert,Clear"
line.long 0x0C "PRESETCTRL1,Peripheral Reset Control 1 Register"
bitfld.long 0x0C 4. " FRG1_RST_N ,Fractional baud rate generator 1 reset control" "Assert,Clear"
bitfld.long 0x0C 3. " FRG0_RST_N ,Fractional baud rate generator 0 reset control" "Assert,Clear"
bitfld.long 0x0C 1. " DAC1_RST_N ,DAC1 reset control" "Assert,Clear"
bitfld.long 0x0C 0. " CAPT_RST_N ,Capacitive Touch reset control" "Assert,Clear"
line.long 0x10 "UART0CLKSEL,UART0 Clock Source Select Register"
bitfld.long 0x10 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x14 "UART1CLKSEL,UART1 Clock Source Select Register"
bitfld.long 0x14 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x18 "UART2CLKSEL,UART2 Clock Source Select Register"
bitfld.long 0x18 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x1C "UART3CLKSEL,UART3 Clock Source Select Register"
bitfld.long 0x1C 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x20 "UART4CLKSEL,UART4 Clock Source Select Register"
bitfld.long 0x20 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x24 "I2C0CLKSEL,I2C0 Clock Source Select Register"
bitfld.long 0x24 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x28 "I2C1CLKSEL,I2C1 Clock Source Select Register"
bitfld.long 0x28 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x2C "I2C2CLKSEL,I2C2 Clock Source Select Register"
bitfld.long 0x2C 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x30 "I2C3CLKSEL,I2C3 Clock Source Select Register"
bitfld.long 0x30 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x34 "SPI0CLKSEL,SPI0 Clock Source Select Register"
bitfld.long 0x34 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
line.long 0x38 "SPI1CLKSEL,SPI1 Clock Source Select Register"
bitfld.long 0x38 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None"
newline
group.long 0xD0++0x0B
line.long 0x00 "FRG0DIV,Fractional Generator 0 Divider Value Register"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider"
line.long 0x04 "FRG0MULT,Fractional Generator 0 Multiplier Value Register"
hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider"
line.long 0x08 "FRG0CLKSEL,FRG0 Clock Source Select Register"
bitfld.long 0x08 0.--1. " SEL ,FRG0_SRC clock source" "FRO,Main clock,SYS PLL,None"
group.long 0xE0++0x0B
line.long 0x00 "FRG1DIV,Fractional Generator 1 Divider Value Register"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider"
line.long 0x04 "FRG1MULT,Fractional Generator 1 Multiplier Value Register"
hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider"
line.long 0x08 "FRG1CLKSEL,FRG0 Clock source Select Register"
bitfld.long 0x08 0.--1. " SEL ,FRG0_SRC clock source" "FRO,Main clock,SYS PLL,None"
group.long 0xF0++0x0B
line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register"
bitfld.long 0x00 0.--2. " SEL ,CLKOUT clock source" "FRO,Main clock,SYS PLL,External clock,Watchdog oscillator,None,None,None"
line.long 0x04 "CLKOUTDIV,CLKOUT Clock Divider Registers"
hexmask.long.byte 0x04 0.--7. 1. " DIV ,CLKOUT clock divider values"
group.long 0xFC++0x03
line.long 0x00 "EXTTRACECMD,External Trace Buffer Command Register"
bitfld.long 0x00 1. " STOP ,Trace stop command" "Not stopped,Stopped"
bitfld.long 0x00 0. " START ,Trace start command" "Not started,Started"
newline
endif
newline
rgroup.long 0x100++0x07
line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0"
sif cpuis("LPC11E*")
bitfld.long 0x00 23. " PIO0_23 ,State of PIO0_23 at power-on reset" "Low,High"
newline
else
bitfld.long 0x00 31. " PIO0_31 ,State of PIO0_31 at power-on reset" "Low,High"
bitfld.long 0x00 30. " PIO0_30 ,State of PIO0_30 at power-on reset" "Low,High"
bitfld.long 0x00 29. " PIO0_29 ,State of PIO0_29 at power-on reset" "Low,High"
newline
bitfld.long 0x00 28. " PIO0_28 ,State of PIO0_28 at power-on reset" "Low,High"
bitfld.long 0x00 27. " PIO0_27 ,State of PIO0_27 at power-on reset" "Low,High"
bitfld.long 0x00 26. " PIO0_26 ,State of PIO0_26 at power-on reset" "Low,High"
newline
bitfld.long 0x00 25. " PIO0_25 ,State of PIO0_25 at power-on reset" "Low,High"
bitfld.long 0x00 24. " PIO0_24 ,State of PIO0_24 at power-on reset" "Low,High"
bitfld.long 0x00 23. " PIO0_23 ,State of PIO0_23 at power-on reset" "Low,High"
newline
endif
bitfld.long 0x00 22. " PIO0_22 ,State of PIO0_22 at power-on reset" "Low,High"
bitfld.long 0x00 21. " PIO0_21 ,State of PIO0_21 at power-on reset" "Low,High"
bitfld.long 0x00 20. " PIO0_20 ,State of PIO0_20 at power-on reset" "Low,High"
newline
bitfld.long 0x00 19. " PIO0_19 ,State of PIO0_19 at power-on reset" "Low,High"
bitfld.long 0x00 18. " PIO0_18 ,State of PIO0_18 at power-on reset" "Low,High"
bitfld.long 0x00 17. " PIO0_17 ,State of PIO0_17 at power-on reset" "Low,High"
newline
bitfld.long 0x00 16. " PIO0_16 ,State of PIO0_16 at power-on reset" "Low,High"
bitfld.long 0x00 15. " PIO0_15 ,State of PIO0_15 at power-on reset" "Low,High"
bitfld.long 0x00 14. " PIO0_14 ,State of PIO0_14 at power-on reset" "Low,High"
newline
bitfld.long 0x00 13. " PIO0_13 ,State of PIO0_13 at power-on reset" "Low,High"
bitfld.long 0x00 12. " PIO0_12 ,State of PIO0_12 at power-on reset" "Low,High"
bitfld.long 0x00 11. " PIO0_11 ,State of PIO0_11 at power-on reset" "Low,High"
newline
bitfld.long 0x00 10. " PIO0_10 ,State of PIO0_10 at power-on reset" "Low,High"
bitfld.long 0x00 9. " PIO0_9 ,State of PIO0_9 at power-on reset" "Low,High"
bitfld.long 0x00 8. " PIO0_8 ,State of PIO0_8 at power-on reset" "Low,High"
newline
bitfld.long 0x00 7. " PIO0_7 ,State of PIO0_7 at power-on reset" "Low,High"
bitfld.long 0x00 6. " PIO0_6 ,State of PIO0_6 at power-on reset" "Low,High"
bitfld.long 0x00 5. " PIO0_5 ,State of PIO0_5 at power-on reset" "Low,High"
newline
bitfld.long 0x00 4. " PIO0_4 ,State of PIO0_4 at power-on reset" "Low,High"
bitfld.long 0x00 3. " PIO0_3 ,State of PIO0_3 at power-on reset" "Low,High"
bitfld.long 0x00 2. " PIO0_2 ,State of PIO0_2 at power-on reset" "Low,High"
newline
bitfld.long 0x00 1. " PIO0_1 ,State of PIO0_1 at power-on reset" "Low,High"
bitfld.long 0x00 0. " PIO0_0 ,State of PIO0_0 at power-on reset" "Low,High"
line.long 0x04 "PIOPORCAP1,POR Captured PIO Status Register 1"
bitfld.long 0x04 31. " PIO1_31 ,State of PIO1_31 at power-on reset" "Low,High"
bitfld.long 0x04 30. " PIO1_30 ,State of PIO1_30 at power-on reset" "Low,High"
bitfld.long 0x04 29. " PIO1_29 ,State of PIO1_29 at power-on reset" "Low,High"
newline
bitfld.long 0x04 28. " PIO1_28 ,State of PIO1_28 at power-on reset" "Low,High"
bitfld.long 0x04 27. " PIO1_27 ,State of PIO1_27 at power-on reset" "Low,High"
bitfld.long 0x04 26. " PIO1_26 ,State of PIO1_26 at power-on reset" "Low,High"
newline
bitfld.long 0x04 25. " PIO1_25 ,State of PIO1_25 at power-on reset" "Low,High"
bitfld.long 0x04 24. " PIO1_24 ,State of PIO1_24 at power-on reset" "Low,High"
bitfld.long 0x04 23. " PIO1_23 ,State of PIO1_23 at power-on reset" "Low,High"
newline
bitfld.long 0x04 22. " PIO1_22 ,State of PIO1_22 at power-on reset" "Low,High"
bitfld.long 0x04 21. " PIO1_21 ,State of PIO1_21 at power-on reset" "Low,High"
bitfld.long 0x04 20. " PIO1_20 ,State of PIO1_20 at power-on reset" "Low,High"
newline
bitfld.long 0x04 19. " PIO1_19 ,State of PIO1_19 at power-on reset" "Low,High"
bitfld.long 0x04 18. " PIO1_18 ,State of PIO1_18 at power-on reset" "Low,High"
bitfld.long 0x04 17. " PIO1_17 ,State of PIO1_17 at power-on reset" "Low,High"
newline
bitfld.long 0x04 16. " PIO1_16 ,State of PIO1_16 at power-on reset" "Low,High"
bitfld.long 0x04 15. " PIO1_15 ,State of PIO1_15 at power-on reset" "Low,High"
bitfld.long 0x04 14. " PIO1_14 ,State of PIO1_14 at power-on reset" "Low,High"
newline
bitfld.long 0x04 13. " PIO1_13 ,State of PIO1_13 at power-on reset" "Low,High"
bitfld.long 0x04 12. " PIO1_12 ,State of PIO1_12 at power-on reset" "Low,High"
bitfld.long 0x04 11. " PIO1_11 ,State of PIO1_11 at power-on reset" "Low,High"
newline
bitfld.long 0x04 10. " PIO1_10 ,State of PIO1_10 at power-on reset" "Low,High"
bitfld.long 0x04 9. " PIO1_9 ,State of PIO1_9 at power-on reset" "Low,High"
bitfld.long 0x04 8. " PIO1_8 ,State of PIO1_8 at power-on reset" "Low,High"
newline
bitfld.long 0x04 7. " PIO1_7 ,State of PIO1_7 at power-on reset" "Low,High"
bitfld.long 0x04 6. " PIO1_6 ,State of PIO1_6 at power-on reset" "Low,High"
bitfld.long 0x04 5. " PIO1_5 ,State of PIO1_5 at power-on reset" "Low,High"
newline
bitfld.long 0x04 4. " PIO1_4 ,State of PIO1_4 at power-on reset" "Low,High"
bitfld.long 0x04 3. " PIO1_3 ,State of PIO1_3 at power-on reset" "Low,High"
bitfld.long 0x04 2. " PIO1_2 ,State of PIO1_2 at power-on reset" "Low,High"
newline
bitfld.long 0x04 1. " PIO1_1 ,State of PIO1_1 at power-on reset" "Low,High"
bitfld.long 0x04 0. " PIO1_0 ,State of PIO1_0 at power-on reset" "Low,High"
sif cpuis("LPC11E6*")
rgroup.long 0x108++0x03
line.long 0x00 "PIOPORCAP2,POR Captured PIO Status Register 2"
bitfld.long 0x00 23. " PIO0_23 ,State of PIO0_23 at power-on reset" "Low,High"
newline
bitfld.long 0x00 22. " PIO0_22 ,State of PIO0_22 at power-on reset" "Low,High"
bitfld.long 0x00 21. " PIO0_21 ,State of PIO0_21 at power-on reset" "Low,High"
bitfld.long 0x00 20. " PIO0_20 ,State of PIO0_20 at power-on reset" "Low,High"
newline
bitfld.long 0x00 19. " PIO0_19 ,State of PIO0_19 at power-on reset" "Low,High"
bitfld.long 0x00 18. " PIO0_18 ,State of PIO0_18 at power-on reset" "Low,High"
bitfld.long 0x00 17. " PIO0_17 ,State of PIO0_17 at power-on reset" "Low,High"
newline
bitfld.long 0x00 16. " PIO0_16 ,State of PIO0_16 at power-on reset" "Low,High"
bitfld.long 0x00 15. " PIO0_15 ,State of PIO0_15 at power-on reset" "Low,High"
bitfld.long 0x00 14. " PIO0_14 ,State of PIO0_14 at power-on reset" "Low,High"
newline
bitfld.long 0x00 13. " PIO0_13 ,State of PIO0_13 at power-on reset" "Low,High"
bitfld.long 0x00 12. " PIO0_12 ,State of PIO0_12 at power-on reset" "Low,High"
bitfld.long 0x00 11. " PIO0_11 ,State of PIO0_11 at power-on reset" "Low,High"
newline
bitfld.long 0x00 10. " PIO0_10 ,State of PIO0_10 at power-on reset" "Low,High"
bitfld.long 0x00 9. " PIO0_9 ,State of PIO0_9 at power-on reset" "Low,High"
bitfld.long 0x00 8. " PIO0_8 ,State of PIO0_8 at power-on reset" "Low,High"
newline
bitfld.long 0x00 7. " PIO0_7 ,State of PIO0_7 at power-on reset" "Low,High"
bitfld.long 0x00 6. " PIO0_6 ,State of PIO0_6 at power-on reset" "Low,High"
bitfld.long 0x00 5. " PIO0_5 ,State of PIO0_5 at power-on reset" "Low,High"
newline
bitfld.long 0x00 4. " PIO0_4 ,State of PIO0_4 at power-on reset" "Low,High"
bitfld.long 0x00 3. " PIO0_3 ,State of PIO0_3 at power-on reset" "Low,High"
bitfld.long 0x00 2. " PIO0_2 ,State of PIO0_2 at power-on reset" "Low,High"
newline
bitfld.long 0x00 1. " PIO0_1 ,State of PIO0_1 at power-on reset" "Low,High"
bitfld.long 0x00 0. " PIO0_0 ,State of PIO0_0 at power-on reset" "Low,High"
endif
newline
sif cpuis("LPC11E6*")
group.long 0x134++0x03
line.long 0x00 "IOCONCLKDIV6,IOCON Glitch Filter Clock Divider Register 6"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
group.long 0x138++0x03
line.long 0x00 "IOCONCLKDIV5,IOCON Glitch Filter Clock Divider Register 5"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
group.long 0x13C++0x03
line.long 0x00 "IOCONCLKDIV4,IOCON Glitch Filter Clock Divider Register 4"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
group.long 0x140++0x03
line.long 0x00 "IOCONCLKDIV3,IOCON Glitch Filter Clock Divider Register 3"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
group.long 0x144++0x03
line.long 0x00 "IOCONCLKDIV2,IOCON Glitch Filter Clock Divider Register 2"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
group.long 0x148++0x03
line.long 0x00 "IOCONCLKDIV1,IOCON Glitch Filter Clock Divider Register 1"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
group.long 0x14C++0x03
line.long 0x00 "IOCONCLKDIV0,IOCON Glitch Filter Clock Divider Register 0"
hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value"
endif
newline
group.long 0x150++0x07
line.long 0x00 "BODCTRL,BOD Control Register"
bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
sif cpuis("LPC11E6*")
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",,Level 2,Level 3"
else
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",Level 1,Level 2,Level 3"
endif
bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "Level 0,Level 1,Level 2,Level 3"
else
newline
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",Level 1,Level 2,Level 3"
bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" ",Level 1,Level 2,Level 3"
endif
line.long 0x04 "SYSTCKCAL,System Tick Counter Calibration Register"
hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value"
group.long 0x170++0x07
line.long 0x00 "IRQLATENCY,IRQ Latency Register"
hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value"
line.long 0x04 "NMISRC,NMI Source Selection Register"
bitfld.long 0x04 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
bitfld.long 0x04 0.--4. " IRQN ,IRQ number of the interrupt" "PIN_INT0,PIN_INT1,PIN_INT2,PIN_INT3,PIN_INT4,PIN_INT5,PIN_INT6,PIN_INT7,GINT0,GINT1,I2C1,USART1_4,USART2_3,SCT0_1,SSP1,I2C0,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART0,USB_IRQ,USB_FIQ,ADC_A,RTC,BOD_WDT,FLASH,DMA,ADC_B,ADC_WAKEUP,?..."
else
newline
bitfld.long 0x04 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0_IRQ,SPI1_IRQ,DAC0_IRQ,UART0_IRQ,UART1_IRQ,UART2_IRQ,,I2C1_IRQ,I2C0_IRQ,SCT_IRQ,MRT_IRQ,CMP_IRQ/CAPT_IRQ,WDT_IRQ,BOD_IRQ,FLASH_IRQ,WKT_IRQ,ADC_SEQA_IRQ,ADC_SEQB_IRQ,ADC_THCMP_IRQ,ADC_OVR_IRQ,DMA_IRQ,I2C2_IRQ,I2C3_IRQ,CT32B0_IRQ,PININT0_IRQ,PININT1_IRQ,PININT2_IRQ,PININT3_IRQ,PININT4_IRQ,PININT5_IRQ/DAC1_IRQ,PININT6_IRQ/USART3_IRQ,PININT7_IRQ/USART4_IRQ"
endif
newline
group.long 0x178++0x03
line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x17C++0x03
line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x180++0x03
line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x184++0x03
line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x188++0x03
line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x18C++0x03
line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x190++0x03
line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
group.long 0x194++0x03
line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7"
sif cpuis("LPC11E*")
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7"
else
bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31"
endif
newline
sif cpuis("LPC11E6*")
group.long 0x198++0x03
line.long 0x00 "USBCLKCTRL,USB Clock Control Register"
bitfld.long 0x00 1. " POL_CLK ,USB polarity clock control" "Falling edge,Rising edge"
bitfld.long 0x00 0. " AP_CLK ,USB signal clock control" "Hardware,Forced"
rgroup.long 0x19C++0x03
line.long 0x00 "USBCLKST,USB Clock Status Register"
bitfld.long 0x00 0. " NEED_CLKST ,USB need_clock signal status" "Low,High"
endif
newline
group.long 0x204++0x03
line.long 0x00 "STARTERP0,Start Logic 0 Interrupt Wake-Up Enable Register 0"
bitfld.long 0x00 7. " PINT7 ,GPIO pin interrupt 7 wake-up" "Disabled,Enabled"
bitfld.long 0x00 6. " PINT6 ,GPIO pin interrupt 6 wake-up" "Disabled,Enabled"
bitfld.long 0x00 5. " PINT5 ,GPIO pin interrupt 5 wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " PINT4 ,GPIO pin interrupt 4 wake-up" "Disabled,Enabled"
bitfld.long 0x00 3. " PINT3 ,GPIO pin interrupt 3 wake-up" "Disabled,Enabled"
bitfld.long 0x00 2. " PINT2 ,GPIO pin interrupt 2 wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " PINT1 ,GPIO pin interrupt 1 wake-up" "Disabled,Enabled"
bitfld.long 0x00 0. " PINT0 ,GPIO pin interrupt 0 wake-up" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x214++0x03
line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-Up Enable Register 1"
bitfld.long 0x00 24. " USART2_3 ,Combined USART2 and USART3 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 23. " USART1_4 ,Combined USART1 and USART4 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 21. " GROUP1INT ,GPIO GROUP1 interrupt wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 20. " GROUP0INT ,GPIO GROUP0 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 19. " USB_WAKEUP ,USB need_clock signal wake-up" "Disabled,Enabled"
bitfld.long 0x00 13. " WWDT_BODINT ,Combined WWDT interrupt or BOD interrupt wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " RTCINT ,RTC interrupt wake-up" "Disabled,Enabled"
else
group.long 0x214++0x03
line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1"
bitfld.long 0x00 31. " USART4 ,USART4 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 30. " USART3 ,USART3 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 22. " I2C3 ,I2C3 interrupt wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 21. " I2C2 ,I2C2 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 15. " WKT ,Self wake-up timer wake-up" "Disabled,Enabled"
bitfld.long 0x00 13. " BOD ,BOD interrupt wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " WWDT ,WWDT interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 11. " Cap_Touch ,Cap Touch interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 8. " I2C0 ,I2C0 interrupt wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " I2C1 ,I2C1 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 5. " USART2 ,USART2 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 4. " USART1 ,USART1 interrupt wake-up" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " USART0 ,USART0 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 1. " SPI1 ,SPI1 interrupt wake-up" "Disabled,Enabled"
bitfld.long 0x00 0. " SPI0 ,SPI0 interrupt wake-up" "Disabled,Enabled"
endif
newline
group.long 0x230++0x03
line.long 0x00 "PDSLEEPCFG,Deep-sleep Configuration Register"
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down"
bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down"
sif cpuis("LPC11E*")
group.long 0x234++0x07
line.long 0x00 "PDAWAKECFG,Wake-up Configuration Register"
sif cpuis("LPC11E6*")
bitfld.long 0x00 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 10. " USBPAD_PD ,USB transceiver wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 8. " USBPLL_PD ,USB PLL wake-up configuration" "Powered,Powered down"
newline
endif
bitfld.long 0x00 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 5. " SYSOSC_PD ,Crystal oscillator wake-up configuration" "Powered,Powered down"
newline
bitfld.long 0x00 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down"
newline
bitfld.long 0x00 1. " IRC_PD ,IRC oscillator power-down wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down"
line.long 0x04 "PDRUNCFG,Power Configuration Register"
sif cpuis("LPC11E6*")
bitfld.long 0x04 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down"
bitfld.long 0x04 10. " USBPAD_PD ,USB transceiver power-down configuration" "Powered,Powered down"
bitfld.long 0x04 8. " USBPLL_PD ,USB PLL power-down configuration" "Powered,Powered down"
newline
endif
bitfld.long 0x04 7. " SYSPLL_PD ,System PLL power-down configuration" "Powered,Powered down"
bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator power-down configuration" "Powered,Powered down"
bitfld.long 0x04 5. " SYSOSC_PD ,Crystal oscillator power-down configuration" "Powered,Powered down"
newline
bitfld.long 0x04 4. " ADC_PD ,ADP power-down configuration" "Powered,Powered down"
bitfld.long 0x04 3. " BOD_PD ,BOD power-down configuration" "Powered,Powered down"
bitfld.long 0x04 2. " FLASH_PD ,Flash power-down configuration" "Powered,Powered down"
newline
bitfld.long 0x04 1. " IRC_PD ,IRC oscillator power-down configuration" "Powered,Powered down"
bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output power-down configuration" "Powered,Powered down"
else
group.long 0x234++0x07
line.long 0x00 "PDAWAKECFG,Wake-up Configuration Register"
bitfld.long 0x00 15. " ACMP ,Analog comparator wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 14. " DAC1 ,DAC1 wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 13. " DAC0 ,DAC0 wake-up configuration" "Powered,Powered down"
newline
bitfld.long 0x00 10. " VREF2_PD ,VREF2 wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down"
newline
bitfld.long 0x00 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down"
newline
bitfld.long 0x00 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 1. " FRO_PD ,FRO oscillator power-down wake-up configuration" "Powered,Powered down"
bitfld.long 0x00 0. " FROOUT_PD ,FRO oscillator output wake-up configuration" "Powered,Powered down"
line.long 0x04 "PDRUNCFG,Power Configuration Register"
bitfld.long 0x04 15. " ACMP ,Analog comparator power down" "Powered,Powered down"
bitfld.long 0x04 14. " DAC1 ,DAC1 power down" "Powered,Powered down"
bitfld.long 0x04 13. " DAC0 ,DAC0 power down" "Powered,Powered down"
newline
bitfld.long 0x04 7. " SYSPLL_PD ,System PLL power down" "Powered,Powered down"
bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator power down" "Powered,Powered down"
bitfld.long 0x04 5. " SYSOSC_PD ,Crystal oscillator power down" "Powered,Powered down"
newline
bitfld.long 0x04 4. " ADC_PD ,ADC power down" "Powered,Powered down"
bitfld.long 0x04 3. " BOD_PD ,BOD power down" "Powered,Powered down"
bitfld.long 0x04 2. " FLASH_PD ,Flash power down" "Powered,Powered down"
newline
bitfld.long 0x04 1. " FRO_PD ,FRO oscillator power down" "Powered,Powered down"
bitfld.long 0x04 0. " FROOUT_PD ,FRO oscillator output power down" "Powered,Powered down"
endif
sif cpuis("LPC11E*")
newline
rgroup.long 0x3F8++0x03
line.long 0x00 "DEVICE_ID,Device ID"
endif
width 0x0B
tree.end
tree "PMU (Power Management Unit)"
base ad:0x40038000
width 13.
group.long 0x00++0x03
line.long 0x00 "PCON,Power Control Register"
eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not entered,Entered"
eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not entered,Entered"
bitfld.long 0x00 3. " NODPD ,No Deep power-down mode enable" "Disabled,Enabled"
bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep power-down,?..."
sif cpuis("LPC11E*")
group.long 0x4++0x03
line.long 0x00 "GPREG0,General Purpose Register 0"
group.long 0x8++0x03
line.long 0x00 "GPREG1,General Purpose Register 1"
group.long 0xC++0x03
line.long 0x00 "GPREG2,General Purpose Register 2"
group.long 0x10++0x03
line.long 0x00 "GPREG3,General Purpose Register 3"
sif cpuis("LPC11E6*")
group.long 0x14++0x03
line.long 0x00 "GPREG4,General Purpose Register 4"
hexmask.long.tbyte 0x00 12.--31. 1. " GPDATA ,Data retained during deep power-down mode"
bitfld.long 0x00 11. " WAKEPAD_DISABLE ,WAKEUP pin disable" "Enabled,Disabled"
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis for enable" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "GPREG4,General Purpose Register 4"
hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during deep power-down mode"
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis for enable" "Disabled,Enabled"
endif
else
group.long 0x4++0x03
line.long 0x00 "GPREG0,General Purpose Register 0"
group.long 0x8++0x03
line.long 0x00 "GPREG1,General Purpose Register 1"
group.long 0xC++0x03
line.long 0x00 "GPREG2,General Purpose Register 2"
group.long 0x10++0x03
line.long 0x00 "GPREG3,General Purpose Register 3"
group.long 0x14++0x03
line.long 0x00 "GPREG4,General Purpose Register 4"
endif
sif !cpuis("LPC11E*")
group.long 0x20++0x07
line.long 0x00 "WUSRCREG,Deep Power Down Wake Up Source Status Register"
eventfld.long 0x00 7. " WUSRCREG[7] ,Pin wake-up status of PIO0_10" "No effect,Wake-up"
eventfld.long 0x00 6. " [6] ,Pin wake-up status of PIO0_11" "No effect,Wake-up"
eventfld.long 0x00 5. " [5] ,Pin wake-up status of PIO0_4" "No effect,Wake-up"
eventfld.long 0x00 4. " [4] ,Pin wake-up status of PIO0_13" "No effect,Wake-up"
newline
eventfld.long 0x00 3. " [3] ,Pin wake-up status of PIO0_17" "No effect,Wake-up"
eventfld.long 0x00 2. " [2] ,Pin wake-up status of PIO0_8" "No effect,Wake-up"
eventfld.long 0x00 1. " [1] ,Pin wake-up status of PIO0_9" "No effect,Wake-up"
eventfld.long 0x00 0. " [0] ,Pin wake-up status of PIO0_15" "No effect,Wake-up"
line.long 0x04 "WUENAREG,Deep Power Down Wake Up Enable Register"
bitfld.long 0x04 7. " WUENAREG[7] ,Pin wake-up enable for PIO0_10" "Disabled,Enabled"
bitfld.long 0x04 6. " [6] ,Pin wake-up enable for PIO0_11" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,Pin wake-up enable for PIO0_4" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,Pin wake-up enable for PIO0_13" "Disabled,Enabled"
newline
bitfld.long 0x04 3. " [3] ,Pin wake-up enable for PIO0_17" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,Pin wake-up enable for PIO0_8" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,Pin wake-up enable for PIO0_9" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Pin wake-up enable for PIO0_15" "Disabled,Enabled"
endif
width 0x0B
tree.end
tree "IOCON (I/O Control)"
base ad:0x40044000
sif cpuis("LPC11E1*")||cpuis("LPC11E3*")
width 15.
group.long 0x00++0x5F
line.long 0x00 "RESET_PIO0_0,I/O Configuration For Pin RESET/PIO0_0"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "Reset,PIO0_0,?..."
line.long 0x04 "PIO0_1,I/O Configuration For Pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_1,CLKOUT,CT32B0_MAT2,USB_FTOGGLE,?..."
line.long 0x08 "PIO0_2,I/O Configuration For Pin PIO0_2/SSEL0/CT16B0_CAP0/IOH_0"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_2,SSEL0,CT16B0_CAP0,IOH_0,?..."
line.long 0x0C "PIO0_3,I/O Configuration For Pin PIO0_3/USB_VBUS/IOH_1"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_3,USB_VBUS,IOH_1,?..."
line.long 0x10 "PIO0_4,I/O Configuration For Pin PIO0_4/SCL/IOH_2"
bitfld.long 0x10 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..."
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C SCL,IOH_2,?..."
line.long 0x14 "PIO0_5,I/O Configuration For Pin PIO0_5/SDA/IOH_3"
bitfld.long 0x14 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..."
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C SDA,IOH_3,?..."
line.long 0x18 "PIO0_6,I/O Configuration For Pin PIO0_6/USB_CONNECT/SCK0/IOH_4"
bitfld.long 0x18 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO0_6,USB_CONNECT,SCK0,SCK0.IOH_4,?..."
line.long 0x1C "PIO0_7,I/O Configuration For Pin PIO0_7/CTS/IOH_5"
bitfld.long 0x1C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x1C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x1C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x1C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x1C 0.--2. " FUNC ,Selects pin function" "PIO0_7,CTS,IOH_5,?..."
line.long 0x20 "PIO0_8,I/O Configuration For Pin PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6"
bitfld.long 0x20 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x20 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x20 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x20 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x20 0.--2. " FUNC ,Selects pin function" "PIO0_8,MISO0,CT16B0_MAT0,IOH_6,?..."
line.long 0x24 "PIO0_9,I/O Configuration For Pin PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7"
bitfld.long 0x24 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x24 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x24 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x24 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x24 0.--2. " FUNC ,Selects pin function" "PIO0_9,MOSI0,CT16B0_MAT1,IOH_7,?..."
line.long 0x28 "SWCLK_PIO0_10,I/O Configuration For Pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2"
bitfld.long 0x28 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x28 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x28 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x28 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x28 0.--2. " FUNC ,Selects pin function" "SWCLK,PIO0_10,SCK0,CT16B0_MAT2,?..."
line.long 0x2C "TDI_PIO0_11,I/O Configuration For Pin TDI/PIO0_11/AD0/CT32B0_MAT3"
bitfld.long 0x2C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x2C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x2C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x2C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x2C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x2C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x2C 0.--2. " FUNC ,Selects pin function" "TDI,PIO0_11,AD0,CT32B0_MAT3,?..."
line.long 0x30 "TMS_PIO0_12,I/O Configuration For Pin TMS/PIO0_12/AD1/CT32B1_CAP0"
bitfld.long 0x30 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x30 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x30 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x30 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x30 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x30 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x30 0.--2. " FUNC ,Selects pin function" "TMS,PIO0_12,AD1,CT32B1_CAP0,?..."
line.long 0x34 "TDO_PIO0_13,I/O Configuration For Pin TDO/PIO0_13/AD2/CT32B1_MAT0"
bitfld.long 0x34 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x34 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x34 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x34 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x34 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x34 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x34 0.--2. " FUNC ,Selects pin function" "TDO,PIO0_13,AD2,CT32B1_MAT0,?..."
line.long 0x38 "TRST_PIO0_14,I/O Configuration For Pin TRST/PIO0_14/AD3/CT32B1_MAT1"
bitfld.long 0x38 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x38 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x38 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x38 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x38 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x38 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x38 0.--2. " FUNC ,Selects pin function" "TRST,PIO0_14,AD3,CT32B1_MAT1,?..."
line.long 0x3C "SWDIO_PIO0_15,I/O Configuration For Pin SWDIO/PIO0_15/AD4/CT32B1_MAT2"
bitfld.long 0x3C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x3C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x3C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x3C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x3C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x3C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x3C 0.--2. " FUNC ,Selects pin function" "SWDIO,PIO0_15,AD4,CT32B1_MAT2,?..."
line.long 0x40 "PIO0_16,I/O Configuration For Pin PIO0_16/AD5/CT32B1_MAT3/IOH_8WAKEUP"
bitfld.long 0x40 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x40 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x40 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x40 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x40 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x40 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x40 0.--2. " FUNC ,Selects pin function" "PIO0_16,AD5,CT32B1_MAT3,IOH_8,?..."
line.long 0x44 "PIO0_17,I/O Configuration For Pin PIO0_17/RTS/CT32B0_CAP0/SCLK"
bitfld.long 0x44 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x44 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x44 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x44 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x44 0.--2. " FUNC ,Selects pin function" "PIO0_17,RTS,CT32B0_CAP0,SCLK,?..."
line.long 0x48 "PIO0_18,I/O Configuration For Pin PIO0_18/RXD/CT32B0_MAT0"
bitfld.long 0x48 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x48 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x48 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x48 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x48 0.--2. " FUNC ,Selects pin function" "PIO0_18,RXD,CT32B0_MAT0,?..."
line.long 0x4C "PIO0_19,I/O Configuration For Pin PIO0_19/TXD/CT32B0_MAT1"
bitfld.long 0x4C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x4C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x4C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x4C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x4C 0.--2. " FUNC ,Selects pin function" "PIO0_19,TXD,CT32B0_MAT1,?..."
line.long 0x50 "PIO0_20,I/O Configuration For Pin PIO0_20/CT16B1_CAP0"
bitfld.long 0x50 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x50 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x50 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x50 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x50 0.--2. " FUNC ,Selects pin function" "PIO0_20,CT16B1_CAP0,?..."
line.long 0x54 "PIO0_21,I/O Configuration For Pin PIO0_21/CT16B1_MAT0/MOSI1"
bitfld.long 0x54 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x54 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x54 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x54 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x54 0.--2. " FUNC ,Selects pin function" "PIO0_21,CT16B1_MAT0,MOSI1,?..."
line.long 0x58 "PIO0_22,I/O Configuration For Pin PIO0_22/AD6/CT16B1_MAT1/MISO1"
bitfld.long 0x58 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x58 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x58 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x58 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x58 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x58 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x58 0.--2. " FUNC ,Selects pin function" "PIO0_22,AD6,CT16B1_MAT1,MISO1,?..."
line.long 0x5C "PIO0_23,I/O Configuration For Pin PIO0_23/AD7/IOH_9"
bitfld.long 0x5C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x5C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x5C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x5C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x5C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x5C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x5C 0.--2. " FUNC ,Selects pin function" "PIO0_23,AD7,IOH_9,?..."
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0x60++0x13
line.long 0x00 "PIO1_0,I/O Configuration For Pin PIO1_0/CT32B1_MAT0/IOH_10"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_0,CT32B1_MAT1,IOH_10,?..."
line.long 0x04 "PIO1_1,I/O Configuration For Pin PIO1_1/CT32B1_MAT1/IOH_11"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_1,CT32B1_MAT1,IOH_11,?..."
line.long 0x08 "PIO1_2,I/O Configuration For Pin PIO1_2/CT32B1_MAT2IOH_12"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_2,CT32B1_MAT2,IOH_12,?..."
line.long 0x0C "PIO1_3,I/O Configuration For Pin PIO1_3/CT32B1_MAT3/IOH_13"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_3,CT32B1_MAT3,IOH_13,?..."
line.long 0x10 "PIO1_4,I/O Configuration For Pin PIO1_4/CT32B1_CAP0/IOH_14"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_4,CT32B1_CAP0,IOH_14,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0x74++0x03
line.long 0x00 "PIO1_5,I/O Configuration For Pin PIO1_5/CT32B1_CAP1/IOH_15"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_5,CT32B1_CAP1,IOH_15,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0x78++0x1B
line.long 0x00 "PIO1_6,I/O Configuration For Pin PIO1_6/IOH_16"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_6,IOH_16,?..."
line.long 0x04 "PIO1_7,I/O Configuration For Pin PIO1_7/IOH_17"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_7,IOH_17,?..."
line.long 0x08 "PIO1_8,I/O Configuration For Pin PIO1_8/IOH_18"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_8,IOH_18,?..."
line.long 0x0C "PIO1_9,I/O Configuration For Pin PIO1_9"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_9,?..."
line.long 0x10 "PIO1_10,I/O Configuration For Pin PIO1_10"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_10,?..."
line.long 0x14 "PIO1_11,I/O Configuration For Pin PIO1_11"
bitfld.long 0x14 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO1_11,?..."
line.long 0x18 "PIO1_12,I/O Configuration For Pin PIO1_12"
bitfld.long 0x18 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO1_12,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0x94++0x07
line.long 0x00 "PIO1_13,I/O Configuration For Pin PIO1_13/DTR/CT16B0_MAT0/TXD"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_13,DTR,CT16B0_MAT0,TXD,?..."
line.long 0x04 "PIO1_14,I/O Configuration For Pin PIO1_14/DSR/CT16B0_MAT1/RXD"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_14,DSR,CT16B0_MAT1,RXD,?..."
endif
sif !cpuis("LPC11U??/?01")&&!cpuis("LPC11U36FBD48")
group.long 0x9C++0x03
line.long 0x00 "PIO1_15,I/O Configuration For Pin PIO1_15/DCD/CT16B0_MAT2/SCK1"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_15,DCD,CT16B0_MAT2,SCK1,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0xA0++0x03
line.long 0x00 "PIO1_16,I/O Configuration For Pin PIO1_16/RI/CT16B0_CAP0"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_16,RI,CT16B0_CAP0,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0xA4++0x07
line.long 0x00 "PIO1_17,I/O Configuration For Pin PIO1_17/CT16B0_CAP1/RXD"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_17,CT16B0_CAP1,RXD,?..."
line.long 0x04 "PIO1_18,I/O Configuration For Pin PIO1_18/CT16B1_CAP1/TXD"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_18,CT16B1_CAP1,TXD,?..."
endif
sif !cpuis("LPC11U??/?01")&&!cpuis("LPC11U36FBD48")
group.long 0xAC++0x03
line.long 0x00 "PIO1_19,I/O Configuration For Pin PIO1_19/DTR/SSEL1"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_19,DTR,SSEL1,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0xB0++0x27
line.long 0x00 "PIO1_20,I/O Configuration For Pin PIO1_20/DSR/SCK1"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_20,DSR,SCK1,?..."
line.long 0x04 "PIO1_21,I/O Configuration For Pin PIO1_21/DCD/MISO1"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_21,DCD,MISO1,?..."
line.long 0x08 "PIO1_22,I/O Configuration For Pin PIO1_22/RI/MOSI1"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_22,RI,MOSI1,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E1*")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0xBC++0x07
line.long 0x00 "PIO1_23,I/O Configuration For Pin PIO1_23/CT16B1_MAT1/SSEL1"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_23,CT16B1_MAT1,SSEL1,?..."
line.long 0x04 "PIO1_24,I/O Configuration For Pin PIO1_24/CT32B0_MAT0"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_24,CT32B0_MAT0,?..."
endif
sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*")
group.long 0xC4++0x13
line.long 0x00 "PIO1_25,I/O Configuration For Pin PIO1_25/CT32B0_MAT1"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_25,CT32B0_MAT1,?..."
line.long 0x04 "PIO1_26,I/O Configuration For Pin PIO1_26/CT32B0_MAT2/RXD/IOH_19"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_26,CT32B0_MAT2,RXD,IOH_19,?..."
line.long 0x08 "PIO1_27,I/O Configuration For Pin PIO1_27/CT32B0_MAT3/TXD/IOH_20"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_27,CT32B0_MAT3,TXD,IOH_20,?..."
line.long 0x0C "PIO1_28,I/O Configuration For Pin PIO1_28/CT32B0_CAP0/SCLK"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_28,CT32B0_CAP0,SCLK,?..."
line.long 0x10 "PIO1_29,I/O Configuration For Pin PIO1_29/SCK0/CT32B0_CAP1"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
bitfld.long 0x10 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_29,SCK0,CT32B0_CAP1,?..."
endif
sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")
group.long 0xDC++0x03
line.long 0x00 "PIO1_31,I/O Configuration For Pin PIO1_31"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_31,?..."
endif
width 0x0B
elif cpuis("LPC11E6*")
width 15.
group.long 0x00++0x03
line.long 0x00 "RESET_PIO0_0,I/O Configuration For Pin RESET/PIO0_0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "RESET,PIO0_0,?..."
group.long 0x04++0x0B
line.long 0x00 "PIO0_1,I/O Configuration For Pin PIO0_1/CLKOUT/CT23B0_MAT2/USB_FTOGGLE"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_1,CLKOUT,CT23B0_MAT2,USB_FTOGGLE,?..."
line.long 0x04 "PIO0_2,I/O Configuration For Pin PIO0_2/SSP0_SSEL/CT16B0_CAP0/R_0"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_2,SSP0_SSEL,CT16B0_CAP0,R_0,?..."
line.long 0x08 "PIO0_3,I/O Configuration For Pin PIO0_3/USB_VBUS/R_1"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_3,USB_VBUS,R_1,?..."
group.long 0x10++0x07
line.long 0x00 "PIO0_4,I/O Configuration For Pin PIO0_4/I2C0_SCL/R_2"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..."
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C0_SCL,R_2,?..."
line.long 0x04 "PIO0_5,I/O Configuration For Pin PIO0_5/I2C0_SDA/R_3"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..."
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C0_SDA,R_3,?..."
group.long 0x18++0x13
line.long 0x00 "PIO0_6,I/O Configuration For Pin PIO0_6/R/SSP0_SCK/R_4"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_6,R,SSP0_SCK,R_4,?..."
line.long 0x04 "PIO0_7,I/O Configuration For Pin PIO0_7/U0_nCTS/R_5/I2C1_SCL"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_7,U0_nCTS,R_5,I2C1_SCL,?..."
line.long 0x08 "PIO0_8,I/O Configuration For Pin PIO0_8/SSP0_MISO/CT16B0_MAT0/R/R_6"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_8,SSP0_MISO,CT16B0_MAT0,R,R_6,?..."
line.long 0x0C "PIO0_9,I/O Configuration For Pin PIO0_9/SSP0_MOSI/CT16B0_MAT1/R_7"
bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_9,SSP0_MOSI,CT16B0_MAT1,R_7,?..."
line.long 0x10 "PIO0_10,I/O Configuration For Pin SWCLK/PIO0_10/SSP0_SCK/CT16B0_MAT2"
bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "SWCLK,PIO0_10,SSP0_SCK,CT16B0_MAT2,?..."
group.long 0x2C++0x17
line.long 0x00 "TDI_PIO0_11,I/O Configuration For Pin TDI/PIO0_11/ADC_9/CT32B0_MAT3/U1_nRTS/U1_SCLK"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "TDI,PIO0_11,ADC_9,CT32B0_MAT3,U1_nRTS,U1_SCLK,?..."
line.long 0x04 "TMS_PIO0_12,I/O Configuration For Pin TMS/PIO0_12/ADC_8/CT32B1_CAP0/U1_CTS/PIO0_12"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x04 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "TMS,PIO0_12,ADC_8,CT32B1_CAP0,U1_CTS,PIO0_12,?..."
line.long 0x08 "TDO_PIO0_13,I/O Configuration For Pin TDO/PIO0_13/ADC_7/CT32B1_MAT0/U1_RXD/PIO0_13"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x08 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "TDO,PIO0_13,ADC_7,CT32B1_MAT0,U1_RXD,PIO0_13,?..."
line.long 0x0C "TRST_PIO0_14,I/O Configuration For Pin nTRST/PIO0_14/ADC_6/CT32B1_MAT1/U1_TXD"
bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x0C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "nTRST,PIO0_14,ADC_6,CT32B1_MAT1,U1_TXD,?..."
line.long 0x10 "SWDIO_PIO0_15,I/O Configuration For Pin SWDIO/PIO0_15/ADC_3/CT32B1_MAT2"
bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x10 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "SWDIO,PIO0_15,ADC_3,CT32B1_MAT2,?..."
line.long 0x14 "PIO0_16,I/O Configuration For Pin PIO0_16/ADC_2/CT32B1_MAT3/R_8"
bitfld.long 0x14 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x14 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x14 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x14 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x14 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO0_16,ADC_2,CT32B1_MAT3,R_8,?..."
group.long 0x44++0x13
line.long 0x00 "PIO0_17,I/O Configuration For Pin PIO0_17/U0_nRTS/CT32B0_CAP0/U0_SCLK"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_17,U0_nRTS,CT32B0_CAP0,U0_SCLK,?..."
line.long 0x04 "PIO0_18,I/O Configuration For Pin PIO0_18/U0_RXD/CT32B0_MAT0"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_18,U0_RXD,CT32B0_MAT0,?..."
line.long 0x08 "PIO0_19,I/O Configuration For Pin PIO0_19/U0_TXD/CT32B0_MAT1"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_19,U0_TXD,CT32B0_MAT1,?..."
line.long 0x0C "PIO0_20,I/O Configuration For Pin PIO0_20/CT16B1_CAP0/U2_RXD"
bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_20,CT16B1_CAP0,U2_RXD,?..."
line.long 0x10 "PIO0_21,I/O Configuration For Pin PIO0_21/CT16B1_MAT0/SSP1_MOSI"
bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_21,CT16B1_MAT0,SSP1_MOSI,?..."
group.long 0x58++0x07
line.long 0x00 "PIO0_22,I/O Configuration For Pin PIO0_22/ADC_11/CT16B1_CAP1/SSP1_MISO"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_22,ADC_11,CT16B1_CAP1,SSP1_MISO,?..."
line.long 0x04 "PIO0_23,I/O Configuration For Pin PIO0_23/ADC_1/R_9/U0_nRI/SSP1_SSEL"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x04 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_23,ADC_1,R_9,U0_nRI,SSP1_SSEL,?..."
sif cpuis("LPC11E*")
group.long 0x60++0x03
line.long 0x00 "PIO1_0,I/O Configuration For Pin PIO1_0/CT32B1_MAT0/R_10/U2_TXD"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_0,CT32B1_MAT0,R_10,U2_TXD,?..."
endif
sif cpuis("LPC11E6?JBD48")||cpuis("LPC11E6?JBD100")
group.long 0x64++0x07
line.long 0x00 "PIO1_1,I/O Configuration For Pin PIO1_1/CT32B1_MAT1/R_11/U0_nDTR"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_1,CT32B1_MAT1,R_11,U0_nDTR,?..."
line.long 0x04 "PIO1_2,I/O Configuration For Pin PIO1_2/CT32B1_MAT2/R_12/U1_RXD"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_2,CT32B1_MAT2,R_12,U1_RXD,?..."
endif
sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E*")
group.long 0x60++0x03
line.long 0x00 "PIO1_0,I/O Configuration For Pin PIO1_0/CT32B1_MAT0/R_10/U2_TXD"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_0,CT32B1_MAT0,R_10,U2_TXD,?..."
endif
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD48")||cpuis("LPC11E6?JBD100")
sif !cpuis("LPC11E*")
group.long 0x64++0x07
line.long 0x00 "PIO1_1,I/O Configuration For Pin PIO1_1/CT32B1_MAT1/R_11/U0_nDTR"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_1,CT32B1_MAT1,R_11,U0_nDTR,?..."
line.long 0x04 "PIO1_2,I/O Configuration For Pin PIO1_2/CT32B1_MAT2/R_12/U1_RXD"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_2,CT32B1_MAT2,R_12,U1_RXD,?..."
endif
group.long 0x6C++0x07
line.long 0x00 "PIO1_3,I/O Configuration For Pin PIO1_3/CT32B1_MAT3/R_13/I2C1_SDA/ADC_5"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_3,CT32B1_MAT3,R_13,I2C1_SDA,ADC_5,?..."
line.long 0x04 "PIO1_4,I/O Configuration For Pin PIO1_4/CT32B1_CAP0/R_14/U0_nDSR"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x04 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_4,CT32B1_CAP0,R_14,U0_nDSR,?..."
group.long 0x74++0x07
line.long 0x00 "PIO1_5,I/O Configuration For Pin PIO1_5/CT32B1_CAP1/R_15/U0_nDCD"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_5,CT32B1_CAP1,R_15,U0_nDCD,?..."
line.long 0x04 "PIO1_6,I/O Configuration For Pin PIO1_6/R_16/U2_RXD/CT32B0_CAP2"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_6,R_16,U2_RXD,CT32B0_CAP2,?..."
endif
sif !cpuis("LPC11U6?JBD48")
group.long 0x7C++0x03
line.long 0x00 "PIO1_7,I/O Configuration For Pin PIO1_7/R_17/U2_nCTS/CT16B1_CAP0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_7,R_17,U2_nCTS,CT16B1_CAP0,?..."
endif
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD48")||cpuis("LPC11E6?JBD100")
group.long 0x80++0x03
line.long 0x00 "PIO1_8,I/O Configuration For Pin PIO1_8/R_18/U1_TXD/CT16B0_CAP0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_8,R_18,U1_TXD,CT16B0_CAP0,?..."
endif
sif !cpuis("LPC11U6?JBD48")
group.long 0x84++0x07
line.long 0x00 "PIO1_9,I/O Configuration For Pin PIO1_9/U0_nCTS/CT16B1_MAT1/ADC_0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_9,U0_nCTS,CT16B1_MAT1,ADC_0,?..."
line.long 0x04 "PIO1_10,I/O Configuration For Pin PIO1_10/U2_nRTS/U2_SCLK/CT16B1_MAT0"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_10,U2_nRTS,U2_SCLK,CT16B1_MAT0,?..."
sif !cpuis("LPC11U6?JBD64")&&!cpuis("LPC11E6?JBD48")&&!cpuis("LPC11E6?JBD100")&&!cpuis("LPC11E6?JBD64")
group.long 0x8C++0x07
line.long 0x00 "PIO1_11,I/O Configuration For Pin PIO1_11/I2C1_SCL/CT16B0_MAT2/U0_nRI"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_11,I2C1_SCL,CT16B0_MAT2,U0_nRI,?..."
line.long 0x04 "PIO1_12,I/O Configuration For Pin PIO1_12/SSP0_MOSI/CT16B0_MAT1/R_21"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_12,SSP0_MOSI,CT16B0_MAT1,R_21,?..."
endif
endif
group.long 0x94++0x03
line.long 0x00 "PIO1_13,I/O Configuration For Pin PIO1_13/U1_nCTS/SCT0_OUT3/R_22"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_13,U1_nCTS,SCT0_OUT3,R_22,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0x98++0x13
line.long 0x00 "PIO1_14,I/O Configuration For Pin PIO1_14/I2C1_SDA/CT32B1_MAT2/R_23"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_14,I2C1_SDA,CT32B1_MAT2,R_23,?..."
line.long 0x04 "PIO1_15,I/O Configuration For Pin PIO1_15/SSP0_SSEL/CT32B1_MAT3/R_24"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_15,SSP0_SSEL,CT32B1_MAT3,R_24,?..."
line.long 0x08 "PIO1_16,I/O Configuration For Pin PIO1_16/SSP0_MISO/CT16B0_MAT0/R_25"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_16,SSP0_MISO,CT16B0_MAT0,R_25,?..."
line.long 0x0C "PIO1_17,I/O Configuration For Pin PIO1_17/CT16B0_CAP2/U0_RXD/R_26"
bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_17,CT16B0_CAP2,U0_RXD,R_26,?..."
line.long 0x10 "PIO1_18,I/O Configuration For Pin PIO1_18/CT16B1_CAP1/U0_TXD/R_27"
bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_18,CT16B1_CAP1,U0_TXD,R_27,?..."
endif
sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48")
group.long 0xAC++0x03
line.long 0x00 "PIO1_19,I/O Configuration For Pin PIO1_19/U2_nCTS/SCT0_OUT0/R_28"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_19,U2_nCTS,SCT0_OUT0,R_28,?..."
endif
group.long 0xB0++0x03
line.long 0x00 "PIO1_20,I/O Configuration For Pin PIO1_20/U0_nDSR/SSP1_SCK/CT16B0_MAT0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_20,U0_nDSR,SSP1_SCK,CT16B0_MAT0,?..."
group.long 0xB4++0x03
line.long 0x00 "PIO1_21,I/O Configuration For Pin PIO1_21/U0_nDCD/SSP1_MISO/CT16B0_CAP2"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_21,U0_nDCD,SSP1_MISO,CT16B0_CAP2,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0xB8++0x03
line.long 0x00 "PIO1_22,I/O Configuration For Pin PIO1_22/SSP1_MOSI/CT32B1_CAP1/ADC_4/R_29"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_22,SSP1_MOSI,CT32B1_CAP1,ADC_4,R_29,?..."
endif
group.long 0xBC++0x07
line.long 0x00 "PIO1_23,I/O Configuration For Pin PIO1_23/CT16B1_MAT1/SSP1_SSEL/U2_TXD"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_23,CT16B1_MAT1,SSP1_SSEL,U2_TXD,?..."
line.long 0x04 "PIO1_24,I/O Configuration For Pin PIO1_24/CT32B0_MAT0/I2C1_SDA"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_24,CT32B0_MAT0,I2C1_SDA,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0xC4++0x03
line.long 0x00 "PIO1_25,I/O Configuration For Pin PIO1_25/U2_nRTS/U2_SCLK/SCT0_IN0/R_30"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_25,U2_nRTS,U2_SCLK,SCT0_IN0,R_30,?..."
endif
sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48")
group.long 0xC8++0x03
line.long 0x00 "PIO1_26,I/O Configuration For Pin PIO1_26/CT32B0_MAT2/U0_RXD/R_19"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_26,CT32B0_MAT2,U0_RXD,R_19,?..."
endif
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")||cpuis("LPC11U6?JBD64")
group.long 0xCC++0x0B
line.long 0x00 "PIO1_27,I/O Configuration For Pin PIO1_27/CT32B0_MAT3/U0_TXD/R_20/SSP1_SCK"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_27,CT32B0_MAT3,U0_TXD,R_20,SSP1_SCK,?..."
line.long 0x04 "PIO1_28,I/O Configuration For Pin PIO1_28/CT32B0_CAP0/U0_SCLK/U0_nRTS"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_28,CT32B0_CAP0,U0_SCLK,U0_nRTS,?..."
line.long 0x08 "PIO1_29,I/O Configuration For Pin PIO1_29/SSP0_SCK/CT32B0_CAP2/U0_nDTR/ADC_10"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x08 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_29,SSP0_SCK,CT32B0_CAP2,U0_nDTR,ADC_10,?..."
endif
sif !cpuis("LPC11U6?JBD48")&&cpuis("LPC11E6?JBD48")
group.long 0xD8++0x03
line.long 0x00 "PIO1_30,I/O Configuration For Pin PIO1_30/I2C1_SCL/SCT0_IN3/R_31"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_30,I2C1_SCL,SCT0_IN3,R_31,?..."
endif
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0xDC++0x03
line.long 0x00 "PIO1_31,I/O Configuration For Pin PIO1_31"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_31,?..."
endif
group.long 0xF0++0x07
line.long 0x00 "PIO2_0,I/O Configuration For Pin PIO2_0/XTALIN"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_0,XTALIN,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E*")||cpuis("LPC11U6?JBD64")||cpuis("LPC11U6?JBD48")
group.long 0xF4++0x03
line.long 0x00 "PIO2_1,I/O Configuration For Pin PIO2_1/XTALOUT"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled"
newline
bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
newline
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_1,XTALOUT,?..."
endif
group.long 0xFC++0x03
line.long 0x00 "PIO2_2,I/O Configuration For Pin PIO2_2/U3_nRTS/U3_SCLK/SCT0_OUT1"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_2,U3_nRTS,U3_SCLK,SCT0_OUT1,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E*")
group.long 0x100++0x07
line.long 0x00 "PIO2_3,I/O Configuration For Pin PIO2_3/U3_RXD/CT32B0_MAT1"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_3,U3_RXD,CT32B0_MAT1,?..."
line.long 0x04 "PIO2_4,I/O Configuration For Pin PIO2_4/U3_TXD/CT32B0_MAT2"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_4,U3_TXD,CT32B0_MAT2,?..."
endif
group.long 0x108++0x03
line.long 0x00 "PIO2_5,I/O Configuration For Pin PIO2_5/U3_nCTS/SCT0_IN1"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_5,U3_nCTS,SCT0_IN1,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")||cpuis("LPC11U6?JBD64")
group.long 0x10C++0x03
line.long 0x00 "PIO2_6,I/O Configuration For Pin PIO2_6/U1_nRTS/U1_SCLK/SCT0_IN2"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_6,U1_nRTS,U1_SCLK,SCT0_IN2,?..."
endif
group.long 0x110++0x03
line.long 0x00 "PIO2_7,I/O Configuration For Pin PIO2_7/SSP0_SCK/SCT0_OUT2"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_7,SSP0_SCK,SCT0_OUT2,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0x114++0x1B
line.long 0x00 "PIO2_8,I/O Configuration For Pin PIO2_8/SCT1_IN0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_8,SCT1_IN0,?..."
line.long 0x04 "PIO2_9,I/O Configuration For Pin PIO2_9/SCT1_IN1"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_9,SCT1_IN1,?..."
line.long 0x08 "PIO2_10,I/O Configuration For Pin PIO2_10/U4_nRTS/U4_SCLK"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_10,U4_nRTS,U4_SCLK,?..."
line.long 0x0C "PIO2_11,I/O Configuration For Pin PIO2_11/U4_RXD"
bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_11,U4_RXD,?..."
line.long 0x10 "PIO2_12,I/O Configuration For Pin PIO2_12/U4_TXD"
bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO2_12,U4_TXD,?..."
line.long 0x14 "PIO2_13,I/O Configuration For Pin PIO2_13/U4_nCTS"
bitfld.long 0x14 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x14 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x14 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO2_13,U4_nCTS,?..."
line.long 0x18 "PIO2_14,I/O Configuration For Pin PIO2_14/SCT1_IN2"
bitfld.long 0x18 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x18 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x18 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO2_14,SCT1_IN2,?..."
endif
sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48")
group.long 0x130++0x03
line.long 0x00 "PIO2_15,I/O Configuration For Pin PIO2_15/SCT1_IN3"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_15,SCT1_IN3,?..."
endif
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0x134++0x07
line.long 0x00 "PIO2_16,I/O Configuration For Pin PIO2_16/SCT1_OUT0"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_16,SCT1_OUT0,?..."
line.long 0x04 "PIO2_17,I/O Configuration For Pin PIO2_17/SCT1_OUT1"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_17,SCT1_OUT1,?..."
endif
sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48")
group.long 0x13C++0x07
line.long 0x00 "PIO2_18,I/O Configuration For Pin PIO2_18/SCT1_OUT2"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_18,SCT1_OUT2,?..."
line.long 0x04 "PIO2_19,I/O Configuration For Pin PIO2_19/SCT1_OUT3"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_19,SCT1_OUT3,?..."
endif
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
group.long 0x144++0x0F
line.long 0x00 "PIO2_20,I/O Configuration For Pin PIO2_20"
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_20,?..."
line.long 0x04 "PIO2_21,I/O Configuration For Pin PIO2_21"
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_21,?..."
line.long 0x08 "PIO2_22,I/O Configuration For Pin PIO2_22"
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_22,?..."
line.long 0x0C "PIO2_23,I/O Configuration For Pin PIO2_23"
bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..."
bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles"
bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled"
bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted"
newline
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_23,?..."
endif
width 0x0B
endif
tree.end
tree "GPIO_PORT (General-Purpose I/O)"
sif cpuis("LPC11E6*")
base ad:0xA0000000
width 8.
tree "Byte Pin Registers"
group.byte 0x0++0x00
line.byte 0x00 "B0,Byte Pin Register Port 0 Pin P0_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_0" "Low,High"
group.byte 0x1++0x00
line.byte 0x00 "B1,Byte Pin Register Port 0 Pin P0_1"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_1" "Low,High"
group.byte 0x2++0x00
line.byte 0x00 "B2,Byte Pin Register Port 0 Pin P0_2"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_2" "Low,High"
group.byte 0x3++0x00
line.byte 0x00 "B3,Byte Pin Register Port 0 Pin P0_3"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_3" "Low,High"
group.byte 0x4++0x00
line.byte 0x00 "B4,Byte Pin Register Port 0 Pin P0_4"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_4" "Low,High"
group.byte 0x5++0x00
line.byte 0x00 "B5,Byte Pin Register Port 0 Pin P0_5"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_5" "Low,High"
group.byte 0x6++0x00
line.byte 0x00 "B6,Byte Pin Register Port 0 Pin P0_6"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_6" "Low,High"
group.byte 0x7++0x00
line.byte 0x00 "B7,Byte Pin Register Port 0 Pin P0_7"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_7" "Low,High"
group.byte 0x8++0x00
line.byte 0x00 "B8,Byte Pin Register Port 0 Pin P0_8"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_8" "Low,High"
group.byte 0x9++0x00
line.byte 0x00 "B9,Byte Pin Register Port 0 Pin P0_9"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_9" "Low,High"
group.byte 0xA++0x00
line.byte 0x00 "B10,Byte Pin Register Port 0 Pin P0_10"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_10" "Low,High"
group.byte 0xB++0x00
line.byte 0x00 "B11,Byte Pin Register Port 0 Pin P0_11"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_11" "Low,High"
group.byte 0xC++0x00
line.byte 0x00 "B12,Byte Pin Register Port 0 Pin P0_12"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_12" "Low,High"
group.byte 0xD++0x00
line.byte 0x00 "B13,Byte Pin Register Port 0 Pin P0_13"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_13" "Low,High"
group.byte 0xE++0x00
line.byte 0x00 "B14,Byte Pin Register Port 0 Pin P0_14"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_14" "Low,High"
group.byte 0xF++0x00
line.byte 0x00 "B15,Byte Pin Register Port 0 Pin P0_15"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_15" "Low,High"
group.byte 0x10++0x00
line.byte 0x00 "B16,Byte Pin Register Port 0 Pin P0_16"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_16" "Low,High"
group.byte 0x11++0x00
line.byte 0x00 "B17,Byte Pin Register Port 0 Pin P0_17"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_17" "Low,High"
group.byte 0x12++0x00
line.byte 0x00 "B18,Byte Pin Register Port 0 Pin P0_18"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_18" "Low,High"
group.byte 0x13++0x00
line.byte 0x00 "B19,Byte Pin Register Port 0 Pin P0_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_19" "Low,High"
group.byte 0x14++0x00
line.byte 0x00 "B20,Byte Pin Register Port 0 Pin P0_20"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_20" "Low,High"
group.byte 0x15++0x00
line.byte 0x00 "B21,Byte Pin Register Port 0 Pin P0_21"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_21" "Low,High"
group.byte 0x16++0x00
line.byte 0x00 "B22,Byte Pin Register Port 0 Pin P0_22"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_22" "Low,High"
group.byte 0x17++0x00
line.byte 0x00 "B23,Byte Pin Register Port 0 Pin P0_23"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_23" "Low,High"
sif cpuis("LPC11E6?JBD100")
group.byte 0x20++0x00
line.byte 0x00 "B32,Byte Pin Register Port 1 Pin P1_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_0" "Low,High"
group.byte 0x21++0x00
line.byte 0x00 "B33,Byte Pin Register Port 1 Pin P1_1"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_1" "Low,High"
group.byte 0x22++0x00
line.byte 0x00 "B34,Byte Pin Register Port 1 Pin P1_2"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_2" "Low,High"
group.byte 0x23++0x00
line.byte 0x00 "B35,Byte Pin Register Port 1 Pin P1_3"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_3" "Low,High"
group.byte 0x24++0x00
line.byte 0x00 "B36,Byte Pin Register Port 1 Pin P1_4"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_4" "Low,High"
group.byte 0x25++0x00
line.byte 0x00 "B37,Byte Pin Register Port 1 Pin P1_5"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_5" "Low,High"
group.byte 0x26++0x00
line.byte 0x00 "B38,Byte Pin Register Port 1 Pin P1_6"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_6" "Low,High"
group.byte 0x27++0x00
line.byte 0x00 "B39,Byte Pin Register Port 1 Pin P1_7"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_7" "Low,High"
group.byte 0x28++0x00
line.byte 0x00 "B40,Byte Pin Register Port 1 Pin P1_8"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_8" "Low,High"
group.byte 0x29++0x00
line.byte 0x00 "B41,Byte Pin Register Port 1 Pin P1_9"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_9" "Low,High"
group.byte 0x2A++0x00
line.byte 0x00 "B42,Byte Pin Register Port 1 Pin P1_10"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_10" "Low,High"
group.byte 0x2B++0x00
line.byte 0x00 "B43,Byte Pin Register Port 1 Pin P1_11"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_11" "Low,High"
group.byte 0x2C++0x00
line.byte 0x00 "B44,Byte Pin Register Port 1 Pin P1_12"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_12" "Low,High"
group.byte 0x2D++0x00
line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_13"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High"
group.byte 0x2E++0x00
line.byte 0x00 "B46,Byte Pin Register Port 1 Pin P1_14"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_14" "Low,High"
group.byte 0x2F++0x00
line.byte 0x00 "B47,Byte Pin Register Port 1 Pin P1_15"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_15" "Low,High"
group.byte 0x30++0x00
line.byte 0x00 "B48,Byte Pin Register Port 1 Pin P1_16"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_16" "Low,High"
group.byte 0x31++0x00
line.byte 0x00 "B49,Byte Pin Register Port 1 Pin P1_17"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_17" "Low,High"
group.byte 0x32++0x00
line.byte 0x00 "B50,Byte Pin Register Port 1 Pin P1_18"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_18" "Low,High"
group.byte 0x33++0x00
line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High"
group.byte 0x34++0x00
line.byte 0x00 "B52,Byte Pin Register Port 1 Pin P1_20"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_20" "Low,High"
group.byte 0x35++0x00
line.byte 0x00 "B53,Byte Pin Register Port 1 Pin P1_21"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_21" "Low,High"
group.byte 0x36++0x00
line.byte 0x00 "B54,Byte Pin Register Port 1 Pin P1_22"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_22" "Low,High"
group.byte 0x37++0x00
line.byte 0x00 "B55,Byte Pin Register Port 1 Pin P1_23"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_23" "Low,High"
group.byte 0x38++0x00
line.byte 0x00 "B56,Byte Pin Register Port 1 Pin P1_24"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_24" "Low,High"
group.byte 0x39++0x00
line.byte 0x00 "B57,Byte Pin Register Port 1 Pin P1_25"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_25" "Low,High"
group.byte 0x3A++0x00
line.byte 0x00 "B58,Byte Pin Register Port 1 Pin P1_26"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_26" "Low,High"
group.byte 0x3B++0x00
line.byte 0x00 "B59,Byte Pin Register Port 1 Pin P1_27"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_27" "Low,High"
group.byte 0x3C++0x00
line.byte 0x00 "B60,Byte Pin Register Port 1 Pin P1_28"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_28" "Low,High"
group.byte 0x3D++0x00
line.byte 0x00 "B61,Byte Pin Register Port 1 Pin P1_29"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_29" "Low,High"
group.byte 0x3E++0x00
line.byte 0x00 "B62,Byte Pin Register Port 1 Pin P1_30"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_30" "Low,High"
group.byte 0x3F++0x00
line.byte 0x00 "B63,Byte Pin Register Port 1 Pin P1_31"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_31" "Low,High"
elif cpuis("LPC11E6?JBD64")
group.byte 0x20++0x00
line.byte 0x00 "B32,Byte Pin Register Port 1 Pin P1_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_0" "Low,High"
group.byte 0x27++0x00
line.byte 0x00 "B39,Byte Pin Register Port 1 Pin P1_7"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_7" "Low,High"
group.byte 0x29++0x01
line.byte 0x00 "B41,Byte Pin Register Port 1 Pin P1_9"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_9" "Low,High"
line.byte 0x01 "B42,Byte Pin Register Port 1 Pin P1_10"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_10" "Low,High"
group.byte 0x2D++0x00
line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_13"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High"
group.byte 0x33++0x02
line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High"
line.byte 0x01 "B52,Byte Pin Register Port 1 Pin P1_20"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_20" "Low,High"
line.byte 0x02 "B53,Byte Pin Register Port 1 Pin P1_21"
bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_21" "Low,High"
group.byte 0x37++0x01
line.byte 0x00 "B55,Byte Pin Register Port 1 Pin P1_23"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_23" "Low,High"
line.byte 0x01 "B56,Byte Pin Register Port 1 Pin P1_24"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_24" "Low,High"
group.byte 0x3A++0x04
line.byte 0x00 "B58,Byte Pin Register Port 1 Pin P1_26"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_26" "Low,High"
line.byte 0x01 "B59,Byte Pin Register Port 1 Pin P1_27"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_27" "Low,High"
line.byte 0x02 "B60,Byte Pin Register Port 1 Pin P1_28"
bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_28" "Low,High"
line.byte 0x03 "B61,Byte Pin Register Port 1 Pin P1_29"
bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_29" "Low,High"
line.byte 0x04 "B62,Byte Pin Register Port 1 Pin P1_30"
bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_30" "Low,High"
elif cpuis("LPC11E6?JBD48")
group.byte 0x2D++0x00
line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_13"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High"
group.byte 0x34++0x01
line.byte 0x00 "B52,Byte Pin Register Port 1 Pin P1_20"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_20" "Low,High"
line.byte 0x01 "B53,Byte Pin Register Port 1 Pin P1_21"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_21" "Low,High"
group.byte 0x37++0x01
line.byte 0x00 "B55,Byte Pin Register Port 1 Pin P1_23"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_23" "Low,High"
line.byte 0x01 "B56,Byte Pin Register Port 1 Pin P1_24"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_24" "Low,High"
endif
sif cpuis("LPC11E6?JBD100")
group.byte 0x40++0x00
line.byte 0x00 "B64,Byte Pin Register Port 2 Pin P2_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_0" "Low,High"
group.byte 0x41++0x00
line.byte 0x00 "B65,Byte Pin Register Port 2 Pin P2_1"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_1" "Low,High"
group.byte 0x42++0x00
line.byte 0x00 "B66,Byte Pin Register Port 2 Pin P2_2"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_2" "Low,High"
group.byte 0x43++0x00
line.byte 0x00 "B67,Byte Pin Register Port 2 Pin P2_3"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_3" "Low,High"
group.byte 0x44++0x00
line.byte 0x00 "B68,Byte Pin Register Port 2 Pin P2_4"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_4" "Low,High"
group.byte 0x45++0x00
line.byte 0x00 "B69,Byte Pin Register Port 2 Pin P2_5"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_5" "Low,High"
group.byte 0x46++0x00
line.byte 0x00 "B70,Byte Pin Register Port 2 Pin P2_6"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_6" "Low,High"
group.byte 0x47++0x00
line.byte 0x00 "B71,Byte Pin Register Port 2 Pin P2_7"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_7" "Low,High"
group.byte 0x48++0x00
line.byte 0x00 "B72,Byte Pin Register Port 2 Pin P2_8"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_8" "Low,High"
group.byte 0x49++0x00
line.byte 0x00 "B73,Byte Pin Register Port 2 Pin P2_9"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_9" "Low,High"
group.byte 0x4A++0x00
line.byte 0x00 "B74,Byte Pin Register Port 2 Pin P2_10"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_10" "Low,High"
group.byte 0x4B++0x00
line.byte 0x00 "B75,Byte Pin Register Port 2 Pin P2_11"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_11" "Low,High"
group.byte 0x4C++0x00
line.byte 0x00 "B76,Byte Pin Register Port 2 Pin P2_12"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_12" "Low,High"
group.byte 0x4D++0x00
line.byte 0x00 "B77,Byte Pin Register Port 2 Pin P2_13"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_13" "Low,High"
group.byte 0x4E++0x00
line.byte 0x00 "B78,Byte Pin Register Port 2 Pin P2_14"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_14" "Low,High"
group.byte 0x4F++0x00
line.byte 0x00 "B79,Byte Pin Register Port 2 Pin P2_15"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_15" "Low,High"
group.byte 0x50++0x00
line.byte 0x00 "B80,Byte Pin Register Port 2 Pin P2_16"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_16" "Low,High"
group.byte 0x51++0x00
line.byte 0x00 "B81,Byte Pin Register Port 2 Pin P2_17"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_17" "Low,High"
group.byte 0x52++0x00
line.byte 0x00 "B82,Byte Pin Register Port 2 Pin P2_18"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_18" "Low,High"
group.byte 0x53++0x00
line.byte 0x00 "B83,Byte Pin Register Port 2 Pin P2_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_19" "Low,High"
group.byte 0x54++0x00
line.byte 0x00 "B84,Byte Pin Register Port 2 Pin P2_20"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_20" "Low,High"
group.byte 0x55++0x00
line.byte 0x00 "B85,Byte Pin Register Port 2 Pin P2_21"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_21" "Low,High"
group.byte 0x56++0x00
line.byte 0x00 "B86,Byte Pin Register Port 2 Pin P2_22"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_22" "Low,High"
group.byte 0x57++0x00
line.byte 0x00 "B87,Byte Pin Register Port 2 Pin P2_23"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_23" "Low,High"
elif cpuis("LPC11E6?JBD64")
group.byte 0x40++0x07
line.byte 0x00 "B64,Byte Pin Register Port 2 Pin P2_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_0" "Low,High"
line.byte 0x01 "B65,Byte Pin Register Port 2 Pin P2_1"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_1" "Low,High"
line.byte 0x02 "B66,Byte Pin Register Port 2 Pin P2_2"
bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO2_2" "Low,High"
line.byte 0x03 "B67,Byte Pin Register Port 2 Pin P2_3"
bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO2_3" "Low,High"
line.byte 0x04 "B68,Byte Pin Register Port 2 Pin P2_4"
bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO2_4" "Low,High"
line.byte 0x05 "B69,Byte Pin Register Port 2 Pin P2_5"
bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO2_5" "Low,High"
line.byte 0x06 "B70,Byte Pin Register Port 2 Pin P2_6"
bitfld.byte 0x06 0. " PBYTE ,State of the pin PIO2_6" "Low,High"
line.byte 0x07 "B71,Byte Pin Register Port 2 Pin P2_7"
bitfld.byte 0x07 0. " PBYTE ,State of the pin PIO2_7" "Low,High"
group.byte 0x4F++0x00
line.byte 0x00 "B79,Byte Pin Register Port 2 Pin P2_15"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_15" "Low,High"
group.byte 0x52++0x01
line.byte 0x00 "B82,Byte Pin Register Port 2 Pin P2_18"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_18" "Low,High"
line.byte 0x01 "B83,Byte Pin Register Port 2 Pin P2_19"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_19" "Low,High"
elif cpuis("LPC11E6?JBD48")
group.byte 0x40++0x07
line.byte 0x00 "B64,Byte Pin Register Port 2 Pin P2_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_0" "Low,High"
line.byte 0x01 "B65,Byte Pin Register Port 2 Pin P2_1"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_1" "Low,High"
line.byte 0x02 "B66,Byte Pin Register Port 2 Pin P2_2"
bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO2_2" "Low,High"
line.byte 0x03 "B67,Byte Pin Register Port 2 Pin P2_3"
bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO2_3" "Low,High"
line.byte 0x04 "B68,Byte Pin Register Port 2 Pin P2_4"
bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO2_4" "Low,High"
line.byte 0x05 "B69,Byte Pin Register Port 2 Pin P2_5"
bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO2_5" "Low,High"
group.byte 0x47++0x00
line.byte 0x00 "B71,Byte Pin Register Port 2 Pin P2_7"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_7" "Low,High"
endif
tree.end
tree "Word Pin Registers"
group.long 0x1000++0x03
line.long 0x00 "W0,Word Pin Register Port 0 Pin P0_0"
group.long 0x1004++0x03
line.long 0x00 "W1,Word Pin Register Port 0 Pin P0_1"
group.long 0x1008++0x03
line.long 0x00 "W2,Word Pin Register Port 0 Pin P0_2"
group.long 0x100C++0x03
line.long 0x00 "W3,Word Pin Register Port 0 Pin P0_3"
group.long 0x1010++0x03
line.long 0x00 "W4,Word Pin Register Port 0 Pin P0_4"
group.long 0x1014++0x03
line.long 0x00 "W5,Word Pin Register Port 0 Pin P0_5"
group.long 0x1018++0x03
line.long 0x00 "W6,Word Pin Register Port 0 Pin P0_6"
group.long 0x101C++0x03
line.long 0x00 "W7,Word Pin Register Port 0 Pin P0_7"
group.long 0x1020++0x03
line.long 0x00 "W8,Word Pin Register Port 0 Pin P0_8"
group.long 0x1024++0x03
line.long 0x00 "W9,Word Pin Register Port 0 Pin P0_9"
group.long 0x1028++0x03
line.long 0x00 "W10,Word Pin Register Port 0 Pin P0_10"
group.long 0x102C++0x03
line.long 0x00 "W11,Word Pin Register Port 0 Pin P0_11"
group.long 0x1030++0x03
line.long 0x00 "W12,Word Pin Register Port 0 Pin P0_12"
group.long 0x1034++0x03
line.long 0x00 "W13,Word Pin Register Port 0 Pin P0_13"
group.long 0x1038++0x03
line.long 0x00 "W14,Word Pin Register Port 0 Pin P0_14"
group.long 0x103C++0x03
line.long 0x00 "W15,Word Pin Register Port 0 Pin P0_15"
group.long 0x1040++0x03
line.long 0x00 "W16,Word Pin Register Port 0 Pin P0_16"
group.long 0x1044++0x03
line.long 0x00 "W17,Word Pin Register Port 0 Pin P0_17"
group.long 0x1048++0x03
line.long 0x00 "W18,Word Pin Register Port 0 Pin P0_18"
group.long 0x104C++0x03
line.long 0x00 "W19,Word Pin Register Port 0 Pin P0_19"
group.long 0x1050++0x03
line.long 0x00 "W20,Word Pin Register Port 0 Pin P0_20"
group.long 0x1054++0x03
line.long 0x00 "W21,Word Pin Register Port 0 Pin P0_21"
group.long 0x1058++0x03
line.long 0x00 "W22,Word Pin Register Port 0 Pin P0_22"
group.long 0x105C++0x03
line.long 0x00 "W23,Word Pin Register Port 0 Pin P0_23"
sif cpuis("LPC11E6?JBD100")
group.long 0x1080++0x03
line.long 0x00 "W32,Word Pin Register Port 1 Pin P1_0"
group.long 0x1084++0x03
line.long 0x00 "W33,Word Pin Register Port 1 Pin P1_1"
group.long 0x1088++0x03
line.long 0x00 "W34,Word Pin Register Port 1 Pin P1_2"
group.long 0x108C++0x03
line.long 0x00 "W35,Word Pin Register Port 1 Pin P1_3"
group.long 0x1090++0x03
line.long 0x00 "W36,Word Pin Register Port 1 Pin P1_4"
group.long 0x1094++0x03
line.long 0x00 "W37,Word Pin Register Port 1 Pin P1_5"
group.long 0x1098++0x03
line.long 0x00 "W38,Word Pin Register Port 1 Pin P1_6"
group.long 0x109C++0x03
line.long 0x00 "W39,Word Pin Register Port 1 Pin P1_7"
group.long 0x10A0++0x03
line.long 0x00 "W40,Word Pin Register Port 1 Pin P1_8"
group.long 0x10A4++0x03
line.long 0x00 "W41,Word Pin Register Port 1 Pin P1_9"
group.long 0x10A8++0x03
line.long 0x00 "W42,Word Pin Register Port 1 Pin P1_10"
group.long 0x10AC++0x03
line.long 0x00 "W43,Word Pin Register Port 1 Pin P1_11"
group.long 0x10B0++0x03
line.long 0x00 "W44,Word Pin Register Port 1 Pin P1_12"
group.long 0x10B4++0x03
line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_13"
group.long 0x10B8++0x03
line.long 0x00 "W46,Word Pin Register Port 1 Pin P1_14"
group.long 0x10BC++0x03
line.long 0x00 "W47,Word Pin Register Port 1 Pin P1_15"
group.long 0x10C0++0x03
line.long 0x00 "W48,Word Pin Register Port 1 Pin P1_16"
group.long 0x10C4++0x03
line.long 0x00 "W49,Word Pin Register Port 1 Pin P1_17"
group.long 0x10C8++0x03
line.long 0x00 "W50,Word Pin Register Port 1 Pin P1_18"
group.long 0x10CC++0x03
line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19"
group.long 0x10D0++0x03
line.long 0x00 "W52,Word Pin Register Port 1 Pin P1_20"
group.long 0x10D4++0x03
line.long 0x00 "W53,Word Pin Register Port 1 Pin P1_21"
group.long 0x10D8++0x03
line.long 0x00 "W54,Word Pin Register Port 1 Pin P1_22"
group.long 0x10DC++0x03
line.long 0x00 "W55,Word Pin Register Port 1 Pin P1_23"
group.long 0x10E0++0x03
line.long 0x00 "W56,Word Pin Register Port 1 Pin P1_24"
group.long 0x10E4++0x03
line.long 0x00 "W57,Word Pin Register Port 1 Pin P1_25"
group.long 0x10E8++0x03
line.long 0x00 "W58,Word Pin Register Port 1 Pin P1_26"
group.long 0x10EC++0x03
line.long 0x00 "W59,Word Pin Register Port 1 Pin P1_27"
group.long 0x10F0++0x03
line.long 0x00 "W60,Word Pin Register Port 1 Pin P1_28"
group.long 0x10F4++0x03
line.long 0x00 "W61,Word Pin Register Port 1 Pin P1_29"
group.long 0x10F8++0x03
line.long 0x00 "W62,Word Pin Register Port 1 Pin P1_30"
group.long 0x10FC++0x03
line.long 0x00 "W63,Word Pin Register Port 1 Pin P1_31"
elif cpuis("LPC11E6?JBD64")
group.long 0x1080++0x03
line.long 0x00 "W32,Word Pin Register Port 1 Pin P1_0"
group.long 0x109C++0x03
line.long 0x00 "W39,Word Pin Register Port 1 Pin P1_7"
group.long 0x10A4++0x07
line.long 0x00 "W41,Word Pin Register Port 1 Pin P1_9"
line.long 0x04 "W42,Word Pin Register Port 1 Pin P1_10"
group.long 0x10B4++0x03
line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_13"
group.long 0x10CC++0x0B
line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19"
line.long 0x04 "W52,Word Pin Register Port 1 Pin P1_20"
line.long 0x08 "W53,Word Pin Register Port 1 Pin P1_21"
group.long 0x10DC++0x07
line.long 0x00 "W55,Word Pin Register Port 1 Pin P1_23"
line.long 0x04 "W56,Word Pin Register Port 1 Pin P1_24"
group.long 0x10E8++0x13
line.long 0x00 "W58,Word Pin Register Port 1 Pin P1_26"
line.long 0x04 "W59,Word Pin Register Port 1 Pin P1_27"
line.long 0x08 "W60,Word Pin Register Port 1 Pin P1_28"
line.long 0x0C "W61,Word Pin Register Port 1 Pin P1_29"
line.long 0x10 "W62,Word Pin Register Port 1 Pin P1_30"
elif cpuis("LPC11E6?JBD48")
group.long 0x10B4++0x03
line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_13"
group.long 0x10D0++0x07
line.long 0x00 "W52,Word Pin Register Port 1 Pin P1_20"
line.long 0x04 "W53,Word Pin Register Port 1 Pin P1_21"
group.long 0x10DC++0x07
line.long 0x00 "W55,Word Pin Register Port 1 Pin P1_23"
line.long 0x04 "W56,Word Pin Register Port 1 Pin P1_24"
endif
sif cpuis("LPC11E6?JBD100")
group.long 0x1100++0x03
line.long 0x00 "W64,Word Pin Register Port 2 Pin P2_0"
group.long 0x1104++0x03
line.long 0x00 "W65,Word Pin Register Port 2 Pin P2_1"
group.long 0x1108++0x03
line.long 0x00 "W66,Word Pin Register Port 2 Pin P2_2"
group.long 0x110C++0x03
line.long 0x00 "W67,Word Pin Register Port 2 Pin P2_3"
group.long 0x1110++0x03
line.long 0x00 "W68,Word Pin Register Port 2 Pin P2_4"
group.long 0x1114++0x03
line.long 0x00 "W69,Word Pin Register Port 2 Pin P2_5"
group.long 0x1118++0x03
line.long 0x00 "W70,Word Pin Register Port 2 Pin P2_6"
group.long 0x111C++0x03
line.long 0x00 "W71,Word Pin Register Port 2 Pin P2_7"
group.long 0x1120++0x03
line.long 0x00 "W72,Word Pin Register Port 2 Pin P2_8"
group.long 0x1124++0x03
line.long 0x00 "W73,Word Pin Register Port 2 Pin P2_9"
group.long 0x1128++0x03
line.long 0x00 "W74,Word Pin Register Port 2 Pin P2_10"
group.long 0x112C++0x03
line.long 0x00 "W75,Word Pin Register Port 2 Pin P2_11"
group.long 0x1130++0x03
line.long 0x00 "W76,Word Pin Register Port 2 Pin P2_12"
group.long 0x1134++0x03
line.long 0x00 "W77,Word Pin Register Port 2 Pin P2_13"
group.long 0x1138++0x03
line.long 0x00 "W78,Word Pin Register Port 2 Pin P2_14"
group.long 0x113C++0x03
line.long 0x00 "W79,Word Pin Register Port 2 Pin P2_15"
group.long 0x1140++0x03
line.long 0x00 "W80,Word Pin Register Port 2 Pin P2_16"
group.long 0x1144++0x03
line.long 0x00 "W81,Word Pin Register Port 2 Pin P2_17"
group.long 0x1148++0x03
line.long 0x00 "W82,Word Pin Register Port 2 Pin P2_18"
group.long 0x114C++0x03
line.long 0x00 "W83,Word Pin Register Port 2 Pin P2_19"
group.long 0x1150++0x03
line.long 0x00 "W84,Word Pin Register Port 2 Pin P2_20"
group.long 0x1154++0x03
line.long 0x00 "W85,Word Pin Register Port 2 Pin P2_21"
group.long 0x1158++0x03
line.long 0x00 "W86,Word Pin Register Port 2 Pin P2_22"
group.long 0x115C++0x03
line.long 0x00 "W87,Word Pin Register Port 2 Pin P2_23"
elif cpuis("LPC11E6?JBD64")
group.long 0x1100++0x1F
line.long 0x00 "W64,Word Pin Register Port 2 Pin P2_0"
line.long 0x04 "W65,Word Pin Register Port 2 Pin P2_1"
line.long 0x08 "W66,Word Pin Register Port 2 Pin P2_2"
line.long 0x0C "W67,Word Pin Register Port 2 Pin P2_3"
line.long 0x10 "W68,Word Pin Register Port 2 Pin P2_4"
line.long 0x14 "W69,Word Pin Register Port 2 Pin P2_5"
line.long 0x18 "W70,Word Pin Register Port 2 Pin P2_6"
line.long 0x1C "W71,Word Pin Register Port 2 Pin P2_7"
group.long 0x113C++0x03
line.long 0x00 "W79,Word Pin Register Port 2 Pin P2_15"
group.long 0x1148++0x07
line.long 0x00 "W82,Word Pin Register Port 2 Pin P2_18"
line.long 0x04 "W83,Word Pin Register Port 2 Pin P2_19"
elif cpuis("LPC11E6?JBD48")
group.long 0x1100++0x17
line.long 0x00 "W64,Word Pin Register Port 2 Pin P2_0"
line.long 0x04 "W65,Word Pin Register Port 2 Pin P2_1"
line.long 0x08 "W66,Word Pin Register Port 2 Pin P2_2"
line.long 0x0C "W67,Word Pin Register Port 2 Pin P2_3"
line.long 0x10 "W68,Word Pin Register Port 2 Pin P2_4"
line.long 0x14 "W69,Word Pin Register Port 2 Pin P2_5"
group.long 0x111C++0x03
line.long 0x00 "W71,Word Pin Register Port 2 Pin P2_7"
endif
newline
tree.end
group.long 0x2000++0x0B
line.long 0x00 "DIR0,Direction Port 0 Register"
bitfld.long 0x00 23. " DIRP[23] ,PIO0_23 pin direction select" "Input,Output"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin direction select" "Input,Output"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin direction select" "Input,Output"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin direction select" "Input,Output"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin direction select" "Input,Output"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 pin direction select" "Input,Output"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin direction select" "Input,Output"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin direction select" "Input,Output"
bitfld.long 0x00 15. " [15] ,PIO0_15 pin direction select" "Input,Output"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin direction select" "Input,Output"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 pin direction select" "Input,Output"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin direction select" "Input,Output"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin direction select" "Input,Output"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin direction select" "Input,Output"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin direction select" "Input,Output"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 pin direction select" "Input,Output"
bitfld.long 0x00 7. " [7] ,PIO0_7 pin direction select" "Input,Output"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin direction select" "Input,Output"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin direction select" "Input,Output"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin direction select" "Input,Output"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 pin direction select" "Input,Output"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin direction select" "Input,Output"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin direction select" "Input,Output"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin direction select" "Input,Output"
line.long 0x04 "DIR1,Direction Port 1 Register"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x04 31. " DIRP[31] ,PIO1_31 pin direction select" "Input,Output"
bitfld.long 0x04 30. " [30] ,PIO1_30 pin direction select" "Input,Output"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin direction select" "Input,Output"
newline
bitfld.long 0x04 26. " [26] ,PIO1_26 pin direction select" "Input,Output"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin direction select" "Input,Output"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin direction select" "Input,Output"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin direction select" "Input,Output"
newline
bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin direction select" "Input,Output"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin direction select" "Input,Output"
newline
bitfld.long 0x04 16. " [16] ,PIO1_16 pin direction select" "Input,Output"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin direction select" "Input,Output"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin direction select" "Input,Output"
newline
bitfld.long 0x04 11. " [11] ,PIO1_11 pin direction select" "Input,Output"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin direction select" "Input,Output"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin direction select" "Input,Output"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin direction select" "Input,Output"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin direction select" "Input,Output"
newline
bitfld.long 0x04 6. " [6] ,PIO1_6 pin direction select" "Input,Output"
bitfld.long 0x04 5. " [5] ,PIO1_5 pin direction select" "Input,Output"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin direction select" "Input,Output"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin direction select" "Input,Output"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin direction select" "Input,Output"
newline
bitfld.long 0x04 1. " [1] ,PIO1_1 pin direction select" "Input,Output"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin direction select" "Input,Output"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " DIRP[30] ,PIO1_30 pin direction select" "Input,Output"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin direction select" "Input,Output"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin direction select" "Input,Output"
newline
bitfld.long 0x04 24. " [24] ,PIO1_24 pin direction select" "Input,Output"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin direction select" "Input,Output"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin direction select" "Input,Output"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin direction select" "Input,Output"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin direction select" "Input,Output"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " DIRP[24] ,PIO1_24 pin direction select" "Input,Output"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output"
endif
line.long 0x08 "DIR2,Direction Port 2 Register"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x08 23. " DIRP[23] ,PIO2_23 pin direction select" "Input,Output"
bitfld.long 0x08 22. " [22] ,PIO2_22 pin direction select" "Input,Output"
bitfld.long 0x08 21. " [21] ,PIO2_21 pin direction select" "Input,Output"
bitfld.long 0x08 20. " [20] ,PIO2_20 pin direction select" "Input,Output"
bitfld.long 0x08 19. " [19] ,PIO2_19 pin direction select" "Input,Output"
newline
bitfld.long 0x08 18. " [18] ,PIO2_18 pin direction select" "Input,Output"
bitfld.long 0x08 17. " [17] ,PIO2_17 pin direction select" "Input,Output"
bitfld.long 0x08 16. " [16] ,PIO2_16 pin direction select" "Input,Output"
bitfld.long 0x08 15. " [15] ,PIO2_15 pin direction select" "Input,Output"
bitfld.long 0x08 14. " [14] ,PIO2_14 pin direction select" "Input,Output"
newline
bitfld.long 0x08 13. " [13] ,PIO2_13 pin direction select" "Input,Output"
bitfld.long 0x08 12. " [12] ,PIO2_12 pin direction select" "Input,Output"
bitfld.long 0x08 11. " [11] ,PIO2_11 pin direction select" "Input,Output"
bitfld.long 0x08 10. " [10] ,PIO2_10 pin direction select" "Input,Output"
bitfld.long 0x08 9. " [9] ,PIO2_9 pin direction select" "Input,Output"
newline
bitfld.long 0x08 8. " [8] ,PIO2_8 pin direction select" "Input,Output"
bitfld.long 0x08 7. " [7] ,PIO2_7 pin direction select" "Input,Output"
bitfld.long 0x08 6. " [6] ,PIO2_6 pin direction select" "Input,Output"
bitfld.long 0x08 5. " [5] ,PIO2_5 pin direction select" "Input,Output"
bitfld.long 0x08 4. " [4] ,PIO2_4 pin direction select" "Input,Output"
newline
bitfld.long 0x08 3. " [3] ,PIO2_3 pin direction select" "Input,Output"
bitfld.long 0x08 2. " [2] ,PIO2_2 pin direction select" "Input,Output"
bitfld.long 0x08 1. " [1] ,PIO2_1 pin direction select" "Input,Output"
bitfld.long 0x08 0. " [0] ,PIO2_0 pin direction select" "Input,Output"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x08 19. " DIRP[19] ,PIO2_19 pin direction select" "Input,Output"
bitfld.long 0x08 18. " [18] ,PIO2_18 pin direction select" "Input,Output"
bitfld.long 0x08 15. " [15] ,PIO2_15 pin direction select" "Input,Output"
bitfld.long 0x08 7. " [7] ,PIO2_7 pin direction select" "Input,Output"
bitfld.long 0x08 6. " [6] ,PIO2_6 pin direction select" "Input,Output"
newline
bitfld.long 0x08 5. " [5] ,PIO2_5 pin direction select" "Input,Output"
bitfld.long 0x08 4. " [4] ,PIO2_4 pin direction select" "Input,Output"
bitfld.long 0x08 3. " [3] ,PIO2_3 pin direction select" "Input,Output"
bitfld.long 0x08 2. " [2] ,PIO2_2 pin direction select" "Input,Output"
bitfld.long 0x08 1. " [1] ,PIO2_1 pin direction select" "Input,Output"
newline
bitfld.long 0x08 0. " [0] ,PIO2_0 pin direction select" "Input,Output"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x08 7. " DIRP[7] ,PIO2_7 pin direction select" "Input,Output"
bitfld.long 0x08 5. " [5] ,PIO2_5 pin direction select" "Input,Output"
bitfld.long 0x08 4. " [4] ,PIO2_4 pin direction select" "Input,Output"
bitfld.long 0x08 3. " [3] ,PIO2_3 pin direction select" "Input,Output"
bitfld.long 0x08 2. " [2] ,PIO2_2 pin direction select" "Input,Output"
newline
bitfld.long 0x08 1. " [1] ,PIO2_1 pin direction select" "Input,Output"
bitfld.long 0x08 0. " [0] ,PIO2_0 pin direction select" "Input,Output"
endif
group.long 0x2080++0x0B
line.long 0x00 "MASK0,Mask Port 0 Register"
bitfld.long 0x00 23. " MASK[23] ,PIO0_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 15. " [15] ,PIO0_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,PIO0_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin mask bit" "Not masked,Masked"
line.long 0x04 "MASK1,Mask Port 1 Register"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x04 31. " MASK[31] ,PIO1_31 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 30. " [30] ,PIO1_30 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 16. " [16] ,PIO1_16 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 11. " [11] ,PIO1_11 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 6. " [6] ,PIO1_6 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 5. " [5] ,PIO1_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 1. " [1] ,PIO1_1 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin mask bit" "Not masked,Masked"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " MASK[30] ,PIO1_30 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin mask bit" "Not masked,Masked"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " MASK[24] ,PIO1_24 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked"
endif
line.long 0x08 "MASK2,Mask Port 2 Register"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x08 23. " MASK[23] ,PIO2_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 22. " [22] ,PIO2_22 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 21. " [21] ,PIO2_21 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 20. " [20] ,PIO2_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 19. " [19] ,PIO2_19 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 18. " [18] ,PIO2_18 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 17. " [17] ,PIO2_17 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 16. " [16] ,PIO2_16 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 15. " [15] ,PIO2_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 14. " [14] ,PIO2_14 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 13. " [13] ,PIO2_13 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 12. " [12] ,PIO2_12 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 11. " [11] ,PIO2_11 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 10. " [10] ,PIO2_10 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 9. " [9] ,PIO2_9 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 8. " [8] ,PIO2_8 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 7. " [7] ,PIO2_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 6. " [6] ,PIO2_6 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 5. " [5] ,PIO2_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 4. " [4] ,PIO2_4 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 3. " [3] ,PIO2_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 2. " [2] ,PIO2_2 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 1. " [1] ,PIO2_1 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 0. " [0] ,PIO2_0 pin mask bit" "Not masked,Masked"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x08 19. " MASK[19] ,PIO2_19 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 18. " [18] ,PIO2_18 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 15. " [15] ,PIO2_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 7. " [7] ,PIO2_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 6. " [6] ,PIO2_6 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 5. " [5] ,PIO2_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 4. " [4] ,PIO2_4 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 3. " [3] ,PIO2_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 2. " [2] ,PIO2_2 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 1. " [1] ,PIO2_1 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 0. " [0] ,PIO2_0 pin mask bit" "Not masked,Masked"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x08 7. " MASK[7] ,PIO2_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 5. " [5] ,PIO2_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 4. " [4] ,PIO2_4 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 3. " [3] ,PIO2_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 2. " [2] ,PIO2_2 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x08 1. " [1] ,PIO2_1 pin mask bit" "Not masked,Masked"
bitfld.long 0x08 0. " [0] ,PIO2_0 pin mask bit" "Not masked,Masked"
endif
group.long 0x2100++0x0B
line.long 0x00 "PIN0,Port Pin Register 0"
bitfld.long 0x00 23. " PORT[23] ,PIO0_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 15. " [15] ,PIO0_15 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 7. " [7] ,PIO0_7 pin state" "Low/Clear,High/Set"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin state read/write" "Low/Clear,High/Set"
line.long 0x04 "PIN1,Port Pin Register 1"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x04 31. " PORT[31] ,PIO1_31 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 30. " [30] ,PIO1_30 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 26. " [26] ,PIO1_26 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 21. " [21] ,PIO1_21 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 16. " [16] ,PIO1_16 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 11. " [11] ,PIO1_11 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 6. " [6] ,PIO1_6 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 5. " [5] ,PIO1_5 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 1. " [1] ,PIO1_1 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " PORT[30] ,PIO1_30 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 24. " [24] ,PIO1_24 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " PORT[24] ,PIO1_24 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin state read/write" "Low/Clear,High/Set"
endif
line.long 0x08 "PIN2,Port Pin Register 2"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x08 23. " PORT[23] ,PIO2_23 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 22. " [22] ,PIO2_22 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 21. " [21] ,PIO2_21 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 20. " [20] ,PIO2_20 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 19. " [19] ,PIO2_19 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 18. " [18] ,PIO2_18 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 17. " [17] ,PIO2_17 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 16. " [16] ,PIO2_16 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 15. " [15] ,PIO2_15 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 14. " [14] ,PIO2_14 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 13. " [13] ,PIO2_13 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 12. " [12] ,PIO2_12 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 11. " [11] ,PIO2_11 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 10. " [10] ,PIO2_10 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 9. " [9] ,PIO2_9 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 8. " [8] ,PIO2_8 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 7. " [7] ,PIO2_7 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 6. " [6] ,PIO2_6 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 5. " [5] ,PIO2_5 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 4. " [4] ,PIO2_4 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 3. " [3] ,PIO2_3 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 2. " [2] ,PIO2_2 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 1. " [1] ,PIO2_1 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 0. " [0] ,PIO2_0 state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x08 19. " PORT[19] ,PIO2_19 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 18. " [18] ,PIO2_18 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 15. " [15] ,PIO2_15 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 7. " [7] ,PIO2_7 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 6. " [6] ,PIO2_6 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 5. " [5] ,PIO2_5 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 4. " [4] ,PIO2_4 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 3. " [3] ,PIO2_3 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 2. " [2] ,PIO2_2 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 1. " [1] ,PIO2_1 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 0. " [0] ,PIO2_0 state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x08 7. " PORT[7] ,PIO2_7 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 5. " [5] ,PIO2_5 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 4. " [4] ,PIO2_4 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 3. " [3] ,PIO2_3 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 2. " [2] ,PIO2_2 state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 1. " [1] ,PIO2_1 state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 0. " [0] ,PIO2_0 state read/write" "Low/Clear,High/Set"
endif
group.long 0x2180++0x0B
line.long 0x00 "MPIN0,Masked Port Register Port 0"
bitfld.long 0x00 23. " MPORTP[23] ,PIO0_23 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 22. " [22] ,PIO0_22 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 21. " [21] ,PIO0_21 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 20. " [20] ,PIO0_20 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 19. " [19] ,PIO0_19 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 17. " [17] ,PIO0_17 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 16. " [16] ,PIO0_16 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 15. " [15] ,PIO0_15 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 14. " [14] ,PIO0_14 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 12. " [12] ,PIO0_12 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 11. " [11] ,PIO0_11 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 10. " [10] ,PIO0_10 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 9. " [9] ,PIO0_9 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 7. " [7] ,PIO0_7 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 6. " [6] ,PIO0_6 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 5. " [5] ,PIO0_5 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 4. " [4] ,PIO0_4 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 2. " [2] ,PIO0_2 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 1. " [1] ,PIO0_1 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 0. " [0] ,PIO0_0 masked pin state read/write" "Low/Clear,High/Set"
line.long 0x04 "MPIN1,Masked Port Register Port 1"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x04 31. " MPORTP[31] ,PIO1_31 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 30. " [30] ,PIO1_30 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 26. " [26] ,PIO1_26 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 21. " [21] ,PIO1_21 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 16. " [16] ,PIO1_16 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 11. " [11] ,PIO1_11 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 6. " [6] ,PIO1_6 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 5. " [5] ,PIO1_5 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 1. " [1] ,PIO1_1 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin masked pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " MPORTP[30] ,PIO1_30 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 24. " [24] ,PIO1_24 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin masked pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " MPORTP[24] ,PIO1_24 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin masked pin state read/write" "Low/Clear,High/Set"
endif
line.long 0x08 "MPIN2,Masked Port Register Port 2"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x08 23. " MPORTP[23] ,PIO2_23 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 22. " [22] ,PIO2_22 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 21. " [21] ,PIO2_21 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 20. " [20] ,PIO2_20 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 19. " [19] ,PIO2_19 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 18. " [18] ,PIO2_18 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 17. " [17] ,PIO2_17 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 16. " [16] ,PIO2_16 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 15. " [15] ,PIO2_15 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 14. " [14] ,PIO2_14 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 13. " [13] ,PIO2_13 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 12. " [12] ,PIO2_12 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 11. " [11] ,PIO2_11 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 10. " [10] ,PIO2_10 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 9. " [9] ,PIO2_9 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 8. " [8] ,PIO2_8 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 7. " [7] ,PIO2_7 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 6. " [6] ,PIO2_6 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 5. " [5] ,PIO2_5 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 4. " [4] ,PIO2_4 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 3. " [3] ,PIO2_3 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 2. " [2] ,PIO2_2 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 1. " [1] ,PIO2_1 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 0. " [0] ,PIO2_0 masked pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x08 19. " MPORTP[19] ,PIO2_19 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 18. " [18] ,PIO2_18 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 15. " [15] ,PIO2_15 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 7. " [7] ,PIO2_7 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 6. " [6] ,PIO2_6 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 5. " [5] ,PIO2_5 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 4. " [4] ,PIO2_4 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 3. " [3] ,PIO2_3 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 2. " [2] ,PIO2_2 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 1. " [1] ,PIO2_1 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 0. " [0] ,PIO2_0 masked pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x08 7. " MPORTP[7] ,PIO2_7 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 5. " [5] ,PIO2_5 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 4. " [4] ,PIO2_4 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 3. " [3] ,PIO2_3 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 2. " [2] ,PIO2_2 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x08 1. " [1] ,PIO2_1 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x08 0. " [0] ,PIO2_0 masked pin state read/write" "Low/Clear,High/Set"
endif
width 9.
group.long 0x2200++0x0B
line.long 0x00 "SETCLR0,Port Set/Clear Register 0"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " P[23] ,PIO0_23 output bit 23" "Not set,Set"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " [22] ,PIO0_22 output bit 22" "Not set,Set"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " [21] ,PIO0_21 output bit 21" "Not set,Set"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " [20] ,PIO0_20 output bit 20" "Not set,Set"
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " [19] ,PIO0_19 output bit 19" "Not set,Set"
newline
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " [18] ,PIO0_18 output bit 18" "Not set,Set"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " [17] ,PIO0_17 output bit 17" "Not set,Set"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " [16] ,PIO0_16 output bit 16" "Not set,Set"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " [15] ,PIO0_15 output bit 15" "Not set,Set"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " [14] ,PIO0_14 output bit 14" "Not set,Set"
newline
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " [13] ,PIO0_13 output bit 13" "Not set,Set"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " [12] ,PIO0_12 output bit 12" "Not set,Set"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " [11] ,PIO0_11 output bit 11" "Not set,Set"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " [10] ,PIO0_10 output bit 10" "Not set,Set"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " [9] ,PIO0_9 output bit 9" "Not set,Set"
newline
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " [8] ,PIO0_8 output bit 8" "Not set,Set"
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " [7] ,PIO0_7 output bit 7" "Not set,Set"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " [6] ,PIO0_6 output bit 6" "Not set,Set"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " [5] ,PIO0_5 output bit 5" "Not set,Set"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " [4] ,PIO0_4 output bit 4" "Not set,Set"
newline
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " [3] ,PIO0_3 output bit 3" "Not set,Set"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " [2] ,PIO0_2 output bit 2" "Not set,Set"
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " [1] ,PIO0_1 output bit 1" "Not set,Set"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " [0] ,PIO0_0 output bit 0" "Not set,Set"
line.long 0x04 "SETCLR1,Port Set/Clear Register 1"
sif cpuis("LPC11E6?JBD100")
setclrfld.long 0x04 31. 0x04 31. 0x80 31. " P[31] ,PIO1_31 output bit 31" "Not set,Set"
setclrfld.long 0x04 30. 0x04 30. 0x80 30. " [30] ,PIO1_30 output bit 30" "Not set,Set"
setclrfld.long 0x04 29. 0x04 29. 0x80 29. " [29] ,PIO1_29 output bit 29" "Not set,Set"
setclrfld.long 0x04 28. 0x04 28. 0x80 28. " [28] ,PIO1_28 output bit 28" "Not set,Set"
setclrfld.long 0x04 27. 0x04 27. 0x80 27. " [27] ,PIO1_27 output bit 27" "Not set,Set"
newline
setclrfld.long 0x04 26. 0x04 26. 0x80 26. " [26] ,PIO1_26 output bit 26" "Not set,Set"
setclrfld.long 0x04 25. 0x04 25. 0x80 25. " [25] ,PIO1_25 output bit 25" "Not set,Set"
setclrfld.long 0x04 24. 0x04 24. 0x80 24. " [24] ,PIO1_24 output bit 24" "Not set,Set"
setclrfld.long 0x04 23. 0x04 23. 0x80 23. " [23] ,PIO1_23 output bit 23" "Not set,Set"
setclrfld.long 0x04 22. 0x04 22. 0x80 22. " [22] ,PIO1_22 output bit 22" "Not set,Set"
newline
setclrfld.long 0x04 21. 0x04 21. 0x80 21. " [21] ,PIO1_21 output bit 21" "Not set,Set"
setclrfld.long 0x04 20. 0x04 20. 0x80 20. " [20] ,PIO1_20 output bit 20" "Not set,Set"
setclrfld.long 0x04 19. 0x04 19. 0x80 19. " [19] ,PIO1_19 output bit 19" "Not set,Set"
setclrfld.long 0x04 18. 0x04 18. 0x80 18. " [18] ,PIO1_18 output bit 18" "Not set,Set"
setclrfld.long 0x04 17. 0x04 17. 0x80 17. " [17] ,PIO1_17 output bit 17" "Not set,Set"
newline
setclrfld.long 0x04 16. 0x04 16. 0x80 16. " [16] ,PIO1_16 output bit 16" "Not set,Set"
setclrfld.long 0x04 15. 0x04 15. 0x80 15. " [15] ,PIO1_15 output bit 15" "Not set,Set"
setclrfld.long 0x04 14. 0x04 14. 0x80 14. " [14] ,PIO1_14 output bit 14" "Not set,Set"
setclrfld.long 0x04 13. 0x04 13. 0x80 13. " [13] ,PIO1_13 output bit 13" "Not set,Set"
setclrfld.long 0x04 12. 0x04 12. 0x80 12. " [12] ,PIO1_12 output bit 12" "Not set,Set"
newline
setclrfld.long 0x04 11. 0x04 11. 0x80 11. " [11] ,PIO1_11 output bit 11" "Not set,Set"
setclrfld.long 0x04 10. 0x04 10. 0x80 10. " [10] ,PIO1_10 output bit 10" "Not set,Set"
setclrfld.long 0x04 9. 0x04 9. 0x80 9. " [9] ,PIO1_9 output bit 9" "Not set,Set"
setclrfld.long 0x04 8. 0x04 8. 0x80 8. " [8] ,PIO1_8 output bit 8" "Not set,Set"
setclrfld.long 0x04 7. 0x04 7. 0x80 7. " [7] ,PIO1_7 output bit 7" "Not set,Set"
newline
setclrfld.long 0x04 6. 0x04 6. 0x80 6. " [6] ,PIO1_6 output bit 6" "Not set,Set"
setclrfld.long 0x04 5. 0x04 5. 0x80 5. " [5] ,PIO1_5 output bit 5" "Not set,Set"
setclrfld.long 0x04 4. 0x04 4. 0x80 4. " [4] ,PIO1_4 output bit 4" "Not set,Set"
setclrfld.long 0x04 3. 0x04 3. 0x80 3. " [3] ,PIO1_3 output bit 3" "Not set,Set"
setclrfld.long 0x04 2. 0x04 2. 0x80 2. " [2] ,PIO1_2 output bit 2" "Not set,Set"
newline
setclrfld.long 0x04 1. 0x04 1. 0x80 1. " [1] ,PIO1_1 output bit 1" "Not set,Set"
setclrfld.long 0x04 0. 0x04 0. 0x80 0. " [0] ,PIO1_0 output bit 0" "Not set,Set"
elif cpuis("LPC11E6?JBD64")
setclrfld.long 0x04 30. 0x04 30. 0x80 30. " P[30] ,PIO1_30 output bit 30" "Not set,Set"
setclrfld.long 0x04 29. 0x04 29. 0x80 29. " [29] ,PIO1_29 output bit 29" "Not set,Set"
setclrfld.long 0x04 28. 0x04 28. 0x80 28. " [28] ,PIO1_28 output bit 28" "Not set,Set"
setclrfld.long 0x04 27. 0x04 27. 0x80 27. " [27] ,PIO1_27 output bit 27" "Not set,Set"
setclrfld.long 0x04 26. 0x04 26. 0x80 26. " [26] ,PIO1_26 output bit 26" "Not set,Set"
newline
setclrfld.long 0x04 24. 0x04 24. 0x80 24. " [24] ,PIO1_24 output bit 24" "Not set,Set"
setclrfld.long 0x04 23. 0x04 23. 0x80 23. " [23] ,PIO1_23 output bit 23" "Not set,Set"
setclrfld.long 0x04 21. 0x04 21. 0x80 21. " [21] ,PIO1_21 output bit 21" "Not set,Set"
setclrfld.long 0x04 20. 0x04 20. 0x80 20. " [20] ,PIO1_20 output bit 20" "Not set,Set"
setclrfld.long 0x04 19. 0x04 19. 0x80 19. " [19] ,PIO1_19 output bit 19" "Not set,Set"
newline
setclrfld.long 0x04 13. 0x04 13. 0x80 13. " [13] ,PIO1_13 output bit 13" "Not set,Set"
setclrfld.long 0x04 10. 0x04 10. 0x80 10. " [10] ,PIO1_10 output bit 10" "Not set,Set"
setclrfld.long 0x04 9. 0x04 9. 0x80 9. " [9] ,PIO1_9 output bit 9" "Not set,Set"
setclrfld.long 0x04 7. 0x04 7. 0x80 7. " [7] ,PIO1_7 output bit 7" "Not set,Set"
setclrfld.long 0x04 0. 0x04 0. 0x80 0. " [0] ,PIO1_0 output bit 0" "Not set,Set"
elif cpuis("LPC11E6?JBD48")
setclrfld.long 0x04 24. 0x04 24. 0x80 24. " P[24] ,PIO1_24 output bit 24" "Not set,Set"
setclrfld.long 0x04 23. 0x04 23. 0x80 23. " [23] ,PIO1_23 output bit 23" "Not set,Set"
setclrfld.long 0x04 21. 0x04 21. 0x80 21. " [21] ,PIO1_21 output bit 21" "Not set,Set"
setclrfld.long 0x04 20. 0x04 20. 0x80 20. " [20] ,PIO1_20 output bit 20" "Not set,Set"
setclrfld.long 0x04 13. 0x04 13. 0x80 13. " [13] ,PIO1_13 output bit 13" "Not set,Set"
endif
line.long 0x08 "SETCLR2,Port Set/Clear Register 2"
sif cpuis("LPC11E6?JBD100")
setclrfld.long 0x08 23. 0x08 23. 0x80 23. " P[23] ,PIO2_23 output bit 23" "Not set,Set"
setclrfld.long 0x08 22. 0x08 22. 0x80 22. " [22] ,PIO2_22 output bit 22" "Not set,Set"
setclrfld.long 0x08 21. 0x08 21. 0x80 21. " [21] ,PIO2_21 output bit 21" "Not set,Set"
setclrfld.long 0x08 20. 0x08 20. 0x80 20. " [20] ,PIO2_20 output bit 20" "Not set,Set"
setclrfld.long 0x08 19. 0x08 19. 0x80 19. " [19] ,PIO2_19 output bit 19" "Not set,Set"
newline
setclrfld.long 0x08 18. 0x08 18. 0x80 18. " [18] ,PIO2_18 output bit 18" "Not set,Set"
setclrfld.long 0x08 17. 0x08 17. 0x80 17. " [17] ,PIO2_17 output bit 17" "Not set,Set"
setclrfld.long 0x08 16. 0x08 16. 0x80 16. " [16] ,PIO2_16 output bit 16" "Not set,Set"
setclrfld.long 0x08 15. 0x08 15. 0x80 15. " [15] ,PIO2_15 output bit 15" "Not set,Set"
setclrfld.long 0x08 14. 0x08 14. 0x80 14. " [14] ,PIO2_14 output bit 14" "Not set,Set"
newline
setclrfld.long 0x08 13. 0x08 13. 0x80 13. " [13] ,PIO2_13 output bit 13" "Not set,Set"
setclrfld.long 0x08 12. 0x08 12. 0x80 12. " [12] ,PIO2_12 output bit 12" "Not set,Set"
setclrfld.long 0x08 11. 0x08 11. 0x80 11. " [11] ,PIO2_11 output bit 11" "Not set,Set"
setclrfld.long 0x08 10. 0x08 10. 0x80 10. " [10] ,PIO2_10 output bit 10" "Not set,Set"
setclrfld.long 0x08 9. 0x08 9. 0x80 9. " [9] ,PIO2_9 output bit 9" "Not set,Set"
newline
setclrfld.long 0x08 8. 0x08 8. 0x80 8. " [8] ,PIO2_8 output bit 8" "Not set,Set"
setclrfld.long 0x08 7. 0x08 7. 0x80 7. " [7] ,PIO2_7 output bit 7" "Not set,Set"
setclrfld.long 0x08 6. 0x08 6. 0x80 6. " [6] ,PIO2_6 output bit 6" "Not set,Set"
setclrfld.long 0x08 5. 0x08 5. 0x80 5. " [5] ,PIO2_5 output bit 5" "Not set,Set"
setclrfld.long 0x08 4. 0x08 4. 0x80 4. " [4] ,PIO2_4 output bit 4" "Not set,Set"
newline
setclrfld.long 0x08 3. 0x08 3. 0x80 3. " [3] ,PIO2_3 output bit 3" "Not set,Set"
setclrfld.long 0x08 2. 0x08 2. 0x80 2. " [2] ,PIO2_2 output bit 2" "Not set,Set"
setclrfld.long 0x08 1. 0x08 1. 0x80 1. " [1] ,PIO2_1 output bit 1" "Not set,Set"
setclrfld.long 0x08 0. 0x08 0. 0x80 0. " [0] ,PIO2_0 output bit 0" "Not set,Set"
elif cpuis("LPC11E6?JBD64")
setclrfld.long 0x08 19. 0x08 19. 0x80 19. " P[19] ,PIO2_19 output bit 19" "Not set,Set"
setclrfld.long 0x08 18. 0x08 18. 0x80 18. " [18] ,PIO2_18 output bit 18" "Not set,Set"
setclrfld.long 0x08 15. 0x08 15. 0x80 15. " [15] ,PIO2_15 output bit 15" "Not set,Set"
setclrfld.long 0x08 7. 0x08 7. 0x80 7. " [7] ,PIO2_7 output bit 7" "Not set,Set"
setclrfld.long 0x08 6. 0x08 6. 0x80 6. " [6] ,PIO2_6 output bit 6" "Not set,Set"
newline
setclrfld.long 0x08 5. 0x08 5. 0x80 5. " [5] ,PIO2_5 output bit 5" "Not set,Set"
setclrfld.long 0x08 4. 0x08 4. 0x80 4. " [4] ,PIO2_4 output bit 4" "Not set,Set"
setclrfld.long 0x08 3. 0x08 3. 0x80 3. " [3] ,PIO2_3 output bit 3" "Not set,Set"
setclrfld.long 0x08 2. 0x08 2. 0x80 2. " [2] ,PIO2_2 output bit 2" "Not set,Set"
setclrfld.long 0x08 1. 0x08 1. 0x80 1. " [1] ,PIO2_1 output bit 1" "Not set,Set"
newline
setclrfld.long 0x08 0. 0x08 0. 0x80 0. " [0] ,PIO2_0 output bit 0" "Not set,Set"
elif cpuis("LPC11E6?JBD48")
setclrfld.long 0x08 7. 0x08 7. 0x80 7. " P[7] ,PIO2_7 output bit 7" "Not set,Set"
setclrfld.long 0x08 5. 0x08 5. 0x80 5. " [5] ,PIO2_5 output bit 5" "Not set,Set"
setclrfld.long 0x08 4. 0x08 4. 0x80 4. " [4] ,PIO2_4 output bit 4" "Not set,Set"
setclrfld.long 0x08 3. 0x08 3. 0x80 3. " [3] ,PIO2_3 output bit 3" "Not set,Set"
setclrfld.long 0x08 2. 0x08 2. 0x80 2. " [2] ,PIO2_2 output bit 2" "Not set,Set"
newline
setclrfld.long 0x08 1. 0x08 1. 0x80 1. " [1] ,PIO2_1 output bit 1" "Not set,Set"
setclrfld.long 0x08 0. 0x08 0. 0x80 0. " [0] ,PIO2_0 output bit 0" "Not set,Set"
endif
wgroup.long 0x2300++0x0B
line.long 0x00 "NOT0,Toggle Port 0"
bitfld.long 0x00 23. " NOTP[23] ,Toggle PIO0_23 output" "No operation,Toggle"
bitfld.long 0x00 22. "[22] ,Toggle PIO0_22 output" "No operation,Toggle"
bitfld.long 0x00 21. " [21] ,Toggle PIO0_21 output" "No operation,Toggle"
bitfld.long 0x00 20. " [20] ,Toggle PIO0_20 output" "No operation,Toggle"
bitfld.long 0x00 19. " [19] ,Toggle PIO0_19 output" "No operation,Toggle"
newline
bitfld.long 0x00 18. " [18] ,Toggle PIO0_18 output" "No operation,Toggle"
bitfld.long 0x00 17. "[17] ,Toggle PIO0_17 output" "No operation,Toggle"
bitfld.long 0x00 16. " [16] ,Toggle PIO0_16 output" "No operation,Toggle"
bitfld.long 0x00 15. " [15] ,Toggle PIO0_15 output" "No operation,Toggle"
bitfld.long 0x00 14. " [14] ,Toggle PIO0_14 output" "No operation,Toggle"
newline
bitfld.long 0x00 13. " [13] ,Toggle PIO0_13 output" "No operation,Toggle"
bitfld.long 0x00 12. "[12] ,Toggle PIO0_12 output" "No operation,Toggle"
bitfld.long 0x00 11. " [11] ,Toggle PIO0_11 output" "No operation,Toggle"
bitfld.long 0x00 10. " [10] ,Toggle PIO0_10 output" "No operation,Toggle"
bitfld.long 0x00 9. " [9] ,Toggle PIO0_9 output" "No operation,Toggle"
newline
bitfld.long 0x00 8. " [8] ,Toggle PIO0_8 output" "No operation,Toggle"
bitfld.long 0x00 7. " [7] ,Toggle PIO0_7 output" "No operation,Toggle"
bitfld.long 0x00 6. " [6] ,Toggle PIO0_6 output" "No operation,Toggle"
bitfld.long 0x00 5. " [5] ,Toggle PIO0_5 output" "No operation,Toggle"
bitfld.long 0x00 4. " [4] ,Toggle PIO0_4 output" "No operation,Toggle"
newline
bitfld.long 0x00 3. " [3] ,Toggle PIO0_3 output" "No operation,Toggle"
bitfld.long 0x00 2. " [2] ,Toggle PIO0_2 output" "No operation,Toggle"
bitfld.long 0x00 1. " [1] ,Toggle PIO0_1 output" "No operation,Toggle"
bitfld.long 0x00 0. " [0] ,Toggle PIO0_0 output" "No operation,Toggle"
line.long 0x04 "NOT1,Toggle Port 1"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x04 31. " NOTP[31] ,Toggle PIO1_31 output" "No operation,Toggle"
bitfld.long 0x04 30. "[30] ,Toggle PIO1_30 output" "No operation,Toggle"
bitfld.long 0x04 29. " [29] ,Toggle PIO1_29 output" "No operation,Toggle"
bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggle"
bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggle"
newline
bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggle"
bitfld.long 0x04 25. "[25] ,Toggle PIO1_25 output" "No operation,Toggle"
bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggle"
bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggle"
bitfld.long 0x04 22. " [22] ,Toggle PIO1_22 output" "No operation,Toggle"
newline
bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggle"
bitfld.long 0x04 20. "[20] ,Toggle PIO1_20 output" "No operation,Toggle"
bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggle"
bitfld.long 0x04 18. " [18] ,Toggle PIO1_18 output" "No operation,Toggle"
bitfld.long 0x04 17. " [17] ,Toggle PIO1_17 output" "No operation,Toggle"
newline
bitfld.long 0x04 16. " [16] ,Toggle PIO1_16 output" "No operation,Toggle"
bitfld.long 0x04 15. "[15] ,Toggle PIO1_15 output" "No operation,Toggle"
bitfld.long 0x04 14. " [14] ,Toggle PIO1_14 output" "No operation,Toggle"
bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggle"
bitfld.long 0x04 12. " [12] ,Toggle PIO1_12 output" "No operation,Toggle"
newline
bitfld.long 0x04 11. " [11] ,Toggle PIO1_11 output" "No operation,Toggle"
bitfld.long 0x04 10. "[10] ,Toggle PIO1_10 output" "No operation,Toggle"
bitfld.long 0x04 9. " [9] ,Toggle PIO1_9 output" "No operation,Toggle"
bitfld.long 0x04 8. " [8] ,Toggle PIO1_8 output" "No operation,Toggle"
bitfld.long 0x04 7. " [7] ,Toggle PIO1_7 output" "No operation,Toggle"
newline
bitfld.long 0x04 6. " [6] ,Toggle PIO1_6 output" "No operation,Toggle"
bitfld.long 0x04 5. " [5] ,Toggle PIO1_5 output" "No operation,Toggle"
bitfld.long 0x04 4. " [4] ,Toggle PIO1_4 output" "No operation,Toggle"
bitfld.long 0x04 3. " [3] ,Toggle PIO1_3 output" "No operation,Toggle"
bitfld.long 0x04 2. " [2] ,Toggle PIO1_2 output" "No operation,Toggle"
newline
bitfld.long 0x04 1. " [1] ,Toggle PIO1_1 output" "No operation,Toggle"
bitfld.long 0x04 0. " [0] ,Toggle PIO1_0 output" "No operation,Toggle"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " NOTP[30] ,Toggle PIO1_30 output" "No operation,Toggle"
bitfld.long 0x04 29. "[29] ,Toggle PIO1_29 output" "No operation,Toggle"
bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggle"
bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggle"
bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggle"
newline
bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggle"
bitfld.long 0x04 23. "[23] ,Toggle PIO1_23 output" "No operation,Toggle"
bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggle"
bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggle"
bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggle"
newline
bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggle"
bitfld.long 0x04 10. "[10] ,Toggle PIO1_10 output" "No operation,Toggle"
bitfld.long 0x04 9. " [9] ,Toggle PIO1_9 output" "No operation,Toggle"
bitfld.long 0x04 7. " [7] ,Toggle PIO1_7 output" "No operation,Toggle"
bitfld.long 0x04 0. " [0] ,Toggle PIO1_0 output" "No operation,Toggle"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " NOTP[24] ,Toggle PIO1_24 output" "No operation,Toggle"
bitfld.long 0x04 23. "[23] ,Toggle PIO1_23 output" "No operation,Toggle"
bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggle"
bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggle"
bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggle"
endif
line.long 0x08 "NOT2,Toggle Port 2"
sif cpuis("LPC11E6?JBD100")
bitfld.long 0x08 23. " NOTP[23] ,Toggle PIO2_23 output" "No operation,Toggle"
bitfld.long 0x08 22. "[22] ,Toggle PIO2_22 output" "No operation,Toggle"
bitfld.long 0x08 21. " [21] ,Toggle PIO2_21 output" "No operation,Toggle"
bitfld.long 0x08 20. " [20] ,Toggle PIO2_20 output" "No operation,Toggle"
bitfld.long 0x08 19. " [19] ,Toggle PIO2_19 output" "No operation,Toggle"
newline
bitfld.long 0x08 18. " [18] ,Toggle PIO2_18 output" "No operation,Toggle"
bitfld.long 0x08 17. "[17] ,Toggle PIO2_17 output" "No operation,Toggle"
bitfld.long 0x08 16. " [16] ,Toggle PIO2_16 output" "No operation,Toggle"
bitfld.long 0x08 15. " [15] ,Toggle PIO2_15 output" "No operation,Toggle"
bitfld.long 0x08 14. " [14] ,Toggle PIO2_14 output" "No operation,Toggle"
newline
bitfld.long 0x08 13. " [13] ,Toggle PIO2_13 output" "No operation,Toggle"
bitfld.long 0x08 12. "[12] ,Toggle PIO2_12 output" "No operation,Toggle"
bitfld.long 0x08 11. " [11] ,Toggle PIO2_11 output" "No operation,Toggle"
bitfld.long 0x08 10. " [10] ,Toggle PIO2_10 output" "No operation,Toggle"
bitfld.long 0x08 9. " [9] ,Toggle PIO2_9 output" "No operation,Toggle"
newline
bitfld.long 0x08 8. " [8] ,Toggle PIO2_8 output" "No operation,Toggle"
bitfld.long 0x08 7. " [7] ,Toggle PIO2_7 output" "No operation,Toggle"
bitfld.long 0x08 6. " [6] ,Toggle PIO2_6 output" "No operation,Toggle"
bitfld.long 0x08 5. " [5] ,Toggle PIO2_5 output" "No operation,Toggle"
bitfld.long 0x08 4. " [4] ,Toggle PIO2_4 output" "No operation,Toggle"
newline
bitfld.long 0x08 3. " [3] ,Toggle PIO2_3 output" "No operation,Toggle"
bitfld.long 0x08 2. " [2] ,Toggle PIO2_2 output" "No operation,Toggle"
bitfld.long 0x08 1. " [1] ,Toggle PIO2_1 output" "No operation,Toggle"
bitfld.long 0x08 0. " [0] ,Toggle PIO2_0 output" "No operation,Toggle"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x08 19. " NOTP[19] ,Toggle PIO2_19 output" "No operation,Toggle"
bitfld.long 0x08 18. "[18] ,Toggle PIO2_18 output" "No operation,Toggle"
bitfld.long 0x08 15. " [15] ,Toggle PIO2_15 output" "No operation,Toggle"
bitfld.long 0x08 7. " [7] ,Toggle PIO2_7 output" "No operation,Toggle"
bitfld.long 0x08 6. " [6] ,Toggle PIO2_6 output" "No operation,Toggle"
newline
bitfld.long 0x08 5. " [5] ,Toggle PIO2_5 output" "No operation,Toggle"
bitfld.long 0x08 4. " [4] ,Toggle PIO2_4 output" "No operation,Toggle"
bitfld.long 0x08 3. " [3] ,Toggle PIO2_3 output" "No operation,Toggle"
bitfld.long 0x08 2. " [2] ,Toggle PIO2_2 output" "No operation,Toggle"
bitfld.long 0x08 1. " [1] ,Toggle PIO2_1 output" "No operation,Toggle"
newline
bitfld.long 0x08 0. " [0] ,Toggle PIO2_0 output" "No operation,Toggle"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x08 7. " NOTP[7] ,Toggle PIO2_7 output" "No operation,Toggle"
bitfld.long 0x08 5. " [5] ,Toggle PIO2_5 output" "No operation,Toggle"
bitfld.long 0x08 4. " [4] ,Toggle PIO2_4 output" "No operation,Toggle"
bitfld.long 0x08 3. " [3] ,Toggle PIO2_3 output" "No operation,Toggle"
bitfld.long 0x08 2. " [2] ,Toggle PIO2_2 output" "No operation,Toggle"
newline
bitfld.long 0x08 1. " [1] ,Toggle PIO2_1 output" "No operation,Toggle"
bitfld.long 0x08 0. " [0] ,Toggle PIO2_0 output" "No operation,Toggle"
endif
width 0x0B
else
base ad:0x50000000
width 8.
tree "Byte Pin Registers"
group.byte 0x0++0x00
line.byte 0x00 "B0,Byte Pin Register Port 0 Pin P0_0"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_0" "Low,High"
group.byte 0x1++0x00
line.byte 0x00 "B1,Byte Pin Register Port 0 Pin P0_1"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_1" "Low,High"
group.byte 0x2++0x00
line.byte 0x00 "B2,Byte Pin Register Port 0 Pin P0_2"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_2" "Low,High"
group.byte 0x3++0x00
line.byte 0x00 "B3,Byte Pin Register Port 0 Pin P0_3"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_3" "Low,High"
group.byte 0x4++0x00
line.byte 0x00 "B4,Byte Pin Register Port 0 Pin P0_4"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_4" "Low,High"
group.byte 0x5++0x00
line.byte 0x00 "B5,Byte Pin Register Port 0 Pin P0_5"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_5" "Low,High"
group.byte 0x6++0x00
line.byte 0x00 "B6,Byte Pin Register Port 0 Pin P0_6"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_6" "Low,High"
group.byte 0x7++0x00
line.byte 0x00 "B7,Byte Pin Register Port 0 Pin P0_7"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_7" "Low,High"
group.byte 0x8++0x00
line.byte 0x00 "B8,Byte Pin Register Port 0 Pin P0_8"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_8" "Low,High"
group.byte 0x9++0x00
line.byte 0x00 "B9,Byte Pin Register Port 0 Pin P0_9"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_9" "Low,High"
group.byte 0xA++0x00
line.byte 0x00 "B10,Byte Pin Register Port 0 Pin P0_10"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_10" "Low,High"
group.byte 0xB++0x00
line.byte 0x00 "B11,Byte Pin Register Port 0 Pin P0_11"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_11" "Low,High"
group.byte 0xC++0x00
line.byte 0x00 "B12,Byte Pin Register Port 0 Pin P0_12"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_12" "Low,High"
group.byte 0xD++0x00
line.byte 0x00 "B13,Byte Pin Register Port 0 Pin P0_13"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_13" "Low,High"
group.byte 0xE++0x00
line.byte 0x00 "B14,Byte Pin Register Port 0 Pin P0_14"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_14" "Low,High"
group.byte 0xF++0x00
line.byte 0x00 "B15,Byte Pin Register Port 0 Pin P0_15"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_15" "Low,High"
group.byte 0x10++0x00
line.byte 0x00 "B16,Byte Pin Register Port 0 Pin P0_16"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_16" "Low,High"
group.byte 0x11++0x00
line.byte 0x00 "B17,Byte Pin Register Port 0 Pin P0_17"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_17" "Low,High"
group.byte 0x12++0x00
line.byte 0x00 "B18,Byte Pin Register Port 0 Pin P0_18"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_18" "Low,High"
group.byte 0x13++0x00
line.byte 0x00 "B19,Byte Pin Register Port 0 Pin P0_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_19" "Low,High"
group.byte 0x14++0x00
line.byte 0x00 "B20,Byte Pin Register Port 0 Pin P0_20"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_20" "Low,High"
group.byte 0x15++0x00
line.byte 0x00 "B21,Byte Pin Register Port 0 Pin P0_21"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_21" "Low,High"
group.byte 0x16++0x00
line.byte 0x00 "B22,Byte Pin Register Port 0 Pin P0_22"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_22" "Low,High"
group.byte 0x17++0x00
line.byte 0x00 "B23,Byte Pin Register Port 0 Pin P0_23"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_23" "Low,High"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
group.byte 0x20++0x00
line.byte 0x00 "B32,Byte Pin Register Port 1 Pin P1_32"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_32" "Low,High"
group.byte 0x21++0x00
line.byte 0x00 "B33,Byte Pin Register Port 1 Pin P1_33"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_33" "Low,High"
group.byte 0x22++0x00
line.byte 0x00 "B34,Byte Pin Register Port 1 Pin P1_34"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_34" "Low,High"
group.byte 0x23++0x00
line.byte 0x00 "B35,Byte Pin Register Port 1 Pin P1_35"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_35" "Low,High"
group.byte 0x24++0x00
line.byte 0x00 "B36,Byte Pin Register Port 1 Pin P1_36"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_36" "Low,High"
group.byte 0x25++0x00
line.byte 0x00 "B37,Byte Pin Register Port 1 Pin P1_37"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_37" "Low,High"
group.byte 0x26++0x00
line.byte 0x00 "B38,Byte Pin Register Port 1 Pin P1_38"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_38" "Low,High"
group.byte 0x27++0x00
line.byte 0x00 "B39,Byte Pin Register Port 1 Pin P1_39"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_39" "Low,High"
group.byte 0x28++0x00
line.byte 0x00 "B40,Byte Pin Register Port 1 Pin P1_40"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_40" "Low,High"
group.byte 0x29++0x00
line.byte 0x00 "B41,Byte Pin Register Port 1 Pin P1_41"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_41" "Low,High"
group.byte 0x2A++0x00
line.byte 0x00 "B42,Byte Pin Register Port 1 Pin P1_42"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_42" "Low,High"
group.byte 0x2B++0x00
line.byte 0x00 "B43,Byte Pin Register Port 1 Pin P1_43"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_43" "Low,High"
group.byte 0x2C++0x00
line.byte 0x00 "B44,Byte Pin Register Port 1 Pin P1_44"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_44" "Low,High"
group.byte 0x2D++0x00
line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_45"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_45" "Low,High"
group.byte 0x2E++0x00
line.byte 0x00 "B46,Byte Pin Register Port 1 Pin P1_46"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_46" "Low,High"
group.byte 0x2F++0x00
line.byte 0x00 "B47,Byte Pin Register Port 1 Pin P1_47"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_47" "Low,High"
group.byte 0x30++0x00
line.byte 0x00 "B48,Byte Pin Register Port 1 Pin P1_48"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_48" "Low,High"
group.byte 0x31++0x00
line.byte 0x00 "B49,Byte Pin Register Port 1 Pin P1_49"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_49" "Low,High"
group.byte 0x32++0x00
line.byte 0x00 "B50,Byte Pin Register Port 1 Pin P1_50"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_50" "Low,High"
group.byte 0x33++0x00
line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_51"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_51" "Low,High"
group.byte 0x34++0x00
line.byte 0x00 "B52,Byte Pin Register Port 1 Pin P1_52"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_52" "Low,High"
group.byte 0x35++0x00
line.byte 0x00 "B53,Byte Pin Register Port 1 Pin P1_53"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_53" "Low,High"
group.byte 0x36++0x00
line.byte 0x00 "B54,Byte Pin Register Port 1 Pin P1_54"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_54" "Low,High"
group.byte 0x37++0x00
line.byte 0x00 "B55,Byte Pin Register Port 1 Pin P1_55"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_55" "Low,High"
group.byte 0x38++0x00
line.byte 0x00 "B56,Byte Pin Register Port 1 Pin P1_56"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_56" "Low,High"
group.byte 0x39++0x00
line.byte 0x00 "B57,Byte Pin Register Port 1 Pin P1_57"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_57" "Low,High"
group.byte 0x3A++0x00
line.byte 0x00 "B58,Byte Pin Register Port 1 Pin P1_58"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_58" "Low,High"
group.byte 0x3B++0x00
line.byte 0x00 "B59,Byte Pin Register Port 1 Pin P1_59"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_59" "Low,High"
group.byte 0x3C++0x00
line.byte 0x00 "B60,Byte Pin Register Port 1 Pin P1_60"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_60" "Low,High"
group.byte 0x3D++0x00
line.byte 0x00 "B61,Byte Pin Register Port 1 Pin P1_61"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_61" "Low,High"
group.byte 0x3F++0x00
line.byte 0x00 "B63,Byte Pin Register Port 1 Pin P1_63"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_63" "Low,High"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
group.byte 0x2D++0x03
line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_12"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High"
line.byte 0x01 "B46,Byte Pin Register Port 1 Pin P1_13"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_14" "Low,High"
line.byte 0x02 "B47,Byte Pin Register Port 1 Pin P1_14"
bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_15" "Low,High"
line.byte 0x03 "B48,Byte Pin Register Port 1 Pin P1_15"
bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_16" "Low,High"
group.byte 0x33++0x0A
line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High"
line.byte 0x01 "B52,Byte Pin Register Port 1 Pin P1_20"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_20" "Low,High"
line.byte 0x02 "B53,Byte Pin Register Port 1 Pin P1_21"
bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_21" "Low,High"
line.byte 0x03 "B54,Byte Pin Register Port 1 Pin P1_22"
bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_22" "Low,High"
line.byte 0x04 "B55,Byte Pin Register Port 1 Pin P1_23"
bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_23" "Low,High"
line.byte 0x05 "B56,Byte Pin Register Port 1 Pin P1_24"
bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO1_24" "Low,High"
line.byte 0x06 "B57,Byte Pin Register Port 1 Pin P1_25"
bitfld.byte 0x06 0. " PBYTE ,State of the pin PIO1_25" "Low,High"
line.byte 0x07 "B58,Byte Pin Register Port 1 Pin P1_26"
bitfld.byte 0x07 0. " PBYTE ,State of the pin PIO1_26" "Low,High"
line.byte 0x08 "B59,Byte Pin Register Port 1 Pin P1_27"
bitfld.byte 0x08 0. " PBYTE ,State of the pin PIO1_27" "Low,High"
line.byte 0x09 "B60,Byte Pin Register Port 1 Pin P1_28"
bitfld.byte 0x09 0. " PBYTE ,State of the pin PIO1_28" "Low,High"
line.byte 0x0A "B61,Byte Pin Register Port 1 Pin P1_29"
bitfld.byte 0x0A 0. " PBYTE ,State of the pin PIO1_29" "Low,High"
group.byte 0x3E++0x00
line.byte 0x00 "B63,Byte Pin Register Port Pin P1_31"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_31" "Low,High"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
group.byte 0x2D++0x03
line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_12"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High"
line.byte 0x01 "B46,Byte Pin Register Port 1 Pin P1_13"
bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_14" "Low,High"
endif
group.byte 0x2F++0x00
line.byte 0x00 "B47,Byte Pin Register Port 1 Pin P1_15"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_15" "Low,High"
group.byte 0x33++0x00
line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_19"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High"
sif cpuis("LPC11E11*")
group.byte 0x38++0x00
line.byte 0x00 "B56,Byte Pin Register Port 1 Pin P1_24"
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_24" "Low,High"
endif
endif
tree.end
tree "Word Pin Registers"
group.long 0x1000++0x03
line.long 0x00 "W0,Word Pin Register Port 0 Pin P0_0"
group.long 0x1004++0x03
line.long 0x00 "W1,Word Pin Register Port 0 Pin P0_1"
group.long 0x1008++0x03
line.long 0x00 "W2,Word Pin Register Port 0 Pin P0_2"
group.long 0x100C++0x03
line.long 0x00 "W3,Word Pin Register Port 0 Pin P0_3"
group.long 0x1010++0x03
line.long 0x00 "W4,Word Pin Register Port 0 Pin P0_4"
group.long 0x1014++0x03
line.long 0x00 "W5,Word Pin Register Port 0 Pin P0_5"
group.long 0x1018++0x03
line.long 0x00 "W6,Word Pin Register Port 0 Pin P0_6"
group.long 0x101C++0x03
line.long 0x00 "W7,Word Pin Register Port 0 Pin P0_7"
group.long 0x1020++0x03
line.long 0x00 "W8,Word Pin Register Port 0 Pin P0_8"
group.long 0x1024++0x03
line.long 0x00 "W9,Word Pin Register Port 0 Pin P0_9"
group.long 0x1028++0x03
line.long 0x00 "W10,Word Pin Register Port 0 Pin P0_10"
group.long 0x102C++0x03
line.long 0x00 "W11,Word Pin Register Port 0 Pin P0_11"
group.long 0x1030++0x03
line.long 0x00 "W12,Word Pin Register Port 0 Pin P0_12"
group.long 0x1034++0x03
line.long 0x00 "W13,Word Pin Register Port 0 Pin P0_13"
group.long 0x1038++0x03
line.long 0x00 "W14,Word Pin Register Port 0 Pin P0_14"
group.long 0x103C++0x03
line.long 0x00 "W15,Word Pin Register Port 0 Pin P0_15"
group.long 0x1040++0x03
line.long 0x00 "W16,Word Pin Register Port 0 Pin P0_16"
group.long 0x1044++0x03
line.long 0x00 "W17,Word Pin Register Port 0 Pin P0_17"
group.long 0x1048++0x03
line.long 0x00 "W18,Word Pin Register Port 0 Pin P0_18"
group.long 0x104C++0x03
line.long 0x00 "W19,Word Pin Register Port 0 Pin P0_19"
group.long 0x1050++0x03
line.long 0x00 "W20,Word Pin Register Port 0 Pin P0_20"
group.long 0x1054++0x03
line.long 0x00 "W21,Word Pin Register Port 0 Pin P0_21"
group.long 0x1058++0x03
line.long 0x00 "W22,Word Pin Register Port 0 Pin P0_22"
group.long 0x105C++0x03
line.long 0x00 "W23,Word Pin Register Port 0 Pin P0_23"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
group.long 0x1000++0x03
line.long 0x00 "W32,Word Pin Register Port 1 Pin P1_0"
group.long 0x1004++0x03
line.long 0x00 "W33,Word Pin Register Port 1 Pin P1_1"
group.long 0x1008++0x03
line.long 0x00 "W34,Word Pin Register Port 1 Pin P1_2"
group.long 0x100C++0x03
line.long 0x00 "W35,Word Pin Register Port 1 Pin P1_3"
group.long 0x1010++0x03
line.long 0x00 "W36,Word Pin Register Port 1 Pin P1_4"
group.long 0x1014++0x03
line.long 0x00 "W37,Word Pin Register Port 1 Pin P1_5"
group.long 0x1018++0x03
line.long 0x00 "W38,Word Pin Register Port 1 Pin P1_6"
group.long 0x101C++0x03
line.long 0x00 "W39,Word Pin Register Port 1 Pin P1_7"
group.long 0x1020++0x03
line.long 0x00 "W40,Word Pin Register Port 1 Pin P1_8"
group.long 0x1024++0x03
line.long 0x00 "W41,Word Pin Register Port 1 Pin P1_9"
group.long 0x1028++0x03
line.long 0x00 "W42,Word Pin Register Port 1 Pin P1_10"
group.long 0x102C++0x03
line.long 0x00 "W43,Word Pin Register Port 1 Pin P1_11"
group.long 0x1030++0x03
line.long 0x00 "W44,Word Pin Register Port 1 Pin P1_12"
group.long 0x1034++0x03
line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_13"
group.long 0x1038++0x03
line.long 0x00 "W46,Word Pin Register Port 1 Pin P1_14"
group.long 0x103C++0x03
line.long 0x00 "W47,Word Pin Register Port 1 Pin P1_15"
group.long 0x1040++0x03
line.long 0x00 "W48,Word Pin Register Port 1 Pin P1_16"
group.long 0x1044++0x03
line.long 0x00 "W49,Word Pin Register Port 1 Pin P1_17"
group.long 0x1048++0x03
line.long 0x00 "W50,Word Pin Register Port 1 Pin P1_18"
group.long 0x104C++0x03
line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19"
group.long 0x1050++0x03
line.long 0x00 "W52,Word Pin Register Port 1 Pin P1_20"
group.long 0x1054++0x03
line.long 0x00 "W53,Word Pin Register Port 1 Pin P1_21"
group.long 0x1058++0x03
line.long 0x00 "W54,Word Pin Register Port 1 Pin P1_22"
group.long 0x105C++0x03
line.long 0x00 "W55,Word Pin Register Port 1 Pin P1_23"
group.long 0x1060++0x03
line.long 0x00 "W56,Word Pin Register Port 1 Pin P1_24"
group.long 0x1064++0x03
line.long 0x00 "W57,Word Pin Register Port 1 Pin P1_25"
group.long 0x1068++0x03
line.long 0x00 "W58,Word Pin Register Port 1 Pin P1_26"
group.long 0x106C++0x03
line.long 0x00 "W59,Word Pin Register Port 1 Pin P1_27"
group.long 0x1070++0x03
line.long 0x00 "W60,Word Pin Register Port 1 Pin P1_28"
group.long 0x1074++0x03
line.long 0x00 "W61,Word Pin Register Port 1 Pin P1_29"
group.long 0x107C++0x03
line.long 0x00 "W63,Word Pin Register Port 1 Pin P1_31"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
group.long 0x10B4++0x0F
line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_12"
line.long 0x04 "W46,Word Pin Register Port 1 Pin P1_13"
line.long 0x08 "W47,Word Pin Register Port 1 Pin P1_14"
line.long 0x0C "W48,Word Pin Register Port 1 Pin P1_15"
group.long 0x10CC++0x2B
line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19"
line.long 0x04 "W52,Word Pin Register Port 1 Pin P1_20"
line.long 0x08 "W53,Word Pin Register Port 1 Pin P1_21"
line.long 0x0C "W54,Word Pin Register Port 1 Pin P1_22"
line.long 0x10 "W55,Word Pin Register Port 1 Pin P1_23"
line.long 0x14 "W56,Word Pin Register Port 1 Pin P1_24"
line.long 0x18 "W57,Word Pin Register Port 1 Pin P1_25"
line.long 0x1C "W58,Word Pin Register Port 1 Pin P1_26"
line.long 0x20 "W59,Word Pin Register Port 1 Pin P1_27"
line.long 0x24 "W60,Word Pin Register Port 1 Pin P1_28"
line.long 0x28 "W61,Word Pin Register Port 1 Pin P1_29"
group.long 0x10FC++0x03
line.long 0x00 "W63,Word Pin Register Port 1 Pin P1_31"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
group.long 0x10B4++0x0F
line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_12"
line.long 0x04 "W46,Word Pin Register Port 1 Pin P1_13"
endif
group.long 0x10BC++0x03
line.long 0x00 "W47,Word Pin Register Port 1 Pin P1_14"
group.long 0x10CC++0x03
line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19"
sif cpuis("LPC11E11*")
group.long 0x10E0++0x03
line.long 0x00 "W56,Word Pin Register Port 1 Pin P1_24"
endif
endif
newline
tree.end
group.long 0x2000++0x07
line.long 0x00 "DIR0,Direction Port 0 Register"
bitfld.long 0x00 23. " DIRP[23] ,PIO0_23 pin direction select" "Input,Output"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin direction select" "Input,Output"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin direction select" "Input,Output"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin direction select" "Input,Output"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin direction select" "Input,Output"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 pin direction select" "Input,Output"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin direction select" "Input,Output"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin direction select" "Input,Output"
bitfld.long 0x00 15. " [15] ,PIO0_15 pin direction select" "Input,Output"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin direction select" "Input,Output"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 pin direction select" "Input,Output"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin direction select" "Input,Output"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin direction select" "Input,Output"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin direction select" "Input,Output"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin direction select" "Input,Output"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 pin direction select" "Input,Output"
bitfld.long 0x00 7. " [7] ,PIO0_7 pin direction select" "Input,Output"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin direction select" "Input,Output"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin direction select" "Input,Output"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin direction select" "Input,Output"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 pin direction select" "Input,Output"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin direction select" "Input,Output"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin direction select" "Input,Output"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin direction select" "Input,Output"
line.long 0x04 "DIR1,Direction Port 1 Register"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
bitfld.long 0x04 31. " DIRP[31] ,PIO1_31 pin direction select" "Input,Output"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin direction select" "Input,Output"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin direction select" "Input,Output"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 pin direction select" "Input,Output"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin direction select" "Input,Output"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin direction select" "Input,Output"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin direction select" "Input,Output"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin direction select" "Input,Output"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin direction select" "Input,Output"
newline
bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin direction select" "Input,Output"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin direction select" "Input,Output"
bitfld.long 0x04 11. " [11] ,PIO1_11 pin direction select" "Input,Output"
newline
bitfld.long 0x04 10. " [10] ,PIO1_10 pin direction select" "Input,Output"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin direction select" "Input,Output"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin direction select" "Input,Output"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin direction select" "Input,Output"
bitfld.long 0x04 6. " [6] ,PIO1_6 pin direction select" "Input,Output"
newline
bitfld.long 0x04 5. " [5] ,PIO1_5 pin direction select" "Input,Output"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin direction select" "Input,Output"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin direction select" "Input,Output"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin direction select" "Input,Output"
bitfld.long 0x04 1. " [1] ,PIO1_1 pin direction select" "Input,Output"
newline
bitfld.long 0x04 0. " [0] ,PIO1_0 pin direction select" "Input,Output"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
bitfld.long 0x04 31. " DIRP[31] ,PIO1_31 pin direction select" "Input,Output"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin direction select" "Input,Output"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin direction select" "Input,Output"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 pin direction select" "Input,Output"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin direction select" "Input,Output"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin direction select" "Input,Output"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin direction select" "Input,Output"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin direction select" "Input,Output"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
bitfld.long 0x04 24. " DIRP[24] ,PIO1_24 pin direction select" "Input,Output"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output"
newline
endif
bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output"
endif
group.long 0x2080++0x07
line.long 0x00 "MASK0,Mask Port 0 Register"
bitfld.long 0x00 23. " MASK[23] ,PIO0_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 15. " [15] ,PIO0_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,PIO0_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin mask bit" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin mask bit" "Not masked,Masked"
line.long 0x04 "MASK1,Mask Port 1 Register"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
bitfld.long 0x04 31. " MASK[31] ,PIO1_31 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 11. " [11] ,PIO1_11 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 10. " [10] ,PIO1_10 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 6. " [6] ,PIO1_6 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 5. " [5] ,PIO1_5 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 1. " [1] ,PIO1_1 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 0. " [0] ,PIO1_0 pin mask bit" "Not masked,Masked"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
bitfld.long 0x04 31. " MASK[31] ,PIO1_31 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin mask bit" "Not masked,Masked"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
bitfld.long 0x04 24. " MASK[24] ,PIO1_24 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked"
newline
endif
bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked"
endif
group.long 0x2100++0x07
line.long 0x00 "PIN0,Port Pin Register 0"
bitfld.long 0x00 23. " PORT[23] ,PIO0_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 15. " [15] ,PIO0_15 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 7. " [7] ,PIO0_7 pin state" "Low/Clear,High/Set"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin state read/write" "Low/Clear,High/Set"
line.long 0x04 "PIN1,Port Pin Register 1"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
bitfld.long 0x04 31. " PORT[31] ,PIO1_31 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 15. " [15] ,PIO1_15 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 11. " [11] ,PIO1_11 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 10. " [10] ,PIO1_10 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 6. " [6] ,PIO1_6 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 5. " [5] ,PIO1_5 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 3. " [3] ,PIO1_3 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 1. " [1] ,PIO1_1 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 0. " [0] ,PIO1_0 pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
bitfld.long 0x04 31. " PORT[31] ,PIO1_31 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
bitfld.long 0x04 24. " PORT[24] ,PIO1_24 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin state read/write" "Low/Clear,High/Set"
newline
endif
bitfld.long 0x04 19. " [19] ,PIO1_19 pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin state read/write" "Low/Clear,High/Set"
endif
group.long 0x2180++0x07
line.long 0x00 "MPIN0,Masked Port Register Port 0"
bitfld.long 0x00 23. " MPORTP[23] ,PIO0_23 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 22. " [22] ,PIO0_22 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 21. " [21] ,PIO0_21 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 20. " [20] ,PIO0_20 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 19. " [19] ,PIO0_19 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 18. " [18] ,PIO0_18 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 17. " [17] ,PIO0_17 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 16. " [16] ,PIO0_16 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 15. " [15] ,PIO0_15 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 14. " [14] ,PIO0_14 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 13. " [13] ,PIO0_13 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 12. " [12] ,PIO0_12 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 11. " [11] ,PIO0_11 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 10. " [10] ,PIO0_10 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 9. " [9] ,PIO0_9 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 8. " [8] ,PIO0_8 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 7. " [7] ,PIO0_7 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 6. " [6] ,PIO0_6 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 5. " [5] ,PIO0_5 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 4. " [4] ,PIO0_4 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x00 3. " [3] ,PIO0_3 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 2. " [2] ,PIO0_2 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 1. " [1] ,PIO0_1 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x00 0. " [0] ,PIO0_0 masked pin state read/write" "Low/Clear,High/Set"
line.long 0x04 "MPIN1,Masked Port Register Port 1"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
bitfld.long 0x04 31. " MPORTP[31] ,PIO1_31 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 26. " [26] ,PIO1_26 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 24. " [24] ,PIO1_24 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 22. " [22] ,PIO1_22 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 18. " [18] ,PIO1_18 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 17. " [17] ,PIO1_17 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 16. " [16] ,PIO1_16 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 14. " [14] ,PIO1_14 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 12. " [12] ,PIO1_12 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 11. " [11] ,PIO1_11 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 10. " [10] ,PIO1_10 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 9. " [9] ,PIO1_9 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 8. " [8] ,PIO1_8 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 7. " [7] ,PIO1_7 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 6. " [6] ,PIO1_6 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 5. " [5] ,PIO1_5 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 4. " [4] ,PIO1_4 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 3. " [3] ,PIO1_3 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 2. " [2] ,PIO1_2 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 1. " [1] ,PIO1_1 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 0. " [0] ,PIO1_0 masked pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
bitfld.long 0x04 31. " MPORTP[31] ,PIO1_31 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 29. " [29] ,PIO1_29 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 28. " [28] ,PIO1_28 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 27. " [27] ,PIO1_27 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 26. " [26] ,PIO1_26 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 25. " [25] ,PIO1_25 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 24. " [24] ,PIO1_24 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 22. " [22] ,PIO1_22 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 16. " [16] ,PIO1_16 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 14. " [14] ,PIO1_14 masked pin state read/write" "Low/Clear,High/Set"
newline
bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state read/write" "Low/Clear,High/Set"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
bitfld.long 0x04 24. " MPORTP[24] ,PIO1_24 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state read/write" "Low/Clear,High/Set"
newline
endif
bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state read/write" "Low/Clear,High/Set"
bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state read/write" "Low/Clear,High/Set"
endif
newline
width 9.
group.long 0x2200++0x07
line.long 0x00 "SETCLR0,Port Set/Clear Register 0"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " P[23] ,PIO0_23 output bit" "Not set,Set"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " [22] ,PIO0_22 output bit" "Not set,Set"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " [21] ,PIO0_21 output bit" "Not set,Set"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " [20] ,PIO0_20 output bit" "Not set,Set"
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " [19] ,PIO0_19 output bit" "Not set,Set"
newline
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " [18] ,PIO0_18 output bit" "Not set,Set"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " [17] ,PIO0_17 output bit" "Not set,Set"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " [16] ,PIO0_16 output bit" "Not set,Set"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " [15] ,PIO0_15 output bit" "Not set,Set"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " [14] ,PIO0_14 output bit" "Not set,Set"
newline
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " [13] ,PIO0_13 output bit" "Not set,Set"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " [12] ,PIO0_12 output bit" "Not set,Set"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " [11] ,PIO0_11 output bit" "Not set,Set"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " [10] ,PIO0_10 output bit" "Not set,Set"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " [9] ,PIO0_9 output bit" "Not set,Set"
newline
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " [8] ,PIO0_8 output bit" "Not set,Set"
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " [7] ,PIO0_7 output bit" "Not set,Set"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " [6] ,PIO0_6 output bit" "Not set,Set"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " [5] ,PIO0_5 output bit" "Not set,Set"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " [4] ,PIO0_4 output bit" "Not set,Set"
newline
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " [3] ,PIO0_3 output bit" "Not set,Set"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " [2] ,PIO0_2 output bit" "Not set,Set"
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " [1] ,PIO0_1 output bit" "Not set,Set"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " [0] ,PIO0_0 output bit" "Not set,Set"
line.long 0x04 "SETCLR1,Port Set/Clear Register 1"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " P[31] ,PIO1_31 output bit" "Not set,Set"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " [29] ,PIO1_29 output bit" "Not set,Set"
setclrfld.long 0x04 28. 0x04 28. 0x84 29. " [28] ,PIO1_28 output bit" "Not set,Set"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " [27] ,PIO1_27 output bit" "Not set,Set"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " [26] ,PIO1_26 output bit" "Not set,Set"
newline
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " [25] ,PIO1_25 output bit" "Not set,Set"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " [24] ,PIO1_24 output bit" "Not set,Set"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " [23] ,PIO1_23 output bit" "Not set,Set"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " [22] ,PIO1_22 output bit" "Not set,Set"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " [21] ,PIO1_21 output bit" "Not set,Set"
newline
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " [20] ,PIO1_20 output bit" "Not set,Set"
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " [19] ,PIO1_19 output bit" "Not set,Set"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " [18] ,PIO1_18 output bit" "Not set,Set"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " [17] ,PIO1_17 output bit" "Not set,Set"
setclrfld.long 0x04 16. 0x04 16. 0x84 15. " [16] ,PIO1_16 output bit" "Not set,Set"
newline
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " [15] ,PIO1_15 output bit" "Not set,Set"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " [14] ,PIO1_14 output bit" "Not set,Set"
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " [13] ,PIO1_13 output bit" "Not set,Set"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " [12] ,PIO1_12 output bit" "Not set,Set"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " [11] ,PIO1_11 output bit" "Not set,Set"
newline
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " [10] ,PIO1_10 output bit" "Not set,Set"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " [9] ,PIO1_9 output bit" "Not set,Set"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " [8] ,PIO1_8 output bit" "Not set,Set"
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " [7] ,PIO1_7 output bit" "Not set,Set"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " [6] ,PIO1_6 output bit" "Not set,Set"
newline
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " [5] ,PIO1_5 output bit" "Not set,Set"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " [4] ,PIO1_4 output bit" "Not set,Set"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " [3] ,PIO1_3 output bit" "Not set,Set"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " [2] ,PIO1_2 output bit" "Not set,Set"
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " [1] ,PIO1_1 output bit" "Not set,Set"
newline
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " [0] ,PIO1_0 output bit" "Not set,Set"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " P[31] ,PIO1_31 output bit" "Not set,Set"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " [29] ,PIO1_29 output bit" "Not set,Set"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " [28] ,PIO1_28 output bit" "Not set,Set"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " [27] ,PIO1_27 output bit" "Not set,Set"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " [26] ,PIO1_26 output bit" "Not set,Set"
newline
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " [25] ,PIO1_25 output bit" "Not set,Set"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " [24] ,PIO1_24 output bit" "Not set,Set"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " [23] ,PIO1_23 output bit" "Not set,Set"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " [22] ,PIO1_22 output bit" "Not set,Set"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " [21] ,PIO1_21 output bit" "Not set,Set"
newline
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " [20] ,PIO1_20 output bit" "Not set,Set"
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " [19] ,PIO1_19 output bit" "Not set,Set"
setclrfld.long 0x04 16. 0x04 16. 0x84 18. " [16] ,PIO1_16 output bit" "Not set,Set"
setclrfld.long 0x04 15. 0x04 15. 0x84 17. " [15] ,PIO1_15 output bit" "Not set,Set"
setclrfld.long 0x04 14. 0x04 14. 0x84 16. " [14] ,PIO1_14 output bit" "Not set,Set"
newline
setclrfld.long 0x04 13. 0x04 13. 0x84 15. " [13] ,PIO1_13 output bit" "Not set,Set"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " P[24] ,PIO1_24 output bit" "Not set,Set"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " [23] ,PIO1_23 output bit" "Not set,Set"
newline
endif
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " [19] ,PIO1_19 output bit" "Not set,Set"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " [15] ,PIO1_15 output bit" "Not set,Set"
endif
wgroup.long 0x2300++0x07
line.long 0x00 "NOT0,Toggle Port 0"
bitfld.long 0x00 23. " NOTP[23] ,Toggle PIO0_23 output" "No operation,Toggle"
bitfld.long 0x00 22. " [22] ,Toggle PIO0_22 output" "No operation,Toggle"
bitfld.long 0x00 21. " [21] ,Toggle PIO0_21 output" "No operation,Toggle"
bitfld.long 0x00 20. " [20] ,Toggle PIO0_20 output" "No operation,Toggle"
newline
bitfld.long 0x00 19. " [19] ,Toggle PIO0_19 output" "No operation,Toggle"
bitfld.long 0x00 18. " [18] ,Toggle PIO0_18 output" "No operation,Toggle"
bitfld.long 0x00 17. " [17] ,Toggle PIO0_17 output" "No operation,Toggle"
bitfld.long 0x00 16. " [16] ,Toggle PIO0_16 output" "No operation,Toggle"
newline
bitfld.long 0x00 15. " [15] ,Toggle PIO0_15 output" "No operation,Toggle"
bitfld.long 0x00 14. " [14] ,Toggle PIO0_14 output" "No operation,Toggle"
bitfld.long 0x00 13. " [13] ,Toggle PIO0_13 output" "No operation,Toggle"
bitfld.long 0x00 12. " [12] ,Toggle PIO0_12 output" "No operation,Toggle"
newline
bitfld.long 0x00 11. " [11] ,Toggle PIO0_11 output" "No operation,Toggle"
bitfld.long 0x00 10. " [10] ,Toggle PIO0_10 output" "No operation,Toggle"
bitfld.long 0x00 9. " [9] ,Toggle PIO0_9 output" "No operation,Toggle"
bitfld.long 0x00 8. " [8] ,Toggle PIO0_8 output" "No operation,Toggle"
newline
bitfld.long 0x00 7. " [7] ,Toggle PIO0_7 output" "No operation,Toggle"
bitfld.long 0x00 6. " [6] ,Toggle PIO0_6 output" "No operation,Toggle"
bitfld.long 0x00 5. " [5] ,Toggle PIO0_5 output" "No operation,Toggle"
bitfld.long 0x00 4. " [4] ,Toggle PIO0_4 output" "No operation,Toggle"
newline
bitfld.long 0x00 3. " [3] ,Toggle PIO0_3 output" "No operation,Toggle"
bitfld.long 0x00 2. " [2] ,Toggle PIO0_2 output" "No operation,Toggle"
bitfld.long 0x00 1. " [1] ,Toggle PIO0_1 output" "No operation,Toggle"
bitfld.long 0x00 0. " [0] ,Toggle PIO0_0 output" "No operation,Toggle"
line.long 0x04 "NOT1,Toggle Port 1"
sif cpuis("LPC11E14*")||cpuis("LPC11E37*")||cpuis("LPC11E36*")
bitfld.long 0x04 31. " NOTP[31] ,Toggle PIO1_31 output" "No operation,Toggle"
bitfld.long 0x04 29. " [29] ,Toggle PIO1_29 output" "No operation,Toggle"
bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggle"
bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggle"
newline
bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggle"
bitfld.long 0x04 25. " [25] ,Toggle PIO1_25 output" "No operation,Toggle"
bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggle"
bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggle"
newline
bitfld.long 0x04 22. " [22] ,Toggle PIO1_22 output" "No operation,Toggle"
bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggle"
bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggle"
bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggle"
newline
bitfld.long 0x04 18. " [18] ,Toggle PIO1_18 output" "No operation,Toggle"
bitfld.long 0x04 17. " [17] ,Toggle PIO1_17 output" "No operation,Toggle"
bitfld.long 0x04 16. " [16] ,Toggle PIO1_16 output" "No operation,Toggle"
bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggle"
newline
bitfld.long 0x04 14. " [14] ,Toggle PIO1_14 output" "No operation,Toggle"
bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggle"
bitfld.long 0x04 12. " [12] ,Toggle PIO1_12 output" "No operation,Toggle"
bitfld.long 0x04 11. " [11] ,Toggle PIO1_11 output" "No operation,Toggle"
newline
bitfld.long 0x04 10. " [10] ,Toggle PIO1_10 output" "No operation,Toggle"
bitfld.long 0x04 9. " [9] ,Toggle PIO1_9 output" "No operation,Toggle"
bitfld.long 0x04 8. " [8] ,Toggle PIO1_8 output" "No operation,Toggle"
bitfld.long 0x04 7. " [7] ,Toggle PIO1_7 output" "No operation,Toggle"
newline
bitfld.long 0x04 6. " [6] ,Toggle PIO1_6 output" "No operation,Toggle"
bitfld.long 0x04 5. " [5] ,Toggle PIO1_5 output" "No operation,Toggle"
bitfld.long 0x04 4. " [4] ,Toggle PIO1_4 output" "No operation,Toggle"
bitfld.long 0x04 3. " [3] ,Toggle PIO1_3 output" "No operation,Toggle"
newline
bitfld.long 0x04 2. " [2] ,Toggle PIO1_2 output" "No operation,Toggle"
bitfld.long 0x04 1. " [1] ,Toggle PIO1_1 output" "No operation,Toggle"
bitfld.long 0x04 0. " [0] ,PIO1_0 output" "No operation,Toggle"
elif cpuis("LPC11E12*")||cpuis("LPC11E13*")
bitfld.long 0x04 31. " NOTP[31] ,Toggle PIO1_31 output" "No operation,Toggle"
bitfld.long 0x04 29. " [29] ,Toggle PIO1_29 output" "No operation,Toggle"
bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggle"
bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggle"
newline
bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggle"
bitfld.long 0x04 25. " [25] ,Toggle PIO1_25 output" "No operation,Toggle"
bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggle"
bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggle"
newline
bitfld.long 0x04 22. " [22] ,Toggle PIO1_22 output" "No operation,Toggle"
bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggle"
bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggle"
bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggle"
newline
bitfld.long 0x04 16. " [16] ,Toggle PIO1_16 output" "No operation,Toggle"
bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggle"
bitfld.long 0x04 14. " [14] ,Toggle PIO1_14 output" "No operation,Toggle"
bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggle"
elif cpuis("LPC11E11*")||cpuis("LPC11E35FHI33")
sif cpuis("LPC11E11*")
bitfld.long 0x04 24. " NOTP[24] ,Toggle PIO1_24 output" "No operation,Toggle"
bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggle"
newline
endif
bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggle"
bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggle"
endif
width 0x0B
endif
tree.end
tree.open "GINT0/1 (Grouped GPIO Input Interrupt)"
tree "GINT0"
base ad:0x4005C000
width 11.
group.long 0x00++0x03
line.long 0x00 "CTRL,GPIO Grouped Interrupt Control Register"
bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level"
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND"
bitfld.long 0x00 0. " INT ,Group interrupt status" "Pending,Active"
group.long 0x20++0x07
line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity"
bitfld.long 0x00 23. " POL[23] ,PIO0_23 pin polarity" "Low,High"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin polarity" "Low,High"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin polarity" "Low,High"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin polarity" "Low,High"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO0_18 pin polarity" "Low,High"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin polarity" "Low,High"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin polarity" "Low,High"
newline
bitfld.long 0x00 15. " [15] ,PIO0_15 pin polarity" "Low,High"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin polarity" "Low,High"
bitfld.long 0x00 13. " [13] ,PIO0_13 pin polarity" "Low,High"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin polarity" "Low,High"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin polarity" "Low,High"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin polarity" "Low,High"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin polarity" "Low,High"
bitfld.long 0x00 8. " [8] ,PIO0_8 pin polarity" "Low,High"
newline
bitfld.long 0x00 7. " [7] ,PIO0_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO0_3 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin polarity" "Low,High"
line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High"
else
bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
endif
elif cpuis("LPC11E11")
bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
elif cpuis("LPC11E12")||cpuis("LPC11E13")
bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
newline
bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
elif cpuis("LPC11E35FHI33")
bitfld.long 0x04 19. " POL[19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High"
else
bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High"
sif cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37")||cpuis("LPC11E37H")
textfld " "
else
bitfld.long 0x04 30. " [30] ,PIO1_30 pin polarity" "Low,High"
endif
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
newline
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin polarity" "Low,High"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin polarity" "Low,High"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High"
newline
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin polarity" "Low,High"
bitfld.long 0x04 11. " [11] ,PIO1_11 pin polarity" "Low,High"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin polarity" "Low,High"
newline
bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High"
bitfld.long 0x04 6. " [6] ,PIO1_6 pin polarity" "Low,High"
bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin polarity" "Low,High"
bitfld.long 0x04 3. " [3] ,PIO1_3pin polarity" "Low,High"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin polarity" "Low,High"
bitfld.long 0x04 1. " [1] ,PIO1_1 pin polarity" "Low,High"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High"
endif
sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*")
group.long 0x28++0x04
line.long 0x00 "PORT_POL2,GPIO Grouped Interrupt Port 2 Polarity"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High"
bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High"
bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
newline
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
else
bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
endif
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64")
bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High"
bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High"
bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High"
newline
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
else
bitfld.long 0x00 23. " POL[23] ,PIO2_23 pin polarity" "Low,High"
bitfld.long 0x00 22. " [22] ,PIO2_22 pin polarity" "Low,High"
bitfld.long 0x00 21. " [21] ,PIO2_21 pin polarity" "Low,High"
bitfld.long 0x00 20. " [20] ,PIO2_20 pin polarity" "Low,High"
bitfld.long 0x00 19. " [19] ,PIO2_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High"
bitfld.long 0x00 17. " [17] ,PIO2_17 pin polarity" "Low,High"
bitfld.long 0x00 16. " [16] ,PIO2_16 pin polarity" "Low,High"
newline
bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High"
bitfld.long 0x00 14. " [14] ,PIO2_14 pin polarity" "Low,High"
bitfld.long 0x00 13. " [13] ,PIO2_13 pin polarity" "Low,High"
bitfld.long 0x00 12. " [12] ,PIO2_12 pin polarity" "Low,High"
bitfld.long 0x00 11. " [11] ,PIO2_11 pin polarity" "Low,High"
bitfld.long 0x00 10. " [10] ,PIO2_10 pin polarity" "Low,High"
bitfld.long 0x00 9. " [9] ,PIO2_9 pin polarity" "Low,High"
bitfld.long 0x00 8. " [8] ,PIO2_8 pin polarity" "Low,High"
newline
bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
endif
endif
group.long 0x40++0x07
line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register"
bitfld.long 0x00 23. " ENA[23] ,Enable PIO0_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,Enable PIO0_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,Enable PIO0_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,Enable PIO0_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 19. " [19] ,Enable PIO0_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO0_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,Enable PIO0_17 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,Enable PIO0_16 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 15. " [15] ,Enable PIO0_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Enable PIO0_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Enable PIO0_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Enable PIO0_12 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Enable PIO0_11 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Enable PIO0_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Enable PIO0_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Enable PIO0_8 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " [7] ,Enable PIO0_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO0_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO0_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO0_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO0_3for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO0_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO0_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO0_0 for group interrupt" "Disabled,Enabled"
line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
endif
elif cpuis("LPC11E11")
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E12")||cpuis("LPC11E13")
bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E35FHI33")
bitfld.long 0x04 19. " ENA[19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled"
sif !cpuis("LPC11E14")&&!cpuis("LPC11E36")&&!cpuis("LPC11E37")&&!cpuis("LPC11E37H")
bitfld.long 0x04 30. " [30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled"
endif
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 18. " [18] ,Enable PIO1_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 17. " [17] ,Enable PIO1_17 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 12. " [12] ,Enable PIO1_12 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,Enable PIO1_11 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,Enable PIO1_8 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 6. " [6] ,Enable PIO1_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,Enable PIO1_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 3. " [3] ,Enable PIO1_3for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,Enable PIO1_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,Enable PIO1_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled"
endif
sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*")
group.long 0x48++0x03
line.long 0x00 "PORT_ENA2,GPIO Grouped Interrupt Port 2 Enable Register"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
endif
elif cpuis("LPC11E66JBD48")||cpuis("LPC11E67JBD48")
bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64")
bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x00 23. " ENA[23] ,Enable PIO2_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,Enable PIO2_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,Enable PIO2_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,Enable PIO2_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 19. " [19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,Enable PIO2_17 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,Enable PIO2_16 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Enable PIO2_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Enable PIO2_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Enable PIO2_12 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Enable PIO2_11 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Enable PIO2_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Enable PIO2_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Enable PIO2_8 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
endif
endif
width 0x0B
tree.end
tree "GINT1"
base ad:0x40060000
width 11.
group.long 0x00++0x03
line.long 0x00 "CTRL,GPIO Grouped Interrupt Control Register"
bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level"
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND"
bitfld.long 0x00 0. " INT ,Group interrupt status" "Pending,Active"
group.long 0x20++0x07
line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity"
bitfld.long 0x00 23. " POL[23] ,PIO0_23 pin polarity" "Low,High"
bitfld.long 0x00 22. " [22] ,PIO0_22 pin polarity" "Low,High"
bitfld.long 0x00 21. " [21] ,PIO0_21 pin polarity" "Low,High"
bitfld.long 0x00 20. " [20] ,PIO0_20 pin polarity" "Low,High"
bitfld.long 0x00 19. " [19] ,PIO0_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO0_18 pin polarity" "Low,High"
bitfld.long 0x00 17. " [17] ,PIO0_17 pin polarity" "Low,High"
bitfld.long 0x00 16. " [16] ,PIO0_16 pin polarity" "Low,High"
newline
bitfld.long 0x00 15. " [15] ,PIO0_15 pin polarity" "Low,High"
bitfld.long 0x00 14. " [14] ,PIO0_14 pin polarity" "Low,High"
bitfld.long 0x00 13. " [13] ,PIO0_13 pin polarity" "Low,High"
bitfld.long 0x00 12. " [12] ,PIO0_12 pin polarity" "Low,High"
bitfld.long 0x00 11. " [11] ,PIO0_11 pin polarity" "Low,High"
bitfld.long 0x00 10. " [10] ,PIO0_10 pin polarity" "Low,High"
bitfld.long 0x00 9. " [9] ,PIO0_9 pin polarity" "Low,High"
bitfld.long 0x00 8. " [8] ,PIO0_8 pin polarity" "Low,High"
newline
bitfld.long 0x00 7. " [7] ,PIO0_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO0_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO0_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO0_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO0_3 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO0_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO0_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO0_0 pin polarity" "Low,High"
line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High"
else
bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
endif
elif cpuis("LPC11E11")
bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
elif cpuis("LPC11E12")||cpuis("LPC11E13")
bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
newline
bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
elif cpuis("LPC11E35FHI33")
bitfld.long 0x04 19. " POL[19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High"
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
newline
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High"
bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High"
else
bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High"
sif cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37")||cpuis("LPC11E37H")
textfld " "
else
bitfld.long 0x04 30. " [30] ,PIO1_30 pin polarity" "Low,High"
endif
bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High"
bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High"
bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High"
bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High"
bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High"
bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High"
newline
bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High"
bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High"
bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High"
bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High"
bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High"
bitfld.long 0x04 18. " [18] ,PIO1_18 pin polarity" "Low,High"
bitfld.long 0x04 17. " [17] ,PIO1_17 pin polarity" "Low,High"
bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High"
newline
bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High"
bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High"
bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High"
bitfld.long 0x04 12. " [12] ,PIO1_12 pin polarity" "Low,High"
bitfld.long 0x04 11. " [11] ,PIO1_11 pin polarity" "Low,High"
bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High"
bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High"
bitfld.long 0x04 8. " [8] ,PIO1_8 pin polarity" "Low,High"
newline
bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High"
bitfld.long 0x04 6. " [6] ,PIO1_6 pin polarity" "Low,High"
bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High"
bitfld.long 0x04 4. " [4] ,PIO1_4 pin polarity" "Low,High"
bitfld.long 0x04 3. " [3] ,PIO1_3pin polarity" "Low,High"
bitfld.long 0x04 2. " [2] ,PIO1_2 pin polarity" "Low,High"
bitfld.long 0x04 1. " [1] ,PIO1_1 pin polarity" "Low,High"
bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High"
endif
sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*")
group.long 0x28++0x04
line.long 0x00 "PORT_POL2,GPIO Grouped Interrupt Port 2 Polarity"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High"
bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High"
bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
newline
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
else
bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
endif
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64")
bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High"
bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High"
bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High"
newline
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
else
bitfld.long 0x00 23. " POL[23] ,PIO2_23 pin polarity" "Low,High"
bitfld.long 0x00 22. " [22] ,PIO2_22 pin polarity" "Low,High"
bitfld.long 0x00 21. " [21] ,PIO2_21 pin polarity" "Low,High"
bitfld.long 0x00 20. " [20] ,PIO2_20 pin polarity" "Low,High"
bitfld.long 0x00 19. " [19] ,PIO2_19 pin polarity" "Low,High"
bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High"
bitfld.long 0x00 17. " [17] ,PIO2_17 pin polarity" "Low,High"
bitfld.long 0x00 16. " [16] ,PIO2_16 pin polarity" "Low,High"
newline
bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High"
bitfld.long 0x00 14. " [14] ,PIO2_14 pin polarity" "Low,High"
bitfld.long 0x00 13. " [13] ,PIO2_13 pin polarity" "Low,High"
bitfld.long 0x00 12. " [12] ,PIO2_12 pin polarity" "Low,High"
bitfld.long 0x00 11. " [11] ,PIO2_11 pin polarity" "Low,High"
bitfld.long 0x00 10. " [10] ,PIO2_10 pin polarity" "Low,High"
bitfld.long 0x00 9. " [9] ,PIO2_9 pin polarity" "Low,High"
bitfld.long 0x00 8. " [8] ,PIO2_8 pin polarity" "Low,High"
newline
bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High"
bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High"
bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High"
bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High"
bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High"
bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High"
bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High"
bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High"
endif
endif
group.long 0x40++0x07
line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register"
bitfld.long 0x00 23. " ENA[23] ,Enable PIO0_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,Enable PIO0_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,Enable PIO0_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,Enable PIO0_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 19. " [19] ,Enable PIO0_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO0_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,Enable PIO0_17 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,Enable PIO0_16 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 15. " [15] ,Enable PIO0_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Enable PIO0_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Enable PIO0_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Enable PIO0_12 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Enable PIO0_11 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Enable PIO0_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Enable PIO0_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Enable PIO0_8 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " [7] ,Enable PIO0_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO0_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO0_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO0_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO0_3for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO0_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO0_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO0_0 for group interrupt" "Disabled,Enabled"
line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
endif
elif cpuis("LPC11E11")
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E12")||cpuis("LPC11E13")
bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E35FHI33")
bitfld.long 0x04 19. " ENA[19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E6?JBD48")
bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E6?JBD64")
bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled"
sif !cpuis("LPC11E14")&&!cpuis("LPC11E36")&&!cpuis("LPC11E37")&&!cpuis("LPC11E37H")
bitfld.long 0x04 30. " [30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled"
endif
bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 18. " [18] ,Enable PIO1_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 17. " [17] ,Enable PIO1_17 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 12. " [12] ,Enable PIO1_12 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,Enable PIO1_11 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,Enable PIO1_8 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 6. " [6] ,Enable PIO1_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,Enable PIO1_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 3. " [3] ,Enable PIO1_3for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,Enable PIO1_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,Enable PIO1_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled"
endif
sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*")
group.long 0x48++0x03
line.long 0x00 "PORT_ENA2,GPIO Grouped Interrupt Port 2 Enable Register"
sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*")
sif cpuis("LPC11U6?JBD64")
bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
endif
elif cpuis("LPC11E66JBD48")||cpuis("LPC11E67JBD48")
bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64")
bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
else
bitfld.long 0x00 23. " ENA[23] ,Enable PIO2_23 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,Enable PIO2_22 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,Enable PIO2_21 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,Enable PIO2_20 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 19. " [19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,Enable PIO2_17 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,Enable PIO2_16 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Enable PIO2_14 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Enable PIO2_13 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Enable PIO2_12 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Enable PIO2_11 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Enable PIO2_10 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Enable PIO2_9 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Enable PIO2_8 for group interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled"
endif
endif
width 0x0B
tree.end
tree.end
tree "PINT (Pin Interrupt And Pattern Match Engine)"
base ad:0xA0004000
width 14.
group.long 0x00++0x07
line.long 0x00 "ISEL,Pin Interrupt Mode Register"
bitfld.long 0x00 7. " PMODE[7] ,Interrupt mode for pin 7 interrupt" "Edge,Level"
bitfld.long 0x00 6. " [6] ,Interrupt mode for pin 6 interrupt" "Edge,Level"
bitfld.long 0x00 5. " [5] ,Interrupt mode for pin 5 interrupt" "Edge,Level"
bitfld.long 0x00 4. " [4] ,Interrupt mode for pin 4 interrupt" "Edge,Level"
newline
bitfld.long 0x00 3. " [3] ,Interrupt mode for pin 3 interrupt" "Edge,Level"
bitfld.long 0x00 2. " [2] ,Interrupt mode for pin 2 interrupt" "Edge,Level"
bitfld.long 0x00 1. " [1] ,Interrupt mode for pin 1 interrupt" "Edge,Level"
bitfld.long 0x00 0. " [0] ,Interrupt mode for pin 0 interrupt" "Edge,Level"
line.long 0x04 "IENR_SET/CLR,Pin Interrupt Level Or Rising Edge Interrupt Enable Set/Clear Register"
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " ENRL[7] ,Enable the rising edge or level interrupt for pin 7 interrupt" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " [6] ,Enable the rising edge or level interrupt for pin 6 interrupt" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " [5] ,Enable the rising edge or level interrupt for pin 5 interrupt" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " [4] ,Enable the rising edge or level interrupt for pin 4 interrupt" "Disabled,Enabled"
newline
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " [3] ,Enable the rising edge or level interrupt for pin 3 interrupt" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " [2] ,Enable the rising edge or level interrupt for pin 2 interrupt" "Disabled,Enabled"
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " [1] ,Enable the rising edge or level interrupt for pin 1 interrupt" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " [0] ,Enable the rising edge or level interrupt for pin 0 interrupt" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "IENF_SET/CLR,Pin Interrupt Active Level Or Falling Edge Interrupt Enable Set/Clear Register"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENAF[7] ,Enable the falling edge or configures the active level interrupt for pin 7 interrupt" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Enable the falling edge or configures the active level interrupt for pin 6 interrupt" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Enable the falling edge or configures the active level interrupt for pin 5 interrupt" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Enable the falling edge or configures the active level interrupt for pin 4 interrupt" "Disabled,Enabled"
newline
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Enable the falling edge or configures the active level interrupt for pin 3 interrupt" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Enable the falling edge or configures the active level interrupt for pin 2 interrupt" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Enable the falling edge or configures the active level interrupt for pin 1 interrupt" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Enable the falling edge or configures the active level interrupt for pin 0 interrupt" "Disabled,Enabled"
group.long 0x1C++0x0B
line.long 0x00 "RISE,Pin Interrupt Rising Edge Register"
eventfld.long 0x00 7. " RDET[7] ,Rising edge detect for pin 7" "Not detected,Detected"
eventfld.long 0x00 6. " [6] ,Rising edge detect for pin 6" "Not detected,Detected"
eventfld.long 0x00 5. " [5] ,Rising edge detect for pin 5" "Not detected,Detected"
eventfld.long 0x00 4. " [4] ,Rising edge detect for pin 4" "Not detected,Detected"
newline
eventfld.long 0x00 3. " [3] ,Rising edge detect for pin 3" "Not detected,Detected"
eventfld.long 0x00 2. " [2] ,Rising edge detect for pin 2" "Not detected,Detected"
eventfld.long 0x00 1. " [1] ,Rising edge detect for pin 1" "Not detected,Detected"
eventfld.long 0x00 0. " [0] ,Rising edge detect for pin 0" "Not detected,Detected"
line.long 0x04 "FALL,Pin Interrupt Falling Edge Register"
eventfld.long 0x04 7. " FDET[7] ,Falling edge detect for pin 7" "Not detected,Detected"
eventfld.long 0x04 6. " [6] ,Falling edge detect for pin 6" "Not detected,Detected"
eventfld.long 0x04 5. " [5] ,Falling edge detect for pin 5" "Not detected,Detected"
eventfld.long 0x04 4. " [4] ,Falling edge detect for pin 4" "Not detected,Detected"
newline
eventfld.long 0x04 3. " [3] ,Falling edge detect for pin 3" "Not detected,Detected"
eventfld.long 0x04 2. " [2] ,Falling edge detect for pin 2" "Not detected,Detected"
eventfld.long 0x04 1. " [1] ,Falling edge detect for pin 1" "Not detected,Detected"
eventfld.long 0x04 0. " [0] ,Falling edge detect for pin 0" "Not detected,Detected"
line.long 0x08 "IST,Pin Interrupt Status Register"
bitfld.long 0x08 7. " PSTAT[7] ,Pin 7 interrupt status" "Not interrupt,Interrupt"
bitfld.long 0x08 6. " [6] ,Pin 6 interrupt status" "Not interrupt,Interrupt"
bitfld.long 0x08 5. " [5] ,Pin 5 interrupt status" "Not interrupt,Interrupt"
bitfld.long 0x08 4. " [4] ,Pin 4 interrupt status" "Not interrupt,Interrupt"
newline
bitfld.long 0x08 3. " [3] ,Pin 3 interrupt status" "Not interrupt,Interrupt"
bitfld.long 0x08 2. " [2] ,Pin 2 interrupt status" "Not interrupt,Interrupt"
bitfld.long 0x08 1. " [1] ,Pin 1 interrupt status" "Not interrupt,Interrupt"
bitfld.long 0x08 0. " [0] ,Pin 0 interrupt status" "Not interrupt,Interrupt"
newline
sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*")
group.long 0x28++0x0B
line.long 0x00 "PMCTRL,Pattern Match Interrupt Control Register"
hexmask.long.byte 0x00 24.--31. 1. " PMAT ,Current state of pattern matches"
bitfld.long 0x00 1. " ENA_RXEV ,RXEV output enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SEL_PMATCH ,8 bit interrupt control function selection" "Pin interrupt,Pattern match"
line.long 0x04 "PMSRC,Pattern Match Interrupt Bit-Slice Source Register"
bitfld.long 0x04 29.--31. " SRC[7] ,Input source for bit slice 7" "Input 0,Input 1,Input 2,Input 3,?..."
bitfld.long 0x04 26.--28. " [6] ,Input source for bit slice 6" "Input 0,Input 1,Input 2,Input 3,?..."
bitfld.long 0x04 23.--25. " [5] ,Input source for bit slice 5" "Input 0,Input 1,Input 2,Input 3,?..."
newline
bitfld.long 0x04 20.--22. " [4] ,Input source for bit slice 4" "Input 0,Input 1,Input 2,Input 3,?..."
bitfld.long 0x04 17.--19. " [3] ,Input source for bit slice 3" "Input 0,Input 1,Input 2,Input 3,?..."
bitfld.long 0x04 14.--16. " [2] ,Input source for bit slice 2" "Input 0,Input 1,Input 2,Input 3,?..."
newline
bitfld.long 0x04 11.--13. " [1] ,Input source for bit slice 1" "Input 0,Input 1,Input 2,Input 3,?..."
bitfld.long 0x04 8.--10. " [0] ,Input source for bit slice 0" "Input 0,Input 1,Input 2,Input 3,?..."
line.long 0x08 "PMCFG,Pattern Match Interrupt Bit Slice Configuration Register"
bitfld.long 0x08 29.--31. " CFG[7] ,Match contribution condition for bit slice 7" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
bitfld.long 0x08 26.--28. " [6] ,Match contribution condition for bit slice 6" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
bitfld.long 0x08 23.--25. " [5] ,Match contribution condition for bit slice 5" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
newline
bitfld.long 0x08 20.--22. " [4] ,Match contribution condition for bit slice 4" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
bitfld.long 0x08 17.--19. " [3] ,Match contribution condition for bit slice 3" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
bitfld.long 0x08 14.--16. " [2] ,Match contribution condition for bit slice 2" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
newline
bitfld.long 0x08 11.--13. " [1] ,Match contribution condition for bit slice 1" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
bitfld.long 0x08 8.--10. " [0] ,Match contribution condition for bit slice 0" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising||falling edge,High level,Low level,Constant 0,Event"
bitfld.long 0x08 6. " PROD_ENDPTS6 ,Determines whether slice 6 is an endpoint" "Not endpoint,Endpoint"
newline
bitfld.long 0x08 5. " PROD_ENDPTS5 ,Determines whether slice 5 is an endpoint" "Not endpoint,Endpoint"
bitfld.long 0x08 4. " PROD_ENDPTS4 ,Determines whether slice 4 is an endpoint" "Not endpoint,Endpoint"
bitfld.long 0x08 3. " PROD_ENDPTS3 ,Determines whether slice 3 is an endpoint" "Not endpoint,Endpoint"
newline
bitfld.long 0x08 2. " PROD_ENDPTS2 ,Determines whether slice 2 is an endpoint" "Not endpoint,Endpoint"
bitfld.long 0x08 1. " PROD_ENDPTS1 ,Determines whether slice 1 is an endpoint" "Not endpoint,Endpoint"
bitfld.long 0x08 0. " PROD_ENDPTS0 ,Determines whether slice 0 is an endpoint" "Not endpoint,Endpoint"
endif
width 0x0B
tree.end
sif cpuis("LPC11E6*")
tree "DMAC (DMA Controller)"
base ad:0x50004000
width 16.
group.long 0x00++0x03 "Global Control And Status Registers"
line.long 0x00 "CTRL,DMA Control Register"
bitfld.long 0x00 0. " ENABLE ,DMA controller master enable" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 2. " ACTIVEERRINT ,Error interrupts pending status" "Not pending,Pending"
bitfld.long 0x00 1. " ACTIVEINT ,Enabled interrupts pending status" "Not pending,Pending"
group.long 0x08++0x03
line.long 0x00 "SRAMBASE,SRAM Base Address Register"
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,Address bits 31:8 of the beginning of the DMA descriptor table"
newline
group.long 0x20++0x03 "Shared Registers"
line.long 0x00 "ENABLESET/CLR0,Channel Enable Set/Clear Read Register 0"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " ENA[15]_set/clr ,Enable for DMA channel 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14]_set/clr ,Enable for DMA channel 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13]_set/clr ,Enable for DMA channel 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12]_set/clr ,Enable for DMA channel 12" "Disabled,Enabled"
newline
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11]_set/clr ,Enable for DMA channel 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10]_set/clr ,Enable for DMA channel 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9]_set/clr ,Enable for DMA channel 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8]_set/clr ,Enable for DMA channel 8" "Disabled,Enabled"
newline
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7]_set/clr ,Enable for DMA channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6]_set/clr ,Enable for DMA channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5]_set/clr ,Enable for DMA channel 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4]_set/clr ,Enable for DMA channel 4" "Disabled,Enabled"
newline
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3]_set/clr ,Enable for DMA channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2]_set/clr ,Enable for DMA channel 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1]_set/clr ,Enable for DMA channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0]_set/clr ,Enable for DMA channel 0" "Disabled,Enabled"
newline
rgroup.long 0x30++0x03
line.long 0x00 "ACTIVE0,Active Status Register 0"
bitfld.long 0x00 15. " ACT[15] ,Active flag for DMA channel 15" "Not active,Active"
bitfld.long 0x00 14. " [14] ,Active flag for DMA channel 14" "Not active,Active"
bitfld.long 0x00 13. " [13] ,Active flag for DMA channel 13" "Not active,Active"
bitfld.long 0x00 12. " [12] ,Active flag for DMA channel 12" "Not active,Active"
bitfld.long 0x00 11. " [11] ,Active flag for DMA channel 11" "Not active,Active"
bitfld.long 0x00 10. " [10] ,Active flag for DMA channel 10" "Not active,Active"
newline
bitfld.long 0x00 9. " [9] ,Active flag for DMA channel 9" "Not active,Active"
bitfld.long 0x00 8. " [8] ,Active flag for DMA channel 8" "Not active,Active"
bitfld.long 0x00 7. " [7] ,Active flag for DMA channel 7" "Not active,Active"
bitfld.long 0x00 6. " [6] ,Active flag for DMA channel 6" "Not active,Active"
bitfld.long 0x00 5. " [5] ,Active flag for DMA channel 5" "Not active,Active"
bitfld.long 0x00 4. " [4] ,Active flag for DMA channel 4" "Not active,Active"
newline
bitfld.long 0x00 3. " [3] ,Active flag for DMA channel 3" "Not active,Active"
bitfld.long 0x00 2. " [2] ,Active flag for DMA channel 2" "Not active,Active"
bitfld.long 0x00 1. " [1] ,Active flag for DMA channel 1" "Not active,Active"
bitfld.long 0x00 0. " [0] ,Active flag for DMA channel 0" "Not active,Active"
rgroup.long 0x38++0x03
line.long 0x00 "BUSY0,Busy Status Register 0"
bitfld.long 0x00 15. " BSY[15] ,Busy flag for DMA channel 15" "Not busy,Busy"
bitfld.long 0x00 14. " [14] ,Busy flag for DMA channel 14" "Not busy,Busy"
bitfld.long 0x00 13. " [13] ,Busy flag for DMA channel 13" "Not busy,Busy"
bitfld.long 0x00 12. " [12] ,Busy flag for DMA channel 12" "Not busy,Busy"
bitfld.long 0x00 11. " [11] ,Busy flag for DMA channel 11" "Not busy,Busy"
bitfld.long 0x00 10. " [10] ,Busy flag for DMA channel 10" "Not busy,Busy"
newline
bitfld.long 0x00 9. " [9] ,Busy flag for DMA channel 9" "Not busy,Busy"
bitfld.long 0x00 8. " [8] ,Busy flag for DMA channel 8" "Not busy,Busy"
bitfld.long 0x00 7. " [7] ,Busy flag for DMA channel 7" "Not busy,Busy"
bitfld.long 0x00 6. " [6] ,Busy flag for DMA channel 6" "Not busy,Busy"
bitfld.long 0x00 5. " [5] ,Busy flag for DMA channel 5" "Not busy,Busy"
bitfld.long 0x00 4. " [4] ,Busy flag for DMA channel 4" "Not busy,Busy"
newline
bitfld.long 0x00 3. " [3] ,Busy flag for DMA channel 3" "Not busy,Busy"
bitfld.long 0x00 2. " [2] ,Busy flag for DMA channel 2" "Not busy,Busy"
bitfld.long 0x00 1. " [1] ,Busy flag for DMA channel 1" "Not busy,Busy"
bitfld.long 0x00 0. " [0] ,Busy flag for DMA channel 0" "Not busy,Busy"
group.long 0x40++0x03
line.long 0x00 "ERRINT0,Error Interrupt Register 0"
bitfld.long 0x00 15. " ERR[15] ,Error Interrupt flag for DMA channel 15" "Not active,Active"
bitfld.long 0x00 14. " [14] ,Error Interrupt flag for DMA channel 14" "Not active,Active"
bitfld.long 0x00 13. " [13] ,Error Interrupt flag for DMA channel 13" "Not active,Active"
bitfld.long 0x00 12. " [12] ,Error Interrupt flag for DMA channel 12" "Not active,Active"
bitfld.long 0x00 11. " [11] ,Error Interrupt flag for DMA channel 11" "Not active,Active"
bitfld.long 0x00 10. " [10] ,Error Interrupt flag for DMA channel 10" "Not active,Active"
newline
bitfld.long 0x00 9. " [9] ,Error Interrupt flag for DMA channel 9" "Not active,Active"
bitfld.long 0x00 8. " [8] ,Error Interrupt flag for DMA channel 8" "Not active,Active"
bitfld.long 0x00 7. " [7] ,Error Interrupt flag for DMA channel 7" "Not active,Active"
bitfld.long 0x00 6. " [6] ,Error Interrupt flag for DMA channel 6" "Not active,Active"
bitfld.long 0x00 5. " [5] ,Error Interrupt flag for DMA channel 5" "Not active,Active"
bitfld.long 0x00 4. " [4] ,Error Interrupt flag for DMA channel 4" "Not active,Active"
newline
bitfld.long 0x00 3. " [3] ,Error Interrupt flag for DMA channel 3" "Not active,Active"
bitfld.long 0x00 2. " [2] ,Error Interrupt flag for DMA channel 2" "Not active,Active"
bitfld.long 0x00 1. " [1] ,Error Interrupt flag for DMA channel 1" "Not active,Active"
bitfld.long 0x00 0. " [0] ,Error Interrupt flag for DMA channel 0" "Not active,Active"
group.long 0x48++0x03
line.long 0x00 "INTENSET/CLR0,Interrupt Enable Set/Clear Read Register 0"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " INTEN[15] ,Interrupt Enable for DMA channel 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,Interrupt Enable for DMA channel 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,Interrupt Enable for DMA channel 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,Interrupt Enable for DMA channel 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,Interrupt Enable for DMA channel 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,Interrupt Enable for DMA channel 10" "Disabled,Enabled"
newline
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,Interrupt Enable for DMA channel 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,Interrupt Enable for DMA channel 8" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,Interrupt Enable for DMA channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,Interrupt Enable for DMA channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,Interrupt Enable for DMA channel 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,Interrupt Enable for DMA channel 4" "Disabled,Enabled"
newline
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,Interrupt Enable for DMA channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,Interrupt Enable for DMA channel 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,Interrupt Enable for DMA channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,Interrupt Enable for DMA channel 0" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "INTA0,Interrupt A Register 0"
bitfld.long 0x00 15. " IA[15] ,Interrupt A status for DMA channel 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [14] ,Interrupt A status for DMA channel 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [13] ,Interrupt A status for DMA channel 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [12] ,Interrupt A status for DMA channel 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. " [11] ,Interrupt A status for DMA channel 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [10] ,Interrupt A status for DMA channel 10" "No interrupt,Interrupt"
newline
bitfld.long 0x00 9. " [9] ,Interrupt A status for DMA channel 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [8] ,Interrupt A status for DMA channel 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. " [7] ,Interrupt A status for DMA channel 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [6] ,Interrupt A status for DMA channel 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [5] ,Interrupt A status for DMA channel 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [4] ,Interrupt A status for DMA channel 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. " [3] ,Interrupt A status for DMA channel 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [2] ,Interrupt A status for DMA channel 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [1] ,Interrupt A status for DMA channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [0] ,Interrupt A status for DMA channel 0" "No interrupt,Interrupt"
group.long 0x60++0x03
line.long 0x00 "INTB0,Interrupt B Register 0"
bitfld.long 0x00 15. " IB[15] ,Interrupt B status for DMA channel 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [14] ,Interrupt B status for DMA channel 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [13] ,Interrupt B status for DMA channel 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [12] ,Interrupt B status for DMA channel 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. " [11] ,Interrupt B status for DMA channel 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [10] ,Interrupt B status for DMA channel 10" "No interrupt,Interrupt"
newline
bitfld.long 0x00 9. " [9] ,Interrupt B status for DMA channel 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [8] ,Interrupt B status for DMA channel 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. " [7] ,Interrupt B status for DMA channel 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [6] ,Interrupt B status for DMA channel 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [5] ,Interrupt B status for DMA channel 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [4] ,Interrupt B status for DMA channel 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. " [3] ,Interrupt B status for DMA channel 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [2] ,Interrupt B status for DMA channel 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [1] ,Interrupt B status for DMA channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [0] ,Interrupt B status for DMA channel 0" "No interrupt,Interrupt"
wgroup.long 0x68++0x03
line.long 0x00 "SETVALID0,Set Valid 0 Register"
bitfld.long 0x00 15. " SV[15] ,SETVALID control for DMA channel 15" "No effect,Set"
bitfld.long 0x00 14. " [14] ,SETVALID control for DMA channel 14" "No effect,Set"
bitfld.long 0x00 13. " [13] ,SETVALID control for DMA channel 13" "No effect,Set"
bitfld.long 0x00 12. " [12] ,SETVALID control for DMA channel 12" "No effect,Set"
bitfld.long 0x00 11. " [11] ,SETVALID control for DMA channel 11" "No effect,Set"
bitfld.long 0x00 10. " [10] ,SETVALID control for DMA channel 10" "No effect,Set"
newline
bitfld.long 0x00 9. " [9] ,SETVALID control for DMA channel 9" "No effect,Set"
bitfld.long 0x00 8. " [8] ,SETVALID control for DMA channel 8" "No effect,Set"
bitfld.long 0x00 7. " [7] ,SETVALID control for DMA channel 7" "No effect,Set"
bitfld.long 0x00 6. " [6] ,SETVALID control for DMA channel 6" "No effect,Set"
bitfld.long 0x00 5. " [5] ,SETVALID control for DMA channel 5" "No effect,Set"
bitfld.long 0x00 4. " [4] ,SETVALID control for DMA channel 4" "No effect,Set"
newline
bitfld.long 0x00 3. " [3] ,SETVALID control for DMA channel 3" "No effect,Set"
bitfld.long 0x00 2. " [2] ,SETVALID control for DMA channel 2" "No effect,Set"
bitfld.long 0x00 1. " [1] ,SETVALID control for DMA channel 1" "No effect,Set"
bitfld.long 0x00 0. " [0] ,SETVALID control for DMA channel 0" "No effect,Set"
wgroup.long 0x70++0x03
line.long 0x00 "SETTRIG0,Set Trigger 0 Register"
bitfld.long 0x00 15. " TRIG[15] ,Set Trigger control bit for DMA channel 15" "No effect,Set"
bitfld.long 0x00 14. " [14] ,Set Trigger control bit for DMA channel 14" "No effect,Set"
bitfld.long 0x00 13. " [13] ,Set Trigger control bit for DMA channel 13" "No effect,Set"
bitfld.long 0x00 12. " [12] ,Set Trigger control bit for DMA channel 12" "No effect,Set"
bitfld.long 0x00 11. " [11] ,Set Trigger control bit for DMA channel 11" "No effect,Set"
bitfld.long 0x00 10. " [10] ,Set Trigger control bit for DMA channel 10" "No effect,Set"
newline
bitfld.long 0x00 9. " [9] ,Set Trigger control bit for DMA channel 9" "No effect,Set"
bitfld.long 0x00 8. " [8] ,Set Trigger control bit for DMA channel 8" "No effect,Set"
bitfld.long 0x00 7. " [7] ,Set Trigger control bit for DMA channel 7" "No effect,Set"
bitfld.long 0x00 6. " [6] ,Set Trigger control bit for DMA channel 6" "No effect,Set"
bitfld.long 0x00 5. " [5] ,Set Trigger control bit for DMA channel 5" "No effect,Set"
bitfld.long 0x00 4. " [4] ,Set Trigger control bit for DMA channel 4" "No effect,Set"
newline
bitfld.long 0x00 3. " [3] ,Set Trigger control bit for DMA channel 3" "No effect,Set"
bitfld.long 0x00 2. " [2] ,Set Trigger control bit for DMA channel 2" "No effect,Set"
bitfld.long 0x00 1. " [1] ,Set Trigger control bit for DMA channel 1" "No effect,Set"
bitfld.long 0x00 0. " [0] ,Set Trigger control bit for DMA channel 0" "No effect,Set"
wgroup.long 0x78++0x03
line.long 0x00 "SETABORT0,Abort 0 Register"
bitfld.long 0x00 15. " ABORTCTRL[15] ,Abort control for DMA channel 15" "No effect,Abort"
bitfld.long 0x00 14. " [14] ,Abort control for DMA channel 14" "No effect,Abort"
bitfld.long 0x00 13. " [13] ,Abort control for DMA channel 13" "No effect,Abort"
bitfld.long 0x00 12. " [12] ,Abort control for DMA channel 12" "No effect,Abort"
bitfld.long 0x00 11. " [11] ,Abort control for DMA channel 11" "No effect,Abort"
bitfld.long 0x00 10. " [10] ,Abort control for DMA channel 10" "No effect,Abort"
newline
bitfld.long 0x00 9. " [9] ,Abort control for DMA channel 9" "No effect,Abort"
bitfld.long 0x00 8. " [8] ,Abort control for DMA channel 8" "No effect,Abort"
bitfld.long 0x00 7. " [7] ,Abort control for DMA channel 7" "No effect,Abort"
bitfld.long 0x00 6. " [6] ,Abort control for DMA channel 6" "No effect,Abort"
bitfld.long 0x00 5. " [5] ,Abort control for DMA channel 5" "No effect,Abort"
bitfld.long 0x00 4. " [4] ,Abort control for DMA channel 4" "No effect,Abort"
newline
bitfld.long 0x00 3. " [3] ,Abort control for DMA channel 3" "No effect,Abort"
bitfld.long 0x00 2. " [2] ,Abort control for DMA channel 2" "No effect,Abort"
bitfld.long 0x00 1. " [1] ,Abort control for DMA channel 1" "No effect,Abort"
bitfld.long 0x00 0. " [0] ,Abort control for DMA channel 0" "No effect,Abort"
width 12.
tree "Channels registers"
if (((per.l(ad:0x50004400+0x400))&(0x20))==(0x00))
group.long 0x400++0x03
line.long 0x00 "CFG0,Configuration Register For Channel 0"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x400++0x03
line.long 0x00 "CFG0,Configuration Register For Channel 0"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x400+0x04)++0x03
line.long 0x00 "CTLSTAT0,Control And Status Register For Channel 0"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x400+0x08)++0x03
line.long 0x00 "XFERCFG0,Transfer Configuration Register For Channel 0"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x410))&(0x20))==(0x00))
group.long 0x410++0x03
line.long 0x00 "CFG1,Configuration Register For Channel 1"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x410++0x03
line.long 0x00 "CFG1,Configuration Register For Channel 1"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x410+0x04)++0x03
line.long 0x00 "CTLSTAT1,Control And Status Register For Channel 1"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x410+0x08)++0x03
line.long 0x00 "XFERCFG1,Transfer Configuration Register For Channel 1"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x420))&(0x20))==(0x00))
group.long 0x420++0x03
line.long 0x00 "CFG2,Configuration Register For Channel 2"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x420++0x03
line.long 0x00 "CFG2,Configuration Register For Channel 2"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x420+0x04)++0x03
line.long 0x00 "CTLSTAT2,Control And Status Register For Channel 2"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x420+0x08)++0x03
line.long 0x00 "XFERCFG2,Transfer Configuration Register For Channel 2"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x430))&(0x20))==(0x00))
group.long 0x430++0x03
line.long 0x00 "CFG3,Configuration Register For Channel 3"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x430++0x03
line.long 0x00 "CFG3,Configuration Register For Channel 3"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x430+0x04)++0x03
line.long 0x00 "CTLSTAT3,Control And Status Register For Channel 3"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x430+0x08)++0x03
line.long 0x00 "XFERCFG3,Transfer Configuration Register For Channel 3"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x440))&(0x20))==(0x00))
group.long 0x440++0x03
line.long 0x00 "CFG4,Configuration Register For Channel 4"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x440++0x03
line.long 0x00 "CFG4,Configuration Register For Channel 4"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x440+0x04)++0x03
line.long 0x00 "CTLSTAT4,Control And Status Register For Channel 4"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x440+0x08)++0x03
line.long 0x00 "XFERCFG4,Transfer Configuration Register For Channel 4"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x450))&(0x20))==(0x00))
group.long 0x450++0x03
line.long 0x00 "CFG5,Configuration Register For Channel 5"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x450++0x03
line.long 0x00 "CFG5,Configuration Register For Channel 5"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x450+0x04)++0x03
line.long 0x00 "CTLSTAT5,Control And Status Register For Channel 5"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x450+0x08)++0x03
line.long 0x00 "XFERCFG5,Transfer Configuration Register For Channel 5"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x460))&(0x20))==(0x00))
group.long 0x460++0x03
line.long 0x00 "CFG6,Configuration Register For Channel 6"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x460++0x03
line.long 0x00 "CFG6,Configuration Register For Channel 6"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x460+0x04)++0x03
line.long 0x00 "CTLSTAT6,Control And Status Register For Channel 6"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x460+0x08)++0x03
line.long 0x00 "XFERCFG6,Transfer Configuration Register For Channel 6"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x470))&(0x20))==(0x00))
group.long 0x470++0x03
line.long 0x00 "CFG7,Configuration Register For Channel 7"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x470++0x03
line.long 0x00 "CFG7,Configuration Register For Channel 7"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x470+0x04)++0x03
line.long 0x00 "CTLSTAT7,Control And Status Register For Channel 7"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x470+0x08)++0x03
line.long 0x00 "XFERCFG7,Transfer Configuration Register For Channel 7"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x480))&(0x20))==(0x00))
group.long 0x480++0x03
line.long 0x00 "CFG8,Configuration Register For Channel 8"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x480++0x03
line.long 0x00 "CFG8,Configuration Register For Channel 8"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x480+0x04)++0x03
line.long 0x00 "CTLSTAT8,Control And Status Register For Channel 8"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x480+0x08)++0x03
line.long 0x00 "XFERCFG8,Transfer Configuration Register For Channel 8"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x490))&(0x20))==(0x00))
group.long 0x490++0x03
line.long 0x00 "CFG9,Configuration Register For Channel 9"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x490++0x03
line.long 0x00 "CFG9,Configuration Register For Channel 9"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x490+0x04)++0x03
line.long 0x00 "CTLSTAT9,Control And Status Register For Channel 9"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x490+0x08)++0x03
line.long 0x00 "XFERCFG9,Transfer Configuration Register For Channel 9"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x4A0))&(0x20))==(0x00))
group.long 0x4A0++0x03
line.long 0x00 "CFG10,Configuration Register For Channel 10"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x4A0++0x03
line.long 0x00 "CFG10,Configuration Register For Channel 10"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x4A0+0x04)++0x03
line.long 0x00 "CTLSTAT10,Control And Status Register For Channel 10"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x4A0+0x08)++0x03
line.long 0x00 "XFERCFG10,Transfer Configuration Register For Channel 10"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x4B0))&(0x20))==(0x00))
group.long 0x4B0++0x03
line.long 0x00 "CFG11,Configuration Register For Channel 11"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x4B0++0x03
line.long 0x00 "CFG11,Configuration Register For Channel 11"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x4B0+0x04)++0x03
line.long 0x00 "CTLSTAT11,Control And Status Register For Channel 11"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x4B0+0x08)++0x03
line.long 0x00 "XFERCFG11,Transfer Configuration Register For Channel 11"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x4C0))&(0x20))==(0x00))
group.long 0x4C0++0x03
line.long 0x00 "CFG12,Configuration Register For Channel 12"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x4C0++0x03
line.long 0x00 "CFG12,Configuration Register For Channel 12"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x4C0+0x04)++0x03
line.long 0x00 "CTLSTAT12,Control And Status Register For Channel 12"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x4C0+0x08)++0x03
line.long 0x00 "XFERCFG12,Transfer Configuration Register For Channel 12"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x4D0))&(0x20))==(0x00))
group.long 0x4D0++0x03
line.long 0x00 "CFG13,Configuration Register For Channel 13"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x4D0++0x03
line.long 0x00 "CFG13,Configuration Register For Channel 13"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x4D0+0x04)++0x03
line.long 0x00 "CTLSTAT13,Control And Status Register For Channel 13"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x4D0+0x08)++0x03
line.long 0x00 "XFERCFG13,Transfer Configuration Register For Channel 13"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x4E0))&(0x20))==(0x00))
group.long 0x4E0++0x03
line.long 0x00 "CFG14,Configuration Register For Channel 14"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x4E0++0x03
line.long 0x00 "CFG14,Configuration Register For Channel 14"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x4E0+0x04)++0x03
line.long 0x00 "CTLSTAT14,Control And Status Register For Channel 14"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x4E0+0x08)++0x03
line.long 0x00 "XFERCFG14,Transfer Configuration Register For Channel 14"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
if (((per.l(ad:0x50004400+0x4F0))&(0x20))==(0x00))
group.long 0x4F0++0x03
line.long 0x00 "CFG15,Configuration Register For Channel 15"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
else
group.long 0x4F0++0x03
line.long 0x00 "CFG15,Configuration Register For Channel 15"
bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3"
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
newline
bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst"
bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level"
bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active"
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
endif
rgroup.long (0x4F0+0x04)++0x03
line.long 0x00 "CTLSTAT15,Control And Status Register For Channel 15"
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending"
group.long (0x4F0+0x08)++0x03
line.long 0x00 "XFERCFG15,Transfer Configuration Register For Channel 15"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width"
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
newline
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
newline
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
tree.end
width 19.
base ad:0x40028000
tree "Configuration Registers"
group.long 0x0++0x03
line.long 0x00 "DMA_ITRIG_INMUX0,DMA Trigger Input Mux Register 0"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x4++0x03
line.long 0x00 "DMA_ITRIG_INMUX1,DMA Trigger Input Mux Register 1"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 1" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x8++0x03
line.long 0x00 "DMA_ITRIG_INMUX2,DMA Trigger Input Mux Register 2"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 2" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0xC++0x03
line.long 0x00 "DMA_ITRIG_INMUX3,DMA Trigger Input Mux Register 3"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 3" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x10++0x03
line.long 0x00 "DMA_ITRIG_INMUX4,DMA Trigger Input Mux Register 4"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 4" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x14++0x03
line.long 0x00 "DMA_ITRIG_INMUX5,DMA Trigger Input Mux Register 5"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 5" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x18++0x03
line.long 0x00 "DMA_ITRIG_INMUX6,DMA Trigger Input Mux Register 6"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 6" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x1C++0x03
line.long 0x00 "DMA_ITRIG_INMUX7,DMA Trigger Input Mux Register 7"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 7" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x20++0x03
line.long 0x00 "DMA_ITRIG_INMUX8,DMA Trigger Input Mux Register 8"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 8" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x24++0x03
line.long 0x00 "DMA_ITRIG_INMUX9,DMA Trigger Input Mux Register 9"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 9" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x28++0x03
line.long 0x00 "DMA_ITRIG_INMUX10,DMA Trigger Input Mux Register 10"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 10" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x2C++0x03
line.long 0x00 "DMA_ITRIG_INMUX11,DMA Trigger Input Mux Register 11"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 11" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x30++0x03
line.long 0x00 "DMA_ITRIG_INMUX12,DMA Trigger Input Mux Register 12"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 12" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x34++0x03
line.long 0x00 "DMA_ITRIG_INMUX13,DMA Trigger Input Mux Register 13"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 13" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x38++0x03
line.long 0x00 "DMA_ITRIG_INMUX14,DMA Trigger Input Mux Register 14"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 14" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
group.long 0x3C++0x03
line.long 0x00 "DMA_ITRIG_INMUX15,DMA Trigger Input Mux Register 15"
bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 15" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..."
tree.end
width 0x0B
tree.end
endif
sif cpuis("LPC11E11*")||cpuis("LPC11E12*")||cpuis("LPC11E13*")||cpuis("LPC11E14*")||cpuis("LPC11E35FHI33*")||cpuis("LPC11E36*")||cpuis("LPC11E37*")
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
base ad:0x40008000
width 15.
if (((per.l(ad:0x40008000+0x0C))&0x80)==0x00)
hgroup.long 0x00++0x03
hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register"
in
group.long 0x04++0x03
line.long 0x00 "IER,Interrupt Enable Register"
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud timeout interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. " ABEOINTEN ,End of auto-baud interrupt enable" "Disabled,Enabled"
sif cpuis("LPC11D14")||cpuis("LPC11C*")
bitfld.long 0x00 2. " RXLIE ,RX line interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " THREIE ,THRE interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " RBRIE ,RBR interrupt enable" "Disabled,Enabled"
else
bitfld.long 0x00 3. " MSINTEN ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RLSINTEN ,Receive line status interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " THREINTEN ,THRE interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RBRINTEN ,RBR interrupt enable" "Disabled,Enabled"
endif
else
group.long 0x00++0x07
line.long 0x00 "DLL,Divisor Latch LSB"
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,USART divisor latch LSB"
line.long 0x04 "DLM,Divisor Latch MSB"
hexmask.long.byte 0x04 0.--7. 1. " DLMSB ,USART divisor latch MSB"
endif
rgroup.long 0x08++0x03
line.long 0x00 "IIR,Interrupt ID"
bitfld.long 0x00 9. " ABTOINT ,Auto-baud timeout interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 8. " ABEOINT ,End of auto-baud interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6.--7. " FIFOEN ,FIFO enable" "0,1,2,3"
sif cpuis("LPC11C*")
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem interrupt,THRE,RDA,RLS,,,CTI,?..."
else
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem status,THRE,RDA,RLS,,,CTI,?..."
endif
newline
bitfld.long 0x00 0. " INTSTATUS ,Interrupt status" "Pending,Not pending"
wgroup.long 0x08++0x03
line.long 0x00 "FCR,FIFO Control Register"
bitfld.long 0x00 6.--7. " RXTL ,Rx trigger level select" "Level 0,Level 1,Level 2,Level 3"
sif !cpuis("LPC11D14")&&!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11C*")
bitfld.long 0x00 3. " DMAMODE ,DMA mode enable" "Disable,Enable"
endif
newline
bitfld.long 0x00 2. " TXFIFORES ,Transmitter FIFO reset" "No effect,Clear"
bitfld.long 0x00 1. " RXFIFORES ,Receiver FIFO reset" "No effect,Clear"
bitfld.long 0x00 0. " FIFOEN ,FIFO enable" "Disable,Enable"
if (((per.l(ad:0x40008000+0x0C))&0x03)==0x00)
group.long 0x0C++0x03
line.long 0x00 "LCR,Line Control Register"
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,1.5 bits"
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
else
group.long 0x0C++0x03
line.long 0x00 "LCR,Line Control Register"
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,2 bits"
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
endif
group.long 0x10++0x03
line.long 0x00 "MCR,USART0 Modem Control Register"
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
bitfld.long 0x00 4. " LMS ,Loopback mode select" "Disabled,Enabled"
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Active,Inactive"
newline
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Active,Inactive"
hgroup.long 0x14++0x03
hide.long 0x00 "LSR,Line Status Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "MSR,Modem Status Register"
in
group.long 0x1C++0x07
line.long 0x00 "SCR,Scratch Pad Register"
hexmask.long.byte 0x00 0.--7. 1. " PAD ,A readable/writable byte"
line.long 0x04 "ACR,Auto-Baud Control Register"
bitfld.long 0x04 9. " ABTOINTCLR ,Auto-baud timeout interrupt clear bit" "No effect,Cleared"
bitfld.long 0x04 8. " ABEOINTCLR ,End of auto-baud interrupt clear bit" "No effect,Cleared"
sif cpuis("LPC11C*")
bitfld.long 0x04 2. " AUTORESTART ,Automatic restart enable" "Disabled,Enabled"
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
else
bitfld.long 0x04 2. " AUTORESTART ,Start mode" "Not restarted,Restarted"
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
endif
newline
bitfld.long 0x04 0. " START ,Auto-baud start" "Stopped,Started"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
group.long 0x24++0x03
line.long 0x00 "ICR,IrDA Control Register"
bitfld.long 0x00 3.--5. " PULSEDIV ,Pulse width configure" "3/(16*baud rate),2*Tpclk,4*Tpclk,8*Tpclk,16*Tpclk,32*Tpclk,64*Tpclk,128*Tpclk"
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed pulse width mode enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IRDAINV ,Serial input invert" "Not inverted,Inverted"
bitfld.long 0x00 0. " IRDAEN ,IrDA mode enable" "Disabled,Enabled"
endif
group.long 0x28++0x03
line.long 0x00 "FDR,Fractional Divider Register"
bitfld.long 0x00 4.--7. " MULVAL ,Baud rate pre-scaler multiplier value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " DIVADDVAL ,Baud rate pre-scaler divisor value" ",None,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
if (((per.l(ad:0x40008000+0x48))&0x01)==0x00)
group.long 0x2C++0x03
line.long 0x00 "OSR,Oversampling Register"
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
else
group.long 0x2C++0x03
line.long 0x00 "OSR,Oversampling Register"
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
endif
endif
group.long 0x30++0x03
line.long 0x00 "TER,Transmit Enable Register"
bitfld.long 0x00 7. " TXEN ,Transmission enable" "Disabled,Enabled"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
group.long 0x40++0x03
line.long 0x00 "HDEN,USART Half-Duplex Enable Register"
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
if (((per.l(ad:0x40008000+0x48))&0x04)==0x00)
group.long 0x48++0x03
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs"
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
newline
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
else
group.long 0x48++0x03
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs"
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
endif
endif
group.long 0x4C++0x0B
line.long 0x00 "RS485CTRL,RS485 Control Register"
bitfld.long 0x00 5. " OINV ,Polarity control" "Not inverted,Inverted"
bitfld.long 0x00 4. " DCTRL ,Auto direction control enable" "Disabled,Enabled"
bitfld.long 0x00 3. " SEL ,Direction control pin select" "RTS,DTR"
bitfld.long 0x00 2. " AADEN ,Auto address detect enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes"
bitfld.long 0x00 0. " NMMEN ,Normal multidrop mode enable" "Disabled,Enabled"
line.long 0x04 "RS485ADRMATCH,RS485 Address Match Register"
hexmask.long.byte 0x04 0.--7. 1. " ADRMATCH ,Address match value"
line.long 0x08 "RS485DLY,RS-485 Delay Value Register"
hexmask.long.byte 0x08 0.--7. 1. " DLY ,Direction control RTS or DTR delay value"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
if (((per.l(ad:0x40008000+0x58))&0x02)==0x02)
group.long 0x58++0x03
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
newline
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
else
group.long 0x58++0x03
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
newline
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
endif
endif
width 0x0B
tree.end
endif
sif cpu()=="LPC11E66JBD48"||cpu()=="LPC11E67JBD100"||cpu()=="LPC11E67JBD48"||cpu()=="LPC11E67JBD64"||cpu()=="LPC11E68JBD100"||cpu()=="LPC11E68JBD48"||cpu()=="LPC11E68JBD64"
tree.open "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
tree "USART0"
base ad:0x40008000
width 15.
if (((per.l(ad:0x40008000+0x0C))&0x80)==0x00)
hgroup.long 0x00++0x03
hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register"
in
group.long 0x04++0x03
line.long 0x00 "IER,Interrupt Enable Register"
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud timeout interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. " ABEOINTEN ,End of auto-baud interrupt enable" "Disabled,Enabled"
sif cpuis("LPC11D14")||cpuis("LPC11C*")
bitfld.long 0x00 2. " RXLIE ,RX line interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " THREIE ,THRE interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " RBRIE ,RBR interrupt enable" "Disabled,Enabled"
else
bitfld.long 0x00 3. " MSINTEN ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RLSINTEN ,Receive line status interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " THREINTEN ,THRE interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RBRINTEN ,RBR interrupt enable" "Disabled,Enabled"
endif
else
group.long 0x00++0x07
line.long 0x00 "DLL,Divisor Latch LSB"
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,USART divisor latch LSB"
line.long 0x04 "DLM,Divisor Latch MSB"
hexmask.long.byte 0x04 0.--7. 1. " DLMSB ,USART divisor latch MSB"
endif
rgroup.long 0x08++0x03
line.long 0x00 "IIR,Interrupt ID"
bitfld.long 0x00 9. " ABTOINT ,Auto-baud timeout interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 8. " ABEOINT ,End of auto-baud interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6.--7. " FIFOEN ,FIFO enable" "0,1,2,3"
sif cpuis("LPC11C*")
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem interrupt,THRE,RDA,RLS,,,CTI,?..."
else
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem status,THRE,RDA,RLS,,,CTI,?..."
endif
newline
bitfld.long 0x00 0. " INTSTATUS ,Interrupt status" "Pending,Not pending"
wgroup.long 0x08++0x03
line.long 0x00 "FCR,FIFO Control Register"
bitfld.long 0x00 6.--7. " RXTL ,Rx trigger level select" "Level 0,Level 1,Level 2,Level 3"
sif !cpuis("LPC11D14")&&!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11C*")
bitfld.long 0x00 3. " DMAMODE ,DMA mode enable" "Disable,Enable"
endif
newline
bitfld.long 0x00 2. " TXFIFORES ,Transmitter FIFO reset" "No effect,Clear"
bitfld.long 0x00 1. " RXFIFORES ,Receiver FIFO reset" "No effect,Clear"
bitfld.long 0x00 0. " FIFOEN ,FIFO enable" "Disable,Enable"
if (((per.l(ad:0x40008000+0x0C))&0x03)==0x00)
group.long 0x0C++0x03
line.long 0x00 "LCR,Line Control Register"
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,1.5 bits"
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
else
group.long 0x0C++0x03
line.long 0x00 "LCR,Line Control Register"
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,2 bits"
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
endif
group.long 0x10++0x03
line.long 0x00 "MCR,USART0 Modem Control Register"
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
bitfld.long 0x00 4. " LMS ,Loopback mode select" "Disabled,Enabled"
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Active,Inactive"
newline
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Active,Inactive"
hgroup.long 0x14++0x03
hide.long 0x00 "LSR,Line Status Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "MSR,Modem Status Register"
in
group.long 0x1C++0x07
line.long 0x00 "SCR,Scratch Pad Register"
hexmask.long.byte 0x00 0.--7. 1. " PAD ,A readable/writable byte"
line.long 0x04 "ACR,Auto-Baud Control Register"
bitfld.long 0x04 9. " ABTOINTCLR ,Auto-baud timeout interrupt clear bit" "No effect,Cleared"
bitfld.long 0x04 8. " ABEOINTCLR ,End of auto-baud interrupt clear bit" "No effect,Cleared"
sif cpuis("LPC11C*")
bitfld.long 0x04 2. " AUTORESTART ,Automatic restart enable" "Disabled,Enabled"
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
else
bitfld.long 0x04 2. " AUTORESTART ,Start mode" "Not restarted,Restarted"
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
endif
newline
bitfld.long 0x04 0. " START ,Auto-baud start" "Stopped,Started"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
group.long 0x24++0x03
line.long 0x00 "ICR,IrDA Control Register"
bitfld.long 0x00 3.--5. " PULSEDIV ,Pulse width configure" "3/(16*baud rate),2*Tpclk,4*Tpclk,8*Tpclk,16*Tpclk,32*Tpclk,64*Tpclk,128*Tpclk"
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed pulse width mode enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IRDAINV ,Serial input invert" "Not inverted,Inverted"
bitfld.long 0x00 0. " IRDAEN ,IrDA mode enable" "Disabled,Enabled"
endif
group.long 0x28++0x03
line.long 0x00 "FDR,Fractional Divider Register"
bitfld.long 0x00 4.--7. " MULVAL ,Baud rate pre-scaler multiplier value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " DIVADDVAL ,Baud rate pre-scaler divisor value" ",None,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
if (((per.l(ad:0x40008000+0x48))&0x01)==0x00)
group.long 0x2C++0x03
line.long 0x00 "OSR,Oversampling Register"
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
else
group.long 0x2C++0x03
line.long 0x00 "OSR,Oversampling Register"
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
endif
endif
group.long 0x30++0x03
line.long 0x00 "TER,Transmit Enable Register"
bitfld.long 0x00 7. " TXEN ,Transmission enable" "Disabled,Enabled"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
group.long 0x40++0x03
line.long 0x00 "HDEN,USART Half-Duplex Enable Register"
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
if (((per.l(ad:0x40008000+0x48))&0x04)==0x00)
group.long 0x48++0x03
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs"
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
newline
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
else
group.long 0x48++0x03
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs"
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
endif
endif
group.long 0x4C++0x0B
line.long 0x00 "RS485CTRL,RS485 Control Register"
bitfld.long 0x00 5. " OINV ,Polarity control" "Not inverted,Inverted"
bitfld.long 0x00 4. " DCTRL ,Auto direction control enable" "Disabled,Enabled"
bitfld.long 0x00 3. " SEL ,Direction control pin select" "RTS,DTR"
bitfld.long 0x00 2. " AADEN ,Auto address detect enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes"
bitfld.long 0x00 0. " NMMEN ,Normal multidrop mode enable" "Disabled,Enabled"
line.long 0x04 "RS485ADRMATCH,RS485 Address Match Register"
hexmask.long.byte 0x04 0.--7. 1. " ADRMATCH ,Address match value"
line.long 0x08 "RS485DLY,RS-485 Delay Value Register"
hexmask.long.byte 0x08 0.--7. 1. " DLY ,Direction control RTS or DTR delay value"
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
if (((per.l(ad:0x40008000+0x58))&0x02)==0x02)
group.long 0x58++0x03
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
newline
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
else
group.long 0x58++0x03
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
newline
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
endif
endif
width 0x0B
tree.end
tree "USART1"
base ad:0x40070000
width 15.
if (((per.l(ad:0x40070000))&0x800)==0x800)
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration Register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..."
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits"
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
endif
if (((per.l(ad:0x40070000))&0x01)==0x01)&&(((per.l(ad:0x40070000+0x08))&0x03)==0x03)
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
newline
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
else
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
endif
group.long 0x08++0x0F
line.long 0x00 "STAT,USART Status Register"
eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred"
eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred"
newline
eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started"
eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected"
rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received"
eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred"
newline
rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected"
rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High"
rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle"
newline
rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle"
rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register"
setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled"
hgroup.long 0x14++0x03
hide.long 0x00 "RXDAT,Receiver Data Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register"
in
group.long 0x1C++0x07
line.long 0x00 "TXDAT,Transmit Data Register"
hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register"
line.long 0x04 "BRG,Baud Rate Generator Register"
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value"
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error"
bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error"
bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error"
newline
bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error"
bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active"
bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
group.long 0x28++0x07
line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication"
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16"
line.long 0x04 "ADDR,Address Register For Automatic Address Matching"
hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching"
width 0x0B
tree.end
tree "USART2"
base ad:0x40074000
width 15.
if (((per.l(ad:0x40074000))&0x800)==0x800)
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration Register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..."
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits"
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
endif
if (((per.l(ad:0x40074000))&0x01)==0x01)&&(((per.l(ad:0x40074000+0x08))&0x03)==0x03)
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
newline
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
else
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
endif
group.long 0x08++0x0F
line.long 0x00 "STAT,USART Status Register"
eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred"
eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred"
newline
eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started"
eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected"
rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received"
eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred"
newline
rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected"
rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High"
rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle"
newline
rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle"
rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register"
setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled"
hgroup.long 0x14++0x03
hide.long 0x00 "RXDAT,Receiver Data Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register"
in
group.long 0x1C++0x07
line.long 0x00 "TXDAT,Transmit Data Register"
hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register"
line.long 0x04 "BRG,Baud Rate Generator Register"
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value"
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error"
bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error"
bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error"
newline
bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error"
bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active"
bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
group.long 0x28++0x07
line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication"
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16"
line.long 0x04 "ADDR,Address Register For Automatic Address Matching"
hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching"
width 0x0B
tree.end
tree "USART3"
base ad:0x40078000
width 15.
if (((per.l(ad:0x40078000))&0x800)==0x800)
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration Register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..."
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits"
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
endif
if (((per.l(ad:0x40078000))&0x01)==0x01)&&(((per.l(ad:0x40078000+0x08))&0x03)==0x03)
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
newline
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
else
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
endif
group.long 0x08++0x0F
line.long 0x00 "STAT,USART Status Register"
eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred"
eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred"
newline
eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started"
eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected"
rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received"
eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred"
newline
rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected"
rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High"
rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle"
newline
rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle"
rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register"
setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled"
hgroup.long 0x14++0x03
hide.long 0x00 "RXDAT,Receiver Data Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register"
in
group.long 0x1C++0x07
line.long 0x00 "TXDAT,Transmit Data Register"
hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register"
line.long 0x04 "BRG,Baud Rate Generator Register"
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value"
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error"
bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error"
bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error"
newline
bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error"
bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active"
bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
group.long 0x28++0x07
line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication"
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16"
line.long 0x04 "ADDR,Address Register For Automatic Address Matching"
hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching"
width 0x0B
tree.end
sif cpu()=="LPC11E67JBD100"||cpu()=="LPC11E68JBD100"
tree "USART4"
base ad:0x4004C000
width 15.
if (((per.l(ad:0x4004C000))&0x800)==0x800)
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration Register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..."
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted"
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted"
bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High"
bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback"
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
newline
bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising"
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz"
newline
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits"
bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd"
bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..."
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
endif
if (((per.l(ad:0x4004C000))&0x01)==0x01)&&(((per.l(ad:0x4004C000+0x08))&0x03)==0x03)
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
newline
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
else
group.long 0x04++0x0F
line.long 0x00 "CTL,USART Control Register"
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous"
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes"
bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled"
endif
group.long 0x08++0x0F
line.long 0x00 "STAT,USART Status Register"
eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred"
eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred"
newline
eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started"
eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected"
rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received"
eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred"
newline
rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred"
eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected"
rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High"
rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle"
newline
rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle"
rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register"
setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled"
newline
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled"
hgroup.long 0x14++0x03
hide.long 0x00 "RXDAT,Receiver Data Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register"
in
group.long 0x1C++0x07
line.long 0x00 "TXDAT,Transmit Data Register"
hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register"
line.long 0x04 "BRG,Baud Rate Generator Register"
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value"
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error"
bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error"
bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error"
newline
bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error"
bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active"
bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready"
bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready"
group.long 0x28++0x07
line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication"
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16"
line.long 0x04 "ADDR,Address Register For Automatic Address Matching"
hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching"
width 0x0B
tree.end
endif
tree.end
endif
tree.open "I2C (Inter-Integrated Circuit)"
tree "I2C0"
base ad:0x40000000
width 18.
group.long 0x00++0x03
line.long 0x00 "CON,I2C0 Control Register"
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
newline
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
rgroup.long 0x04++0x03
line.long 0x00 "STAT,I2C0 Status Register"
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
newline
group.long 0x08++0x0F
line.long 0x00 "DAT,I2C0 Data Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
line.long 0x04 "ADR0,I2C0 Slave Address Register 0"
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Slave mode address"
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
line.long 0x08 "SCLH,I2C0 SCL High Duty Cycle Register"
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL HIGH time period selection"
line.long 0x0C "SCLL,I2C0 SCL Low Duty Cycle Register"
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL LOW time period selection"
group.long 0x1C++0x03
line.long 0x00 "MMCTRL,I2C0 Monitor Mode Control Register"
sif cpuis("LPC1311")||cpuis("LPC1313")||cpuis("LPC1342")||cpuis("LPC1343")||cpuis("EM773")||cpuis("LPC11A02")||cpuis("LPC11A04")||cpuis("LPC11A11")||cpuis("LPC11A12")||cpuis("LPC11A13")||cpuis("LPC11A14")
bitfld.long 0x00 3. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
else
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
endif
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
group.long 0x20++0x03
line.long 0x00 "ADR1,I2C0 Slave Address Register 1"
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
group.long 0x24++0x03
line.long 0x00 "ADR2,I2C0 Slave Address Register 2"
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
group.long 0x28++0x03
line.long 0x00 "ADR3,I2C0 Slave Address Register 3"
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
sif cpuis("LPC4072FBD80")||cpuis("LPC4072FET80")||cpuis("LPC4074FBD144")||cpuis("LPC4076FBD144")||cpuis("LPC4076FET180")||cpuis("LPC4078FBD100")||cpuis("LPC4078FBD144")||cpuis("LPC4078FBD208")||cpuis("LPC4078FBD80")||cpuis("LPC4078FET180")||cpuis("LPC4078FET208")||(cpu()=="LPC4088FBD144")||cpuis("LPC4088FBD208")||cpuis("LPC4088FET180")||cpuis("LPC4088FET208")||cpuis("LPC11E*")
group.long 0x2C++0x03
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
elif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")
rgroup.long 0x2C++0x03
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
else
hgroup.long 0x2C++0x03
hide.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
in
endif
group.long 0x30++0x03
line.long 0x00 "MASK0,I2C0 Mask Register 0"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
group.long 0x34++0x03
line.long 0x00 "MASK1,I2C0 Mask Register 1"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
group.long 0x38++0x03
line.long 0x00 "MASK2,I2C0 Mask Register 2"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
group.long 0x3C++0x03
line.long 0x00 "MASK3,I2C0 Mask Register 3"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
width 0x0B
tree.end
sif cpuis("LPC11E6*")
tree "I2C1"
base ad:0x40020000
width 18.
group.long 0x00++0x03
line.long 0x00 "CON,I2C1 Control Register"
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
newline
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
rgroup.long 0x04++0x03
line.long 0x00 "STAT,I2C1 Status Register"
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
newline
group.long 0x08++0x0F
line.long 0x00 "DAT,I2C1 Data Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
line.long 0x04 "ADR0,I2C1 Slave Address Register 0"
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Slave mode address"
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
line.long 0x08 "SCLH,I2C1 SCL High Duty Cycle Register"
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL HIGH time period selection"
line.long 0x0C "SCLL,I2C1 SCL Low Duty Cycle Register"
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL LOW time period selection"
group.long 0x1C++0x03
line.long 0x00 "MMCTRL,I2C1 Monitor Mode Control Register"
sif cpuis("LPC1311")||cpuis("LPC1313")||cpuis("LPC1342")||cpuis("LPC1343")||cpuis("EM773")||cpuis("LPC11A02")||cpuis("LPC11A04")||cpuis("LPC11A11")||cpuis("LPC11A12")||cpuis("LPC11A13")||cpuis("LPC11A14")
bitfld.long 0x00 3. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
else
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
endif
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
group.long 0x20++0x03
line.long 0x00 "ADR1,I2C1 Slave Address Register 1"
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
group.long 0x24++0x03
line.long 0x00 "ADR2,I2C1 Slave Address Register 2"
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
group.long 0x28++0x03
line.long 0x00 "ADR3,I2C1 Slave Address Register 3"
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
sif cpuis("LPC4072FBD80")||cpuis("LPC4072FET80")||cpuis("LPC4074FBD144")||cpuis("LPC4076FBD144")||cpuis("LPC4076FET180")||cpuis("LPC4078FBD100")||cpuis("LPC4078FBD144")||cpuis("LPC4078FBD208")||cpuis("LPC4078FBD80")||cpuis("LPC4078FET180")||cpuis("LPC4078FET208")||(cpu()=="LPC4088FBD144")||cpuis("LPC4088FBD208")||cpuis("LPC4088FET180")||cpuis("LPC4088FET208")||cpuis("LPC11E*")
group.long 0x2C++0x03
line.long 0x00 "DATA_BUFFER,I2C1 Data Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
elif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")
rgroup.long 0x2C++0x03
line.long 0x00 "DATA_BUFFER,I2C1 Data Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
else
hgroup.long 0x2C++0x03
hide.long 0x00 "DATA_BUFFER,I2C1 Data Buffer Register"
in
endif
group.long 0x30++0x03
line.long 0x00 "MASK0,I2C1 Mask Register 0"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
group.long 0x34++0x03
line.long 0x00 "MASK1,I2C1 Mask Register 1"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
group.long 0x38++0x03
line.long 0x00 "MASK2,I2C1 Mask Register 2"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
group.long 0x3C++0x03
line.long 0x00 "MASK3,I2C1 Mask Register 3"
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
width 0x0B
tree.end
endif
tree.end
tree.open "SSP0/1 (Synchronous Serial Port)"
tree "SSP0"
base ad:0x40040000
width 7.
if (((per.l(ad:0x40040000))&0x30)==0x00)
group.long 0x00++0x03
line.long 0x00 "CR0,Control Register 0"
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First transition,Second transition"
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
newline
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
else
group.long 0x00++0x03
line.long 0x00 "CR0,Control Register 0"
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
newline
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
endif
if (((per.l(ad:0x40040000+0x04))&0x02)==0x02)
group.long 0x04++0x03
line.long 0x00 "CR1,Control Register 1"
bitfld.long 0x00 3. " SOD ,Slave output disabled" "No,Yes"
rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LBM ,Loop back mode" "Serial input,Serial output"
else
group.long 0x04++0x03
line.long 0x00 "CR1,Control Register 1"
bitfld.long 0x00 3. " SOD ,Slave output disabled" "No,Yes"
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LBM ,Loop back mode" "Serial input,Serial output"
endif
hgroup.long 0x08++0x03
hide.long 0x00 "DR,Data Register"
in
rgroup.long 0x0C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 4. " BSY ,Busy" "Not busy,Busy"
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "No,Yes"
newline
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "No,Yes"
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
group.long 0x10++0x07
line.long 0x00 "CPSR,Clock Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Prescaler output clock"
line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register"
bitfld.long 0x04 3. " TXIM ,Tx FIFO half empty interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 2. " RXIM ,Rx FIFO half full interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 1. " RTIM ,Rx FIFO receive time-out condition interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RORIM ,Rx FIFO receive overrun interrupt enable" "Disabled,Enabled"
rgroup.long 0x18++0x07
line.long 0x00 "RIS,Raw Interrupt Status Register"
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty raw interrupt status" "Not occurred,Occurred"
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full raw interrupt status" "Not occurred,Occurred"
bitfld.long 0x00 1. " RTRIS ,Rx FIFO not empty raw interrupt status" "Not occurred,Occurred"
bitfld.long 0x00 0. " RORRIS ,Rx FIFO full raw interrupt status" "Not occurred,Occurred"
line.long 0x04 "MIS,Masked Interrupt Status Register"
bitfld.long 0x04 3. " TXMIS ,Tx FIFO half empty masked interrupt status" "Not occurred,Occurred"
bitfld.long 0x04 2. " RXMIS ,Rx FIFO half full masked interrupt status" "Not occurred,Occurred"
bitfld.long 0x04 1. " RTMIS ,Rx FIFO not empty masked interrupt status" "Not occurred,Occurred"
bitfld.long 0x04 0. " RORMIS ,Rx FIFO full masked interrupt status" "Not occurred,Occurred"
wgroup.long 0x20++0x03
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 1. " RTIC ,RX FIFO was not empty interrupt clear" "Not cleared,Cleared"
bitfld.long 0x00 0. " RORIC ,Frame was received when RX FIFO was full interrupt clear" "Not cleared,Cleared"
sif cpuis("LPC11E6*")
group.long 0x24++0x03
line.long 0x00 "DMACR,DMA Control Register"
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
endif
width 0x0B
tree.end
tree "SSP1"
base ad:0x40058000
width 7.
if (((per.l(ad:0x40058000))&0x30)==0x00)
group.long 0x00++0x03
line.long 0x00 "CR0,Control Register 0"
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First transition,Second transition"
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
newline
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
else
group.long 0x00++0x03
line.long 0x00 "CR0,Control Register 0"
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
newline
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
endif
if (((per.l(ad:0x40058000+0x04))&0x02)==0x02)
group.long 0x04++0x03
line.long 0x00 "CR1,Control Register 1"
bitfld.long 0x00 3. " SOD ,Slave output disabled" "No,Yes"
rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LBM ,Loop back mode" "Serial input,Serial output"
else
group.long 0x04++0x03
line.long 0x00 "CR1,Control Register 1"
bitfld.long 0x00 3. " SOD ,Slave output disabled" "No,Yes"
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LBM ,Loop back mode" "Serial input,Serial output"
endif
hgroup.long 0x08++0x03
hide.long 0x00 "DR,Data Register"
in
rgroup.long 0x0C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 4. " BSY ,Busy" "Not busy,Busy"
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "No,Yes"
newline
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "No,Yes"
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
group.long 0x10++0x07
line.long 0x00 "CPSR,Clock Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Prescaler output clock"
line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register"
bitfld.long 0x04 3. " TXIM ,Tx FIFO half empty interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 2. " RXIM ,Rx FIFO half full interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 1. " RTIM ,Rx FIFO receive time-out condition interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RORIM ,Rx FIFO receive overrun interrupt enable" "Disabled,Enabled"
rgroup.long 0x18++0x07
line.long 0x00 "RIS,Raw Interrupt Status Register"
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty raw interrupt status" "Not occurred,Occurred"
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full raw interrupt status" "Not occurred,Occurred"
bitfld.long 0x00 1. " RTRIS ,Rx FIFO not empty raw interrupt status" "Not occurred,Occurred"
bitfld.long 0x00 0. " RORRIS ,Rx FIFO full raw interrupt status" "Not occurred,Occurred"
line.long 0x04 "MIS,Masked Interrupt Status Register"
bitfld.long 0x04 3. " TXMIS ,Tx FIFO half empty masked interrupt status" "Not occurred,Occurred"
bitfld.long 0x04 2. " RXMIS ,Rx FIFO half full masked interrupt status" "Not occurred,Occurred"
bitfld.long 0x04 1. " RTMIS ,Rx FIFO not empty masked interrupt status" "Not occurred,Occurred"
bitfld.long 0x04 0. " RORMIS ,Rx FIFO full masked interrupt status" "Not occurred,Occurred"
wgroup.long 0x20++0x03
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 1. " RTIC ,RX FIFO was not empty interrupt clear" "Not cleared,Cleared"
bitfld.long 0x00 0. " RORIC ,Frame was received when RX FIFO was full interrupt clear" "Not cleared,Cleared"
sif cpuis("LPC11E6*")
group.long 0x24++0x03
line.long 0x00 "DMACR,DMA Control Register"
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
endif
width 0x0B
tree.end
tree.end
sif cpuis("LPC11E6*")
tree "USB2.0 (Full-Speed Device Controller)"
base ad:0x40080000
width 14.
group.long 0x00++0x2F
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status Register"
rbitfld.long 0x00 28. " VBUSDEBOUNCED ,Vbus detect indication" "Not detected,Detected"
eventfld.long 0x00 26. " DRES_C ,Device status - reset change" "No reset,Reset"
eventfld.long 0x00 25. " DSUS_C ,Device status - suspend change" "Not toggled,Toggled"
eventfld.long 0x00 24. " DCON_C ,Device status - connect change" "Not occurred,Occurred"
newline
rbitfld.long 0x00 20. " LPM_REWP ,LPM remote wake-up enabled by USB host" "Disabled,Enabled"
bitfld.long 0x00 19. " LPM_SUS ,Device status - LPM suspend" "Not suspended,Suspended"
bitfld.long 0x00 17. " DSUS ,Device status - suspend" "Not suspended,Suspended"
bitfld.long 0x00 16. " DCON ,Device status - connect" "Not connected,Connected"
newline
bitfld.long 0x00 15. " INTONNAK_CI ,Interrupt on NAK for control IN EP" "AK,AK & NAK"
bitfld.long 0x00 14. " INTONNAK_CO ,Interrupt on NAK for control OUT EP" "AK,AK & NAK"
bitfld.long 0x00 13. " INTONNAK_AI ,Interrupt on NAK for interrupt and bulk IN EP" "AK,AK & NAK"
bitfld.long 0x00 12. " INTONNAK_AO ,Interrupt on NAK for interrupt and bulk OUT EP" "AK,AK & NAK"
newline
bitfld.long 0x00 11. " LPM_SUP ,LPM support" "Not supported,Supported"
bitfld.long 0x00 9. " PLL_ON ,PLL clock on" "Functional,High"
eventfld.long 0x00 8. " SETUP ,SETUP token received" "Not received,Received"
bitfld.long 0x00 7. " DEV_EN ,USB device enable" "Disabled,Enabled"
newline
hexmask.long.byte 0x00 0.--6. 0x01 " DEV_ADDR ,USB device address"
line.long 0x04 "INFO,USB Info Register"
bitfld.long 0x04 11.--14. " ERR_CODE ,Last occurred error code" "No error,PID encoding error,PID unknown,Packet unexpected,Token CRC error,Data CRC error,Time out,Babble,Truncated EOP,Sent/Received NAK,Sent Stall,Overrun,Sent empty packet,Bitstuff error,Sync error,Wrong data toggle"
hexmask.long.word 0x04 0.--10. 1. " FRAME_NR ,Frame number"
line.long 0x08 "EPLISTSTART,USB EP Command/Status List Start Address"
hexmask.long.tbyte 0x08 8.--31. 0x01 " EP_LIST ,Start address of the USB EP command/status list"
line.long 0x0C "DATABUFSTART,USB Data Buffer Start Address"
hexmask.long.word 0x0C 22.--31. 0x40 " DA_BUF ,Start address of the buffer pointer page"
line.long 0x10 "LPM,Link Power Management"
bitfld.long 0x10 8. " DATA_PENDING ,Data pending" "Not pending,Pending"
bitfld.long 0x10 4.--7. " HIRD_SW ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x10 0.--3. " HIRD_HW ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "EPSKIP,USB Endpoint Skip"
bitfld.long 0x14 29. " SKIP[29] ,Endpoint 29 skip request" "Not occurred,Occurred"
bitfld.long 0x14 28. " [28] ,Endpoint 28 skip request" "Not occurred,Occurred"
bitfld.long 0x14 27. " [27] ,Endpoint 27 skip request" "Not occurred,Occurred"
bitfld.long 0x14 26. " [26] ,Endpoint 26 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 25. " [25] ,Endpoint 25 skip request" "Not occurred,Occurred"
bitfld.long 0x14 24. " [24] ,Endpoint 24 skip request" "Not occurred,Occurred"
bitfld.long 0x14 23. " [23] ,Endpoint 23 skip request" "Not occurred,Occurred"
bitfld.long 0x14 22. " [22] ,Endpoint 22 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 21. " [21] ,Endpoint 21 skip request" "Not occurred,Occurred"
bitfld.long 0x14 20. " [20] ,Endpoint 20 skip request" "Not occurred,Occurred"
bitfld.long 0x14 19. " [19] ,Endpoint 19 skip request" "Not occurred,Occurred"
bitfld.long 0x14 18. " [18] ,Endpoint 18 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 17. " [17] ,Endpoint 17 skip request" "Not occurred,Occurred"
bitfld.long 0x14 16. " [16] ,Endpoint 16 skip request" "Not occurred,Occurred"
bitfld.long 0x14 15. " [15] ,Endpoint 15 skip request" "Not occurred,Occurred"
bitfld.long 0x14 14. " [14] ,Endpoint 14 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 13. " [13] ,Endpoint 13 skip request" "Not occurred,Occurred"
bitfld.long 0x14 12. " [12] ,Endpoint 12 skip request" "Not occurred,Occurred"
bitfld.long 0x14 11. " [11] ,Endpoint 11 skip request" "Not occurred,Occurred"
bitfld.long 0x14 10. " [10] ,Endpoint 10 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 9. " [9] ,Endpoint 9 skip request" "Not occurred,Occurred"
bitfld.long 0x14 8. " [8] ,Endpoint 8 skip request" "Not occurred,Occurred"
bitfld.long 0x14 7. " [7] ,Endpoint 7 skip request" "Not occurred,Occurred"
bitfld.long 0x14 6. " [6] ,Endpoint 6 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 5. " [5] ,Endpoint 5 skip request" "Not occurred,Occurred"
bitfld.long 0x14 4. " [4] ,Endpoint 4 skip request" "Not occurred,Occurred"
bitfld.long 0x14 3. " [3] ,Endpoint 3 skip request" "Not occurred,Occurred"
bitfld.long 0x14 2. " [2] ,Endpoint 2 skip request" "Not occurred,Occurred"
newline
bitfld.long 0x14 1. " [1] ,Endpoint 1 skip request" "Not occurred,Occurred"
bitfld.long 0x14 0. " [0] ,Endpoint 0 skip request" "Not occurred,Occurred"
line.long 0x18 "EPINUSE,USB Endpoint Buffer In Use"
bitfld.long 0x18 9. " BUF[9] ,Endpoint 9 buffer in use" "Buffer 0,Buffer 1"
bitfld.long 0x18 8. " [8] ,Endpoint 8 buffer in use" "Buffer 0,Buffer 1"
bitfld.long 0x18 7. " [7] ,Endpoint 7 buffer in use" "Buffer 0,Buffer 1"
bitfld.long 0x18 6. " [6] ,Endpoint 6 buffer in use" "Buffer 0,Buffer 1"
newline
bitfld.long 0x18 5. " [5] ,Endpoint 5 buffer in use" "Buffer 0,Buffer 1"
bitfld.long 0x18 4. " [4] ,Endpoint 4 buffer in use" "Buffer 0,Buffer 1"
bitfld.long 0x18 3. " [3] ,Endpoint 3 buffer in use" "Buffer 0,Buffer 1"
bitfld.long 0x18 2. " [2] ,Endpoint 2 buffer in use" "Buffer 0,Buffer 1"
line.long 0x1C "EPBUFCFG,USB Endpoint Buffer Configuration"
bitfld.long 0x1C 9. " BUF_SB[9] ,Endpoint 9 buffer usage" "Single-buffer,Double-buffer"
bitfld.long 0x1C 8. " [8] ,Endpoint 8 buffer usage" "Single-buffer,Double-buffer"
bitfld.long 0x1C 7. " [7] ,Endpoint 7 buffer usage" "Single-buffer,Double-buffer"
bitfld.long 0x1C 6. " [6] ,Endpoint 6 buffer usage" "Single-buffer,Double-buffer"
newline
bitfld.long 0x1C 5. " [5] ,Endpoint 5 buffer usage" "Single-buffer,Double-buffer"
bitfld.long 0x1C 4. " [4] ,Endpoint 4 buffer usage" "Single-buffer,Double-buffer"
bitfld.long 0x1C 3. " [3] ,Endpoint 3 buffer usage" "Single-buffer,Double-buffer"
bitfld.long 0x1C 2. " [2] ,Endpoint 2 buffer usage" "Single-buffer,Double-buffer"
line.long 0x20 "INTSTAT,USB Interrupt Status Register"
eventfld.long 0x20 31. " DEV_INT ,Device status interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 30. " FRAME_INT ,Frame interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 9. " EP4IN ,EP4 IN interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 8. " EP4OUT ,EP4 OUT interrupt status" "No interrupt,Interrupt"
newline
eventfld.long 0x20 7. " EP3IN ,EP3 IN interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 6. " EP3OUT ,EP3 OUT interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 5. " EP2IN ,EP2 IN interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 4. " EP2OUT ,EP2 OUT interrupt status" "No interrupt,Interrupt"
newline
eventfld.long 0x20 3. " EP1IN ,EP1 IN interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 2. " EP1OUT ,EP1 OUT interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 1. " EP0IN ,EP0 IN interrupt status" "No interrupt,Interrupt"
eventfld.long 0x20 0. " EP0OUT ,EP0 OUT interrupt status" "No interrupt,Interrupt"
line.long 0x24 "INTEN,USB Interrupt Enable Register"
bitfld.long 0x24 31. " DEV_INT_EN ,DEV interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 30. " FRAME_INT_EN ,FRAME interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 9. " EP4IN_INT_EN ,EP4IN interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 8. " EP4OUT_INT_EN ,EP4OUT interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x24 7. " EP3IN_INT_EN ,EP3IN interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 6. " EP3OUT_INT_EN ,EP3OUT interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 5. " EP2IN_INT_EN ,EP2IN interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 4. " EP2OUT_INT_EN ,EP2OUT interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x24 3. " EP1IN_INT_EN ,EP1IN interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 2. " EP1OUT_INT_EN ,EP1OUT interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 1. " EP0IN_INT_EN ,EP0IN interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 0. " EP0OUT_INT_EN ,EP0OUT interrupt enable" "Disabled,Enabled"
line.long 0x28 "INTSETSTAT,USB Set Interrupt Status Register"
bitfld.long 0x28 31. " DEV_SET_INT ,DEV set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 30. " FRAME_SET_INT ,FRAME set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 9. " EP4IN_SET_INT ,EP4IN set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 8. " EP4OUT_SET_INT ,EP4OUT set interrupt status" "No interrupt,Interrupt"
newline
bitfld.long 0x28 7. " EP3IN_SET_INT ,EP3IN set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 6. " EP3OUT_SET_INT ,EP3OUT set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 5. " EP2IN_SET_INT ,EP2IN set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 4. " EP2OUT_SET_INT ,EP2OUT set interrupt status" "No interrupt,Interrupt"
newline
bitfld.long 0x28 3. " EP1IN_SET_INT ,EP1IN set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 2. " EP1OUT_SET_INT ,EP1OUT set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 1. " EP0IN_SET_INT ,EP0IN set interrupt status" "No interrupt,Interrupt"
bitfld.long 0x28 0. " EP0OUT_SET_INT ,EP0OUT set interrupt status" "No interrupt,Interrupt"
line.long 0x2C "INTROUTING,USB Interrupt Routing Register"
bitfld.long 0x2C 31. " DEV_INT_ROUTE_INT ,Hardware interrupt line for DEV_INT select" "IRQ,FIQ"
bitfld.long 0x2C 30. " FRAME_INT_ROUTE_INT ,Hardware interrupt line for FRAME_INT select" "IRQ,FIQ"
bitfld.long 0x2C 9. " EP4IN_ROUTE_INT ,Hardware interrupt line for EP4IN select" "IRQ,FIQ"
bitfld.long 0x2C 8. " EP4OUT_ROUTE_INT ,Hardware interrupt line for EP4OUT select" "IRQ,FIQ"
newline
bitfld.long 0x2C 7. " EP3IN_ROUTE_INT ,Hardware interrupt line for EP3IN select" "IRQ,FIQ"
bitfld.long 0x2C 6. " EP3OUT_ROUTE_INT ,Hardware interrupt line for EP3OUT select" "IRQ,FIQ"
bitfld.long 0x2C 5. " EP2IN_ROUTE_INT ,Hardware interrupt line for EP2IN select" "IRQ,FIQ"
bitfld.long 0x2C 4. " EP2OUT_ROUTE_INT ,Hardware interrupt line for EP2OUT select" "IRQ,FIQ"
newline
bitfld.long 0x2C 3. " EP1IN_ROUTE_INT ,Hardware interrupt line for EP1IN select" "IRQ,FIQ"
bitfld.long 0x2C 2. " EP1OUT_ROUTE_INT ,Hardware interrupt line for EP1OUT select" "IRQ,FIQ"
bitfld.long 0x2C 1. " EP0IN_ROUTE_INT ,Hardware interrupt line for EP0IN select" "IRQ,FIQ"
bitfld.long 0x2C 0. " EP0OUT_ROUTE_INT ,Hardware interrupt line for EP0OUT select" "IRQ,FIQ"
rgroup.long 0x34++0x03
line.long 0x00 "EPTOGGLE,USB Endpoint Toggle"
bitfld.long 0x00 9. " EP4IN_TOGGLE ,Endpoint EP4IN data toggle value" "0,1"
bitfld.long 0x00 8. " EP4OUT_TOGGLE ,Endpoint EP4OUT data toggle value" "0,1"
bitfld.long 0x00 7. " EP3IN_TOGGLE ,Endpoint EP3IN data toggle value" "0,1"
bitfld.long 0x00 6. " EP3OUT_TOGGLE ,Endpoint EP3OUT data toggle value" "0,1"
newline
bitfld.long 0x00 5. " EP2IN_TOGGLE ,Endpoint EP2IN data toggle value" "0,1"
bitfld.long 0x00 4. " EP2OUT_TOGGLE ,Endpoint EP2OUT data toggle value" "0,1"
bitfld.long 0x00 3. " EP1IN_TOGGLE ,Endpoint EP1IN data toggle value" "0,1"
bitfld.long 0x00 2. " EP1OUT_TOGGLE ,Endpoint EP1OUT data toggle value" "0,1"
newline
bitfld.long 0x00 1. " EP0IN_TOGGLE ,Endpoint EP0IN data toggle value" "0,1"
bitfld.long 0x00 0. " EP0OUT_TOGGLE ,Endpoint EP0OUT data toggle value" "0,1"
width 0x0B
tree.end
endif
tree "ADC (Analog-to-Digital Converter)"
base ad:0x4001C000
sif cpuis("LPC11E6*")
width 13.
group.long 0x00++0x03
line.long 0x00 "CTRL,A/D Control Register"
bitfld.long 0x00 30. " CALMODE ,Writing a 1 to this bit initiates a self-calibration cycle" "Not initiated,Initiated"
bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock divide value"
if (((per.l((ad:0x4001C000+0x08)))&0x80000000)==0x00)
group.long 0x08++0x03
line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register"
bitfld.long 0x00 31. " SEQA_ENA ,Sequence enable" "Disabled,Enabled"
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
newline
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
newline
bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7"
newline
sif cpuis("LPC112*")
bitfld.long 0x00 8. " CHANNEL[8] ,Include channel 8 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
newline
bitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
newline
bitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
else
bitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included"
endif
newline
bitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included"
newline
bitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
bitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
endif
newline
bitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
endif
endif
else
group.long 0x08++0x03
line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register"
bitfld.long 0x00 31. " SEQA_ENA ,Sequence enable" "Disabled,Enabled"
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
newline
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
newline
bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7"
newline
sif cpuis("LPC112*")
rbitfld.long 0x00 8. " CHANNEL[8] ,Include channel 8 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
newline
rbitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
newline
rbitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
else
rbitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
rbitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included"
endif
newline
rbitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included"
newline
rbitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
rbitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
endif
newline
rbitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
rbitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
endif
endif
endif
if (((per.l((ad:0x4001C000+0x0C)))&0x80000000)==0x00)
group.long 0x0C++0x03
line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register"
bitfld.long 0x00 31. " SEQB_ENA ,Sequence enable" "Disabled,Enabled"
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
newline
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
newline
bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7"
newline
sif cpuis("LPC112*")
bitfld.long 0x00 8. " CHANNEL[8] ,Include channel 8 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
newline
bitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
newline
bitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
else
bitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included"
endif
newline
bitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included"
newline
bitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
bitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
endif
newline
bitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
bitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
endif
endif
else
group.long 0x0C++0x03
line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register"
bitfld.long 0x00 31. " SEQB_ENA ,Sequence enable" "Disabled,Enabled"
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
newline
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
newline
bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7"
newline
sif cpuis("LPC112*")
rbitfld.long 0x00 8. " CHANNEL[8] ,Include channel 8 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
newline
rbitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
newline
rbitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
else
rbitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
rbitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included"
endif
newline
rbitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included"
newline
rbitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
rbitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included"
endif
newline
rbitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included"
rbitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included"
sif !cpuis("LPC11U6??BD48")&&!cpuis("LPC11E6?JBD48")
newline
rbitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included"
endif
endif
endif
sif cpuis("LPC11E6*")||cpuis("LPC112*")
hgroup.long 0x10++0x03
hide.long 0x00 "SEQA_GDAT,A/D Sequence-A Global Data Register"
in
hgroup.long 0x14++0x03
hide.long 0x00 "SEQB_GDAT,A/D Sequence-B Global Data Register"
in
else
group.long 0x10++0x07
line.long 0x00 "SEQA_GDAT,A/D Sequence-A Global Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
line.long 0x04 "SEQB_GDAT,A/D Sequence-B Global Data Register"
bitfld.long 0x04 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x04 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x04 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x04 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x04 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x04 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
endif
width 7.
sif cpuis("LPC112*")
tree "Channels 1-8 Data Registers"
hgroup.long 0x24++0x03
hide.long 0x00 "DAT1,A/D Channel 1 Data Register"
in
hgroup.long 0x28++0x03
hide.long 0x00 "DAT2,A/D Channel 2 Data Register"
in
hgroup.long 0x2C++0x03
hide.long 0x00 "DAT3,A/D Channel 3 Data Register"
in
hgroup.long 0x30++0x03
hide.long 0x00 "DAT4,A/D Channel 4 Data Register"
in
hgroup.long 0x34++0x03
hide.long 0x00 "DAT5,A/D Channel 5 Data Register"
in
hgroup.long 0x38++0x03
hide.long 0x00 "DAT6,A/D Channel 6 Data Register"
in
hgroup.long 0x3C++0x03
hide.long 0x00 "DAT7,A/D Channel 7 Data Register"
in
hgroup.long 0x40++0x03
hide.long 0x00 "DAT8,A/D Channel 8 Data Register"
in
tree.end
elif cpuis("LPC11E6**")
tree "Channels 0-12 Data Registers"
hgroup.long 0x20++0x03
hide.long 0x00 "DAT0,A/D Channel 0 Data Register"
in
hgroup.long 0x24++0x03
hide.long 0x00 "DAT1,A/D Channel 1 Data Register"
in
hgroup.long 0x28++0x03
hide.long 0x00 "DAT2,A/D Channel 2 Data Register"
in
hgroup.long 0x2C++0x03
hide.long 0x00 "DAT3,A/D Channel 3 Data Register"
in
hgroup.long 0x30++0x03
hide.long 0x00 "DAT4,A/D Channel 4 Data Register"
in
hgroup.long 0x34++0x03
hide.long 0x00 "DAT5,A/D Channel 5 Data Register"
in
hgroup.long 0x38++0x03
hide.long 0x00 "DAT6,A/D Channel 6 Data Register"
in
hgroup.long 0x3C++0x03
hide.long 0x00 "DAT7,A/D Channel 7 Data Register"
in
hgroup.long 0x40++0x03
hide.long 0x00 "DAT8,A/D Channel 8 Data Register"
in
hgroup.long 0x44++0x03
hide.long 0x00 "DAT9,A/D Channel 9 Data Register"
in
hgroup.long 0x48++0x03
hide.long 0x00 "DAT10,A/D Channel 10 Data Register"
in
hgroup.long 0x4C++0x03
hide.long 0x00 "DAT11,A/D Channel 11 Data Register"
in
tree.end
else
tree "Channels 0-11 Data Registers"
sif !cpuis("LPC11U3??BD48")&&!cpuis("LPC11E6?JBD48")
rgroup.long 0x20++0x03
line.long 0x00 "DAT0,A/D Channel 0 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
endif
rgroup.long 0x24++0x03
line.long 0x00 "DAT1,A/D Channel 1 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
rgroup.long 0x28++0x03
line.long 0x00 "DAT2,A/D Channel 2 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
rgroup.long 0x2C++0x03
line.long 0x00 "DAT3,A/D Channel 3 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
rgroup.long 0x30++0x03
line.long 0x00 "DAT4,A/D Channel 4 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
rgroup.long 0x34++0x03
line.long 0x00 "DAT5,A/D Channel 5 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
endif
rgroup.long 0x38++0x03
line.long 0x00 "DAT6,A/D Channel 6 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
rgroup.long 0x3C++0x03
line.long 0x00 "DAT7,A/D Channel 7 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
rgroup.long 0x40++0x03
line.long 0x00 "DAT8,A/D Channel 8 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
rgroup.long 0x44++0x03
line.long 0x00 "DAT9,A/D Channel 9 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
sif !cpuis("LPC11U3??BD48")&&!cpuis("LPC11E6?JBD48")
rgroup.long 0x48++0x03
line.long 0x00 "DAT10,A/D Channel 10 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
endif
rgroup.long 0x4C++0x03
line.long 0x00 "DAT11,A/D Channel 11 Data Register"
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
newline
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
tree.end
endif
width 13.
newline
group.long 0x50++0x1F
line.long 0x00 "THR0_LOW,A/D Low Compare Threshold Register 0"
hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared"
line.long 0x04 "THR1_LOW,A/D Low Compare Threshold Register 1"
hexmask.long.word 0x04 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared"
line.long 0x08 "THR0_HIGH,A/D High Compare Threshold Register 0"
hexmask.long.word 0x08 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared"
line.long 0x0c "THR1_HIGH,A/D High Compare Threshold Register 1"
hexmask.long.word 0x0c 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared"
line.long 0x10 "CHAN_THRSEL,A/D Channel-Threshold Select Register"
sif cpuis("LPC112*")
bitfld.long 0x10 8. " CH[8]_THRSEL ,Threshold select by channel 8" "Threshold 0,Threshold 1"
bitfld.long 0x10 7. " [7] ,Threshold select by channel 7" "Threshold 0,Threshold 1"
bitfld.long 0x10 6. " [6] ,Threshold select by channel 6" "Threshold 0,Threshold 1"
bitfld.long 0x10 5. " [5] ,Threshold select by channel 5" "Threshold 0,Threshold 1"
newline
bitfld.long 0x10 4. " [4] ,Threshold select by channel 4" "Threshold 0,Threshold 1"
bitfld.long 0x10 3. " [3] ,Threshold select by channel 3" "Threshold 0,Threshold 1"
bitfld.long 0x10 2. " [2] ,Threshold select by channel 2" "Threshold 0,Threshold 1"
bitfld.long 0x10 1. " [1] ,Threshold select by channel 1" "Threshold 0,Threshold 1"
newline
bitfld.long 0x10 0. " [0] ,Threshold select by channel 0" "Threshold 0,Threshold 1"
else
bitfld.long 0x10 11. " CH[11]_THRSEL ,Threshold select by channel 11" "Threshold 0,Threshold 1"
sif !cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x10 10. " [10] ,Threshold select by channel 10" "Threshold 0,Threshold 1"
endif
newline
bitfld.long 0x10 9. " [9] ,Threshold select by channel 9" "Threshold 0,Threshold 1"
bitfld.long 0x10 8. " [8] ,Threshold select by channel 8" "Threshold 0,Threshold 1"
newline
bitfld.long 0x10 7. " [7] ,Threshold select by channel 7" "Threshold 0,Threshold 1"
bitfld.long 0x10 6. " [6] ,Threshold select by channel 6" "Threshold 0,Threshold 1"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
bitfld.long 0x10 5. " [5] ,Threshold select by channel 5" "Threshold 0,Threshold 1"
bitfld.long 0x10 4. " [4] ,Threshold select by channel 4" "Threshold 0,Threshold 1"
endif
newline
bitfld.long 0x10 3. " [3] ,Threshold select by channel 3" "Threshold 0,Threshold 1"
bitfld.long 0x10 2. " [2] ,Threshold select by channel 2" "Threshold 0,Threshold 1"
bitfld.long 0x10 1. " [1] ,Threshold select by channel 1" "Threshold 0,Threshold 1"
sif !cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x10 0. " [0] ,Threshold select by channel 0" "Threshold 0,Threshold 1"
endif
endif
line.long 0x14 "INTEN,A/D Interrupt Enable Register"
sif cpuis("LPC112*")
bitfld.long 0x14 19.--20. " ADCMPINTEN[8] ,Threshold comparison for channel 8 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 17.--18. " [7] ,Threshold comparison for channel 7 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 15.--16. " [6] ,Threshold comparison for channel 6 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 13.--14. " [5] ,Threshold comparison for channel 5 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
newline
bitfld.long 0x14 11.--12. " [4] ,Threshold comparison for channel 4 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 9.--10. " [3] ,Threshold comparison for channel 3 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 7.--8. " [2] ,Threshold comparison for channel 2 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 5.--6. " [1] ,Threshold comparison for channel 1 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
newline
bitfld.long 0x14 3.--4. " [0] ,Threshold comparison for channel 0 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
else
bitfld.long 0x14 25.--26. " ADCMPINTEN[11] ,Threshold comparison for channel 11 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
sif !cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x14 23.--24. " [10] ,Threshold comparison for channel 10 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
endif
newline
bitfld.long 0x14 21.--22. " [9] ,Threshold comparison for channel 9 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 19.--20. " [8] ,Threshold comparison for channel 8 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
newline
bitfld.long 0x14 17.--18. " [7] ,Threshold comparison for channel 7 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 15.--16. " [6] ,Threshold comparison for channel 6 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
bitfld.long 0x14 13.--14. " [5] ,Threshold comparison for channel 5 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 11.--12. " [4] ,Threshold comparison for channel 4 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
endif
newline
bitfld.long 0x14 9.--10. " [3] ,Threshold comparison for channel 3 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 7.--8. " [2] ,Threshold comparison for channel 2 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
bitfld.long 0x14 5.--6. " [1] ,Threshold comparison for channel 1 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
sif !cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x14 3.--4. " [0] ,Threshold comparison for channel 0 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
endif
endif
newline
bitfld.long 0x14 2. " OVR_INTEN ,Overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 1. " SEQB_INTEN ,Sequence B interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 0. " SEQA_INTEN ,Sequence A interrupt enable" "Disabled,Enabled"
line.long 0x18 "FLAGS,A/D Flags Register"
bitfld.long 0x18 31. " OVR_INT ,Overrun interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x18 30. " THCMP_INT ,Threshold Comparison Interrupt" "No interrupt,Interrupt"
bitfld.long 0x18 29. " SEQB_INT ,Sequence B interrupt/DMA trigger" "No interrupt,Interrupt"
bitfld.long 0x18 28. " SEQA_INT ,Sequence A interrupt/DMA trigger" "No interrupt,Interrupt"
newline
bitfld.long 0x18 25. " SEQB_OVR ,Mirrors the global OVERRUN status flag in the SEQB_GDAT register" "No overrun,Overrun"
bitfld.long 0x18 24. " SEQA_OVR ,Mirrors the global OVERRUN status flag in the SEQA_GDAT register" "No overrun,Overrun"
newline
sif cpuis("LPC112*")
bitfld.long 0x18 20. " OVERRUN[8] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 8" "No overrun,Overrun"
bitfld.long 0x18 19. " [7] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 7" "No overrun,Overrun"
bitfld.long 0x18 18. " [6] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 6" "No overrun,Overrun"
bitfld.long 0x18 17. " [5] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 5" "No overrun,Overrun"
newline
bitfld.long 0x18 16. " [4] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 4" "No overrun,Overrun"
bitfld.long 0x18 15. " [3] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 3" "No overrun,Overrun"
bitfld.long 0x18 14. " [2] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 2" "No overrun,Overrun"
bitfld.long 0x18 13. " [1] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 1" "No overrun,Overrun"
newline
bitfld.long 0x18 12. " [0] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 0" "No overrun,Overrun"
newline
eventfld.long 0x18 8. " THCMP[8] ,Threshold comparison event on Channel 8" "Not occurred,Occurred"
eventfld.long 0x18 7. " [7] ,Threshold comparison event on Channel 7" "Not occurred,Occurred"
eventfld.long 0x18 6. " [6] ,Threshold comparison event on Channel 6" "Not occurred,Occurred"
eventfld.long 0x18 5. " [5] ,Threshold comparison event on Channel 5" "Not occurred,Occurred"
newline
eventfld.long 0x18 4. " [4] ,Threshold comparison event on Channel 4" "Not occurred,Occurred"
eventfld.long 0x18 3. " [3] ,Threshold comparison event on Channel 3" "Not occurred,Occurred"
eventfld.long 0x18 2. " [2] ,Threshold comparison event on Channel 2" "Not occurred,Occurred"
eventfld.long 0x18 1. " [1] ,Threshold comparison event on Channel 1" "Not occurred,Occurred"
newline
eventfld.long 0x18 0. " [0] ,Threshold comparison event on Channel 0" "Not occurred,Occurred"
else
bitfld.long 0x18 23. " OVERRUN[11] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 11" "No overrun,Overrun"
sif !cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x18 22. " [10] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 10" "No overrun,Overrun"
endif
newline
bitfld.long 0x18 21. " [9] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 9" "No overrun,Overrun"
bitfld.long 0x18 20. " [8] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 8" "No overrun,Overrun"
newline
bitfld.long 0x18 19. " [7] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 7" "No overrun,Overrun"
bitfld.long 0x18 18. " [6] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 6" "No overrun,Overrun"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
bitfld.long 0x18 17. " [5] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 5" "No overrun,Overrun"
bitfld.long 0x18 16. " [4] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 4" "No overrun,Overrun"
endif
newline
bitfld.long 0x18 15. " [3] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 3" "No overrun,Overrun"
bitfld.long 0x18 14. " [2] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 2" "No overrun,Overrun"
bitfld.long 0x18 13. " [1] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 1" "No overrun,Overrun"
sif !cpuis("LPC11E6?JBD48")
newline
bitfld.long 0x18 12. " [0] ,Mirrors the OVERRRUN status flag from the result register for A/D channel 0" "No overrun,Overrun"
endif
newline
eventfld.long 0x18 11. " THCMP[11] ,Threshold comparison event on Channel 11" "Not occurred,Occurred"
sif !cpuis("LPC11E6?JBD48")
newline
eventfld.long 0x18 10. " [10] ,Threshold comparison event on Channel 10" "Not occurred,Occurred"
endif
newline
eventfld.long 0x18 9. " [9] ,Threshold comparison event on Channel 9" "Not occurred,Occurred"
eventfld.long 0x18 8. " [8] ,Threshold comparison event on Channel 8" "Not occurred,Occurred"
newline
eventfld.long 0x18 7. " [7] ,Threshold comparison event on Channel 7" "Not occurred,Occurred"
eventfld.long 0x18 6. " [6] ,Threshold comparison event on Channel 6" "Not occurred,Occurred"
sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")
newline
eventfld.long 0x18 5. " [5] ,Threshold comparison event on Channel 5" "Not occurred,Occurred"
eventfld.long 0x18 4. " [4] ,Threshold comparison event on Channel 4" "Not occurred,Occurred"
endif
newline
eventfld.long 0x18 3. " [3] ,Threshold comparison event on Channel 3" "Not occurred,Occurred"
eventfld.long 0x18 2. " [2] ,Threshold comparison event on Channel 2" "Not occurred,Occurred"
eventfld.long 0x18 1. " [1] ,Threshold comparison event on Channel 1" "Not occurred,Occurred"
sif !cpuis("LPC11E6?JBD48")
newline
eventfld.long 0x18 0. " [0] ,Threshold comparison event on Channel 0" "Not occurred,Occurred"
endif
endif
line.long 0x1C "TRM,ADC Trim Register"
bitfld.long 0x1C 5. " VRANGE ,Voltage supply range" "2.7 V - 3.6 V,2.4 V - 2.7 V"
width 0x0B
else
width 10.
if (((per.l(ad:0x4001C000)&0x07000000)==0x00))||(((per.l(ad:0x4001C000)&0x07000000)==0x01000000))
group.long 0x00++0x03
line.long 0x00 "CR,A/D Control Register"
newline
sif cpuis("LPC1102")||cpuis("LPC1104")
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,,,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
else
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on CT16B0_CAP0,Edge on CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
endif
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
bitfld.long 0x00 16. " BURST ,Conversion control mode" "Software,Repeated"
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider"
newline
sif cpuis("LPC1102")||cpuis("LPC1104")
bitfld.long 0x00 4. " SEL[4] ,AD4 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
newline
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
else
bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion" "Not selected,Selected"
newline
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
endif
else
group.long 0x00++0x03
line.long 0x00 "CR,A/D Control Register"
bitfld.long 0x00 27. " EDGE ,Start conversion edge" "Rising,Falling"
newline
sif cpuis("LPC1102")||cpuis("LPC1104")
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,,,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
else
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on CT16B0_CAP0,Edge on CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
endif
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
bitfld.long 0x00 16. " BURST ,Conversion control mode" "Software,Repeated"
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider"
newline
sif cpuis("LPC1102")||cpuis("LPC1104")
bitfld.long 0x00 4. " SEL[4] ,AD4 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
newline
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
else
bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion" "Not selected,Selected"
newline
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
endif
endif
hgroup.long 0x04++0x03
hide.long 0x00 "GDR,A/D Global Data Register"
in
newline
group.long 0x0C++0x03
line.long 0x00 "INTEN,A/D Interrupt Enable Register"
bitfld.long 0x00 8. " ADGINTEN ,Source of generated interrupt" "Individual,Global"
newline
sif cpuis("LPC1102")||cpuis("LPC1104")
bitfld.long 0x00 4. " ADINTEN[4] ,Channel 4 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Channel 3 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Channel 2 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Channel 1 conversion completion interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Channel 0 conversion completion interrupt enable" "Disabled,Enabled"
else
bitfld.long 0x00 7. " ADINTEN[7] ,Channel 7 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Channel 6 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Channel 5 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Channel 4 conversion completion interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " [3] ,Channel 3 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Channel 2 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Channel 1 conversion completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Channel 0 conversion completion interrupt enable" "Disabled,Enabled"
endif
hgroup.long 0x10++0x03
hide.long 0x00 "DR0,A/D Channel 0 Data Register"
in
newline
hgroup.long 0x14++0x03
hide.long 0x00 "DR1,A/D Channel 1 Data Register"
in
newline
hgroup.long 0x18++0x03
hide.long 0x00 "DR2,A/D Channel 2 Data Register"
in
newline
hgroup.long 0x1C++0x03
hide.long 0x00 "DR3,A/D Channel 3 Data Register"
in
newline
hgroup.long 0x20++0x03
hide.long 0x00 "DR4,A/D Channel 4 Data Register"
in
newline
hgroup.long 0x24++0x03
hide.long 0x00 "DR5,A/D Channel 5 Data Register"
in
newline
hgroup.long 0x28++0x03
hide.long 0x00 "DR6,A/D Channel 6 Data Register"
in
newline
hgroup.long 0x2C++0x03
hide.long 0x00 "DR7,A/D Channel 7 Data Register"
in
newline
rgroup.long 0x30++0x03
line.long 0x00 "STAT,A/D Status Register"
bitfld.long 0x00 16. " ADINT ,A/D interrupt flag" "No interrupt,Interrupt"
newline
sif cpuis("LPC1102")||cpuis("LPC1104")
bitfld.long 0x00 12. " OVERRUN[4] ,Mirrors OVERRUN status flag for channel 4" "No overrun,Overrun"
bitfld.long 0x00 11. " [3] ,Mirrors OVERRUN status flag for channel 3" "No overrun,Overrun"
bitfld.long 0x00 10. " [2] ,Mirrors OVERRUN status flag for channel 2" "No overrun,Overrun"
bitfld.long 0x00 9. " [1] ,Mirrors OVERRUN status flag for channel 1" "No overrun,Overrun"
newline
bitfld.long 0x00 8. " [0] ,Mirrors OVERRUN status flag for channel 0" "No overrun,Overrun"
bitfld.long 0x00 4. " DONE[4] ,Mirrors DONE status flag for channel 4" "Not done,Done"
bitfld.long 0x00 3. " [3] ,Mirrors DONE status flag for channel 3" "Not done,Done"
bitfld.long 0x00 2. " [2] ,Mirrors DONE status flag for channel 2" "Not done,Done"
newline
bitfld.long 0x00 1. " [1] ,Mirrors DONE status flag for channel 1" "Not done,Done"
bitfld.long 0x00 0. " [0] ,Mirrors DONE status flag for channel 0" "Not done,Done"
else
bitfld.long 0x00 15. " OVERRUN[7] ,Mirrors OVERRUN status flag for channel 7" "No overrun,Overrun"
bitfld.long 0x00 14. " [6] ,Mirrors OVERRUN status flag for channel 6" "No overrun,Overrun"
bitfld.long 0x00 13. " [5] ,Mirrors OVERRUN status flag for channel 5" "No overrun,Overrun"
bitfld.long 0x00 12. " [4] ,Mirrors OVERRUN status flag for channel 4" "No overrun,Overrun"
newline
bitfld.long 0x00 11. " [3] ,Mirrors OVERRUN status flag for channel 3" "No overrun,Overrun"
bitfld.long 0x00 10. " [2] ,Mirrors OVERRUN status flag for channel 2" "No overrun,Overrun"
bitfld.long 0x00 9. " [1] ,Mirrors OVERRUN status flag for channel 1" "No overrun,Overrun"
bitfld.long 0x00 8. " [0] ,Mirrors OVERRUN status flag for channel 0" "No overrun,Overrun"
newline
bitfld.long 0x00 7. " DONE[7] ,Mirrors DONE status flag for channel 7" "Not done,Done"
bitfld.long 0x00 6. " [6] ,Mirrors DONE status flag for channel 6" "Not done,Done"
bitfld.long 0x00 5. " [5] ,Mirrors DONE status flag for channel 5" "Not done,Done"
bitfld.long 0x00 4. " [4] ,Mirrors DONE status flag for channel 4" "Not done,Done"
newline
bitfld.long 0x00 3. " [3] ,Mirrors DONE status flag for channel 3" "Not done,Done"
bitfld.long 0x00 2. " [2] ,Mirrors DONE status flag for channel 2" "Not done,Done"
bitfld.long 0x00 1. " [1] ,Mirrors DONE status flag for channel 1" "Not done,Done"
bitfld.long 0x00 0. " [0] ,Mirrors DONE status flag for channel 0" "Not done,Done"
endif
width 0x0B
endif
tree.end
sif cpuis("LPC11E6*")
tree.open "SCT0/1 (State Configurable Timer)"
tree "SCT0"
base ad:0x5000C000
width 15.
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCT Configuration Register"
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
newline
endif
sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*")
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled"
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled"
newline
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled"
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled"
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled"
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " NORELAOD ,Prevents the lower and higher match registers from being reloaded" "Disabled,Enabled"
newline
sif cpuis("LPC11E*")
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
else
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)"
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field"
endif
newline
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit"
else
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCT Configuration Register"
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 18. " AUTOLIMIT_H ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
newline
endif
sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*")
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled"
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled"
newline
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled"
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled"
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled"
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled"
newline
bitfld.long 0x00 8. " NORELOADH ,Prevents the higher match registers from being reloaded" "Disabled,Enabled"
bitfld.long 0x00 7. " NORELAODL ,Prevents the lower match registers from being reloaded" "Disabled,Enabled"
newline
sif cpuis("LPC11E*")
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
else
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)"
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field"
endif
newline
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit"
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x04++0x03
line.long 0x00 "CTRL,SCT Control Register"
hexmask.long.byte 0x00 5.--12. 1. " PRE ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
bitfld.long 0x00 4. " BIDIR ,L or unified counter direction select" "Limit then zero,Limit then down"
newline
bitfld.long 0x00 3. " CLRCTR ,Unified clear counter" "Not cleared,Cleared"
bitfld.long 0x00 2. " HALT ,Unified halt counter" "Not halted,Halted"
newline
bitfld.long 0x00 1. " STOP ,Unified stop counter" "Not stopped,Stopped"
bitfld.long 0x00 0. " DOWN ,Unified counting down counter" "No action,Counting down"
else
group.word 0x04++0x03
line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit"
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
bitfld.word 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit then zero,Limit then down"
newline
bitfld.word 0x00 3. " CLRCTR_L ,Unified clear counter" "Not cleared,Cleared"
bitfld.word 0x00 2. " HALT_L ,Unified halt counter" "Not halted,Halted"
newline
bitfld.word 0x00 1. " STOP_L ,Unified stop counter" "Not stopped,Stopped"
bitfld.word 0x00 0. " DOWN_L ,Unified counting down counter" "No action,Counting down"
line.word 0x02 "CTRL_H,SCT Control Register High Counter 16-bit"
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter lock"
bitfld.word 0x02 4. " BIDIR_H ,Direction select" "Limit then zero,Limit then down"
newline
bitfld.word 0x02 3. " CLRCTR_H ,Unified clear counter" "Not cleared,Cleared"
bitfld.word 0x02 2. " HALT_H ,Unified halt counter" "Not halted,Halted"
newline
bitfld.word 0x02 1. " STOP_H ,Unified stop counter" "Not stopped,Stopped"
bitfld.word 0x02 0. " DOWN_H ,Unified counting down counter" "No action,Counting down"
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x08++0x03
line.long 0x00 "LIMIT,SCT Limit Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit" "Not used,Used"
bitfld.long 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit" "Not used,Used"
bitfld.long 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit" "Not used,Used"
bitfld.long 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit" "Not used,Used"
bitfld.long 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit" "Not used,Used"
bitfld.long 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit" "Not used,Used"
newline
endif
bitfld.long 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit" "Not used,Used"
bitfld.long 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit" "Not used,Used"
bitfld.long 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit" "Not used,Used"
bitfld.long 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit" "Not used,Used"
else
group.word 0x08++0x03
line.word 0x00 "LIMIT_L,SCT Limit Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used"
else
newline
bitfld.word 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit L" "Not used,Used"
bitfld.word 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit L" "Not used,Used"
bitfld.word 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit L" "Not used,Used"
bitfld.word 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit L" "Not used,Used"
bitfld.word 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit L" "Not used,Used"
bitfld.word 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used"
endif
bitfld.word 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit L" "Not used,Used"
bitfld.word 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit L" "Not used,Used"
bitfld.word 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit L" "Not used,Used"
line.word 0x02 "LIMIT_H,SCT Limit Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used"
else
newline
bitfld.word 0x02 15. " LIMMSK_H31 ,Event 31 used as counter limit H" "Not used,Used"
bitfld.word 0x02 14. " LIMMSK_H30 ,Event 30 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 13. " LIMMSK_H29 ,Event 29 used as counter limit H" "Not used,Used"
bitfld.word 0x02 12. " LIMMSK_H28 ,Event 28 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 11. " LIMMSK_H27 ,Event 27 used as counter limit H" "Not used,Used"
bitfld.word 0x02 10. " LIMMSK_H26 ,Event 26 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 9. " LIMMSK_H25 ,Event 25 used as counter limit H" "Not used,Used"
bitfld.word 0x02 8. " LIMMSK_H24 ,Event 24 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 7. " LIMMSK_H23 ,Event 23 used as counter limit H" "Not used,Used"
bitfld.word 0x02 6. " LIMMSK_H22 ,Event 22 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used"
endif
bitfld.word 0x02 4. " LIMMSK_H20 ,Event 20 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 3. " LIMMSK_H19 ,Event 19 used as counter limit H" "Not used,Used"
bitfld.word 0x02 2. " LIMMSK_H18 ,Event 18 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 1. " LIMMSK_H17 ,Event 17 used as counter limit H" "Not used,Used"
bitfld.word 0x02 0. " LIMMSK_H16 ,Event 16 used as counter limit H" "Not used,Used"
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x0C++0x03
line.long 0x00 "HALT,SCT Halt Condition Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted"
bitfld.long 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted"
newline
bitfld.long 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted"
bitfld.long 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted"
newline
bitfld.long 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted"
bitfld.long 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted"
newline
bitfld.long 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted"
bitfld.long 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted"
newline
bitfld.long 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted"
bitfld.long 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted"
newline
endif
bitfld.long 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
bitfld.long 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted"
newline
bitfld.long 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted"
bitfld.long 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted"
newline
bitfld.long 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted"
bitfld.long 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted"
else
group.word 0x0C++0x03
line.word 0x00 "HALT_L,SCT Halt Condition Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
else
newline
bitfld.word 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted"
bitfld.word 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted"
newline
bitfld.word 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted"
bitfld.word 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted"
newline
bitfld.word 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted"
bitfld.word 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted"
newline
bitfld.word 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted"
bitfld.word 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted"
newline
bitfld.word 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted"
bitfld.word 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted"
newline
bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
endif
bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted"
newline
bitfld.word 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted"
bitfld.word 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted"
newline
bitfld.word 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted"
bitfld.word 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted"
line.word 0x02 "HALT_H,SCT Halt Condition Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted"
else
newline
bitfld.word 0x02 15. " HALTMSK_H31 ,Counter halted H event 31" "Not halted,Halted"
bitfld.word 0x02 14. " HALTMSK_H30 ,Counter halted H event 30" "Not halted,Halted"
newline
bitfld.word 0x02 13. " HALTMSK_H29 ,Counter halted H event 29" "Not halted,Halted"
bitfld.word 0x02 12. " HALTMSK_H28 ,Counter halted H event 28" "Not halted,Halted"
newline
bitfld.word 0x02 11. " HALTMSK_H27 ,Counter halted H event 27" "Not halted,Halted"
bitfld.word 0x02 10. " HALTMSK_H26 ,Counter halted H event 26" "Not halted,Halted"
newline
bitfld.word 0x02 9. " HALTMSK_H25 ,Counter halted H event 25" "Not halted,Halted"
bitfld.word 0x02 8. " HALTMSK_H24 ,Counter halted H event 24" "Not halted,Halted"
newline
bitfld.word 0x02 7. " HALTMSK_H23 ,Counter halted H event 23" "Not halted,Halted"
bitfld.word 0x02 6. " HALTMSK_H22 ,Counter halted H event 22" "Not halted,Halted"
newline
bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted"
bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted"
endif
newline
bitfld.word 0x02 3. " HALTMSK_H19 ,Counter halted H event 19" "Not halted,Halted"
bitfld.word 0x02 2. " HALTMSK_H18 ,Counter halted H event 18" "Not halted,Halted"
newline
bitfld.word 0x02 1. " HALTMSK_H17 ,Counter halted H event 17" "Not halted,Halted"
bitfld.word 0x02 0. " HALTMSK_H16 ,Counter halted H event 16" "Not halted,Halted"
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x10++0x03
line.long 0x00 "STOP,SCT Stop Condition Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped"
newline
endif
bitfld.long 0x00 5. " STOPMSK_L5 ,Event 6 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped"
else
group.word 0x10++0x03
line.word 0x00 "STOP_L,SCT Stop Condition Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped"
else
newline
bitfld.word 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped"
endif
bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped"
line.word 0x02 "STOP_H,SCT Stop Condition Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped"
else
newline
bitfld.word 0x02 15. " STOPMSK_H31 ,Event 31 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 14. " STOPMSK_H30 ,Event 30 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 13. " STOPMSK_H29 ,Event 29 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 12. " STOPMSK_H28 ,Event 28 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 11. " STOPMSK_H27 ,Event 27 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 10. " STOPMSK_H26 ,Event 26 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 9. " STOPMSK_H25 ,Event 25 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 8. " STOPMSK_H24 ,Event 24 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 7. " STOPMSK_H23 ,Event 23 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 6. " STOPMSK_H22 ,Event 22 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped"
endif
bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 3. " STOPMSK_H19 ,Event 19 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 2. " STOPMSK_H18 ,Event 18 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 1. " STOPMSK_H17 ,Event 17 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 0. " STOPMSK_H16 ,Event 16 counter stopped" "Not stopped,Stopped"
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x14++0x03
line.long 0x00 "START,SCT Start Condition Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started"
bitfld.long 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started"
newline
bitfld.long 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started"
bitfld.long 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started"
newline
bitfld.long 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started"
bitfld.long 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started"
newline
bitfld.long 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started"
bitfld.long 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started"
newline
bitfld.long 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started"
bitfld.long 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started"
newline
endif
bitfld.long 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
bitfld.long 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started"
newline
bitfld.long 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started"
bitfld.long 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started"
newline
bitfld.long 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started"
bitfld.long 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started"
else
group.word 0x14++0x03
line.word 0x00 "START_L,SCT Start Condition Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
else
newline
bitfld.word 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started"
bitfld.word 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started"
newline
bitfld.word 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started"
bitfld.word 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started"
newline
bitfld.word 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started"
bitfld.word 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started"
newline
bitfld.word 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started"
bitfld.word 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started"
newline
bitfld.word 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started"
bitfld.word 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started"
newline
bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
endif
bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started"
newline
bitfld.word 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started"
bitfld.word 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started"
newline
bitfld.word 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started"
bitfld.word 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started"
line.word 0x02 "START_H,SCT Start Condition Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started"
else
newline
bitfld.word 0x02 15. " STARTMSK_H31 ,Event 31 counter started" "Not started,Started"
bitfld.word 0x02 14. " STARTMSK_H30 ,Event 30 counter started" "Not started,Started"
newline
bitfld.word 0x02 13. " STARTMSK_H29 ,Event 29 counter started" "Not started,Started"
bitfld.word 0x02 12. " STARTMSK_H28 ,Event 28 counter started" "Not started,Started"
newline
bitfld.word 0x02 11. " STARTMSK_H27 ,Event 27 counter started" "Not started,Started"
bitfld.word 0x02 10. " STARTMSK_H26 ,Event 26 counter started" "Not started,Started"
newline
bitfld.word 0x02 9. " STARTMSK_H25 ,Event 25 counter started" "Not started,Started"
bitfld.word 0x02 8. " STARTMSK_H24 ,Event 24 counter started" "Not started,Started"
newline
bitfld.word 0x02 7. " STARTMSK_H23 ,Event 23 counter started" "Not started,Started"
bitfld.word 0x02 6. " STARTMSK_H22 ,Event 22 counter started" "Not started,Started"
newline
bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started"
endif
bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter started" "Not started,Started"
newline
bitfld.word 0x02 3. " STARTMSK_H19 ,Event 19 counter started" "Not started,Started"
bitfld.word 0x02 2. " STARTMSK_H18 ,Event 18 counter started" "Not started,Started"
newline
bitfld.word 0x02 1. " STARTMSK_H17 ,Event 17 counter started" "Not started,Started"
bitfld.word 0x02 0. " STARTMSK_H16 ,Event 16 counter started" "Not started,Started"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x18++0x03
line.long 0x00 "DITHER_L,SCT Dither Condition Register"
bitfld.long 0x00 15. " DITHMSK_L15 ,Event 15 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 14. " DITHMSK_L14 ,Event 14 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 13. " DITHMSK_L13 ,Event 13 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 12. " DITHMSK_L12 ,Event 12 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 11. " DITHMSK_L11 ,Event 11 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 10. " DITHMSK_L10 ,Event 10 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 9. " DITHMSK_L9 ,Event 9 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 8. " DITHMSK_L8 ,Event 8 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 7. " DITHMSK_L7 ,Event 7 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 6. " DITHMSK_L6 ,Event 6 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 5. " DITHMSK_L5 ,Event 5 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 4. " DITHMSK_L4 ,Event 4 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 3. " DITHMSK_L3 ,Event 3 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 2. " DITHMSK_L2 ,Event 2 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 1. " DITHMSK_L1 ,Event 1 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 0. " DITHMSK_L0 ,Event 0 dither mask" "Not dithered,Dithered"
else
group.word 0x18++0x03
line.word 0x00 "DITHER_L,SCT Dither Condition Register"
bitfld.word 0x00 15. " DITHMSK_L15 ,Event 15 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 14. " DITHMSK_L14 ,Event 14 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 13. " DITHMSK_L13 ,Event 13 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 12. " DITHMSK_L12 ,Event 12 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 11. " DITHMSK_L11 ,Event 11 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 10. " DITHMSK_L10 ,Event 10 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 9. " DITHMSK_L9 ,Event 9 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 8. " DITHMSK_L8 ,Event 8 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 7. " DITHMSK_L7 ,Event 7 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 6. " DITHMSK_L6 ,Event 6 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 5. " DITHMSK_L5 ,Event 5 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 4. " DITHMSK_L4 ,Event 4 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 3. " DITHMSK_L3 ,Event 3 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 2. " DITHMSK_L2 ,Event 2 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 1. " DITHMSK_L1 ,Event 1 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 0. " DITHMSK_L0 ,Event 0 dither pattern mask" "Not dithered,Dithered"
line.word 0x02 "DITHER_H,SCT Dither Condition Register"
bitfld.word 0x02 15. " DITHMSK_H31 ,Event 31 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 14. " DITHMSK_H30 ,Event 30 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 13. " DITHMSK_H29 ,Event 29 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 12. " DITHMSK_H28 ,Event 28 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 11. " DITHMSK_H27 ,Event 27 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 10. " DITHMSK_H26 ,Event 26 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 9. " DITHMSK_H25 ,Event 25 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 8. " DITHMSK_H24 ,Event 24 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 7. " DITHMSK_H23 ,Event 23 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 6. " DITHMSK_H22 ,Event 22 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 5. " DITHMSK_H21 ,Event 21 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 4. " DITHMSK_H20 ,Event 20 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 3. " DITHMSK_H19 ,Event 19 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 2. " DITHMSK_H18 ,Event 18 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 1. " DITHMSK_H17 ,Event 17 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 0. " DITHMSK_H16 ,Event 16 dither pattern mask" "Not dithered,Dithered"
endif
endif
newline
width 15.
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x40++0x03
line.long 0x00 "COUNT,SCT Counter Register"
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,L counter value"
else
group.word 0x40++0x03
line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit"
line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit"
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x44++0x03
line.long 0x00 "STATE,SCT State Register"
bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
else
group.word 0x44++0x03
line.word 0x00 "STATE_L,SCT State Register Low Counter 16-bit"
bitfld.word 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.word 0x02 "STATE_H,SCT State Register High Counter 16-bit"
bitfld.word 0x02 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
rgroup.long 0x48++0x03
line.long 0x00 "INPUT,SCT Input Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 23. " SIN7 ,Input 7 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 22. " SIN6 ,Input 6 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 21. " SIN5 ,Input 5 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 20. " SIN4 ,Input 4 state synchronized to the SCT clock" "0,1"
newline
endif
bitfld.long 0x00 19. " SIN3 ,Input 3 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 18. " SIN2 ,Input 2 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 17. " SIN1 ,Input 1 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 16. " SIN0 ,Input 0 state synchronized to the SCT clock" "0,1"
newline
sif !cpuis("LPC11E*")
bitfld.long 0x00 7. " AIN7 ,Real-time status of input 7" "0,1"
bitfld.long 0x00 6. " AIN6 ,Real-time status of input 6" "0,1"
bitfld.long 0x00 5. " AIN5 ,Real-time status of input 5" "0,1"
bitfld.long 0x00 4. " AIN4 ,Real-time status of input 4" "0,1"
newline
endif
bitfld.long 0x00 3. " AIN3 ,Real-time status of input 3" "0,1"
bitfld.long 0x00 2. " AIN2 ,Real-time status of input 2" "0,1"
bitfld.long 0x00 1. " AIN1 ,Real-time status of input 1" "0,1"
bitfld.long 0x00 0. " AIN0 ,Real-time status of input 0" "0,1"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x4C++0x03
line.long 0x00 "REGMODE,SCT Match/Capture Registers Mode Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 4. " REGMOD[4] ,5th pair of match/capture registers" "Match,Capture"
else
newline
bitfld.long 0x00 15. " REGMOD[15] ,16th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
newline
bitfld.long 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
newline
bitfld.long 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
endif
newline
bitfld.long 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
else
group.word 0x4C++0x03
line.word 0x00 "REGMODE_L,SCT Match/Capture Registers Mode Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 4. " REGMOD_L[4] ,5th pair of match/capture registers" "Match,Capture"
newline
else
bitfld.word 0x00 15. " REGMOD_L[15] ,16th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
newline
endif
bitfld.word 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
line.word 0x02 "REGMODE_H,SCT Match/Capture Registers Mode Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 4. " REGMOD_H[4] ,5th pair of match/capture registers" "Match,Capture"
newline
else
bitfld.word 0x02 15. " REGMOD_H[15] ,16th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x02 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x02 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
newline
endif
bitfld.word 0x02 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
endif
sif cpuis("LPC11E*")
if (((((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)&&(((per.l(ad:0x5000C000))&0x01)==0x00))||((((per.l(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.l(ad:0x5000C000))&0x01)==0x01)))
group.long 0x50++0x13
line.long 0x00 "OUTPUT,SCT Output Register"
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
else
rgroup.long 0x50++0x13
line.long 0x00 "OUTPUT,SCT Output Register"
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
endif
else
group.long 0x50++0x13
line.long 0x00 "OUTPUT,SCT Output Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " OUT15 ,Output 15" "Low,High"
bitfld.long 0x00 14. " OUT14 ,Output 14" "Low,High"
bitfld.long 0x00 13. " OUT13 ,Output 13" "Low,High"
bitfld.long 0x00 12. " OUT12 ,Output 12" "Low,High"
newline
bitfld.long 0x00 11. " OUT11 ,Output 11" "Low,High"
bitfld.long 0x00 10. " OUT10 ,Output 10" "Low,High"
bitfld.long 0x00 9. " OUT9 ,Output 9" "Low,High"
bitfld.long 0x00 8. " OUT8 ,Output 8" "Low,High"
newline
bitfld.long 0x00 7. " OUT7 ,Output 7" "Low,High"
bitfld.long 0x00 6. " OUT6 ,Output 6" "Low,High"
bitfld.long 0x00 5. " OUT5 ,Output 5" "Low,High"
bitfld.long 0x00 4. " OUT4 ,Output 4" "Low,High"
newline
endif
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
endif
newline
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,?..."
bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,?..."
bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,?..."
bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,?..."
bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,?..."
bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,?..."
bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,?..."
bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,?..."
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,?..."
newline
endif
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,?..."
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,?..."
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,?..."
else
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,H is counting down,?..."
newline
endif
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,H is counting down,?..."
endif
group.long 0x58++0x0B
line.long 0x00 "RES,SCT Conflict Resolution Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 30.--31. " O15RES ,Effect of simultaneous set and clear on output 15" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 28.--29. " O14RES ,Effect of simultaneous set and clear on output 14" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 26.--27. " O13RES ,Effect of simultaneous set and clear on output 13" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 24.--25. " O12RES ,Effect of simultaneous set and clear on output 12" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 22.--23. " O11RES ,Effect of simultaneous set and clear on output 11" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 20.--21. " O10RES ,Effect of simultaneous set and clear on output 10" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 18.--19. " O9RES ,Effect of simultaneous set and clear on output 9" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 16.--17. " O8RES ,Effect of simultaneous set and clear on output 8" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 14.--15. " O7RES ,Effect of simultaneous set and clear on output 7" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 12.--13. " O6RES ,Effect of simultaneous set and clear on output 6" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set output,Clear output,Toggle output"
newline
endif
bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set output,Clear output,Toggle output"
line.long 0x04 "DMAREQ0,SCT DMA 0 Request Register"
rbitfld.long 0x04 31. " DRQ0 ,Indicates the state of DMA request 0" "Not requested,Requested"
bitfld.long 0x04 30. " DRL0 ,The SCT set DMA request 0 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested"
sif !cpuis("LPC11E*")
bitfld.long 0x04 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 14. " [14] ,Event 14 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 13. " [13] ,Event 13 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 12. " [12] ,Event 12 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 11. " [11] ,Event 11 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 10. " [10] ,Event 10 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 9. " [9] ,Event 9 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 8. " [8] ,Event 8 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 7. " [7] ,Event 7 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 6. " [6] ,Event 6 sets DMA request 0" "Not set,Set"
endif
newline
sif cpuis("LPC11E*")
bitfld.long 0x04 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
else
bitfld.long 0x04 5. " [5] ,Event 5 sets DMA request 0" "Not set,Set"
endif
bitfld.long 0x04 4. " [4] ,Event 4 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 3. " [3] ,Event 3 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 2. " [2] ,Event 2 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 1. " [1] ,Event 1 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 0. " [0] ,Event 0 sets DMA request 0" "Not set,Set"
line.long 0x08 "DMAREQ1,SCT DMA 1 Request Register"
rbitfld.long 0x08 31. " DRQ1 ,Indicates the state of DMA request 1" "Not requested,Requested"
bitfld.long 0x08 30. " DRL1 ,The SCT set DMA request 1 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested"
sif !cpuis("LPC11E*")
bitfld.long 0x08 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 14. " [14] ,Event 14 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 13. " [13] ,Event 13 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 12. " [12] ,Event 12 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 11. " [11] ,Event 11 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 10. " [10] ,Event 10 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 9. " [9] ,Event 9 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 8. " [8] ,Event 8 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 7. " [7] ,Event 7 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 6. " [6] ,Event 6 sets DMA request 1" "Not set,Set"
endif
newline
sif cpuis("LPC11E*")
bitfld.long 0x08 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
else
bitfld.long 0x08 5. " [5] ,Event 5 sets DMA request 1" "Not set,Set"
endif
bitfld.long 0x08 4. " [4] ,Event 4 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 3. " [3] ,Event 3 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 2. " [2] ,Event 2 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 1. " [1] ,Event 1 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 0. " [0] ,Event 0 sets DMA request 1" "Not set,Set"
sif cpuis("LPC11E*")
group.long 0xF0++0x07
line.long 0x00 "EVEN,SCT Flag Enable Register"
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled"
line.long 0x04 "EVFLAG,SCT Event Flag Register"
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred" "Not occurred,Occurred"
bitfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred"
bitfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred"
bitfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred"
bitfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred"
else
group.long 0xF0++0x07
line.long 0x00 "EVEN,SCT Flag Enable Register"
bitfld.long 0x00 15. " IEN15 ,Event 15 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Event 14 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Event 13 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " [12] ,Event 12 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Event 11 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Event 10 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " [9] ,Event 9 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Event 8 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Event 7 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " [6] ,Event 6 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Event 5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled"
line.long 0x04 "EVFLAG,SCT Event Flag Register"
eventfld.long 0x04 15. " FLAG15 ,Event 15occurred" "Not occurred,Occurred"
eventfld.long 0x04 14. " [14] ,Event 14 occurred" "Not occurred,Occurred"
eventfld.long 0x04 13. " [13] ,Event 13 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 12. " [12] ,Event 12 occurred" "Not occurred,Occurred"
eventfld.long 0x04 11. " [11] ,Event 11 occurred" "Not occurred,Occurred"
eventfld.long 0x04 10. " [10] ,Event 10 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 9. " [9] ,Event 9 occurred" "Not occurred,Occurred"
eventfld.long 0x04 8. " [8] ,Event 8 occurred" "Not occurred,Occurred"
eventfld.long 0x04 7. " [7] ,Event 7 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 6. " [6] ,Event 6 occurred" "Not occurred,Occurred"
eventfld.long 0x04 5. " [5] ,Event 5 occurred" "Not occurred,Occurred"
eventfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred"
eventfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred"
eventfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred"
endif
group.long 0xF8++0x03
line.long 0x00 "CONEN,SCT Conflict Enable Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 3. " NCEN[3] ,No change conflict event 3 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled"
else
bitfld.long 0x00 15. " NCEN[15] ,No change conflict event 15 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,No change conflict event 14 enable" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,No change conflict event 13 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " [12] ,No change conflict event 12 enable" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,No change conflict event 11 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,No change conflict event 10 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " [9] ,No change conflict event 9 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,No change conflict event 8 enable" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,No change conflict event 7 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " [6] ,No change conflict event 6 enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,No change conflict event 5 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,No change conflict event 4 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " [3] ,No change conflict event 3 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled"
endif
sif cpuis("LPC11E*")
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,SCT Conflict Flag Register"
bitfld.long 0x00 31. " BUSERRH ,Bus error from this SCT involved writing CTR H/STATE H/MATCH H/Output register" "No error,Error"
bitfld.long 0x00 30. " BUSERRL ,Bus error from this SCT involved writing CTR L-Unified/STATE L-Unified/MATCH L-Unified/Output register" "No error,Error"
bitfld.long 0x00 3. " NCFLAG[3] ,No-change conflict event 3 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 2. " [2] ,No-change conflict event 2 occurred" "Not occurred,Occurred"
bitfld.long 0x00 1. " [1] ,No-change conflict event 1 occurred" "Not occurred,Occurred"
bitfld.long 0x00 0. " [0] ,No-change conflict event 0 occurred" "Not occurred,Occurred"
else
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,SCT Conflict Flag Register"
bitfld.long 0x00 31. " BUSERRH ,Bus error" "No error,Error"
bitfld.long 0x00 30. " BUSERRL ,Bus error" "No error,Error"
bitfld.long 0x00 15. " NCFLAG15 ,No-change conflict event 15 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 14. " NCFLAG14 ,No-change conflict event 14 occurred" "Not occurred,Occurred"
bitfld.long 0x00 13. " NCFLAG13 ,No-change conflict event 13 occurred" "Not occurred,Occurred"
bitfld.long 0x00 12. " NCFLAG12 ,No-change conflict event 12 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 11. " NCFLAG11 ,No-change conflict event 11 occurred" "Not occurred,Occurred"
bitfld.long 0x00 10. " NCFLAG10 ,No-change conflict event 10 occurred" "Not occurred,Occurred"
bitfld.long 0x00 9. " NCFLAG9 ,No-change conflict event 9 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 8. " NCFLAG8 ,No-change conflict event 8 occurred" "Not occurred,Occurred"
bitfld.long 0x00 7. " NCFLAG7 ,No-change conflict event 7 occurred" "Not occurred,Occurred"
bitfld.long 0x00 6. " NCFLAG6 ,No-change conflict event 6 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 5. " NCFLAG5 ,No-change conflict event 5 occurred" "Not occurred,Occurred"
bitfld.long 0x00 4. " NCFLAG4 ,No-change conflict event 4 occurred" "Not occurred,Occurred"
bitfld.long 0x00 3. " NCFLAG3 ,No-change conflict event 3 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 2. " NCFLAG2 ,No-change conflict event 2 occurred" "Not occurred,Occurred"
bitfld.long 0x00 1. " NCFLAG1 ,No-change conflict event 1 occurred" "Not occurred,Occurred"
bitfld.long 0x00 0. " NCFLAG0 ,No-change conflict event 0 occurred" "Not occurred,Occurred"
endif
width 26.
tree "Event 0 (Regmode0 0/1)"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000C000+0x4C))&(1<<0.))==(1<<0.))
rgroup.long 0x100++0x03
line.long 0x00 "CAP0,SCT Capture Register 0"
else
rgroup.long 0x100++0x03
line.long 0x00 "MATCH0,SCT Match Register 0"
endif
else
if (((per.l(ad:0x5000C000+0x4C))&(1<<0.))==(1<<0.))
group.long 0x100++0x03
line.long 0x00 "CAP0,SCT Capture Register 0"
else
group.long 0x100++0x03
line.long 0x00 "MATCH0,SCT Match Register 0"
endif
endif
else
if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<0.))==(1<<0.))
group.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
group.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<0.))==(1<<0.))
group.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
else
group.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<0.))==(1<<0.))
rgroup.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
rgroup.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<0.))==(1<<0.))
group.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
else
group.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<0.))==(1<<0.))
group.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
group.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<0.))==(1<<0.))
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 Low Counter 16-bit"
else
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000C000+0x4C))&(1<<0.))==(1<<0.))
rgroup.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
rgroup.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<0.))==(1<<0.))
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
else
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x140++0x03
line.long 0x00 "FRACMAT0_L,SCT Fractional Match Register 0"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x140++0x03
line.word 0x00 "FRACMAT0_L,SCT Fractional Match Register 0"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT0_H,SCT Fractional Match Register 0"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x100+0x100)++0x03
line.long 0x00 "MATCHREL0/CAPCTRL0,SCT Match/capture Reload Register 0"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x100+0x100)++0x03
line.word 0x00 "MATCHREL0_L/CAPCTRL0_L,SCT Match/capture Reload Register 0"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL0_H/CAPCTRL0_H,SCT Match/capture Reload Register 0"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x140+0x100)++0x03
line.long 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x140+0x100)++0x03
line.word 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL0_H,SCT Fractional Match Reload Register 0"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x100+0x200)++0x03
line.long 0x00 "EV0_STATE,SCT Event State Mask 0"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x100+0x204)++0x03
line.long 0x00 "EVCTRL0,SCT Event Control Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x100+0x204)++0x03
line.long 0x00 "EVCTRL0,SCT Event Control Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x100+0x400)++0x07
line.long 0x00 "OUT0_SET,SCT Output Set Register 0"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set"
line.long 0x04 "OUT0_CLR,SCT Output Clear Register 0"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared"
else
group.long (0x100+0x400)++0x07
line.long 0x00 "OUTPUTSET0,SCT Output Set Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 0" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 0" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 0" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 0" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 0" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 0" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 0" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 0" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 0" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 0" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 0" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set"
line.long 0x04 "OUTPUTCL0,SCT Output Clear Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 0" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 0" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared"
endif
tree.end
tree "Event 1 (Regmode1 0/1)"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000C000+0x4C))&(1<<1.))==(1<<1.))
rgroup.long 0x104++0x03
line.long 0x00 "CAP1,SCT Capture Register 1"
else
rgroup.long 0x104++0x03
line.long 0x00 "MATCH1,SCT Match Register 1"
endif
else
if (((per.l(ad:0x5000C000+0x4C))&(1<<1.))==(1<<1.))
group.long 0x104++0x03
line.long 0x00 "CAP1,SCT Capture Register 1"
else
group.long 0x104++0x03
line.long 0x00 "MATCH1,SCT Match Register 1"
endif
endif
else
if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<1.))==(1<<1.))
group.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
group.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<1.))==(1<<1.))
group.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
else
group.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<1.))==(1<<1.))
rgroup.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
rgroup.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<1.))==(1<<1.))
group.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
else
group.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<1.))==(1<<1.))
group.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
group.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<1.))==(1<<1.))
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 Low Counter 16-bit"
else
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000C000+0x4C))&(1<<1.))==(1<<1.))
rgroup.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
rgroup.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<1.))==(1<<1.))
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
else
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x144++0x03
line.long 0x00 "FRACMAT1_L,SCT Fractional Match Register 1"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x144++0x03
line.word 0x00 "FRACMAT1_L,SCT Fractional Match Register 1"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT1_H,SCT Fractional Match Register 1"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x104+0x100)++0x03
line.long 0x00 "MATCHREL1/CAPCTRL1,SCT Match/capture Reload Register 1"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x104+0x100)++0x03
line.word 0x00 "MATCHREL1_L/CAPCTRL1_L,SCT Match/capture Reload Register 1"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL1_H/CAPCTRL1_H,SCT Match/capture Reload Register 1"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x144+0x100)++0x03
line.long 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x144+0x100)++0x03
line.word 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL1_H,SCT Fractional Match Reload Register 1"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x108+0x200)++0x03
line.long 0x00 "EV1_STATE,SCT Event State Mask 1"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x108+0x204)++0x03
line.long 0x00 "EVCTRL1,SCT Event Control Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x108+0x204)++0x03
line.long 0x00 "EVCTRL1,SCT Event Control Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x108+0x400)++0x07
line.long 0x00 "OUT1_SET,SCT Output Set Register 1"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set"
line.long 0x04 "OUT1_CLR,SCT Output Clear Register 1"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared"
else
group.long (0x108+0x400)++0x07
line.long 0x00 "OUTPUTSET1,SCT Output Set Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 1" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 1" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 1" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 1" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 1" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 1" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 1" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 1" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 1" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 1" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 1" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set"
line.long 0x04 "OUTPUTCL1,SCT Output Clear Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 1" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 1" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared"
endif
tree.end
tree "Event 2 (Regmode2 0/1)"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000C000+0x4C))&(1<<2.))==(1<<2.))
rgroup.long 0x108++0x03
line.long 0x00 "CAP2,SCT Capture Register 2"
else
rgroup.long 0x108++0x03
line.long 0x00 "MATCH2,SCT Match Register 2"
endif
else
if (((per.l(ad:0x5000C000+0x4C))&(1<<2.))==(1<<2.))
group.long 0x108++0x03
line.long 0x00 "CAP2,SCT Capture Register 2"
else
group.long 0x108++0x03
line.long 0x00 "MATCH2,SCT Match Register 2"
endif
endif
else
if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<2.))==(1<<2.))
group.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
group.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<2.))==(1<<2.))
group.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
else
group.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<2.))==(1<<2.))
rgroup.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
rgroup.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<2.))==(1<<2.))
group.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
else
group.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<2.))==(1<<2.))
group.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
group.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<2.))==(1<<2.))
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 Low Counter 16-bit"
else
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000C000+0x4C))&(1<<2.))==(1<<2.))
rgroup.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
rgroup.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<2.))==(1<<2.))
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
else
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x148++0x03
line.long 0x00 "FRACMAT2_L,SCT Fractional Match Register 2"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x148++0x03
line.word 0x00 "FRACMAT2_L,SCT Fractional Match Register 2"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT2_H,SCT Fractional Match Register 2"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x108+0x100)++0x03
line.long 0x00 "MATCHREL2/CAPCTRL2,SCT Match/capture Reload Register 2"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x108+0x100)++0x03
line.word 0x00 "MATCHREL2_L/CAPCTRL2_L,SCT Match/capture Reload Register 2"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL2_H/CAPCTRL2_H,SCT Match/capture Reload Register 2"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x148+0x100)++0x03
line.long 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x148+0x100)++0x03
line.word 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL2_H,SCT Fractional Match Reload Register 2"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x110+0x200)++0x03
line.long 0x00 "EV2_STATE,SCT Event State Mask 2"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x110+0x204)++0x03
line.long 0x00 "EVCTRL2,SCT Event Control Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x110+0x204)++0x03
line.long 0x00 "EVCTRL2,SCT Event Control Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x110+0x400)++0x07
line.long 0x00 "OUT2_SET,SCT Output Set Register 2"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set"
line.long 0x04 "OUT2_CLR,SCT Output Clear Register 2"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared"
else
group.long (0x110+0x400)++0x07
line.long 0x00 "OUTPUTSET2,SCT Output Set Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 2" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 2" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 2" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 2" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 2" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 2" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 2" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 2" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 2" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 2" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 2" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set"
line.long 0x04 "OUTPUTCL2,SCT Output Clear Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 2" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 2" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared"
endif
tree.end
tree "Event 3 (Regmode3 0/1)"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000C000+0x4C))&(1<<3.))==(1<<3.))
rgroup.long 0x10C++0x03
line.long 0x00 "CAP3,SCT Capture Register 3"
else
rgroup.long 0x10C++0x03
line.long 0x00 "MATCH3,SCT Match Register 3"
endif
else
if (((per.l(ad:0x5000C000+0x4C))&(1<<3.))==(1<<3.))
group.long 0x10C++0x03
line.long 0x00 "CAP3,SCT Capture Register 3"
else
group.long 0x10C++0x03
line.long 0x00 "MATCH3,SCT Match Register 3"
endif
endif
else
if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<3.))==(1<<3.))
group.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
group.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<3.))==(1<<3.))
group.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
else
group.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<3.))==(1<<3.))
rgroup.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
rgroup.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<3.))==(1<<3.))
group.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
else
group.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&(1<<3.))==(1<<3.))
group.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
group.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<3.))==(1<<3.))
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 Low Counter 16-bit"
else
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000C000+0x4C))&(1<<3.))==(1<<3.))
rgroup.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
rgroup.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&(1<<3.))==(1<<3.))
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
else
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long 0x14C++0x03
line.long 0x00 "FRACMAT3_L,SCT Fractional Match Register 3"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x14C++0x03
line.word 0x00 "FRACMAT3_L,SCT Fractional Match Register 3"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT3_H,SCT Fractional Match Register 3"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x10C+0x100)++0x03
line.long 0x00 "MATCHREL3/CAPCTRL3,SCT Match/capture Reload Register 3"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x10C+0x100)++0x03
line.word 0x00 "MATCHREL3_L/CAPCTRL3_L,SCT Match/capture Reload Register 3"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL3_H/CAPCTRL3_H,SCT Match/capture Reload Register 3"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x14C+0x100)++0x03
line.long 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x14C+0x100)++0x03
line.word 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL3_H,SCT Fractional Match Reload Register 3"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x118+0x200)++0x03
line.long 0x00 "EV3_STATE,SCT Event State Mask 3"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x118+0x204)++0x03
line.long 0x00 "EVCTRL3,SCT Event Control Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x118+0x204)++0x03
line.long 0x00 "EVCTRL3,SCT Event Control Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x118+0x400)++0x07
line.long 0x00 "OUT3_SET,SCT Output Set Register 3"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set"
line.long 0x04 "OUT3_CLR,SCT Output Clear Register 3"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared"
else
group.long (0x118+0x400)++0x07
line.long 0x00 "OUTPUTSET3,SCT Output Set Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 3" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 3" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 3" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 3" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 3" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 3" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 3" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 3" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 3" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 3" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 3" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set"
line.long 0x04 "OUTPUTCL3,SCT Output Clear Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 3" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 3" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared"
endif
tree.end
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")||cpuis("LPC11E*")
tree "Event 4 (Regmode4 0/1)"
if (((per.l(ad:0x5000C000))&0x01)==0x01)
if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000C000+0x4C))&0x10)==0x10)
rgroup.long 0x110++0x03
line.long 0x00 "CAP4,SCT Capture Register 4"
else
rgroup.long 0x110++0x03
line.long 0x00 "MATCH4,SCT Match Register 4"
endif
else
if (((per.l(ad:0x5000C000+0x4C))&0x10)==0x10)
group.long 0x110++0x03
line.long 0x00 "CAP4,SCT Capture Register 4"
else
group.long 0x110++0x03
line.long 0x00 "MATCH4,SCT Match Register 4"
endif
endif
else
if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10)
group.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
group.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10)
group.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
else
group.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10)
rgroup.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
rgroup.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10)
group.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
else
group.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10)
group.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
group.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10)
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 Low Counter 16-bit"
else
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10)
rgroup.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
rgroup.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10)
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
else
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
endif
endif
endif
if (((per.l(ad:0x5000C000))&0x01)==0x01)
group.long (0x210)++0x03
line.long 0x00 "MATCHREL4/CAPCTRL4,SCT Match/capture Reload Register 4"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x210)++0x03
line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT Match/capture Reload Register 4"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT Match/capture Reload Register 4"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
group.long (0x320)++0x07
line.long 0x00 "EVSTATEMSK4,SCT Event State Mask 4"
sif cpuis("LPC11E*")
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
line.long 0x04 "EVCTRL4,SCT Event Control Register 4"
bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "Event 5 (Regmode5 0/1)"
group.long (0x328)++0x07
line.long 0x00 "EVSTATEMSK5,SCT Event State Mask 5"
sif cpuis("LPC11E*")
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
line.long 0x04 "EVCTRL5,SCT Event Control Register 5"
bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
endif
width 0x0B
tree.end
tree "SCT1"
base ad:0x5000E000
width 15.
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCT Configuration Register"
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
newline
endif
sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*")
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled"
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled"
newline
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled"
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled"
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled"
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " NORELAOD ,Prevents the lower and higher match registers from being reloaded" "Disabled,Enabled"
newline
sif cpuis("LPC11E*")
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
else
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)"
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field"
endif
newline
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit"
else
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCT Configuration Register"
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 18. " AUTOLIMIT_H ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
newline
endif
sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*")
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled"
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled"
newline
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled"
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled"
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled"
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled"
newline
bitfld.long 0x00 8. " NORELOADH ,Prevents the higher match registers from being reloaded" "Disabled,Enabled"
bitfld.long 0x00 7. " NORELAODL ,Prevents the lower match registers from being reloaded" "Disabled,Enabled"
newline
sif cpuis("LPC11E*")
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
else
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)"
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field"
endif
newline
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit"
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x04++0x03
line.long 0x00 "CTRL,SCT Control Register"
hexmask.long.byte 0x00 5.--12. 1. " PRE ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
bitfld.long 0x00 4. " BIDIR ,L or unified counter direction select" "Limit then zero,Limit then down"
newline
bitfld.long 0x00 3. " CLRCTR ,Unified clear counter" "Not cleared,Cleared"
bitfld.long 0x00 2. " HALT ,Unified halt counter" "Not halted,Halted"
newline
bitfld.long 0x00 1. " STOP ,Unified stop counter" "Not stopped,Stopped"
bitfld.long 0x00 0. " DOWN ,Unified counting down counter" "No action,Counting down"
else
group.word 0x04++0x03
line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit"
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
bitfld.word 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit then zero,Limit then down"
newline
bitfld.word 0x00 3. " CLRCTR_L ,Unified clear counter" "Not cleared,Cleared"
bitfld.word 0x00 2. " HALT_L ,Unified halt counter" "Not halted,Halted"
newline
bitfld.word 0x00 1. " STOP_L ,Unified stop counter" "Not stopped,Stopped"
bitfld.word 0x00 0. " DOWN_L ,Unified counting down counter" "No action,Counting down"
line.word 0x02 "CTRL_H,SCT Control Register High Counter 16-bit"
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter lock"
bitfld.word 0x02 4. " BIDIR_H ,Direction select" "Limit then zero,Limit then down"
newline
bitfld.word 0x02 3. " CLRCTR_H ,Unified clear counter" "Not cleared,Cleared"
bitfld.word 0x02 2. " HALT_H ,Unified halt counter" "Not halted,Halted"
newline
bitfld.word 0x02 1. " STOP_H ,Unified stop counter" "Not stopped,Stopped"
bitfld.word 0x02 0. " DOWN_H ,Unified counting down counter" "No action,Counting down"
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x08++0x03
line.long 0x00 "LIMIT,SCT Limit Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit" "Not used,Used"
bitfld.long 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit" "Not used,Used"
bitfld.long 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit" "Not used,Used"
bitfld.long 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit" "Not used,Used"
bitfld.long 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit" "Not used,Used"
bitfld.long 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit" "Not used,Used"
newline
endif
bitfld.long 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit" "Not used,Used"
bitfld.long 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit" "Not used,Used"
bitfld.long 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit" "Not used,Used"
newline
bitfld.long 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit" "Not used,Used"
bitfld.long 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit" "Not used,Used"
else
group.word 0x08++0x03
line.word 0x00 "LIMIT_L,SCT Limit Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used"
else
newline
bitfld.word 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit L" "Not used,Used"
bitfld.word 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit L" "Not used,Used"
bitfld.word 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit L" "Not used,Used"
bitfld.word 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit L" "Not used,Used"
bitfld.word 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit L" "Not used,Used"
bitfld.word 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used"
endif
bitfld.word 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit L" "Not used,Used"
bitfld.word 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit L" "Not used,Used"
newline
bitfld.word 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit L" "Not used,Used"
bitfld.word 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit L" "Not used,Used"
line.word 0x02 "LIMIT_H,SCT Limit Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used"
else
newline
bitfld.word 0x02 15. " LIMMSK_H31 ,Event 31 used as counter limit H" "Not used,Used"
bitfld.word 0x02 14. " LIMMSK_H30 ,Event 30 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 13. " LIMMSK_H29 ,Event 29 used as counter limit H" "Not used,Used"
bitfld.word 0x02 12. " LIMMSK_H28 ,Event 28 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 11. " LIMMSK_H27 ,Event 27 used as counter limit H" "Not used,Used"
bitfld.word 0x02 10. " LIMMSK_H26 ,Event 26 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 9. " LIMMSK_H25 ,Event 25 used as counter limit H" "Not used,Used"
bitfld.word 0x02 8. " LIMMSK_H24 ,Event 24 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 7. " LIMMSK_H23 ,Event 23 used as counter limit H" "Not used,Used"
bitfld.word 0x02 6. " LIMMSK_H22 ,Event 22 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used"
endif
bitfld.word 0x02 4. " LIMMSK_H20 ,Event 20 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 3. " LIMMSK_H19 ,Event 19 used as counter limit H" "Not used,Used"
bitfld.word 0x02 2. " LIMMSK_H18 ,Event 18 used as counter limit H" "Not used,Used"
newline
bitfld.word 0x02 1. " LIMMSK_H17 ,Event 17 used as counter limit H" "Not used,Used"
bitfld.word 0x02 0. " LIMMSK_H16 ,Event 16 used as counter limit H" "Not used,Used"
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x0C++0x03
line.long 0x00 "HALT,SCT Halt Condition Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted"
bitfld.long 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted"
newline
bitfld.long 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted"
bitfld.long 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted"
newline
bitfld.long 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted"
bitfld.long 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted"
newline
bitfld.long 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted"
bitfld.long 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted"
newline
bitfld.long 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted"
bitfld.long 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted"
newline
endif
bitfld.long 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
bitfld.long 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted"
newline
bitfld.long 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted"
bitfld.long 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted"
newline
bitfld.long 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted"
bitfld.long 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted"
else
group.word 0x0C++0x03
line.word 0x00 "HALT_L,SCT Halt Condition Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
else
newline
bitfld.word 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted"
bitfld.word 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted"
newline
bitfld.word 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted"
bitfld.word 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted"
newline
bitfld.word 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted"
bitfld.word 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted"
newline
bitfld.word 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted"
bitfld.word 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted"
newline
bitfld.word 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted"
bitfld.word 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted"
newline
bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
endif
bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted"
newline
bitfld.word 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted"
bitfld.word 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted"
newline
bitfld.word 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted"
bitfld.word 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted"
line.word 0x02 "HALT_H,SCT Halt Condition Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted"
else
newline
bitfld.word 0x02 15. " HALTMSK_H31 ,Counter halted H event 31" "Not halted,Halted"
bitfld.word 0x02 14. " HALTMSK_H30 ,Counter halted H event 30" "Not halted,Halted"
newline
bitfld.word 0x02 13. " HALTMSK_H29 ,Counter halted H event 29" "Not halted,Halted"
bitfld.word 0x02 12. " HALTMSK_H28 ,Counter halted H event 28" "Not halted,Halted"
newline
bitfld.word 0x02 11. " HALTMSK_H27 ,Counter halted H event 27" "Not halted,Halted"
bitfld.word 0x02 10. " HALTMSK_H26 ,Counter halted H event 26" "Not halted,Halted"
newline
bitfld.word 0x02 9. " HALTMSK_H25 ,Counter halted H event 25" "Not halted,Halted"
bitfld.word 0x02 8. " HALTMSK_H24 ,Counter halted H event 24" "Not halted,Halted"
newline
bitfld.word 0x02 7. " HALTMSK_H23 ,Counter halted H event 23" "Not halted,Halted"
bitfld.word 0x02 6. " HALTMSK_H22 ,Counter halted H event 22" "Not halted,Halted"
newline
bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted"
bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted"
endif
newline
bitfld.word 0x02 3. " HALTMSK_H19 ,Counter halted H event 19" "Not halted,Halted"
bitfld.word 0x02 2. " HALTMSK_H18 ,Counter halted H event 18" "Not halted,Halted"
newline
bitfld.word 0x02 1. " HALTMSK_H17 ,Counter halted H event 17" "Not halted,Halted"
bitfld.word 0x02 0. " HALTMSK_H16 ,Counter halted H event 16" "Not halted,Halted"
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x10++0x03
line.long 0x00 "STOP,SCT Stop Condition Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped"
newline
endif
bitfld.long 0x00 5. " STOPMSK_L5 ,Event 6 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped"
newline
bitfld.long 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped"
bitfld.long 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped"
else
group.word 0x10++0x03
line.word 0x00 "STOP_L,SCT Stop Condition Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped"
else
newline
bitfld.word 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped"
endif
bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped"
bitfld.word 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped"
line.word 0x02 "STOP_H,SCT Stop Condition Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped"
else
newline
bitfld.word 0x02 15. " STOPMSK_H31 ,Event 31 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 14. " STOPMSK_H30 ,Event 30 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 13. " STOPMSK_H29 ,Event 29 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 12. " STOPMSK_H28 ,Event 28 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 11. " STOPMSK_H27 ,Event 27 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 10. " STOPMSK_H26 ,Event 26 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 9. " STOPMSK_H25 ,Event 25 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 8. " STOPMSK_H24 ,Event 24 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 7. " STOPMSK_H23 ,Event 23 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 6. " STOPMSK_H22 ,Event 22 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped"
endif
bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 3. " STOPMSK_H19 ,Event 19 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 2. " STOPMSK_H18 ,Event 18 counter stopped" "Not stopped,Stopped"
newline
bitfld.word 0x02 1. " STOPMSK_H17 ,Event 17 counter stopped" "Not stopped,Stopped"
bitfld.word 0x02 0. " STOPMSK_H16 ,Event 16 counter stopped" "Not stopped,Stopped"
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x14++0x03
line.long 0x00 "START,SCT Start Condition Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started"
bitfld.long 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started"
newline
bitfld.long 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started"
bitfld.long 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started"
newline
bitfld.long 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started"
bitfld.long 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started"
newline
bitfld.long 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started"
bitfld.long 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started"
newline
bitfld.long 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started"
bitfld.long 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started"
newline
endif
bitfld.long 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
bitfld.long 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started"
newline
bitfld.long 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started"
bitfld.long 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started"
newline
bitfld.long 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started"
bitfld.long 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started"
else
group.word 0x14++0x03
line.word 0x00 "START_L,SCT Start Condition Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
else
newline
bitfld.word 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started"
bitfld.word 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started"
newline
bitfld.word 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started"
bitfld.word 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started"
newline
bitfld.word 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started"
bitfld.word 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started"
newline
bitfld.word 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started"
bitfld.word 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started"
newline
bitfld.word 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started"
bitfld.word 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started"
newline
bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
endif
bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started"
newline
bitfld.word 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started"
bitfld.word 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started"
newline
bitfld.word 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started"
bitfld.word 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started"
line.word 0x02 "START_H,SCT Start Condition Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started"
else
newline
bitfld.word 0x02 15. " STARTMSK_H31 ,Event 31 counter started" "Not started,Started"
bitfld.word 0x02 14. " STARTMSK_H30 ,Event 30 counter started" "Not started,Started"
newline
bitfld.word 0x02 13. " STARTMSK_H29 ,Event 29 counter started" "Not started,Started"
bitfld.word 0x02 12. " STARTMSK_H28 ,Event 28 counter started" "Not started,Started"
newline
bitfld.word 0x02 11. " STARTMSK_H27 ,Event 27 counter started" "Not started,Started"
bitfld.word 0x02 10. " STARTMSK_H26 ,Event 26 counter started" "Not started,Started"
newline
bitfld.word 0x02 9. " STARTMSK_H25 ,Event 25 counter started" "Not started,Started"
bitfld.word 0x02 8. " STARTMSK_H24 ,Event 24 counter started" "Not started,Started"
newline
bitfld.word 0x02 7. " STARTMSK_H23 ,Event 23 counter started" "Not started,Started"
bitfld.word 0x02 6. " STARTMSK_H22 ,Event 22 counter started" "Not started,Started"
newline
bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started"
endif
bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter started" "Not started,Started"
newline
bitfld.word 0x02 3. " STARTMSK_H19 ,Event 19 counter started" "Not started,Started"
bitfld.word 0x02 2. " STARTMSK_H18 ,Event 18 counter started" "Not started,Started"
newline
bitfld.word 0x02 1. " STARTMSK_H17 ,Event 17 counter started" "Not started,Started"
bitfld.word 0x02 0. " STARTMSK_H16 ,Event 16 counter started" "Not started,Started"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x18++0x03
line.long 0x00 "DITHER_L,SCT Dither Condition Register"
bitfld.long 0x00 15. " DITHMSK_L15 ,Event 15 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 14. " DITHMSK_L14 ,Event 14 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 13. " DITHMSK_L13 ,Event 13 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 12. " DITHMSK_L12 ,Event 12 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 11. " DITHMSK_L11 ,Event 11 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 10. " DITHMSK_L10 ,Event 10 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 9. " DITHMSK_L9 ,Event 9 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 8. " DITHMSK_L8 ,Event 8 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 7. " DITHMSK_L7 ,Event 7 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 6. " DITHMSK_L6 ,Event 6 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 5. " DITHMSK_L5 ,Event 5 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 4. " DITHMSK_L4 ,Event 4 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 3. " DITHMSK_L3 ,Event 3 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 2. " DITHMSK_L2 ,Event 2 dither mask" "Not dithered,Dithered"
newline
bitfld.long 0x00 1. " DITHMSK_L1 ,Event 1 dither mask" "Not dithered,Dithered"
bitfld.long 0x00 0. " DITHMSK_L0 ,Event 0 dither mask" "Not dithered,Dithered"
else
group.word 0x18++0x03
line.word 0x00 "DITHER_L,SCT Dither Condition Register"
bitfld.word 0x00 15. " DITHMSK_L15 ,Event 15 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 14. " DITHMSK_L14 ,Event 14 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 13. " DITHMSK_L13 ,Event 13 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 12. " DITHMSK_L12 ,Event 12 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 11. " DITHMSK_L11 ,Event 11 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 10. " DITHMSK_L10 ,Event 10 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 9. " DITHMSK_L9 ,Event 9 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 8. " DITHMSK_L8 ,Event 8 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 7. " DITHMSK_L7 ,Event 7 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 6. " DITHMSK_L6 ,Event 6 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 5. " DITHMSK_L5 ,Event 5 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 4. " DITHMSK_L4 ,Event 4 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 3. " DITHMSK_L3 ,Event 3 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 2. " DITHMSK_L2 ,Event 2 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x00 1. " DITHMSK_L1 ,Event 1 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x00 0. " DITHMSK_L0 ,Event 0 dither pattern mask" "Not dithered,Dithered"
line.word 0x02 "DITHER_H,SCT Dither Condition Register"
bitfld.word 0x02 15. " DITHMSK_H31 ,Event 31 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 14. " DITHMSK_H30 ,Event 30 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 13. " DITHMSK_H29 ,Event 29 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 12. " DITHMSK_H28 ,Event 28 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 11. " DITHMSK_H27 ,Event 27 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 10. " DITHMSK_H26 ,Event 26 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 9. " DITHMSK_H25 ,Event 25 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 8. " DITHMSK_H24 ,Event 24 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 7. " DITHMSK_H23 ,Event 23 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 6. " DITHMSK_H22 ,Event 22 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 5. " DITHMSK_H21 ,Event 21 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 4. " DITHMSK_H20 ,Event 20 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 3. " DITHMSK_H19 ,Event 19 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 2. " DITHMSK_H18 ,Event 18 dither pattern mask" "Not dithered,Dithered"
newline
bitfld.word 0x02 1. " DITHMSK_H17 ,Event 17 dither pattern mask" "Not dithered,Dithered"
bitfld.word 0x02 0. " DITHMSK_H16 ,Event 16 dither pattern mask" "Not dithered,Dithered"
endif
endif
newline
width 15.
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x40++0x03
line.long 0x00 "COUNT,SCT Counter Register"
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,L counter value"
else
group.word 0x40++0x03
line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit"
line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit"
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x44++0x03
line.long 0x00 "STATE,SCT State Register"
bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
else
group.word 0x44++0x03
line.word 0x00 "STATE_L,SCT State Register Low Counter 16-bit"
bitfld.word 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.word 0x02 "STATE_H,SCT State Register High Counter 16-bit"
bitfld.word 0x02 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
rgroup.long 0x48++0x03
line.long 0x00 "INPUT,SCT Input Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 23. " SIN7 ,Input 7 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 22. " SIN6 ,Input 6 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 21. " SIN5 ,Input 5 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 20. " SIN4 ,Input 4 state synchronized to the SCT clock" "0,1"
newline
endif
bitfld.long 0x00 19. " SIN3 ,Input 3 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 18. " SIN2 ,Input 2 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 17. " SIN1 ,Input 1 state synchronized to the SCT clock" "0,1"
bitfld.long 0x00 16. " SIN0 ,Input 0 state synchronized to the SCT clock" "0,1"
newline
sif !cpuis("LPC11E*")
bitfld.long 0x00 7. " AIN7 ,Real-time status of input 7" "0,1"
bitfld.long 0x00 6. " AIN6 ,Real-time status of input 6" "0,1"
bitfld.long 0x00 5. " AIN5 ,Real-time status of input 5" "0,1"
bitfld.long 0x00 4. " AIN4 ,Real-time status of input 4" "0,1"
newline
endif
bitfld.long 0x00 3. " AIN3 ,Real-time status of input 3" "0,1"
bitfld.long 0x00 2. " AIN2 ,Real-time status of input 2" "0,1"
bitfld.long 0x00 1. " AIN1 ,Real-time status of input 1" "0,1"
bitfld.long 0x00 0. " AIN0 ,Real-time status of input 0" "0,1"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x4C++0x03
line.long 0x00 "REGMODE,SCT Match/Capture Registers Mode Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 4. " REGMOD[4] ,5th pair of match/capture registers" "Match,Capture"
else
newline
bitfld.long 0x00 15. " REGMOD[15] ,16th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
newline
bitfld.long 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
newline
bitfld.long 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
endif
newline
bitfld.long 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
bitfld.long 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
else
group.word 0x4C++0x03
line.word 0x00 "REGMODE_L,SCT Match/Capture Registers Mode Register Low Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x00 4. " REGMOD_L[4] ,5th pair of match/capture registers" "Match,Capture"
newline
else
bitfld.word 0x00 15. " REGMOD_L[15] ,16th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
newline
endif
bitfld.word 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
bitfld.word 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
line.word 0x02 "REGMODE_H,SCT Match/Capture Registers Mode Register High Counter 16-bit"
sif cpuis("LPC11E*")
bitfld.word 0x02 4. " REGMOD_H[4] ,5th pair of match/capture registers" "Match,Capture"
newline
else
bitfld.word 0x02 15. " REGMOD_H[15] ,16th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x02 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
newline
bitfld.word 0x02 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
newline
endif
bitfld.word 0x02 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
bitfld.word 0x02 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
endif
sif cpuis("LPC11E*")
if (((((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)&&(((per.l(ad:0x5000E000))&0x01)==0x00))||((((per.l(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.l(ad:0x5000E000))&0x01)==0x01)))
group.long 0x50++0x13
line.long 0x00 "OUTPUT,SCT Output Register"
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
else
rgroup.long 0x50++0x13
line.long 0x00 "OUTPUT,SCT Output Register"
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
endif
else
group.long 0x50++0x13
line.long 0x00 "OUTPUT,SCT Output Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 15. " OUT15 ,Output 15" "Low,High"
bitfld.long 0x00 14. " OUT14 ,Output 14" "Low,High"
bitfld.long 0x00 13. " OUT13 ,Output 13" "Low,High"
bitfld.long 0x00 12. " OUT12 ,Output 12" "Low,High"
newline
bitfld.long 0x00 11. " OUT11 ,Output 11" "Low,High"
bitfld.long 0x00 10. " OUT10 ,Output 10" "Low,High"
bitfld.long 0x00 9. " OUT9 ,Output 9" "Low,High"
bitfld.long 0x00 8. " OUT8 ,Output 8" "Low,High"
newline
bitfld.long 0x00 7. " OUT7 ,Output 7" "Low,High"
bitfld.long 0x00 6. " OUT6 ,Output 6" "Low,High"
bitfld.long 0x00 5. " OUT5 ,Output 5" "Low,High"
bitfld.long 0x00 4. " OUT4 ,Output 4" "Low,High"
newline
endif
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
endif
newline
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,?..."
bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,?..."
bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,?..."
bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,?..."
bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,?..."
bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,?..."
bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,?..."
bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,?..."
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,?..."
newline
endif
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,?..."
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,?..."
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,?..."
newline
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,?..."
else
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,H is counting down,?..."
newline
endif
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,H is counting down,?..."
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,H is counting down,?..."
newline
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,H is counting down,?..."
endif
group.long 0x58++0x0B
line.long 0x00 "RES,SCT Conflict Resolution Register"
sif !cpuis("LPC11E*")
bitfld.long 0x00 30.--31. " O15RES ,Effect of simultaneous set and clear on output 15" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 28.--29. " O14RES ,Effect of simultaneous set and clear on output 14" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 26.--27. " O13RES ,Effect of simultaneous set and clear on output 13" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 24.--25. " O12RES ,Effect of simultaneous set and clear on output 12" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 22.--23. " O11RES ,Effect of simultaneous set and clear on output 11" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 20.--21. " O10RES ,Effect of simultaneous set and clear on output 10" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 18.--19. " O9RES ,Effect of simultaneous set and clear on output 9" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 16.--17. " O8RES ,Effect of simultaneous set and clear on output 8" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 14.--15. " O7RES ,Effect of simultaneous set and clear on output 7" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 12.--13. " O6RES ,Effect of simultaneous set and clear on output 6" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set output,Clear output,Toggle output"
newline
endif
bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set output,Clear output,Toggle output"
bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set output,Clear output,Toggle output"
newline
bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set output,Clear output,Toggle output"
line.long 0x04 "DMAREQ0,SCT DMA 0 Request Register"
rbitfld.long 0x04 31. " DRQ0 ,Indicates the state of DMA request 0" "Not requested,Requested"
bitfld.long 0x04 30. " DRL0 ,The SCT set DMA request 0 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested"
sif !cpuis("LPC11E*")
bitfld.long 0x04 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 14. " [14] ,Event 14 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 13. " [13] ,Event 13 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 12. " [12] ,Event 12 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 11. " [11] ,Event 11 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 10. " [10] ,Event 10 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 9. " [9] ,Event 9 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 8. " [8] ,Event 8 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 7. " [7] ,Event 7 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 6. " [6] ,Event 6 sets DMA request 0" "Not set,Set"
endif
newline
sif cpuis("LPC11E*")
bitfld.long 0x04 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
else
bitfld.long 0x04 5. " [5] ,Event 5 sets DMA request 0" "Not set,Set"
endif
bitfld.long 0x04 4. " [4] ,Event 4 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 3. " [3] ,Event 3 sets DMA request 0" "Not set,Set"
newline
bitfld.long 0x04 2. " [2] ,Event 2 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 1. " [1] ,Event 1 sets DMA request 0" "Not set,Set"
bitfld.long 0x04 0. " [0] ,Event 0 sets DMA request 0" "Not set,Set"
line.long 0x08 "DMAREQ1,SCT DMA 1 Request Register"
rbitfld.long 0x08 31. " DRQ1 ,Indicates the state of DMA request 1" "Not requested,Requested"
bitfld.long 0x08 30. " DRL1 ,The SCT set DMA request 1 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested"
sif !cpuis("LPC11E*")
bitfld.long 0x08 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 14. " [14] ,Event 14 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 13. " [13] ,Event 13 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 12. " [12] ,Event 12 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 11. " [11] ,Event 11 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 10. " [10] ,Event 10 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 9. " [9] ,Event 9 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 8. " [8] ,Event 8 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 7. " [7] ,Event 7 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 6. " [6] ,Event 6 sets DMA request 1" "Not set,Set"
endif
newline
sif cpuis("LPC11E*")
bitfld.long 0x08 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
else
bitfld.long 0x08 5. " [5] ,Event 5 sets DMA request 1" "Not set,Set"
endif
bitfld.long 0x08 4. " [4] ,Event 4 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 3. " [3] ,Event 3 sets DMA request 1" "Not set,Set"
newline
bitfld.long 0x08 2. " [2] ,Event 2 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 1. " [1] ,Event 1 sets DMA request 1" "Not set,Set"
bitfld.long 0x08 0. " [0] ,Event 0 sets DMA request 1" "Not set,Set"
sif cpuis("LPC11E*")
group.long 0xF0++0x07
line.long 0x00 "EVEN,SCT Flag Enable Register"
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled"
line.long 0x04 "EVFLAG,SCT Event Flag Register"
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred" "Not occurred,Occurred"
bitfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred"
bitfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred"
bitfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred"
bitfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred"
else
group.long 0xF0++0x07
line.long 0x00 "EVEN,SCT Flag Enable Register"
bitfld.long 0x00 15. " IEN15 ,Event 15 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Event 14 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Event 13 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " [12] ,Event 12 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Event 11 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Event 10 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " [9] ,Event 9 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Event 8 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Event 7 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " [6] ,Event 6 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Event 5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled"
line.long 0x04 "EVFLAG,SCT Event Flag Register"
eventfld.long 0x04 15. " FLAG15 ,Event 15occurred" "Not occurred,Occurred"
eventfld.long 0x04 14. " [14] ,Event 14 occurred" "Not occurred,Occurred"
eventfld.long 0x04 13. " [13] ,Event 13 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 12. " [12] ,Event 12 occurred" "Not occurred,Occurred"
eventfld.long 0x04 11. " [11] ,Event 11 occurred" "Not occurred,Occurred"
eventfld.long 0x04 10. " [10] ,Event 10 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 9. " [9] ,Event 9 occurred" "Not occurred,Occurred"
eventfld.long 0x04 8. " [8] ,Event 8 occurred" "Not occurred,Occurred"
eventfld.long 0x04 7. " [7] ,Event 7 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 6. " [6] ,Event 6 occurred" "Not occurred,Occurred"
eventfld.long 0x04 5. " [5] ,Event 5 occurred" "Not occurred,Occurred"
eventfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred"
eventfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred"
eventfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred"
newline
eventfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred"
endif
group.long 0xF8++0x03
line.long 0x00 "CONEN,SCT Conflict Enable Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 3. " NCEN[3] ,No change conflict event 3 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled"
else
bitfld.long 0x00 15. " NCEN[15] ,No change conflict event 15 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,No change conflict event 14 enable" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,No change conflict event 13 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " [12] ,No change conflict event 12 enable" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,No change conflict event 11 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,No change conflict event 10 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " [9] ,No change conflict event 9 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,No change conflict event 8 enable" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,No change conflict event 7 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " [6] ,No change conflict event 6 enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,No change conflict event 5 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,No change conflict event 4 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " [3] ,No change conflict event 3 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled"
endif
sif cpuis("LPC11E*")
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,SCT Conflict Flag Register"
bitfld.long 0x00 31. " BUSERRH ,Bus error from this SCT involved writing CTR H/STATE H/MATCH H/Output register" "No error,Error"
bitfld.long 0x00 30. " BUSERRL ,Bus error from this SCT involved writing CTR L-Unified/STATE L-Unified/MATCH L-Unified/Output register" "No error,Error"
bitfld.long 0x00 3. " NCFLAG[3] ,No-change conflict event 3 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 2. " [2] ,No-change conflict event 2 occurred" "Not occurred,Occurred"
bitfld.long 0x00 1. " [1] ,No-change conflict event 1 occurred" "Not occurred,Occurred"
bitfld.long 0x00 0. " [0] ,No-change conflict event 0 occurred" "Not occurred,Occurred"
else
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,SCT Conflict Flag Register"
bitfld.long 0x00 31. " BUSERRH ,Bus error" "No error,Error"
bitfld.long 0x00 30. " BUSERRL ,Bus error" "No error,Error"
bitfld.long 0x00 15. " NCFLAG15 ,No-change conflict event 15 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 14. " NCFLAG14 ,No-change conflict event 14 occurred" "Not occurred,Occurred"
bitfld.long 0x00 13. " NCFLAG13 ,No-change conflict event 13 occurred" "Not occurred,Occurred"
bitfld.long 0x00 12. " NCFLAG12 ,No-change conflict event 12 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 11. " NCFLAG11 ,No-change conflict event 11 occurred" "Not occurred,Occurred"
bitfld.long 0x00 10. " NCFLAG10 ,No-change conflict event 10 occurred" "Not occurred,Occurred"
bitfld.long 0x00 9. " NCFLAG9 ,No-change conflict event 9 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 8. " NCFLAG8 ,No-change conflict event 8 occurred" "Not occurred,Occurred"
bitfld.long 0x00 7. " NCFLAG7 ,No-change conflict event 7 occurred" "Not occurred,Occurred"
bitfld.long 0x00 6. " NCFLAG6 ,No-change conflict event 6 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 5. " NCFLAG5 ,No-change conflict event 5 occurred" "Not occurred,Occurred"
bitfld.long 0x00 4. " NCFLAG4 ,No-change conflict event 4 occurred" "Not occurred,Occurred"
bitfld.long 0x00 3. " NCFLAG3 ,No-change conflict event 3 occurred" "Not occurred,Occurred"
newline
bitfld.long 0x00 2. " NCFLAG2 ,No-change conflict event 2 occurred" "Not occurred,Occurred"
bitfld.long 0x00 1. " NCFLAG1 ,No-change conflict event 1 occurred" "Not occurred,Occurred"
bitfld.long 0x00 0. " NCFLAG0 ,No-change conflict event 0 occurred" "Not occurred,Occurred"
endif
width 26.
tree "Event 0 (Regmode0 0/1)"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000E000+0x4C))&(1<<0.))==(1<<0.))
rgroup.long 0x100++0x03
line.long 0x00 "CAP0,SCT Capture Register 0"
else
rgroup.long 0x100++0x03
line.long 0x00 "MATCH0,SCT Match Register 0"
endif
else
if (((per.l(ad:0x5000E000+0x4C))&(1<<0.))==(1<<0.))
group.long 0x100++0x03
line.long 0x00 "CAP0,SCT Capture Register 0"
else
group.long 0x100++0x03
line.long 0x00 "MATCH0,SCT Match Register 0"
endif
endif
else
if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<0.))==(1<<0.))
group.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
group.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<0.))==(1<<0.))
group.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
else
group.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<0.))==(1<<0.))
rgroup.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
rgroup.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<0.))==(1<<0.))
group.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
else
group.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<0.))==(1<<0.))
group.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
group.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<0.))==(1<<0.))
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 Low Counter 16-bit"
else
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000E000+0x4C))&(1<<0.))==(1<<0.))
rgroup.word 0x100++0x01
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
else
rgroup.word 0x100++0x01
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<0.))==(1<<0.))
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
else
rgroup.word (0x100+0x02)++0x01
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x140++0x03
line.long 0x00 "FRACMAT0_L,SCT Fractional Match Register 0"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x140++0x03
line.word 0x00 "FRACMAT0_L,SCT Fractional Match Register 0"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT0_H,SCT Fractional Match Register 0"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x100+0x100)++0x03
line.long 0x00 "MATCHREL0/CAPCTRL0,SCT Match/capture Reload Register 0"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x100+0x100)++0x03
line.word 0x00 "MATCHREL0_L/CAPCTRL0_L,SCT Match/capture Reload Register 0"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL0_H/CAPCTRL0_H,SCT Match/capture Reload Register 0"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x140+0x100)++0x03
line.long 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x140+0x100)++0x03
line.word 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL0_H,SCT Fractional Match Reload Register 0"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x100+0x200)++0x03
line.long 0x00 "EV0_STATE,SCT Event State Mask 0"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x100+0x204)++0x03
line.long 0x00 "EVCTRL0,SCT Event Control Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x100+0x204)++0x03
line.long 0x00 "EVCTRL0,SCT Event Control Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x100+0x400)++0x07
line.long 0x00 "OUT0_SET,SCT Output Set Register 0"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set"
line.long 0x04 "OUT0_CLR,SCT Output Clear Register 0"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared"
else
group.long (0x100+0x400)++0x07
line.long 0x00 "OUTPUTSET0,SCT Output Set Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 0" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 0" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 0" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 0" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 0" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 0" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 0" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 0" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 0" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 0" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 0" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set"
line.long 0x04 "OUTPUTCL0,SCT Output Clear Register 0"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 0" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 0" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared"
endif
tree.end
tree "Event 1 (Regmode1 0/1)"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000E000+0x4C))&(1<<1.))==(1<<1.))
rgroup.long 0x104++0x03
line.long 0x00 "CAP1,SCT Capture Register 1"
else
rgroup.long 0x104++0x03
line.long 0x00 "MATCH1,SCT Match Register 1"
endif
else
if (((per.l(ad:0x5000E000+0x4C))&(1<<1.))==(1<<1.))
group.long 0x104++0x03
line.long 0x00 "CAP1,SCT Capture Register 1"
else
group.long 0x104++0x03
line.long 0x00 "MATCH1,SCT Match Register 1"
endif
endif
else
if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<1.))==(1<<1.))
group.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
group.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<1.))==(1<<1.))
group.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
else
group.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<1.))==(1<<1.))
rgroup.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
rgroup.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<1.))==(1<<1.))
group.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
else
group.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<1.))==(1<<1.))
group.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
group.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<1.))==(1<<1.))
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 Low Counter 16-bit"
else
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000E000+0x4C))&(1<<1.))==(1<<1.))
rgroup.word 0x104++0x01
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
else
rgroup.word 0x104++0x01
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<1.))==(1<<1.))
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
else
rgroup.word (0x104+0x02)++0x01
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x144++0x03
line.long 0x00 "FRACMAT1_L,SCT Fractional Match Register 1"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x144++0x03
line.word 0x00 "FRACMAT1_L,SCT Fractional Match Register 1"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT1_H,SCT Fractional Match Register 1"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x104+0x100)++0x03
line.long 0x00 "MATCHREL1/CAPCTRL1,SCT Match/capture Reload Register 1"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x104+0x100)++0x03
line.word 0x00 "MATCHREL1_L/CAPCTRL1_L,SCT Match/capture Reload Register 1"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL1_H/CAPCTRL1_H,SCT Match/capture Reload Register 1"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x144+0x100)++0x03
line.long 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x144+0x100)++0x03
line.word 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL1_H,SCT Fractional Match Reload Register 1"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x108+0x200)++0x03
line.long 0x00 "EV1_STATE,SCT Event State Mask 1"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x108+0x204)++0x03
line.long 0x00 "EVCTRL1,SCT Event Control Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x108+0x204)++0x03
line.long 0x00 "EVCTRL1,SCT Event Control Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x108+0x400)++0x07
line.long 0x00 "OUT1_SET,SCT Output Set Register 1"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set"
line.long 0x04 "OUT1_CLR,SCT Output Clear Register 1"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared"
else
group.long (0x108+0x400)++0x07
line.long 0x00 "OUTPUTSET1,SCT Output Set Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 1" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 1" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 1" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 1" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 1" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 1" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 1" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 1" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 1" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 1" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 1" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set"
line.long 0x04 "OUTPUTCL1,SCT Output Clear Register 1"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 1" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 1" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared"
endif
tree.end
tree "Event 2 (Regmode2 0/1)"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000E000+0x4C))&(1<<2.))==(1<<2.))
rgroup.long 0x108++0x03
line.long 0x00 "CAP2,SCT Capture Register 2"
else
rgroup.long 0x108++0x03
line.long 0x00 "MATCH2,SCT Match Register 2"
endif
else
if (((per.l(ad:0x5000E000+0x4C))&(1<<2.))==(1<<2.))
group.long 0x108++0x03
line.long 0x00 "CAP2,SCT Capture Register 2"
else
group.long 0x108++0x03
line.long 0x00 "MATCH2,SCT Match Register 2"
endif
endif
else
if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<2.))==(1<<2.))
group.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
group.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<2.))==(1<<2.))
group.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
else
group.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<2.))==(1<<2.))
rgroup.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
rgroup.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<2.))==(1<<2.))
group.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
else
group.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<2.))==(1<<2.))
group.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
group.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<2.))==(1<<2.))
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 Low Counter 16-bit"
else
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000E000+0x4C))&(1<<2.))==(1<<2.))
rgroup.word 0x108++0x01
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
else
rgroup.word 0x108++0x01
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<2.))==(1<<2.))
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
else
rgroup.word (0x108+0x02)++0x01
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x148++0x03
line.long 0x00 "FRACMAT2_L,SCT Fractional Match Register 2"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x148++0x03
line.word 0x00 "FRACMAT2_L,SCT Fractional Match Register 2"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT2_H,SCT Fractional Match Register 2"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x108+0x100)++0x03
line.long 0x00 "MATCHREL2/CAPCTRL2,SCT Match/capture Reload Register 2"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x108+0x100)++0x03
line.word 0x00 "MATCHREL2_L/CAPCTRL2_L,SCT Match/capture Reload Register 2"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL2_H/CAPCTRL2_H,SCT Match/capture Reload Register 2"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x148+0x100)++0x03
line.long 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x148+0x100)++0x03
line.word 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL2_H,SCT Fractional Match Reload Register 2"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x110+0x200)++0x03
line.long 0x00 "EV2_STATE,SCT Event State Mask 2"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x110+0x204)++0x03
line.long 0x00 "EVCTRL2,SCT Event Control Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x110+0x204)++0x03
line.long 0x00 "EVCTRL2,SCT Event Control Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x110+0x400)++0x07
line.long 0x00 "OUT2_SET,SCT Output Set Register 2"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set"
line.long 0x04 "OUT2_CLR,SCT Output Clear Register 2"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared"
else
group.long (0x110+0x400)++0x07
line.long 0x00 "OUTPUTSET2,SCT Output Set Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 2" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 2" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 2" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 2" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 2" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 2" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 2" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 2" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 2" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 2" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 2" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set"
line.long 0x04 "OUTPUTCL2,SCT Output Clear Register 2"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 2" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 2" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared"
endif
tree.end
tree "Event 3 (Regmode3 0/1)"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000E000+0x4C))&(1<<3.))==(1<<3.))
rgroup.long 0x10C++0x03
line.long 0x00 "CAP3,SCT Capture Register 3"
else
rgroup.long 0x10C++0x03
line.long 0x00 "MATCH3,SCT Match Register 3"
endif
else
if (((per.l(ad:0x5000E000+0x4C))&(1<<3.))==(1<<3.))
group.long 0x10C++0x03
line.long 0x00 "CAP3,SCT Capture Register 3"
else
group.long 0x10C++0x03
line.long 0x00 "MATCH3,SCT Match Register 3"
endif
endif
else
if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<3.))==(1<<3.))
group.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
group.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<3.))==(1<<3.))
group.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
else
group.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<3.))==(1<<3.))
rgroup.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
rgroup.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<3.))==(1<<3.))
group.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
else
group.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&(1<<3.))==(1<<3.))
group.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
group.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<3.))==(1<<3.))
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 Low Counter 16-bit"
else
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000E000+0x4C))&(1<<3.))==(1<<3.))
rgroup.word 0x10C++0x01
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
else
rgroup.word 0x10C++0x01
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&(1<<3.))==(1<<3.))
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
else
rgroup.word (0x10C+0x02)++0x01
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
endif
endif
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long 0x14C++0x03
line.long 0x00 "FRACMAT3_L,SCT Fractional Match Register 3"
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word 0x14C++0x03
line.word 0x00 "FRACMAT3_L,SCT Fractional Match Register 3"
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMAT3_H,SCT Fractional Match Register 3"
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x10C+0x100)++0x03
line.long 0x00 "MATCHREL3/CAPCTRL3,SCT Match/capture Reload Register 3"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x10C+0x100)++0x03
line.word 0x00 "MATCHREL3_L/CAPCTRL3_L,SCT Match/capture Reload Register 3"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL3_H/CAPCTRL3_H,SCT Match/capture Reload Register 3"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x14C+0x100)++0x03
line.long 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3"
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.word (0x14C+0x100)++0x03
line.word 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3"
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x02 "FRACMATREL3_H,SCT Fractional Match Reload Register 3"
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long (0x118+0x200)++0x03
line.long 0x00 "EV3_STATE,SCT Event State Mask 3"
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
newline
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
newline
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
newline
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
newline
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
newline
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
newline
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
newline
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
else
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x118+0x204)++0x03
line.long 0x00 "EVCTRL3,SCT Event Control Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
textfld " "
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long (0x118+0x204)++0x03
line.long 0x00 "EVCTRL3,SCT Event Control Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
endif
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("LPC11E*")
group.long (0x118+0x400)++0x07
line.long 0x00 "OUT3_SET,SCT Output Set Register 3"
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set"
newline
bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set"
line.long 0x04 "OUT3_CLR,SCT Output Clear Register 3"
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared"
newline
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared"
else
group.long (0x118+0x400)++0x07
line.long 0x00 "OUTPUTSET3,SCT Output Set Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
newline
else
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 3" "Not set,Set"
bitfld.long 0x00 14. " [14] ,Event 14 to set output 3" "Not set,Set"
bitfld.long 0x00 13. " [13] ,Event 13 to set output 3" "Not set,Set"
bitfld.long 0x00 12. " [12] ,Event 12 to set output 3" "Not set,Set"
newline
bitfld.long 0x00 11. " [11] ,Event 11 to set output 3" "Not set,Set"
bitfld.long 0x00 10. " [10] ,Event 10 to set output 3" "Not set,Set"
bitfld.long 0x00 9. " [9] ,Event 9 to set output 3" "Not set,Set"
bitfld.long 0x00 8. " [8] ,Event 8 to set output 3" "Not set,Set"
newline
bitfld.long 0x00 7. " [7] ,Event 7 to set output 3" "Not set,Set"
bitfld.long 0x00 6. " [6] ,Event 6 to set output 3" "Not set,Set"
bitfld.long 0x00 5. " [5] ,Event 5 to set output 3" "Not set,Set"
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
newline
endif
bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set"
bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set"
bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set"
bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set"
line.long 0x04 "OUTPUTCL3,SCT Output Clear Register 3"
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
newline
else
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 3" "Not cleared,Cleared"
newline
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 3" "Not cleared,Cleared"
newline
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
newline
endif
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared"
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared"
endif
tree.end
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")||cpuis("LPC11E*")
tree "Event 4 (Regmode4 0/1)"
if (((per.l(ad:0x5000E000))&0x01)==0x01)
if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00)
if (((per.l(ad:0x5000E000+0x4C))&0x10)==0x10)
rgroup.long 0x110++0x03
line.long 0x00 "CAP4,SCT Capture Register 4"
else
rgroup.long 0x110++0x03
line.long 0x00 "MATCH4,SCT Match Register 4"
endif
else
if (((per.l(ad:0x5000E000+0x4C))&0x10)==0x10)
group.long 0x110++0x03
line.long 0x00 "CAP4,SCT Capture Register 4"
else
group.long 0x110++0x03
line.long 0x00 "MATCH4,SCT Match Register 4"
endif
endif
else
if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10)
group.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
group.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10)
group.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
else
group.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10)
rgroup.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
rgroup.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10)
group.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
else
group.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
endif
elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)
if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10)
group.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
group.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10)
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 Low Counter 16-bit"
else
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 Low Counter 16-bit"
endif
else
if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10)
rgroup.word 0x110++0x01
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
else
rgroup.word 0x110++0x01
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
endif
if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10)
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
else
rgroup.word (0x110+0x02)++0x01
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
endif
endif
endif
if (((per.l(ad:0x5000E000))&0x01)==0x01)
group.long (0x210)++0x03
line.long 0x00 "MATCHREL4/CAPCTRL4,SCT Match/capture Reload Register 4"
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
newline
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
newline
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
newline
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
newline
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
else
group.word (0x210)++0x03
line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT Match/capture Reload Register 4"
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT Match/capture Reload Register 4"
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
newline
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
newline
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
newline
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
endif
group.long (0x320)++0x07
line.long 0x00 "EVSTATEMSK4,SCT Event State Mask 4"
sif cpuis("LPC11E*")
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
line.long 0x04 "EVCTRL4,SCT Event Control Register 4"
bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "Event 5 (Regmode5 0/1)"
group.long (0x328)++0x07
line.long 0x00 "EVSTATEMSK5,SCT Event State Mask 5"
sif cpuis("LPC11E*")
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
newline
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
newline
endif
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
line.long 0x04 "EVCTRL5,SCT Event Control Register 5"
bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
newline
bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
newline
bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output"
bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H"
bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
endif
width 0x0B
tree.end
tree.end
endif
tree.open "CT16B0/1 (16-bit Counter/Timers)"
tree "CT16B0"
base ad:0x4000C000
width 6.
group.long 0x00++0x07
line.long 0x00 "IR,Interrupt Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt"
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt"
newline
endif
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt"
line.long 0x04 "TCR,Timer Control Register"
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
else
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
endif
group.long 0x0C++0x07
line.long 0x00 "PR,Timer Prescale Register"
hexmask.long.word 0x00 0.--15. 1. " PR ,Prescale max value"
line.long 0x04 "PC,Timer Prescale Counter Register"
hexmask.long.word 0x04 0.--15. 1. " PC ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 8. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled"
bitfld.long 0x00 7. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled"
bitfld.long 0x00 6. " CAP1RE ,Capture on CT16B0_CAP1 rising edge" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B0_CAP0 event" "Disabled,Enabled"
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B0_CAP0 falling edge" "Disabled,Enabled"
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B0_CAP0 rising edge" "Disabled,Enabled"
sif cpuis("LPC11E6*")
rgroup.long 0x2C++0x03
line.long 0x00 "CR0,Capture Register 0"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR1,Capture Register 1"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR2,Capture Register 2"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
else
rgroup.long 0x2C++0x03
line.long 0x00 "CR0,Capture Register 0"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR1,Capture Register 1"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
endif
else
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
endif
sif cpuis("LPC11E*")
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising edge of CAP0,Falling edge of CAP0,,,Rising edge of CAP1,Falling edge of CAP1,?..."
bitfld.long 0x00 4. " ENCC ,Clearing of timer and the prescaler enable" "Disabled,Enabled"
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CT16B0_CAP0,,CT16B0_CAP1,?..."
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer: rising edges,Counter: rising edges,Counter: falling edges,Counter: both edges"
else
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
endif
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 3. " PWMEN3 ,PWM mode enable for channel 3" "Disabled,Enabled"
bitfld.long 0x00 2. " PWMEN2 ,PWM mode enable for channel 2" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 1. " PWMEN1 ,PWM mode enable for channel 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PWMEN0 ,PWM mode enable for channel 0" "Disabled,Enabled"
width 0x0B
tree.end
tree "CT16B1"
base ad:0x40010000
width 6.
group.long 0x00++0x07
line.long 0x00 "IR,Interrupt Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt"
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt"
newline
endif
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt"
line.long 0x04 "TCR,Timer Control Register"
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
else
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
endif
group.long 0x0C++0x07
line.long 0x00 "PR,Timer Prescale Register"
hexmask.long.word 0x00 0.--15. 1. " PR ,Prescale max value"
line.long 0x04 "PC,Timer Prescale Counter Register"
hexmask.long.word 0x04 0.--15. 1. " PC ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B1_CAP1 event" "Disabled,Enabled"
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B1_CAP1 falling edge" "Disabled,Enabled"
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B1_CAP1 rising edge" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B1_CAP0 event" "Disabled,Enabled"
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B1_CAP0 falling edge" "Disabled,Enabled"
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B1_CAP0 rising edge" "Disabled,Enabled"
rgroup.long 0x2C++0x03
line.long 0x00 "CR0,Capture Register 0"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR1,Capture Register 1"
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
else
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value"
endif
sif cpuis("LPC11E*")
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising edge of CAP0,Falling edge of CAP0,Rising edge of CAP1,Falling edge of CAP1,?..."
bitfld.long 0x00 4. " ENCC ,Clearing of timer and the prescaler enable" "Disabled,Enabled"
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CT16B1_CAP0,CT16B1_CAP1,?..."
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer: rising edges,Counter: rising edges,Counter: falling edges,Counter: both edges"
else
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
endif
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 3. " PWMEN3 ,PWM mode enable for channel 3" "Disabled,Enabled"
bitfld.long 0x00 2. " PWMEN2 ,PWM mode enable for channel 2" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 1. " PWMEN1 ,PWM mode enable for channel 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PWMEN0 ,PWM mode enable for channel 0" "Disabled,Enabled"
width 0x0B
tree.end
tree.end
tree.open "CT32B0/1 (32-bit Counter/Timers)"
tree "CT32B0"
base ad:0x40014000
width 6.
group.long 0x00++0x07
line.long 0x00 "IR,Interrupt Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt"
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt"
newline
endif
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt"
line.long 0x04 "TCR,Timer Control Register"
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
else
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
endif
group.long 0x0C++0x07
line.long 0x00 "PR,Timer Prescale Register"
line.long 0x04 "PC,Timer Prescale Counter Register"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 8. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
bitfld.long 0x00 7. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
bitfld.long 0x00 6. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B0_CAP0 event" "Disabled,Enabled"
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B0_CAP0 falling edge" "Disabled,Enabled"
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B0_CAP0 rising edge" "Disabled,Enabled"
sif cpuis("LPC11E6*")
rgroup.long 0x2C++0x03
line.long 0x00 "CR0,Capture Register 0"
rgroup.long 0x30++0x03
line.long 0x00 "CR1,Capture Register 1"
rgroup.long 0x34++0x03
line.long 0x00 "CR2,Capture Register 2"
else
rgroup.long 0x2C++0x03
line.long 0x00 "CR0,Capture Register 0"
rgroup.long 0x34++0x03
line.long 0x00 "CR1,Capture Register 1"
endif
else
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
endif
sif cpuis("LPC11E*")
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising edge of CAP0,Falling edge of CAP0,,,Rising edge of CAP1,Falling edge of CAP1,?..."
bitfld.long 0x00 4. " ENCC ,Clearing of timer and the prescaler enable" "Disabled,Enabled"
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CT32B0_CAP0,,CT32B0_CAP1,?..."
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer: rising edges,Counter: rising edges,Counter: falling edges,Counter: both edges"
else
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
endif
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 3. " PWMEN3 ,PWM mode enable for channel 3" "Disabled,Enabled"
bitfld.long 0x00 2. " PWMEN2 ,PWM mode enable for channel 2" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 1. " PWMEN1 ,PWM mode enable for channel 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PWMEN0 ,PWM mode enable for channel 0" "Disabled,Enabled"
width 0x0B
tree.end
tree "CT32B1"
base ad:0x40018000
width 6.
group.long 0x00++0x07
line.long 0x00 "IR,Interrupt Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt"
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt"
newline
endif
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt"
line.long 0x04 "TCR,Timer Control Register"
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
else
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter Register"
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
endif
group.long 0x0C++0x07
line.long 0x00 "PR,Timer Prescale Register"
line.long 0x04 "PC,Timer Prescale Counter Register"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
sif cpuis("LPC11E*")
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B1_CAP0 event" "Disabled,Enabled"
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B1_CAP0 falling edge" "Disabled,Enabled"
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B1_CAP0 rising edge" "Disabled,Enabled"
rgroup.long 0x2C++0x03
line.long 0x00 "CR0,Capture Register 0"
rgroup.long 0x30++0x03
line.long 0x00 "CR1,Capture Register 1"
else
group.long 0x18++0x03
line.long 0x00 "MR0,Match Register 0"
group.long 0x1C++0x03
line.long 0x00 "MR1,Match Register 1"
group.long 0x20++0x03
line.long 0x00 "MR2,Match Register 2"
group.long 0x24++0x03
line.long 0x00 "MR3,Match Register 3"
endif
sif cpuis("LPC11E*")
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising edge of CAP0,Falling edge of CAP0,Rising edge of CAP1,Falling edge of CAP1,?..."
bitfld.long 0x00 4. " ENCC ,Clearing of timer and the prescaler enable" "Disabled,Enabled"
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CT32B1_CAP0,CT32B1_CAP1,?..."
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer: rising edges,Counter: rising edges,Counter: falling edges,Counter: both edges"
else
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle"
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle"
newline
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
endif
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
sif cpuis("LPC11E*")
bitfld.long 0x00 3. " PWMEN3 ,PWM mode enable for channel 3" "Disabled,Enabled"
bitfld.long 0x00 2. " PWMEN2 ,PWM mode enable for channel 2" "Disabled,Enabled"
newline
endif
bitfld.long 0x00 1. " PWMEN1 ,PWM mode enable for channel 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PWMEN0 ,PWM mode enable for channel 0" "Disabled,Enabled"
width 0x0B
tree.end
tree.end
sif cpuis("LPC11E6*")
tree "RTC (Real Time Clock)"
base ad:0x40024000
width 7.
sif cpuis("LPC11U6*")
group.long 0x00++0x03
line.long 0x00 "CTRL,RTC Control Register"
bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1.024 kHz clock enable" "Disabled,Enabled"
bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1.024 kHz timer wake-up enable for deep power-down" "Disabled,Enabled"
bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " WAKE1KHZ ,RTC 1.024 kHz timer wake-up flag status" "Run,Time-out"
bitfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm"
bitfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected"
bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset"
elif cpuis("LPC11E6*")
group.long 0x00++0x03
line.long 0x00 "CTRL,RTC Control Register"
bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1 kHz clock enable" "Disabled,Enabled"
bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1 kHz timer wake-up enable for deep power-down" "Disabled,Enabled"
bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled"
newline
eventfld.long 0x00 3. " WAKE1KHZ ,RTC 1 kHz timer wake-up flag status" "Run,Time-out"
eventfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm"
eventfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected"
bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset"
else
group.long 0x00++0x03
line.long 0x00 "CTRL,RTC Control Register"
bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1 kHz clock enable" "Disabled,Enabled"
bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1 kHz timer wake-up enable for deep power-down" "Disabled,Enabled"
bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " WAKE1KHZ ,RTC 1 kHz timer wake-up flag status" "Run,Time-out"
bitfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm"
bitfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected"
bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset"
endif
group.long 0x04++0x03
line.long 0x00 "MATCH,RTC Match Register"
if (((per.l((ad:0x40024000)))&0x80)==0x80)
rgroup.long 0x08++0x03
line.long 0x00 "COUNT,RTC Counter Register"
else
group.long 0x08++0x03
line.long 0x00 "COUNT,RTC Counter Register"
endif
group.long 0x0C++0x03
line.long 0x00 "WAKE,RTC High-Resolution/Wake-Up Timer Control Register"
hexmask.long.word 0x00 0.--15. 1. " VAL ,High-resolution/Wake-up timer current value"
width 0x0B
tree.end
endif
tree "WWDT (Windowed Watchdog Timer)"
base ad:0x40004000
width 9.
group.long 0x00++0x07
line.long 0x00 "MOD,Watchdog Mode Register"
bitfld.long 0x00 5. " LOCK ,Prevents disabling or powering down the watchdog oscillator" "Not locked,Locked"
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Flexible,Threshold"
bitfld.long 0x00 3. " WDINT ,Warning interrupt flag" "No interrupt,Interrupt"
bitfld.long 0x00 2. " WDTOF ,Watchdog time-out flag" "No timeout,Timeout"
newline
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable" "Disabled,Enabled"
bitfld.long 0x00 0. " WDEN ,Watchdog enable" "Disabled,Enabled"
line.long 0x04 "TC,Watchdog Timer Constant Register"
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value"
wgroup.long 0x08++0x03
line.long 0x00 "FEED,Watchdog Feed Register"
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value"
rgroup.long 0x0C++0x03
line.long 0x00 "TV,Watchdog Timer Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
sif cpuis("LPC11E*")||cpuis("LPC11U*")||cpuis("LPC11U6*")
group.long 0x10++0x03
line.long 0x00 "CLKSEL,Watchdog Clock Select Register"
bitfld.long 0x00 31. " LOCK ,Lock" "Not locked,Locked"
bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,WDOSC"
endif
group.long 0x14++0x07
line.long 0x00 "WARNINT,Watchdog Timer Warning Interrupt Register"
hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value"
line.long 0x04 "WINDOW,Watchdog Timer Window Register"
hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value"
width 0x0B
tree.end
sif cpuis("LPC11E6*")
tree "CRC"
base ad:0x50000000
width 9.
group.long 0x00++0x07
line.long 0x00 "MODE,CRC Mode Register"
bitfld.long 0x00 5. " CMPL_SUM ,Data 1's complement enable for CRC_SUM" "Disabled,Enabled"
bitfld.long 0x00 4. " BIT_RVS_SUM ,Bit order for CRC_SUM" "Not reversed,Reversed"
bitfld.long 0x00 3. " CMPL_WR ,Data 1's complement enable for CRC_WR_DATA" "Disabled,Enabled"
newline
bitfld.long 0x00 2. " BIT_RVS_WR ,Bit order for CRC_WR_DATA" "Not reversed,Reversed"
bitfld.long 0x00 0.--1. " CRC_POLY ,CRC polynomial select" "CRC-CCITT,CRC-16,CRC-32,CRC-32"
line.long 0x04 "SEED,CRC Seed Register"
rgroup.long 0x08++0x03
line.long 0x00 "SUM,CRC Checksum Register"
wgroup.long 0x08++0x03
line.long 0x00 "WR_DATA,CRC Data Register"
width 0x0B
tree.end
endif
tree "FLASHCTRL (Flash Controller)"
base ad:0x4003C000
width 11.
group.long 0x10++0x03
line.long 0x00 "FLASHCFG,Flash Configuration Register"
bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..."
group.long 0x20++0x07
line.long 0x00 "FMSSTART,Signature Start Address Register"
hexmask.long.tbyte 0x00 0.--16. 1. " START ,Start address for signature generation"
line.long 0x04 "FMSSTOP,Signature Stop-Address Register"
sif cpuis("LPC111*")||cpuis("LPC112*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC11D14")
bitfld.long 0x04 17. " SIG_START ,Signature generation start" "Not started,Started"
else
bitfld.long 0x04 17. " SIG_START ,Signature generation start" "Not started,Started"
endif
newline
hexmask.long.tbyte 0x04 0.--16. 1. " STOPA ,Stop address for signature generation"
rgroup.long 0x2C++0x03
line.long 0x00 "FMSW0,Signature Word 0"
sif cpuis("LPC11D14")||cpuis("LPC11C*")||cpuis("LPC11E11")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")
rgroup.long 0x30++0x0B
line.long 0x00 "FMSW1,Signature Word 1"
line.long 0x04 "FMSW2,Signature Word 2"
line.long 0x08 "FMSW3,Signature Word 3"
elif cpuis("LPC11E35FHI33")||cpuis("LPC11E36")||cpuis("LPC11E37")||cpuis("LPC11E37H")||cpuis("LPC111*")||cpuis("LPC112*")||cpuis("LPC11*LV")||cpuis("LPC110*")
rgroup.long 0xC0++0x0B
line.long 0x00 "FMSW1,Signature Word 1"
line.long 0x04 "FMSW2,Signature Word 2"
line.long 0x08 "FMSW3,Signature Word 3"
endif
sif cpuis("LPC11E11")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E35FHI33")||cpuis("LPC11E36")||cpuis("LPC11E37")||cpuis("LPC11E37H")
group.long 0x9C++0x0B
line.long 0x00 "EEMSSTART,EEPROM BIST start address register"
hexmask.long.word 0x00 0.--13. 1. " STARTA ,BIST start address"
line.long 0x04 "EEMSSTOP,EEPROM BIST stop address register"
eventfld.long 0x04 31. " STRTBIST ,BIST start bit" "Stop,Start"
bitfld.long 0x04 30. " DEVSEL ,BIST device select bit" "Not selected,Selected"
hexmask.long.word 0x04 0.--13. 1. " STOPA ,BIST stop address"
line.long 0x08 "EEMSSIG,EEPROM signature register "
hexmask.long.word 0x08 16.--31. 1. " PARITY_SIG ,BIST 16-bit signature calculated from only the parity bits of the data bytes"
hexmask.long.word 0x08 0.--15. 1. " DATA_SIG ,BIST 16-bit signature calculated from only the data bytes"
endif
sif cpuis("LPC111*")||cpuis("LPC112*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC11D14")||cpuis("LPC11C*")||cpuis("LPC11E1?")||cpuis("LPC11E3*")
rgroup.long 0x0FE0++0x03
line.long 0x00 "FMSTAT,Flash Module Status Register"
bitfld.long 0x00 2. " SIG_DONE ,Signature generation completion flag" "Not occurred,Occurred"
wgroup.long 0x0FE8++0x03
line.long 0x00 "FMSTATCLR,Flash Module Status Clear Register"
bitfld.long 0x00 2. " SIG_DONE_CLR ,Signature generation completion flag clear" "No effect,Clear"
endif
width 0x0B
tree.end
newline
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