42873 lines
2.9 MiB
42873 lines
2.9 MiB
; --------------------------------------------------------------------------------
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; @Title: KinetisE On-Chip Peripherals
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; @Props: Released
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; @Author: NAN, ASK, STR, KMB, FSZ
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; @Changelog: 2018-02-21 KMB
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; 2018-02-27 FSZ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: MKE04P80M48SF0RM.pdf (Rev 2, 2014-02)
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; MKE02P64M40SF0RM.pdf (Rev 2, 2014-02)
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; MKE06P80M48SF0RM.pdf (Rev 2, 2014-02)
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; KE1xFP100M168SF0RM.pdf (Rev. 2, 2016-09)
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; KE1xZP100M72SF0RM.pdf (Rev. 2, 2016-09)
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; MKE04P80M48SF0RM.pdf (Rev. 3, 2016-07)
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; MKE02Z64M20SF0RM.pdf (Rev 3, 2013-07)
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; MKE02P64M40SF0RM.pdf (Rev 3, 2014-11)
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; @Core: Cortex-M0P, Cortex-M4
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; @Chip: MKE02Z32VLC2R, MKE02Z32VLD2R, MKE02Z32VLC4R, MKE02Z32VLD4R,
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; MKE02Z64VLD4R, MKE02Z64VLH4R, MKE02Z16VFM4, MKE02Z32VFM4,
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; MKE02Z64VFM4, MKE02Z64VLC4, MKE04Z64VLK4R, MKE04Z128VLH4R,
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; MKE14Z128VLH7, MKE14Z256VLH7, MKE14Z128VLL7, MKE14Z256VLL7,
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; MKE15Z128VLH7, MKE15Z256VLH7, MKE15Z128VLL7, MKE15Z256VLL7,
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; MKE14F256VLL16, MKE14F512VLL16, MKE14F256VLH16, MKE14F512VLH16,
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; MKE16F256VLL16, MKE16F512VLL16, MKE16F256VLH16, MKE16F512VLH16,
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; MKE18F256VLL16, MKE18F512VLL16, MKE18F256VLH16, MKE18F512VLH16,
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; MKE02Z16VLC2R, MKE02Z32VFM4R
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perkinetise.per 17736 2024-04-08 09:26:07Z kwisniewski $
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sif cpuis("MKE1?F*")
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
else
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
config 16. 8.
|
|
tree "Port Data Registers"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "Port A"
|
|
base ad:0x40049000
|
|
width 13.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "PORTA_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE0/ACMP0_IN0/TSI0_CH17,PTA0,FTM2_CH1,LPI2C0_SCLS,FXIO_D2,FTM2_QD_PHA,LPUART0_CTS,TRGMUX_OUT3"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE0/ACMP0_IN0,PTA0,FTM2_CH1,LPI2C0_SCLS,FXIO_D2,FTM2_QD_PHA,LPUART0_CTS,TRGMUX_OUT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTA_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE1/ACMP0_IN1/TSI0_CH18,PTA1,FTM1_CH1,LPI2C0_SDAS,FXIO_D3,FTM1_QD_PHA,LPUART0_RTS,TRGMUX_OUT0"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE1/ACMP0_IN1,PTA1,FTM1_CH1,LPI2C0_SDAS,FXIO_D3,FTM1_QD_PHA,LPUART0_RTS,TRGMUX_OUT0"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTA_PCR2,Pin Control Register 2"
|
|
bitfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE0,PTA2,,LPI2C0_SDA,EWM_OUT_b,,LPUART0_RX,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE0,PTA2,FTM3_CH0,LPI2C0_SDA,EWM_OUT_b,,LPUART0_RX,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTA_PCR3,Pin Control Register 3"
|
|
bitfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC1_SE1,PTA3,,LPI2C0_SCL,EWM_IN,,LPUART0_TX,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC1_SE1,PTA3,FTM3_CH1,LPI2C0_SCL,EWM_IN,,LPUART0_TX,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTA_PCR4,Pin Control Register 4"
|
|
bitfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA4,,,ACMP0_OUT,EWM_OUT_b,,SWD_DIO"
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA4,,,ACMP0_OUT,EWM_OUT_b,,JTAG_TMS/SWD_DIO"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x14 "PORTA_PCR5,Pin Control Register 5"
|
|
bitfld.long 0x14 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x14 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA5,,TCLK1,,,,RESET_b"
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA5,,TCLK1,,,JTAG_TRST_b,RESET_b"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x18 "PORTA_PCR6,Pin Control Register 6"
|
|
bitfld.long 0x18 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "ADC0_SE2/ACMP1_IN0,PTA6,FTM0_FLT1,LPSPI1_PCS1,,,LPUART1_CTS,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x1C "PORTA_PCR7,Pin Control Register 7"
|
|
bitfld.long 0x1C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x1C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "ADC0_SE3/ACMP1_IN1,PTA7,FTM0_FLT2,,RTC_CLKIN,,LPUART1_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "PORTA_PCR8,Pin Control Register 8"
|
|
bitfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA8,,,FXIO_D6,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA8,,,FXIO_D6,FTM3_FLT3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTA_PCR9,Pin Control Register 9"
|
|
bitfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA9,,,FXIO_D7,,FTM1_FLT3,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA9,,,FXIO_D7,FTM3_FLT2,FTM1_FLT3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "PORTA_PCR10,Pin Control Register 10"
|
|
bitfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA10,,LPUART0_TX,FXIO_D0,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA10,FTM1_CH4,LPUART0_TX,FXIO_D0,,,JTAG_TDO/noetm_Trace_SWO"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTA_PCR11,Pin Control Register 11"
|
|
bitfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA11,,LPUART0_RX,FXIO_D1,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA11,FTM1_CH5,LPUART0_RX,FXIO_D1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTA_PCR12,Pin Control Register 12"
|
|
bitfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA12,,,LPI2C1_SDAS,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC2_SE5,PTA12,FTM1_CH6,CAN1_RX,LPI2C1_SDAS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTA_PCR13,Pin Control Register 13"
|
|
bitfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA13,,,LPI2C1_SCLS,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC2_SE4,PTA13,FTM1_CH7,CAN1_TX,LPI2C1_SCLS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "PORTA_PCR14,Pin Control Register 14"
|
|
bitfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA14,FTM0_FLT0,,EWM_IN,,,BUSOUT"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA14,FTM0_FLT0,FTM3_FLT1,EWM_IN,,FTM1_FLT0,BUSOUT"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTA_PCR15,Pin Control Register 15"
|
|
bitfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA15,FTM1_CH2,LPSPI0_PCS3,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC1_SE12,PTA15,FTM1_CH2,LPSPI0_PCS3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTA_PCR16,Pin Control Register 16"
|
|
bitfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA16,FTM1_CH3,LPSPI1_PCS2,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE13,PTA16,FTM1_CH3,LPSPI1_PCS2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTA_PCR17,Pin Control Register 17"
|
|
bitfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA17,FTM0_CH6,,EWM_OUT_b,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTA17,FTM0_CH6,FTM3_FLT0,EWM_OUT_b,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 31. " GPWE_[15] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " [14] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " [13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " [9] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " [8] ,Global Pin Write Enable" "Disable,Enable"
|
|
else
|
|
bitfld.long 0x00 29. " GPWE_[13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " [11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " [7] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " [6] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " [5] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " [4] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " [2] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " [1] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [0] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "PORTA_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 17. " GPWE_[17] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [16] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
endif
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
eventfld.long 0x00 17. " ISF_[17] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 13. " ISF_[13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.long 0xC0++0xB
|
|
line.long 0x00 "PORTA_DFER,Digital Filter Enable Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " DFE_[17] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Digital Filter Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 13. " DFE_[13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Digital Filter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTA_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock Source" "Bus clock,LPO clock"
|
|
line.long 0x08 "PORTA_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x4004A000
|
|
width 13.
|
|
group.long 0x0++0x1F
|
|
line.long 0x00 "PORTB_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE4,PTB0,LPUART0_RX,LPSPI0_PCS0,LPTMR0_ALT3,PWT_IN3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTB_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE5,PTB1,LPUART0_TX,LPSPI0_SOUT,TCLK0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTB_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC0_SE6/TSI0_CH20,PTB2,FTM1_CH0,LPSPI0_SCK,FTM1_QD_PHB,,TRGMUX_IN3,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC0_SE6,PTB2,FTM1_CH0,LPSPI0_SCK,FTM1_QD_PHB,,TRGMUX_IN3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTB_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC0_SE7/TSI0_CH21,PTB3,FTM1_CH1,LPSPI0_SIN,FTM1_QD_PHA,,TRGMUX_IN2,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC0_SE7,PTB3,FTM1_CH1,LPSPI0_SIN,FTM1_QD_PHA,,TRGMUX_IN2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTB_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "ACMP1_IN2/TSI0_CH8,PTB4,FTM0_CH4,LPSPI0_SOUT,,,TRGMUX_IN1,?..."
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "ACMP1_IN2,PTB4,FTM0_CH4,LPSPI0_SOUT,,,TRGMUX_IN1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x14 "PORTB_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x14 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "TSI0_CH9,PTB5,FTM0_CH5,LPSPI0_PCS1,,,TRGMUX_IN0,ACMP1_OUT"
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTB5,FTM0_CH5,LPSPI0_PCS1,,,TRGMUX_IN0,ACMP1_OUT"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x18 "PORTB_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "XTAL,PTB6,LPI2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x1C "PORTB_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x1C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "EXTAL,PTB7,LPI2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PORTB_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB8,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC2_SE11,PTB8,FTM3_CH0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTB_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB9,,LPI2C0_SCLS,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC2_SE10,PTB9,FTM3_CH1,LPI2C0_SCLS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTB_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB10,,LPI2C0_SDAS,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC2_SE9,PTB10,FTM3_CH2,LPI2C0_SDAS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTB_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB11,,LPI2C0_HREQ,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC2_SE8,PTB11,FTM3_CH3,LPI2C0_HREQ,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PORTB_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC1_SE7,PTB12,FTM0_CH0,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC1_SE7,PTB12,FTM0_CH0,FTM3_FLT2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTB_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC1_SE8,PTB13,FTM0_CH1,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC1_SE8,PTB13,FTM0_CH1,FTM3_FLT1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "PORTB_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC1_SE9,PTB14,FTM0_CH2,LPSPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTB_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB15,FTM0_CH3,LPSPI1_SIN,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC1_SE14,PTB15,FTM0_CH3,LPSPI1_SIN,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTB_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB16,FTM0_CH4,LPSPI1_SOUT,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE15,PTB16,FTM0_CH4,LPSPI1_SOUT,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTB_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTB17,FTM0_CH5,LPSPI1_PCS3,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC2_SE3,PTB17,FTM0_CH5,LPSPI1_PCS3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 31. " GPWE_[15] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " [14] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " [13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " [9] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " [8] ,Global Pin Write Enable" "Disable,Enable"
|
|
else
|
|
bitfld.long 0x00 29. " GPWE_[13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " [7] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " [6] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " [5] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " [4] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " [2] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " [1] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [0] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "PORTB_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 17. " GPWE_[17] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [16] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
endif
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
eventfld.long 0x00 17. " ISF_[17] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 13. " ISF_[13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.long 0xC0++0xB
|
|
line.long 0x00 "PORTB_DFER,Digital Filter Enable Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " DFE_[17] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Digital Filter Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 13. " DFE_[13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Digital Filter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTB_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock Source" "Bus clock,LPO clock"
|
|
line.long 0x08 "PORTB_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port C"
|
|
base ad:0x4004B000
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "PORTC_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE8/ACMP1_IN4/TSI0_CH22,PTC0,FTM0_CH0,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE8/ACMP1_IN4,PTC0,FTM0_CH0,,,,FTM1_CH6,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTC_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE9/ACMP1_IN3/TSI0_CH23,PTC1,FTM0_CH1,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE9/ACMP1_IN3,PTC1,FTM0_CH1,,,,FTM1_CH7,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTC_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC0_SE10/ACMP0_IN5/XTAL32,PTC2,FTM0_CH2,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC0_SE10/ACMP0_IN5/XTAL32,PTC2,FTM0_CH2,CAN0_RX,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTC_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC0_SE11/ACMP0_IN4/EXTAL32,PTC3,FTM0_CH3,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC0_SE11/ACMP0_IN4/EXTAL32,PTC3,FTM0_CH3,CAN0_TX,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTC_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "ACMP0_IN2,PTC4,FTM1_CH0,RTC_CLKOUT,,EWM_IN,FTM1_QD_PHB,SWD_CLK"
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "ACMP0_IN2,PTC4,FTM1_CH0,RTC_CLKOUT,,EWM_IN,FTM1_QD_PHB,JTAG_TCLK/SWD_CLK"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x14 "PORTC_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x14 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "TSI0_CH12,PTC5,FTM2_CH0,RTC_CLKOUT,LPI2C1_HREQ,,FTM2_QD_PHB,?..."
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTC5,FTM2_CH0,RTC_CLKOUT,LPI2C1_HREQ,,FTM2_QD_PHB,JTAG_TDI"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x18 "PORTC_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "ADC1_SE4/TSI0_CH15,PTC6,LPUART1_RX,?..."
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "ADC1_SE4,PTC6,LPUART1_RX,CAN1_RX,FTM3_CH2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x1C "PORTC_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x1C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "ADC1_SE5/TSI0_CH16,PTC7,LPUART1_TX,?..."
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "ADC1_SE5,PTC7,LPUART1_TX,CAN1_TX,FTM3_CH3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x20 "PORTC_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x20 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC8,LPUART1_RX,,,,LPUART0_CTS,?..."
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin Mux Control" "ADC2_SE14,PTC8,LPUART1_RX,FTM1_FLT0,,,LPUART0_CTS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x24 "PORTC_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x24 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC9,LPUART1_TX,,,,LPUART0_RTS,?..."
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin Mux Control" "ADC2_SE15,PTC9,LPUART1_TX,FTM1_FLT1,,,LPUART0_RTS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "PORTC_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC10,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC10,FTM3_CH4,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTC_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC11,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC11,FTM3_CH5,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTC_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC12,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC12,FTM3_CH6,FTM2_CH6,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTC_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC13,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTC13,FTM3_CH7,FTM2_CH7,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "PORTC_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE12,PTC14,FTM1_CH2,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC0_SE12/ACMP2_IN5,PTC14,FTM1_CH2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTC_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE13,PTC15,FTM1_CH3,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC0_SE13/ACMP2_IN4,PTC15,FTM1_CH3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTC_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC0_SE14,PTC16,FTM1_FLT2,,LPI2C1_SDAS,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTC_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC0_SE15,PTC17,FTM1_FLT3,,LPI2C1_SCLS,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
wgroup.long 0x80++0x7
|
|
line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE_[15] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " [14] ,Global Pin Write Enable" "Disable,Enable"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x00 29. " [13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " [11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 25. " [9] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " [8] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " [7] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " [6] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [5] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " [4] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " [3] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " [2] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [1] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [0] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE_[17] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " [16] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 17. " ISF_[17] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
eventfld.long 0x00 13. " [13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 9. " [9] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " [5] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.long 0xC0++0xB
|
|
line.long 0x00 "PORTC_DFER,Digital Filter Enable Register"
|
|
bitfld.long 0x00 17. " DFE_[17] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Digital Filter Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Digital Filter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock Source" "Bus clock,LPO clock"
|
|
line.long 0x08 "PORTC_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port D"
|
|
base ad:0x4004C000
|
|
width 13.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "PORTD_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "TSI0_CH4,PTD0,FTM0_CH2,LPSPI1_SCK,FTM2_CH0,,FXIO_D0,TRGMUX_OUT1"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC2_SE0,PTD0,FTM0_CH2,LPSPI1_SCK,FTM2_CH0,,FXIO_D0,TRGMUX_OUT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTD_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "TSI0_CH5,PTD1,FTM0_CH3,LPSPI1_SIN,FTM2_CH1,,FXIO_D1,TRGMUX_OUT2"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC2_SE1,PTD1,FTM0_CH3,LPSPI1_SIN,FTM2_CH1,,FXIO_D1,TRGMUX_OUT2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTD_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE2,PTD2,,LPSPI1_SOUT,FXIO_D4,,TRGMUX_IN5,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE2,PTD2,FTM3_CH4,LPSPI1_SOUT,FXIO_D4,,TRGMUX_IN5,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTD_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC1_SE3,PTD3,,LPSPI1_PCS0,FXIO_D5,,TRGMUX_IN4,NMI_b"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "ADC1_SE3,PTD3,FTM3_CH5,LPSPI1_PCS0,FXIO_D5,,TRGMUX_IN4,NMI_b"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTD_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "ADC1_SE6,PTD4,FTM0_FLT3,?..."
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "ADC1_SE6/ACMP1_IN6,PTD4,FTM0_FLT3,FTM3_FLT3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x14 "PORTD_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x14 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "TSI0_CH6,PTD5,FTM2_CH3,LPTMR0_ALT2,,PWT_IN2,TRGMUX_IN7,?..."
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTD5,FTM2_CH3,LPTMR0_ALT2,FTM2_FLT1,PWT_IN2,TRGMUX_IN7,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x18 "PORTD_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "TSI0_CH7,PTD6,LPUART2_RX,,FTM2_FLT2,?..."
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTD6,LPUART2_RX,,FTM2_FLT2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x1C "PORTD_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x1C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "TSI0_CH10,PTD7,LPUART2_TX,,FTM2_FLT3,?..."
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTD7,LPUART2_TX,,FTM2_FLT3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x20++0x1B
|
|
line.long 0x00 "PORTD_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD8,LPI2C1_SDA,,FTM2_FLT2,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD8,LPI2C1_SDA,,FTM2_FLT2,,FTM1_CH4,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTD_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ACMP1_IN5,PTD9,LPI2C1_SCL,,FTM2_FLT3,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ACMP1_IN5,PTD9,LPI2C1_SCL,,FTM2_FLT3,,FTM1_CH5,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTD_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD10,FTM2_CH0,FTM2_QD_PHB,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTD_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD11,FTM2_CH1,FTM2_QD_PHA,,,LPUART2_CTS,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTD_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD12,FTM2_CH2,LPI2C1_HREQ,,,LPUART2_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x14 "PORTD_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x14 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD13,,,,,,RTC_CLKOUT"
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD13,FTM2_CH4,,,,,RTC_CLKOUT"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x18 "PORTD_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD14,,,,,,CLKOUT"
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD14,FTM2_CH5,,,,,CLKOUT"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "PORTD_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD15,FTM0_CH0,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ACMP2_IN1,PTD15,FTM0_CH0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTD_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD16,FTM0_CH1,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ACMP2_IN0,PTD16,FTM0_CH1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTD_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTD17,FTM0_FLT2,LPUART2_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
wgroup.long 0x80++0x7
|
|
line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE_[15] ,Global Pin Write Enable" "Disable,Enable"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 30. " [14] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " [13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " [9] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " [8] ,Global Pin Write Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " [7] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " [6] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " [5] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " [4] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " [2] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " [1] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [0] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
line.long 0x04 "PORTD_GPCHR,Global Pin Control High Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x04 17. " GPWE_[17] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " [16] ,Global Pin Write Enable" "Disable,Enable"
|
|
else
|
|
bitfld.long 0x04 16. " GPWE_[16] ,Global Pin Write Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
eventfld.long 0x00 17. " ISF_[17] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 16. " ISF_[16] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.long 0xC0++0xB
|
|
line.long 0x00 "PORTD_DFER,Digital Filter Enable Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " DFE_[17] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Digital Filter Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 16. " DFE_[16] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Digital Filter Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Digital Filter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock Source" "Bus clock,LPO clock"
|
|
line.long 0x08 "PORTD_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port E"
|
|
base ad:0x4004D000
|
|
width 13.
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "PORTE_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "TSI0_CH13,PTE0,LPSPI0_SCK,TCLK1,LPI2C1_SDA,,FTM1_FLT2,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "ADC2_SE7,PTE0,LPSPI0_SCK,TCLK1,LPI2C1_SDA,,FTM1_FLT2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTE_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "TSI0_CH14,PTE1,LPSPI0_SIN,LPI2C0_HREQ,LPI2C1_SCL,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "ADC2_SE6,PTE1,LPSPI0_SIN,LPI2C0_HREQ,LPI2C1_SCL,,FTM1_FLT1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTE_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE10/TSI0_CH19,PTE2,LPSPI0_SOUT,LPTMR0_ALT3,,PWT_IN3,LPUART1_CTS,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ADC1_SE10,PTE2,LPSPI0_SOUT,LPTMR0_ALT3,FTM3_CH6,PWT_IN3,LPUART1_CTS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTE_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "TSI0_CH24,PTE3,FTM0_FLT0,LPUART2_RTS,,,TRGMUX_IN6,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTE3,FTM0_FLT0,LPUART2_RTS,FTM2_FLT0,,TRGMUX_IN6,ACMP2_OUT"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTE_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "TSI0_CH1,PTE4,BUSOUT,FTM2_QD_PHB,FTM2_CH2,,FXIO_D6,EWM_OUT_b"
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTE4,BUSOUT,FTM2_QD_PHB,FTM2_CH2,CAN0_RX,FXIO_D6,EWM_OUT_b"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x14 "PORTE_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x14 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "TSI0_CH0,PTE5,TCLK2,FTM2_QD_PHA,FTM2_CH3,,FXIO_D7,EWM_IN"
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin Mux Control" "DISABLED,PTE5,TCLK2,FTM2_QD_PHA,FTM2_CH3,CAN0_TX,FXIO_D7,EWM_IN"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x18 "PORTE_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "ADC1_SE11,PTE6,LPSPI0_PCS2,,,,LPUART1_RTS,?..."
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin Mux Control" "ADC1_SE11/ACMP0_IN6,PTE6,LPSPI0_PCS2,,FTM3_CH7,,LPUART1_RTS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x1C "PORTD_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x1C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE7,FTM0_CH7,?..."
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin Mux Control" "ADC2_SE2/ACMP2_IN6,PTE7,FTM0_CH7,FTM3_FLT0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x20 "PORTE_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x20 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin Mux Control" "ACMP0_IN3/TSI0_CH11,PTE8,FTM0_CH6,?..."
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin Mux Control" "ACMP0_IN3,PTE8,FTM0_CH6,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x24 "PORTE_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x24 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin Mux Control" "DAC0_OUT,PTE9,FTM0_CH7,LPUART2_CTS,?..."
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin Mux Control" "ACMP2_IN2/DAC0_OUT,PTE9,FTM0_CH7,LPUART2_CTS,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x28 "PORTE_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x28 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin Mux Control" "TSI0_CH2,PTE10,CLKOUT,,,,FXIO_D4,TRGMUX_OUT4"
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin Mux Control" "ADC2_SE12,PTE10,CLKOUT,,FTM2_CH4,,FXIO_D4,TRGMUX_OUT4"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x2C "PORTE_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x2C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin Mux Control" "TSI0_CH3,PTE11,PWT_IN1,LPTMR0_ALT1,,,FXIO_D5,TRGMUX_OUT5"
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin Mux Control" "ADC2_SE13,PTE11,PWT_IN1,LPTMR0_ALT1,FTM2_CH5,,FXIO_D5,TRGMUX_OUT5"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "PORTE_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE12,FTM0_FLT3,LPUART2_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x04 "PORTE_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE13,?..."
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE13,,,FTM2_FLT0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x08 "PORTE_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE14,FTM0_FLT1,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin Mux Control" "ACMP2_IN3,PTE14,FTM0_FLT1,,FTM2_FLT1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x0C "PORTE_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE15,,,,,FXIO_D2,TRGMUX_OUT6"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE15,,,FTM2_CH6,,FXIO_D2,TRGMUX_OUT6"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
line.long 0x10 "PORTE_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt Status Flag" "Not detected,Detected"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt Configuration" "ISF is disabled,ISF flag and DMA request on rising edge,ISF flag and DMA request on falling edge,ISF flag and DMA request on either edge,,,,,ISF flag and Interrupt when logic 0,ISF flag and Interrupt on rising-edge,ISF flag and Interrupt on falling-edge,ISF flag and Interrupt on either edge,ISF flag and Interrupt when logic 1,,,"
|
|
bitfld.long 0x10 15. " LK ,Lock Register" "Not locked,Locked"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE16,,,,,FXIO_D3,TRGMUX_OUT7"
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin Mux Control" "Disabled,PTE16,,,FTM2_CH7,,FXIO_D3,TRGMUX_OUT7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive Strength Enable" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PE ,Pull Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull Select" "Pulldown,Pullup"
|
|
endif
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 31. " GPWE_[15] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " [14] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " [13] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " [12] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " [9] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " [8] ,Global Pin Write Enable" "Disable,Enable"
|
|
else
|
|
bitfld.long 0x00 27. " GPWE_[11] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " [10] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " [9] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " [8] ,Global Pin Write Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " [7] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " [6] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " [5] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " [4] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " [2] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " [1] ,Global Pin Write Enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " [0] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "PORTE_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 16. " GPWE_[16] ,Global Pin Write Enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
endif
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
eventfld.long 0x00 16. " ISF_[16] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 11. " ISF_[11] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.long 0xC0++0xB
|
|
line.long 0x00 "PORTE_DFER,Digital Filter Enable Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 16. " DFE_[16] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Digital Filter Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 11. " DFE_[11] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Digital Filter Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Digital Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Digital Filter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTE_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock Source" "Bus clock,LPO clock"
|
|
line.long 0x08 "PORTE_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
base ad:0x40049000
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VFM4R"))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VFM4R"))
|
|
line.long 0x00 "PORT_IOFLT,Port Filter Register"
|
|
else
|
|
line.long 0x00 "PORT_IOFLT0,Port Filter Register 0"
|
|
endif
|
|
bitfld.long 0x00 29.--31. " FLTDIV3 ,Port Filter Division Set 3" "LPOCLK,LPOCLK/2,LPOCLK/4,LPOCLK/8,LPOCLK/16,LPOCLK/32,LPOCLK/64,LPOCLK/128"
|
|
bitfld.long 0x00 26.--28. " FLTDIV2 ,Port Filter Division Set 2" "BUSCLK/32,BUSCLK/64,BUSCLK/128,BUSCLK/256,BUSCLK/512,BUSCLK/1024,BUSCLK/2048,BUSCLK/4096"
|
|
bitfld.long 0x00 24.--25. " FLTDIV1 ,Port Filter Division Set 1" "BUSCLK/2,BUSCLK/4,BUSCLK/8,BUSCLK/16"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " FLTNMI ,Filter Selection for Input from NMI" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 20.--21. " FLTKBI1 ,Filter Selection for Input from KBI1" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 18.--19. " FLTKBI0 ,Filter selection for Input from KBI0" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
sif (!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 14.--15. " FLTH ,Filter Selection for Input from PTH" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
sif (!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R"))
|
|
bitfld.long 0x00 12.--13. " FLTG ,Filter Selection for Input from PTG" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 10.--11. " FLTF ,Filter Selection for Input from PTF" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FLTE ,Filter Selection for Input from PTE" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 4.--5. " FLTC ,Filter Selection for Input from PTC" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 2.--3. " FLTB ,Filter Selection for Input from PTB" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " FLTA ,Filter Selection for Input from PTA" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R"))&&!cpuis("MKE02Z32VFM4R"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORT_IOFLT1,Port Filter Register 1"
|
|
bitfld.long 0x00 14.--15. " FLTI2C1 ,Filter Selection For Input from SCL1/SDA1" "No filter,FLTDIV1,FLTDIV2,BUSCLK"
|
|
bitfld.long 0x00 12.--13. " FLTI2C0 ,Filter Selection For Input from SCL0/SDA0" "No filter,FLTDIV1,FLTDIV2,BUSCLK"
|
|
bitfld.long 0x00 10.--11. " FLTPWT ,Filter Selection For Input from PWT_IN1/PWT_IN0" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FLTFTM1 ,Filter Selection For Input from FTM1CH0/FTM1CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTFTM0 ,Filter Selection For Input from FTM0CH0/FTM0CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 4.--5. " FLTIRQ ,Filter Selection for Input from IRQ" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " FLTI ,Filter Selection for Input from PTI" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
endif
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VFM4R"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORT_PUEL,Port Pullup Enable Low Register"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PORT_PUE0,Port Pullup Enable Register 0"
|
|
endif
|
|
sif (!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTDPE7 ,Pull Enable for Port D Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PTDPE6 ,Pull Enable for Port D Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PTDPE5 ,Pull Enable for Port D Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PTDPE4 ,Pull Enable for Port D Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " PTDPE3 ,Pull Enable for Port D Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " PTDPE2 ,Pull Enable for Port D Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PTDPE1 ,Pull Enable for Port D Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PTDPE0 ,Pull Enable for Port D Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PTCPE7 ,Pull Enable for Port C Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PTCPE6 ,Pull Enable for Port C Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PTCPE5 ,Pull Enable for Port C Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PTCPE4 ,Pull Enable for Port C Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTCPE3 ,Pull Enable for Port C Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PTCPE2 ,Pull Enable for Port C Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PTCPE1 ,Pull Enable for Port C Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PTCPE0 ,Pull Enable for Port C Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PTBPE7 ,Pull Enable for Port B Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PTBPE6 ,Pull Enable for Port B Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PTBPE5 ,Pull Enable for Port B Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PTBPE4 ,Pull Enable for Port B Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PTBPE3 ,Pull Enable for Port B Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PTBPE2 ,Pull Enable for Port B Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTBPE1 ,Pull Enable for Port B Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PTBPE0 ,Pull Enable for Port B Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PTAPE7 ,Pull Enable for Port A Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTAPE6 ,Pull Enable for Port A Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTAPE5 ,Pull Enable for Port A Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PTAPE4 ,Pull Enable for Port A Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PTAPE3 ,Pull Enable for Port A Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTAPE2 ,Pull Enable for Port A Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTAPE1 ,Pull Enable for Port A Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTAPE0 ,Pull Enable for Port A Bit 0" "Disabled,Enabled"
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_PUE1,Port Pullup Enable Register 1"
|
|
elif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PORT_PUEH,Port Pullup Enable High Register"
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE06Z64VLD4")&&!cpuis("MKE06Z128VLD4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 31. " PTHPE7 ,Pull Enable for Port H Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PTHPE6 ,Pull Enable for Port H Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE06Z64VLD4")&&!cpuis("MKE06Z128VLD4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 29. " PTHPE5 ,Pull Enable for Port H Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PTHPE4 ,Pull Enable for Port H Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PTHPE3 ,Pull Enable for Port H Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4"))&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 26. " PTHPE2 ,Pull Enable for Port H Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE06Z64VLD4")&&!cpuis("MKE06Z128VLD4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 25. " PTHPE1 ,Pull Enable for Port H Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PTHPE0 ,Pull Enable for Port H Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 23. " PTGPE7 ,Pull Enable for Port G Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PTGPE6 ,Pull Enable for Port G Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PTGPE5 ,Pull Enable for Port G Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PTGPE4 ,Pull Enable for Port G Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE06Z64VLD4")&&!cpuis("MKE06Z128VLD4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 19. " PTGPE3 ,Pull Enable for Port G Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PTGPE2 ,Pull Enable for Port G Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PTGPE1 ,Pull Enable for Port G Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PTGPE0 ,Pull Enable for Port G Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PTFPE7 ,Pull Enable for Port F Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PTFPE6 ,Pull Enable for Port F Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PTFPE5 ,Pull Enable for Port F Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PTFPE4 ,Pull Enable for Port F Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PTFPE3 ,Pull Enable for Port F Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PTFPE2 ,Pull Enable for Port F Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTFPE1 ,Pull Enable for Port F Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PTFPE0 ,Pull Enable for Port F Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4"))&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE06Z64VLD4")&&!cpuis("MKE06Z128VLD4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 6. " PTEPE6 ,Pull Enable for Port E Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTEPE5 ,Pull Enable for Port E Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTEPE4 ,Pull Enable for Port E Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTEPE3 ,Pull Enable for Port E Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PORT_PUE2,Port Pullup Enable Register 2"
|
|
sif (cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTIPE6 ,Pull Enable for Port I Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTIPE5 ,Pull Enable for Port I Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " PTIPE4 ,Pull Enable for Port I Bit 4" "Disabled,Enabled"
|
|
sif (cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTIPE3 ,Pull Enable for Port I Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTIPE2 ,Pull Enable for Port I Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTIPE1 ,Pull Enable for Port I Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
group.long 0x14++0x03
|
|
else
|
|
group.long 0x0C++0x03
|
|
endif
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE06Z64VLD4")&&!cpuis("MKE06Z128VLD4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z32VFM4R")))
|
|
bitfld.long 0x00 7. " PTH1 ,High Current Drive Capability of PTH1" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTH0 ,High Current Drive Capability of PTH0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4"))&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 5. " PTE1 ,High Current Drive Capability of PTE1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTE0 ,High Current Drive Capability of PTE0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PTD1 ,High Current Drive Capability of PTD1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTD0 ,High Current Drive Capability of PTD0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTB4 ,High Current Drive Capability of PTB4" "Disabled,Enabled"
|
|
width 0x0B
|
|
elif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R"))
|
|
width 12.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_IOFLT0,Port Filter Register 0"
|
|
bitfld.long 0x00 29.--31. " FLTDIV3 ,Port Filter Division Set 3" "LPOCLK,LPOCLK/2,LPOCLK/4,LPOCLK/8,LPOCLK/16,LPOCLK/32,LPOCLK/64,LPOCLK/128"
|
|
bitfld.long 0x00 26.--28. " FLTDIV2 ,Port Filter Division Set 2" "BUSCLK/32,BUSCLK/64,BUSCLK/128,BUSCLK/256,BUSCLK/512,BUSCLK/1024,BUSCLK/2048,BUSCLK/4096"
|
|
bitfld.long 0x00 24.--25. " FLTDIV1 ,Port Filter Division Set 1" "BUSCLK/2,BUSCLK/4,BUSCLK/8,BUSCLK/16"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " FLTNMI ,Filter Selection for Input from NMI" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 20.--21. " FLTKBI1 ,Filter Selection for Input from KBI1" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 18.--19. " FLTKBI0 ,Filter selection for Input from KBI0" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 14.--15. " FLTH ,Filter Selection for Input from PTH" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 12.--13. " FLTG ,Filter Selection for Input from PTG" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " FLTF ,Filter Selection for Input from PTF" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 8.--9. " FLTE ,Filter Selection for Input from PTE" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FLTC ,Filter Selection for Input from PTC" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 2.--3. " FLTB ,Filter Selection for Input from PTB" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 0.--1. " FLTA ,Filter Selection for Input from PTA" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
line.long 0x04 "PORT_IOFLT1,Port Filter Register 1"
|
|
bitfld.long 0x04 14.--15. " FLTI2C1 ,Filter Selection For Input from SCL1/SDA1" "No filter,FLTDIV1,FLTDIV2,BUSCLK"
|
|
bitfld.long 0x04 12.--13. " FLTI2C0 ,Filter Selection For Input from SCL0/SDA0" "No filter,FLTDIV1,FLTDIV2,BUSCLK"
|
|
bitfld.long 0x04 10.--11. " FLTPWT ,Filter Selection For Input from PWT_IN1/PWT_IN0" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " FLTFTM1 ,Filter Selection For Input from FTM1CH0/FTM1CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x04 6.--7. " FLTFTM0 ,Filter Selection For Input from FTM0CH0/FTM0CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x04 4.--5. " FLTIRQ ,Filter Selection for Input from IRQ" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " FLTI ,Filter Selection for Input from PTI" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
line.long 0x08 "PORT_PUE0,Port Pullup Enable Register 0"
|
|
bitfld.long 0x08 31. " PTDPE7 ,Pull Enable for Port D Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " PTDPE6 ,Pull Enable for Port D Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " PTDPE5 ,Pull Enable for Port D Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " PTDPE4 ,Pull Enable for Port D Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " PTDPE3 ,Pull Enable for Port D Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " PTDPE2 ,Pull Enable for Port D Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PTDPE1 ,Pull Enable for Port D Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " PTDPE0 ,Pull Enable for Port D Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " PTCPE7 ,Pull Enable for Port C Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " PTCPE6 ,Pull Enable for Port C Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " PTCPE5 ,Pull Enable for Port C Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " PTCPE4 ,Pull Enable for Port C Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTCPE3 ,Pull Enable for Port C Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " PTCPE2 ,Pull Enable for Port C Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " PTCPE1 ,Pull Enable for Port C Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " PTCPE0 ,Pull Enable for Port C Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " PTBPE7 ,Pull Enable for Port B Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " PTBPE6 ,Pull Enable for Port B Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PTBPE5 ,Pull Enable for Port B Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " PTBPE4 ,Pull Enable for Port B Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " PTBPE3 ,Pull Enable for Port B Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " PTBPE2 ,Pull Enable for Port B Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " PTBPE1 ,Pull Enable for Port B Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " PTBPE0 ,Pull Enable for Port B Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PTAPE7 ,Pull Enable for Port A Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PTAPE6 ,Pull Enable for Port A Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " PTAPE5 ,Pull Enable for Port A Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PTAPE4 ,Pull Enable for Port A Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " PTAPE3 ,Pull Enable for Port A Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PTAPE2 ,Pull Enable for Port A Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PTAPE1 ,Pull Enable for Port A Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PTAPE0 ,Pull Enable for Port A Bit 0" "Disabled,Enabled"
|
|
line.long 0x0C "PORT_PUE1,Port Pullup Enable Register 1"
|
|
sif (!cpuis("MKE04Z64VLD4")&&!cpuis("MKE04Z128VLD4"))
|
|
bitfld.long 0x0C 31. " PTHPE7 ,Pull Enable for Port H Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PTHPE6 ,Pull Enable for Port H Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKE04Z64VLD4")&&!cpuis("MKE04Z128VLD4")&&!cpuis("MKE04Z64VQH4")&&!cpuis("MKE04Z128VQH4")&&!cpuis("MKE04Z64VLH4")&&!cpuis("MKE04Z128VLH4")&&!cpuis("MKE04Z128VLH4R"))
|
|
bitfld.long 0x0C 29. " PTHPE5 ,Pull Enable for Port H Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " PTHPE4 ,Pull Enable for Port H Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " PTHPE3 ,Pull Enable for Port H Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 26. " PTHPE2 ,Pull Enable for Port H Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("MKE04Z64VLD4")&&!cpuis("MKE04Z128VLD4"))
|
|
bitfld.long 0x0C 25. " PTHPE1 ,Pull Enable for Port H Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " PTHPE0 ,Pull Enable for Port H Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R"))
|
|
bitfld.long 0x0C 23. " PTGPE7 ,Pull Enable for Port G Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " PTGPE6 ,Pull Enable for Port G Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " PTGPE5 ,Pull Enable for Port G Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PTGPE4 ,Pull Enable for Port G Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKE04Z64VLD4")&&!cpuis("MKE04Z128VLD4"))
|
|
bitfld.long 0x0C 19. " PTGPE3 ,Pull Enable for Port G Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " PTGPE2 ,Pull Enable for Port G Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " PTGPE1 ,Pull Enable for Port G Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " PTGPE0 ,Pull Enable for Port G Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " PTFPE7 ,Pull Enable for Port F Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PTFPE6 ,Pull Enable for Port F Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " PTFPE5 ,Pull Enable for Port F Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " PTFPE4 ,Pull Enable for Port F Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " PTFPE3 ,Pull Enable for Port F Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " PTFPE2 ,Pull Enable for Port F Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " PTFPE1 ,Pull Enable for Port F Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " PTFPE0 ,Pull Enable for Port F Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")))
|
|
bitfld.long 0x0C 6. " PTEPE6 ,Pull Enable for Port E Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " PTEPE5 ,Pull Enable for Port E Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " PTEPE4 ,Pull Enable for Port E Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PTEPE3 ,Pull Enable for Port E Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "PORT_PUE2,Port Pullup Enable Register 2"
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x10 6. " PTIPE6 ,Pull Enable for Port I Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " PTIPE5 ,Pull Enable for Port I Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 4. " PTIPE4 ,Pull Enable for Port I Bit 4" "Disabled,Enabled"
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
textline " "
|
|
bitfld.long 0x10 3. " PTIPE3 ,Pull Enable for Port I Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PTIPE2 ,Pull Enable for Port I Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PTIPE1 ,Pull Enable for Port I Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " PTIPE0 ,Pull Enable for Port I Bit 0" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x14 "PORT_HDRVE,Port High Drive Enable Register"
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")))
|
|
bitfld.long 0x14 7. " PTH1 ,High Current Drive Capability of PTH1" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " PTH0 ,High Current Drive Capability of PTH0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 5. " PTE1 ,High Current Drive Capability of PTE1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " PTE0 ,High Current Drive Capability of PTE0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PTD1 ,High Current Drive Capability of PTD1" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PTD0 ,High Current Drive Capability of PTD0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " PTB4 ,High Current Drive Capability of PTB4" "Disabled,Enabled"
|
|
width 0xB
|
|
else
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PORT_IOFLT,Port Filter Register"
|
|
bitfld.long 0x00 29.--31. " FLTDIV3 ,Port Filter Division Set 3" "LPOCLK,LPOCLK/2,LPOCLK/4,LPOCLK/8,LPOCLK/16,LPOCLK/32,LPOCLK/64,LPOCLK/128"
|
|
bitfld.long 0x00 26.--28. " FLTDIV2 ,Port Filter Division Set 2" "BUSCLK/32,BUSCLK/64,BUSCLK/128,BUSCLK/256,BUSCLK/512,BUSCLK/1024,BUSCLK/2048,BUSCLK/4096"
|
|
bitfld.long 0x00 24.--25. " FLTDIV1 ,Port Filter Division Set 1" "BUSCLK/2,BUSCLK/4,BUSCLK/8,BUSCLK/16"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " FLTNMI ,Filter Selection for Input from NMI" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 20.--21. " FLTKBI1 ,Filter Selection for Input from KBI1" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 18.--19. " FLTKBI0 ,Filter selection for Input from KBI0" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
sif (cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
elif (cpuis("MKE02Z32VLD2R"))
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 14.--15. " FLTH ,Filter Selection for Input from PTH" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 8.--9. " FLTE ,Filter Selection for Input from PTE" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
else
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 14.--15. " FLTH ,Filter Selection for Input from PTH" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 12.--13. " FLTG ,Filter Selection for Input from PTG" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " FLTF ,Filter Selection for Input from PTF" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 8.--9. " FLTE ,Filter Selection for Input from PTE" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FLTC ,Filter Selection for Input from PTC" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 2.--3. " FLTB ,Filter Selection for Input from PTB" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 0.--1. " FLTA ,Filter Selection for Input from PTA" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
line.long 0x04 "PORT_PUEL,Port Pullup Enable Low Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x04 31. " PTDPE7 ,Pull Enable for Port D Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " PTDPE6 ,Pull Enable for Port D Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PTDPE5 ,Pull Enable for Port D Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " PTDPE4 ,Pull Enable for Port D Bit 4" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 27. " PTDPE3 ,Pull Enable for Port D Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " PTDPE2 ,Pull Enable for Port D Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PTDPE1 ,Pull Enable for Port D Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " PTDPE0 ,Pull Enable for Port D Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PTCPE7 ,Pull Enable for Port C Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " PTCPE6 ,Pull Enable for Port C Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PTCPE5 ,Pull Enable for Port C Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " PTCPE4 ,Pull Enable for Port C Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PTCPE3 ,Pull Enable for Port C Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PTCPE2 ,Pull Enable for Port C Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PTCPE1 ,Pull Enable for Port C Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PTCPE0 ,Pull Enable for Port C Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PTBPE7 ,Pull Enable for Port B Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PTBPE6 ,Pull Enable for Port B Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PTBPE5 ,Pull Enable for Port B Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PTBPE4 ,Pull Enable for Port B Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PTBPE3 ,Pull Enable for Port B Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " PTBPE2 ,Pull Enable for Port B Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PTBPE1 ,Pull Enable for Port B Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " PTBPE0 ,Pull Enable for Port B Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PTAPE7 ,Pull Enable for Port A Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PTAPE6 ,Pull Enable for Port A Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PTAPE5 ,Pull Enable for Port A Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PTAPE4 ,Pull Enable for Port A Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PTAPE3 ,Pull Enable for Port A Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PTAPE2 ,Pull Enable for Port A Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PTAPE1 ,Pull Enable for Port A Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PTAPE0 ,Pull Enable for Port A Bit 0" "Disabled,Enabled"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VLC2R"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PORT_PUEH,Port Pullup Enable High Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")
|
|
bitfld.long 0x00 31. " PTHPE7 ,Pull Enable for Port H Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PTHPE6 ,Pull Enable for Port H Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " PTHPE2 ,Pull Enable for Port H Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PTHPE1 ,Pull Enable for Port H Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PTHPE0 ,Pull Enable for Port H Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PTGPE3 ,Pull Enable for Port G Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PTGPE2 ,Pull Enable for Port G Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PTGPE1 ,Pull Enable for Port G Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PTGPE0 ,Pull Enable for Port G Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PTFPE7 ,Pull Enable for Port F Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PTFPE6 ,Pull Enable for Port F Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PTFPE5 ,Pull Enable for Port F Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PTFPE4 ,Pull Enable for Port F Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PTFPE3 ,Pull Enable for Port F Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PTFPE2 ,Pull Enable for Port F Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PTFPE1 ,Pull Enable for Port F Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PTFPE0 ,Pull Enable for Port F Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PTEPE6 ,Pull Enable for Port E Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTEPE5 ,Pull Enable for Port E Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTEPE4 ,Pull Enable for Port E Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTEPE3 ,Pull Enable for Port E Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
elif cpuis("MKE02Z16VLD2")||cpuis("MKE02Z32VLD2")||cpuis("MKE02Z64VLD2")||cpuis("MKE02Z32VLD2R")
|
|
bitfld.long 0x00 26. " PTHPE2 ,Pull Enable for Port H Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")
|
|
bitfld.long 0x00 7. " PTH1 ,High Current Drive Capability of PTH1" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTH0 ,High Current Drive Capability of PTH0" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif cpuis("MKE02Z16VLD2")||cpuis("MKE02Z32VLD2")||cpuis("MKE02Z64VLD2")||cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLD2R")
|
|
bitfld.long 0x00 5. " PTE1 ,High Current Drive Capability of PTE1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTE0 ,High Current Drive Capability of PTE0" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTD1 ,High Current Drive Capability of PTD1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTD0 ,High Current Drive Capability of PTD0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTB4 ,High Current Drive Capability of PTB4" "Disabled,Enabled"
|
|
width 0x0B
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.open "System Modules"
|
|
tree "SIM (System Integration Module)"
|
|
base ad:0x40048000
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R"))
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SRSID,System Reset Status and ID Register"
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "KE0x,?..."
|
|
sif cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,KEx2,?..."
|
|
elif cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,,,KEx4,,KEx6,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,KEx2,,KEx4,,KEx6,?..."
|
|
endif
|
|
bitfld.long 0x00 20.--23. " RevID ,Device Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PINID ,Device Pin ID" "8-pin,16-pin,20-pin,24-pin,32-pin,44-pin,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
bitfld.long 0x00 13. " SACKERR ,Stop Mode Acknowledge Error Reset" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " MDMAP ,MDM-AP System Reset Request" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SW ,Software" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " LOCKUP ,Core Lockup" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " POR ,Power-On Reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PIN ,External Reset Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " WDOG ,Watchdog" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " LOC ,Internal Clock Source Module Reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LVD ,Low Voltage Detect" "Not occurred,Occurred"
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT,System Options Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT0,System Options Register 0"
|
|
endif
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DELAY ,FTM2 Trigger Delay"
|
|
rbitfld.long 0x00 23. " DLYACT ,FTM2 Trigger Delay Active" "Inactive,Active"
|
|
sif (!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " ADHWT ,ADC Hardware Trigger Source" "RTC->ADC,FTM0->ADC,FTM2 init,FTM2 match,PIT ch0,PIT ch1,ACMP0->ADC,ACMP1->ADC"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLKOE ,Bus Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " BUSREF ,BUS Clock Output select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TXDME ,UART0_TX Modulation Select" "Not selected,FTM0 ch. 0"
|
|
bitfld.long 0x00 14. " FTMSYNC ,FTM2 Synchronization Select" "Not selected,PWM"
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z64VLH4R"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXDFE ,UART0_RX Filter Select" "Not selected,ACMP"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXDCE ,UART0_RX Capture Select" "Not selected,FTM0 ch. 1"
|
|
bitfld.long 0x00 11. " ACIC ,Analog Comparator to Input Capture Enable" "Not connected,FTM1 ch. 0"
|
|
bitfld.long 0x00 10. " RTCC ,Real-Time Counter Capture" "Not connected,FTM1 ch. 1"
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ADHWT ,ADC Hardware Trigger Source" "RTC overflow,PIT overflow,FTM2 init,FTM2 match"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RXDFE ,UART0 RxD Filter Select" "Disabled,ACMP0,ACMP1,"
|
|
bitfld.long 0x00 5. " ACTRG ,ACMP Trigger FTM2 selection" "ACMP0 out,ACMP1 out"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " SWDE ,Single Wire Debug Port Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RSTPE ,RESET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIE ,NMI Pin Enable" "Disabled,Enabled"
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R")))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SOPT1,System Options Register"
|
|
bitfld.long 0x00 4.--5. " UARTPWTS ,PWT UART RX select" "UART0,UART1,UART2,?..."
|
|
bitfld.long 0x00 3. " ACPWTS ,PWT ACMP_OUT select" "ACMP1_OUT,ACMP0_OUT"
|
|
bitfld.long 0x00 1. " I2C0OINV ,I2C0 Output Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " I2C04WEN ,I2C0 4-Wire Interface Enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINSEL0,Pin Selection Register 0"
|
|
bitfld.long 0x00 30.--31. " PWTCLKPS ,PWT TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
bitfld.long 0x00 28.--29. " FTM2CLKPS ,FTM2 TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
bitfld.long 0x00 26.--27. " FTM1CLKPS ,FTM1 TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " FTM0CLKPS ,FTM0 TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PINSEL,Pin Selection Register"
|
|
bitfld.long 0x00 15. " FTM2PS3 ,FTM2_CH3 Port Pin Select" "PTC3,PTD1"
|
|
bitfld.long 0x00 14. " FTM2PS2 ,FTM2_CH2 Port Pin Select" "PTC2,PTD0"
|
|
textline " "
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")))
|
|
bitfld.long 0x00 13. " FTM2PS1 ,FTM2_CH1 Port Pin Select" "PTC1,PTH1"
|
|
bitfld.long 0x00 12. " FTM2PS0 ,FTM2_CH0 Port Pin Select" "PTC0,PTH0"
|
|
else
|
|
bitfld.long 0x00 13. " FTM2PS1 ,FTM2_CH1 Port Pin Select" "PTC1,?..."
|
|
bitfld.long 0x00 12. " FTM2PS0 ,FTM2_CH0 Port Pin Select" "PTC0,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")))
|
|
bitfld.long 0x00 11. " FTM1PS1 ,FTM1_CH1 Port Pin Select" "PTC5,PTE7"
|
|
bitfld.long 0x00 10. " FTM1PS0 ,FTM1_CH0 Port Pin Select" "PTC4,PTH2"
|
|
else
|
|
bitfld.long 0x00 11. " FTM1PS1 ,FTM1_CH1 Port Pin Select" "PTC5,?..."
|
|
bitfld.long 0x00 10. " FTM1PS0 ,FTM1_CH0 Port Pin Select" "PTC4,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " FTM0PS1 ,FTM0_CH1 Port Pin Select" "PTA1,PTB3"
|
|
bitfld.long 0x00 8. " FTM0PS0 ,FTM0_CH0 Port Pin Select" "PTA0,PTB2"
|
|
bitfld.long 0x00 7. " UART0PS ,UART0 Pin Select" "PTB0 and PTB1,PTA2 and PTA3"
|
|
textline " "
|
|
sif (cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLC4R"))
|
|
bitfld.long 0x00 6. " SPI0PS ,SPI0 Pin Select" "PTB[2:5],PTE[0:2]"
|
|
elif (!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4"))
|
|
bitfld.long 0x00 6. " SPI0PS ,SPI0 Pin Select" "PTB[2:5],PTE[0:3]"
|
|
else
|
|
bitfld.long 0x00 6. " SPI0PS ,SPI0 Pin Select" "PTB[2:5],?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C0PS ,I2C0 Port Pin Select" "PTA[3:2],PTB[7:6]"
|
|
bitfld.long 0x00 4. " RTCPS ,RTCO Pin Select" "PTC4,PTC5"
|
|
sif (cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R"))
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " IRQPS ,IRQ Port Pin Select" "PTA5,,,,,PTI4,?..."
|
|
elif (!(cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z64VLH4R")))
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " IRQPS ,IRQ Port Pin Select" "PTA5,PTI0,PTI1,PTI2,PTI3,PTI4,PTI5,PTI6"
|
|
endif
|
|
sif ((!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z16VLD4")&&!cpuis("MKE02Z32VLD4")&&!cpuis("MKE02Z64VLD4")&&!cpuis("MKE02Z32VLH4")&&!cpuis("MKE02Z64VLH4")&&!cpuis("MKE02Z32VQH4")&&!cpuis("MKE02Z64VQH4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z64VLH4R")&&!cpuis("MKE02Z32VLD4R")))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PINSEL1,Pin Selection Register 1"
|
|
sif (cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 16. " MSCANPS ,MSCAN Pin Select (TX/RX)" "PTC7/PTC6,PTE7/PTH2"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")))
|
|
bitfld.long 0x00 15. " PWTIN1PS ,PWTIN1 Pin Select" "PTB0,PTH7"
|
|
else
|
|
bitfld.long 0x00 15. " PWTIN1PS ,PWTIN1 Pin Select" "PTB0,?..."
|
|
endif
|
|
textline " "
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")))
|
|
bitfld.long 0x00 14. " PWTIN0PS ,PWTIN0 Pin Select" "PTD5,PTE2"
|
|
else
|
|
bitfld.long 0x00 14. " PWTIN0PS ,PWTIN0 Pin Select" "PTD5,?..."
|
|
endif
|
|
textline " "
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 13. " UART2PS ,UART2 Pin Select (TX/RX)" "PTD7/PTD6,PTI1/PTI0"
|
|
bitfld.long 0x00 12. " UART1PS ,UART1 Pin Select (TX/RX)" "PTC7/PTC6,PTF3/PTF2"
|
|
elif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE02Z16VLC4")))
|
|
bitfld.long 0x00 13. " UART2PS ,UART2 Pin Select (TX/RX)" "PTD7/PTD6,?..."
|
|
bitfld.long 0x00 12. " UART1PS ,UART1 Pin Select (TX/RX)" "PTC7/PTC6,PTF3/PTF2"
|
|
else
|
|
bitfld.long 0x00 13. " UART2PS ,UART2 Pin Select (TX/RX)" "PTD7/PTD6,?..."
|
|
bitfld.long 0x00 12. " UART1PS ,UART1 Pin Select (TX/RX)" "PTC7/PTC6,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z64VLK4R"))
|
|
bitfld.long 0x00 11. " SPI1PS ,SPI1 Pin Select" "PTD[0:3],PTG[4:7]"
|
|
bitfld.long 0x00 10. " I2C1PS ,I2C1 Pin Select (SCL/SDA)" "PTE1/PTE0,PTH4/PTH3"
|
|
bitfld.long 0x00 9. " FTM2PS5 ,FTM2 Channel 5 Pin Select" "PTB5,PTG7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FTM2PS4 ,FTM2 Channel4 Pin Select" "PTB4,PTG6"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " FTM2PS3 ,FTM2 Channel 3 Pin Select" "PTC3,PTD1,PTG5,?..."
|
|
bitfld.long 0x00 4.--5. " FTM2PS2 ,FTM2 Channel 2 Pin Select" "PTC2,PTD0,PTG4,?..."
|
|
else
|
|
bitfld.long 0x00 11. " SPI1PS ,SPI1 Pin Select" "PTD[0:3],?..."
|
|
bitfld.long 0x00 10. " I2C1PS ,I2C1 Pin Select" "PTE1/PTE0,?..."
|
|
bitfld.long 0x00 9. " FTM2PS5 ,FTM2 Channel 5 Pin Select" "PTB5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " FTM2PS4 ,FTM2 Channel4 Pin Select" "PTB4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " FTM2PS3 ,FTM2 Channel 3 Pin Select" "PTC3,PTD1,?..."
|
|
bitfld.long 0x00 4.--5. " FTM2PS2 ,FTM2 Channel 2 Pin Select" "PTC2,PTD0,?..."
|
|
endif
|
|
sif (!(cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")))
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " FTM2PS1 ,FTM2 Channel 1 Pin Select" "PTC1,PTH1,PTF1,?..."
|
|
bitfld.long 0x00 0.--1. " FTM2PS0 ,FTM2 Channel 0 Pin Select" "PTC0,PTH0,PTF0,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLH4R"))
|
|
group.long 0x0C++0x03
|
|
else
|
|
group.long 0x14++0x03
|
|
endif
|
|
line.long 0x00 "SCGC,System Clock Gating Control Register"
|
|
bitfld.long 0x00 31. " ACMP1 ,ACMP1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACMP0 ,ACMP0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADC ,ADC Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQ ,IRQ Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " KBI1 ,KBI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBI0 ,KBI0 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!(cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")))
|
|
bitfld.long 0x00 22. " UART2 ,UART2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " UART1 ,UART1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 21. " UART1 ,UART1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPI1 ,SPI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI0 ,SPI0 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R")
|
|
bitfld.long 0x00 17. " I2C1 ,I2C1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " I2C0 ,I2C0 Clock Gate Control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 17. " I2C ,I2C Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " SWD ,SWD Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FLASH ,FLASH Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CRC ,CRC Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FTM2 ,FTM2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FTM1 ,FTM1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FTM0 ,FTM0 Clock Gate Control" "Disabled,Enabled"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R")
|
|
textline " "
|
|
bitfld.long 0x00 4. " PWT ,PWT Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIT ,PIT Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RTC ,RTC Clock Gate Control" "Disabled,Enabled"
|
|
sif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLD4R"))
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "UUIDL,Universally Unique Identifier Low Register"
|
|
line.long 0x04 "UUIDH,Universally Unique Identifier High Register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUSDIV,BUS Clock Divider Register"
|
|
bitfld.long 0x00 0. " BUSDIV ,BUS Clock Divider" "ICSOUTCLK,ICSOUTCLK/2"
|
|
else
|
|
rgroup.long 0x18++0x0B
|
|
line.long 0x00 "UUIDL,Universally Unique Identifier Low Register"
|
|
line.long 0x04 "UUIDML,Universally Unique Identifier Middle Low Register"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4"||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R"))
|
|
line.long 0x08 "UUIDMH,Universally Unique Identifier Middle High Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID[80:64] ,Universally Unique Identifier"
|
|
else
|
|
line.long 0x08 "UUIDMH,Universally Unique Identifier Middle High Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CLKDIV,Clock Divider Register"
|
|
bitfld.long 0x00 28.--29. " OUTDIV1 ,Clock 1 output divider value" "ICSOUTCLK,ICSOUTCLK/2,ICSOUTCLK/3,ICSOUTCLK/4"
|
|
bitfld.long 0x00 24. " OUTDIV2 ,Clock 2 output divider value" "Divider1,Divider1/2"
|
|
bitfld.long 0x00 20. " OUTDIV3 ,Clock 3 output divider value" "ICSOUTCLK,ICSOUTCLK/2"
|
|
endif
|
|
width 0x0B
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
width 9.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHIPCTL,Chip Control Register"
|
|
sif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 18.--19. " RTC32KCLKSEL ,RTC 32K clock input select" "OSC32,RTC_CLKIN,?..."
|
|
bitfld.long 0x00 16.--17. " PWTCLKSEL ,PWT clock source select" "TCLK0,TCLK1,TCLK2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PDB_BB_SEL ,PDB back-to-back select" "PDB0 ch0 ADC0 COCO/PDB1 ch0 ADC1 COCO,PDB0/PDB1 ch0 ADC0/ADC1 COCO"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CLKOUTSEL ,CLKOUT Select" ",SCGCLKOUT,RTC CLK,LPO CLK"
|
|
bitfld.long 0x00 4.--5. " CLKOUTDIV ,CLKOUT divider ratio" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 1. " ADC_INTERLEAVE_EN[1] ,ADC interleave channel enable 1 - PTB1 to ADC0_SE4 and ADC1_SE15" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,ADC interleave channel enable 0 - PTB0 to ADC0_SE4 and ADC1_SE14" "Disabled,Enabled"
|
|
elif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 18.--19. " RTC32KCLKSEL ,RTC 32K clock input select" "OSC32,RTC_CLKIN,SOSC_CLK,?..."
|
|
bitfld.long 0x00 16.--17. " PWTCLKSEL ,PWT clock source select" "TCLK0,TCLK1,TCLK2,?..."
|
|
bitfld.long 0x00 15. " CAN_FLT_CLK_SEL ,CAN filter clock select" "LPO CLK,SIRC CLK"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PDB_BB_SEL ,PDB back-to-back select" "PDB0 ch0 ADC0 COCO/PDB1 ch0 ADC1 COCO,PDB0/PDB1 ch0 ADC0/ADC1 COCO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TRACECLK_SEL ,Debug trace clock select" "Core,Platform"
|
|
bitfld.long 0x00 6.--7. " CLKOUTSEL ,CLKOUT Select" ",SCGCLKOUT,RTC CLK,LPO CLK"
|
|
bitfld.long 0x00 4.--5. " CLKOUTDIV ,CLKOUT divider ratio" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADC_INTERLEAVE_EN[3] ,ADC interleave channel enable 3 - PTB14 to ADC1_SE9 and ADC2_SE9" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,ADC interleave channel enable 2 - PTB13 to ADC1_SE8 and ADC2_SE8" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,ADC interleave channel enable 1 - PTB1 to ADC0_SE4 and ADC1_SE15" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,ADC interleave channel enable 0 - PTB0 to ADC0_SE4 and ADC1_SE14" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FTMOPT0,FTM Option Register 0"
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 30.--31. " FTM3CLKSEL ,FTM3 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
bitfld.long 0x00 28.--29. " FTM2CLKSEL ,FTM2 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
bitfld.long 0x00 26.--27. " FTM1CLKSEL ,FTM1 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
bitfld.long 0x00 24.--25. " FTM0CLKSEL ,FTM0 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FTM3FLT2SEL ,FTM3 fault 2 select" "FTM3_FLT2 pin,TRGMUX_FTM3 out"
|
|
bitfld.long 0x00 13. " FTM3FLT1SEL ,FTM3 fault 1 select" "FTM3_FLT1 pin,TRGMUX_FTM3 out"
|
|
bitfld.long 0x00 12. " FTM3FLT0SEL ,FTM3 fault 0 select" "FTM3_FLT0 pin,TRGMUX_FTM3 out"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FTM2FLT2SEL ,FTM2 fault 2 select" "FTM2_FLT2 pin,TRGMUX_FTM2 out"
|
|
bitfld.long 0x00 9. " FTM2FLT1SEL ,FTM2 fault 1 select" "FTM2_FLT1 pin,TRGMUX_FTM2 out"
|
|
bitfld.long 0x00 8. " FTM2FLT0SEL ,FTM2 fault 0 select" "FTM2_FLT0 pin,TRGMUX_FTM2 out"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FTM1FLT2SEL ,FTM1 fault 2 select" "FTM1_FLT2 pin,TRGMUX_FTM1 out"
|
|
bitfld.long 0x00 5. " FTM1FLT1SEL ,FTM1 fault 1 select" "FTM1_FLT1 pin,TRGMUX_FTM1 out"
|
|
bitfld.long 0x00 4. " FTM1FLT0SEL ,FTM1 fault 0 select" "FTM1_FLT0 pin,TRGMUX_FTM1 out"
|
|
textline " "
|
|
elif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 28.--29. " FTM2CLKSEL ,FTM2 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
bitfld.long 0x00 26.--27. " FTM1CLKSEL ,FTM1 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
bitfld.long 0x00 24.--25. " FTM0CLKSEL ,FTM0 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " FTM0FLT2SEL ,FTM0 fault 2 select" "FTM0_FLT2 pin,TRGMUX_FTM0 out"
|
|
bitfld.long 0x00 1. " FTM0FLT1SEL ,FTM0 fault 1 select" "FTM0_FLT1 pin,TRGMUX_FTM0 out"
|
|
bitfld.long 0x00 0. " FTM0FLT0SEL ,FTM0 fault 0 select" "FTM0_FLT0 pin,TRGMUX_FTM0 out"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADCOPT,ADC Options Register"
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 20.--21. " ADC2PRETRGSEL ,ADC2 pre-trigger source select" "PDB pre-trigger,TRGMUX pre-trigger,Software pre-trigger,?..."
|
|
bitfld.long 0x00 17.--19. " ADC2SWPRETRG ,ADC2 software pre-trigger sources" "Disabled,,,,SW pre-trigger 0,SW pre-trigger 1,SW pre-trigger 2,SW pre-trigger 3"
|
|
bitfld.long 0x00 16. " ADC2TRGSEL ,ADC2 trigger source select" "PDB output,TRGMUX output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " ADC1PRETRGSEL ,ADC1 pre-trigger source select" "PDB pre-trigger,TRGMUX pre-trigger,Software pre-trigger,?..."
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 9.--11. " ADC1SWPRETRG ,ADC1 software pre-trigger sources" "Disabled,,,,SW pre-trigger 0,SW pre-trigger 1,SW pre-trigger 2,SW pre-trigger 3"
|
|
elif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 9.--10. " ADC1SWPRETRG ,ADC1 software pre-trigger sources" "Disabled,SW pre-trigger 0,SW pre-trigger 1,Disabled"
|
|
endif
|
|
bitfld.long 0x00 8. " ADC1TRGSEL ,ADC1 trigger source select" "PDB output,TRGMUX output"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ADC0PRETRGSEL ,ADC0 pre-trigger source select" "PDB pre-trigger,TRGMUX pre-trigger,Software pre-trigger,?..."
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 1.--3. " ADC0SWPRETRG ,ADC0 software pre-trigger sources" "Disabled,,,,SW pre-trigger 0,SW pre-trigger 1,SW pre-trigger 2,SW pre-trigger 3"
|
|
elif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 1.--2. " ADC0SWPRETRG ,ADC0 software pre-trigger sources" "Disabled,SW pre-trigger 0,SW pre-trigger 1,Disabled"
|
|
endif
|
|
bitfld.long 0x00 0. " ADC0TRGSEL ,ADC0 trigger source select" "PDB output,TRGMUX output"
|
|
line.long 0x04 "FTMOPT1,FTM Option Register 1"
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x04 31. " FTM3_OUTSEL[7] ,FTM3 channel 7 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [6] ,FTM3 channel 6 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [5] ,FTM3 channel 5 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [4] ,FTM3 channel 4 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [3] ,FTM3 channel 3 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [2] ,FTM3 channel 2 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [1] ,FTM3 channel 1 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [0] ,FTM3 channel 0 FTM2_CH1 modulation select" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 23. " FTM0_OUTSEL[7] ,FTM0 channel 7 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,FTM0 channel 6 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,FTM0 channel 5 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,FTM0 channel 4 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [3] ,FTM0 channel 3 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,FTM0 channel 2 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,FTM0 channel 1 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,FTM0 channel 0 FTM1_CH1 modulation select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FTM2CH1SEL ,FTM2 CH1 select" "FTM2_CH1 input,Xor(Ftm2_ch0 FTM2_CH1 FTM1_CH1)"
|
|
textline " "
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x04 6.--7. " FTM2CH0SEL ,FTM2 CH0 select" "FTM2_CH0 input,CMP0 output,CMP1 output,CMP2 output"
|
|
bitfld.long 0x04 4.--5. " FTM1CH0SEL ,FTM1 CH0 select" "FTM1_CH0 input,CMP0 output,CMP1 output,CMP2 output"
|
|
bitfld.long 0x04 3. " FTM3SYNCBIT ,FTM3 sync bit" "0,1"
|
|
else
|
|
bitfld.long 0x04 6.--7. " FTM2CH0SEL ,FTM2 CH0 select" "FTM2_CH0 input,CMP0 output,CMP1 output,?..."
|
|
bitfld.long 0x04 4.--5. " FTM1CH0SEL ,FTM1 CH0 select" "FTM1_CH0 input,CMP0 output,CMP1 output,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " FTM2SYNCBIT ,FTM2 sync bit" "0,1"
|
|
bitfld.long 0x04 1. " FTM1SYNCBIT ,FTM1 sync bit" "0,1"
|
|
bitfld.long 0x04 0. " FTM0SYNCBIT ,FTM0 sync bit" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis E-series Family ID" ",KE1x Family,?..."
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis E-series Sub-Family ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis Series ID" ",,Kinetis E+ series,?..."
|
|
textline " "
|
|
sif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,16 KB,32KB,?..."
|
|
elif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,,32KB,64 KB,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--11. " PROJECTID ,Project ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PINID ,Pin identification"
|
|
sif (cpuis("MKE??F*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PLATCGC,Platform Clock Gating Control Register"
|
|
bitfld.long 0x00 2. " CGCDMA ,DMA clock gating control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CGCMPU ,MPU clock gating control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CGCMSCM ,MSCM clock gating control" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x4C++0x17
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 28.--31. " NVMSIZE ,FlexNVM size" "0 KB,,,32KB,,64 KB,,,,,,,,,,64KB"
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" "8 KB,16 KB,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,,,512 KB"
|
|
bitfld.long 0x00 16.--19. " EEERAMSIZE ,EEE SRAM SIZE" ",,4 KB,2 KB,1 KB,512 B,256 B,128 B,64 B,32 B,?..."
|
|
bitfld.long 0x00 12.--15. " DEPART ,FlexNVM partition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 28.--31. " NVMSIZE ,FlexNVM size" "0 KB,,,32KB,,?..."
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,,,,,128 KB,,256 KB,?..."
|
|
bitfld.long 0x00 16.--19. " EEERAMSIZE ,EEE SRAM SIZE" ",,,2 KB,1 KB,512 B,256 B,128 B,64 B,32 B,?..."
|
|
bitfld.long 0x00 12.--15. " DEPART ,FlexNVM partition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash Doze" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash Disable" "No,Yes"
|
|
line.long 0x04 "FCFG2,Flash Configuration Register 2"
|
|
hexmask.long.byte 0x04 24.--30. 0x01 " MAXADDR0 ,Max address block 0"
|
|
hexmask.long.byte 0x04 16.--22. 0x01 " MAXADDR1 ,Max address block 1"
|
|
line.long 0x08 "UIDH,Unique Identification Register High"
|
|
line.long 0x0C "UIDMH,Unique Identification Register Mid-High"
|
|
line.long 0x10 "UIDML,Unique Identification Register Mid Low"
|
|
line.long 0x14 "UIDL,Unique Identification Register Low"
|
|
sif (cpuis("MKE??F*"))
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CLKDIV4,System Clock Divider Register 4"
|
|
bitfld.long 0x00 28. " TRACEDIVEN ,Debug trace divider control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " TRACEDIV ,Trace clock divider divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " TRACEFRAC ,Trace clock divider fraction" "0,1"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MISCTRL,Miscellaneous Control Register"
|
|
sif (cpuis("MKE??F*"))
|
|
bitfld.long 0x00 16. " SW_INTERRUPT ,Software Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " SW_TRG ,Software trigger bit to TRGMUX" "0,1"
|
|
elif (cpuis("MKE??Z*"))
|
|
bitfld.long 0x00 18. " UART2ODE ,UART2 Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UART1ODE ,UART1 Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " UART0ODE ,UART0 Open Drain Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMA_INT_SEL[7] ,DMA channel 7 and channel 3 interrupt select" "CH 3,CH 7"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel 6 and channel 2 interrupt select" "CH 2,CH 6"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel 5 and channel 1 interrupt select" "CH 1,CH 5"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel 4 and channel 0 interrupt select" "CH 0,CH 4"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SW_TRG ,Software trigger bit to TRGMUX" "0,1"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SIM_SRSID,System Reset Status and ID Register"
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "KE0x,?..."
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,KEx2,?..."
|
|
bitfld.long 0x00 20.--23. " RevID ,Device Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PINID ,Device Pin ID" "8-pin,16-pin,20-pin,24-pin,32-pin,44-pin,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
bitfld.long 0x00 13. " SACKERR ,Stop Mode Acknowledge Error Reset" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " MDMAP ,MDM-AP System Reset Request" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SW ,Software" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " LOCKUP ,Core Lockup" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " POR ,Power-On Reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PIN ,External Reset Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " WDOG ,Watchdog" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " LOC ,Internal Clock Source Module Reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LVD ,Low Voltage Detect" "Not occurred,Occurred"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SIM_SOPT,System Options Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DELAY ,FTM2 Trigger Delay"
|
|
rbitfld.long 0x00 23. " DLYACT ,FTM2 Trigger Delay Active" "Inactive,Active"
|
|
bitfld.long 0x00 19. " CLKOE ,Bus Clock Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " BUSREF ,BUS Clock Output select" "Bclk,Bclk/2,Bclk/4,Bclk/8,Bclk/16,Bclk/32,Bclk/64,Bclk/128"
|
|
bitfld.long 0x00 15. " TXDME ,UART0_TX Modulation Select" "Not selected,FTM0"
|
|
bitfld.long 0x00 14. " FTMSYNC ,FTM2 Synchronization Select" "Not selected,selected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXDFE ,UART0_RX Filter Select" "Not selected,ACMP"
|
|
bitfld.long 0x00 12. " RXDCE ,UART0_RX Capture Select" "Not selected,FTM0"
|
|
bitfld.long 0x00 11. " ACIC ,Analog Comparator to Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RTCC ,Real-Time Counter Capture" "Disabled,FTM1"
|
|
bitfld.long 0x00 8.--9. " ADHWT ,ADC Hardware Trigger Source" "RTC,PIT,FTM2 init,FTM2 match"
|
|
bitfld.long 0x00 2. " RSTPE ,PTA5/IRQ/FTM0_CLK/RESET Pins as Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SWDE ,Single Wire Debug Port Pin Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NMIE ,PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 Pins as NMI Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SIM_PINSEL,Pin Selection Register"
|
|
bitfld.long 0x04 15. " FTM2PS3 ,FTM2[3] Port Pin Select" "PTC3,PTD1"
|
|
bitfld.long 0x04 14. " FTM2PS2 ,FTM2[2] Port Pin Select" "PTC2,PTD0"
|
|
textline " "
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")
|
|
bitfld.long 0x04 13. " FTM2PS1 ,FTM2[1] Port Pin Select" "PTC1,PTH1"
|
|
bitfld.long 0x04 12. " FTM2PS0 ,FTM2[0] Port Pin Select" "PTC0,PTH0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 13. " FTM2PS1 ,FTM2[1] Port Pin Select" "PTC1,?..."
|
|
bitfld.long 0x04 12. " FTM2PS0 ,FTM2[0] Port Pin Select" "PTC0,?..."
|
|
textline " "
|
|
endif
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x04 11. " FTM1PS1 ,FTM1[1] Port Pin Select" "PTC5,PTE7"
|
|
bitfld.long 0x04 10. " FTM1PS0 ,FTM1[0] Port Pin Select" "PTC4,PTH2"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 11. " FTM1PS1 ,FTM1[1] Port Pin Select" "PTC5,?..."
|
|
bitfld.long 0x04 10. " FTM1PS0 ,FTM1[0] Port Pin Select" "PTC4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " FTM0PS1 ,FTM0[1] Port Pin Select" "PTA1,PTB3"
|
|
bitfld.long 0x04 8. " FTM0PS0 ,FTM0[0] Port Pin Select" "PTA0,PTB2"
|
|
bitfld.long 0x04 7. " UART0PS ,UART0 Pin Select" "PTB0/PTB1,PTA2/PTA3"
|
|
textline " "
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")
|
|
bitfld.long 0x04 6. " SPI0PS ,SPI0 Pin Select" "PTB[2:5],PTE[0:3]"
|
|
else
|
|
bitfld.long 0x04 6. " SPI0PS ,SPI0 Pin Select" "PTB[2:5],?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 5. " I2C0PS ,I2C0 Port Pin Select" "PTA[3:2],PTB[7:6]"
|
|
bitfld.long 0x04 4. " RTCPS ,RTCO Pin Select" "PTC4,PTC5"
|
|
line.long 0x08 "SIM_SCGC,System Clock Gating Control Register"
|
|
bitfld.long 0x08 31. " ACMP1 ,ACMP1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " ACMP0 ,ACMP0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " ADC ,ADC Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQ ,IRQ Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " KBI1 ,KBI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " KBI0 ,KBI0 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R")
|
|
bitfld.long 0x08 21. " UART1 ,UART1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 22. " UART2 ,UART2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " UART1 ,UART1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 19. " SPI1 ,SPI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " SPI0 ,SPI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " I2C ,I2C Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SWD ,SWD Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " FLASH ,FLASH Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CRC ,CRC Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " FTM2 ,FTM2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " FTM1 ,FTM1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " FTM0 ,FTM0 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PIT ,PIT Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RTC ,RTC Clock Gate Control" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "SIM_UUIDL,Universally Unique Identifier Low Register"
|
|
line.long 0x04 "SIM_UUIDH,Universally Unique Identifier High Register"
|
|
line.long 0x08 "SIM_BUSDIV,BUS Clock Divider Register"
|
|
bitfld.long 0x08 0. " BUSDIV ,BUS Clock Divider" "ICSOUTCLK,ICSOUTCLK/2"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
tree "MMDVSQ (Memory-Mapped Divide and Square Root)"
|
|
base ad:0xF0004000
|
|
width 8.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DEND,Dividend Register"
|
|
line.long 0x04 "DSOR,Divisor Register"
|
|
line.long 0x08 "CSR,Control/Status Register"
|
|
rbitfld.long 0x08 31. " BUSY ,Busy" "Idle,Busy"
|
|
rbitfld.long 0x08 30. " DIVIDE ,Divide" "Not divided,Divided"
|
|
rbitfld.long 0x08 29. " SQRT ,Square root" "Was not a square root,Was a square root"
|
|
newline
|
|
bitfld.long 0x08 5. " DFS ,Disable fast start" "DSOR,CSR"
|
|
rbitfld.long 0x08 4. " DZ ,Divide-by-zero" "Non-zero divisor,Zero divisor"
|
|
bitfld.long 0x08 3. " DZE ,Divide-by-zero-enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " REM ,Remainder calculation" "Return quotient,Return reminder"
|
|
bitfld.long 0x08 1. " USGN ,Unsigned calculation" "Signed divide,Unsigned divide"
|
|
bitfld.long 0x08 0. " SRT ,Start" "No effect,Start"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "RES,Result Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "RCND,Radicand Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "SMC (System Mode Controller)"
|
|
base ad:0x4007E000
|
|
width 14.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "SMC_VERID,SMC Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor Version Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature Specification Number"
|
|
line.long 0x04 "SMC_PARAM,SMC Parameter Register"
|
|
bitfld.long 0x04 6. " EVLLS0 ,Existence of VLLS0 feature" "Not available,Available"
|
|
bitfld.long 0x04 5. " ELLS2 ,Existence of LLS2 feature" "Not available,Available"
|
|
bitfld.long 0x04 3. " ELLS ,Existence of LLS feature" "Not available,Available"
|
|
bitfld.long 0x04 0. " EHSRUN ,Existence of HSRUN feature" "Not available,Available"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SMC_PMPROT,Power Mode Protection Register"
|
|
sif cpuis("MKE1?Z???VLH7")||cpuis("MKE1?Z???VLL7")
|
|
bitfld.long 0x00 5. " AVLP ,Very-Low-Power Modes allow" "Not allowed,Allowed"
|
|
else
|
|
bitfld.long 0x00 7. " AHSRUN ,High Speed Run mode allow" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " AVLP ,Very-Low-Power Modes allow" "Not allowed,Allowed"
|
|
endif
|
|
line.long 0x04 "SMC_PMCTRL,Power Mode Control Register"
|
|
sif cpuis("MKE1?Z???VLH7")||cpuis("MKE1?Z???VLL7")
|
|
bitfld.long 0x04 5.--6. " RUNM ,Run Mode Control" "Normal,,Very-Low-Power Run,?..."
|
|
else
|
|
bitfld.long 0x04 5.--6. " RUNM ,Run Mode Control" "Normal,,Very-Low-Power Run,High Speed"
|
|
endif
|
|
bitfld.long 0x04 3. " STOPA ,Stop Aborted" "Not aborted,Aborted"
|
|
bitfld.long 0x04 0.--2. " STOPM ,Stop Mode Control" "Normal,,Very-Low-Power,?..."
|
|
if (((per.l(ad:0x4007E000+0x0C))&0x70)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SMC_STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. " PSTOPO ,Partial Stop Option" "STOP,PSTOP1,PSTOP2,?..."
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SMC_STOPCTRL,Stop Control Register"
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SMC_PMSTAT,Power Mode Status Register"
|
|
sif cpuis("MKE1?Z???VLH7")||cpuis("MKE1?Z???VLL7")
|
|
bitfld.long 0x00 4. " PMSTAT[4] ,Current power mode is VLPS" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Current power mode is VLPW" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Current power mode is VLPR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Current power mode is STOP" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Current power mode is RUN" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 7. " PMSTAT[7] ,Current power mode is HSRUN" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Current power mode is VLPS" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Current power mode is VLPW" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Current power mode is VLPR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Current power mode is STOP" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Current power mode is RUN" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x4007D000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
width 13.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "PMC_LVDSC1,Low Voltage Detect Status and Control 1 Register"
|
|
rbitfld.byte 0x00 7. " LVDF ,Low-Voltage Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " LVDACK ,Low-Voltage Detect Acknowledge [read/write]" "Not occurred/No effect,Occurred/Acknowledge"
|
|
bitfld.byte 0x00 5. " LVDIE ,Low-Voltage Detect Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LVDRE ,Low-Voltage Detect Reset Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "PMC_LVDSC2,System Power Management Status and Control 2 Register"
|
|
rbitfld.byte 0x01 7. " LVWF ,Low-Voltage Warning Flag" "No warning,Warning"
|
|
bitfld.byte 0x01 6. " LVWACK ,Low-Voltage Warning Acknowledge [read/write]" "Not occurred/No effect,Occurred/Acknowledge"
|
|
bitfld.byte 0x01 5. " LVWIE ,Low-Voltage Warning Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "PMC_REGSC,Regulator Status and Control Register"
|
|
bitfld.byte 0x02 7. " LPODIS ,LPO Disable Bit" "No,Yes"
|
|
rbitfld.byte 0x02 6. " LPOSTAT ,LPO Status" "Low phase,High phase"
|
|
rbitfld.byte 0x02 2. " REGFPM ,Regulator in Full Performance Mode Status Bit" "Low power mode/Transition,Full performance mode"
|
|
bitfld.byte 0x02 1. " CLKBIASDIS ,Clock Bias Disable Bit" "No effect,Disabled"
|
|
bitfld.byte 0x02 0. " BIASEN ,Bias Enable Bit" "Disabled,Enabled"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "PMC_LPOTRIM,Low Power Oscillator Trim Register"
|
|
bitfld.byte 0x00 0.--4. " LPOTRIM ,LPO trimming bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
width 0xB
|
|
else
|
|
width 12.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "PMC_SPMSC1,System Power Management Status and Control 1 Register"
|
|
rbitfld.byte 0x00 7. " LVWF ,Low-Voltage Warning Flag" "No warning,Warning"
|
|
bitfld.byte 0x00 6. " LVWACK ,Low-Voltage Warning Acknowledge [read/write]" "Not occurred/No effect,Occurred/Acknowledge"
|
|
bitfld.byte 0x00 5. " LVWIE ,Low-Voltage Warning Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LVDRE ,Low-Voltage Detect Reset Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LVDSE ,Low-Voltage Detect Stop Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LVDE ,Low-Voltage Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " BGBE ,Bandgap Buffer Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "PMC_SPMSC2,System Power Management Status and Control 2 Register"
|
|
bitfld.byte 0x01 6. " LVDV ,Low-Voltage Detect Voltage Select" "V_LVDL,V_LVDH"
|
|
bitfld.byte 0x01 4.--5. " LVWV ,Low-Voltage Warning Voltage Select" "V_LVW1,V_LVW2,V_LVW3,V_LVW4"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "MCM (Miscellaneous Control Module)"
|
|
base ad:0xF0003000
|
|
width 11.
|
|
rgroup.word 0x08++0x03
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
bitfld.word 0x00 7. " ASC7 ,Crossbar switch slave input port 7 connection present" "Absent,Present"
|
|
bitfld.word 0x00 6. " ASC6 ,Crossbar switch slave input port 6 connection present" "Absent,Present"
|
|
bitfld.word 0x00 5. " ASC5 ,Crossbar switch slave input port 5 connection present" "Absent,Present"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ASC4 ,Crossbar switch slave input port 4 connection present" "Absent,Present"
|
|
bitfld.word 0x00 3. " ASC3 ,Crossbar switch slave input port 3 connection present" "Absent,Present"
|
|
bitfld.word 0x00 2. " ASC2 ,Crossbar switch slave input port 2 connection present" "Absent,Present"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ASC1 ,Crossbar switch slave input port 1 connection present" "Absent,Present"
|
|
bitfld.word 0x00 0. " ASC0 ,Crossbar switch slave input port 0 connection present" "Absent,Present"
|
|
line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
bitfld.word 0x02 7. " AMC7 ,Crossbar switch master input port 7 connection present" "Absent,Present"
|
|
bitfld.word 0x02 6. " AMC6 ,Crossbar switch master input port 6 connection present" "Absent,Present"
|
|
bitfld.word 0x02 5. " AMC5 ,Crossbar switch master input port 5 connection present" "Absent,Present"
|
|
textline " "
|
|
bitfld.word 0x02 4. " AMC4 ,Crossbar switch master input port 4 connection present" "Absent,Present"
|
|
bitfld.word 0x02 3. " AMC3 ,Crossbar switch master input port 3 connection present" "Absent,Present"
|
|
bitfld.word 0x02 2. " AMC2 ,Crossbar switch master input port 2 connection present" "Absent,Present"
|
|
textline " "
|
|
bitfld.word 0x02 1. " AMC1 ,Crossbar switch master input port 1 connection present" "Absent,Present"
|
|
bitfld.word 0x02 0. " AMC0 ,Crossbar switch master input port 0 connection present" "Absent,Present"
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Fixed priority,Fixed priority"
|
|
bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Fixed priority,Fixed priority"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBRR ,Crossbar round-robin arbitration enable" "Fixed-priority,Round-robin"
|
|
line.long 0x04 "ISCR,Interrupt Status And Control Register"
|
|
bitfld.long 0x04 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CWBEE ,Cache write buffer error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 15. " FIDC ,FPU input denormal interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x04 12. " FIXC ,FPU inexact interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 11. " FUFC ,FPU underflow interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 10. " FOFC ,FPU overflow interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 9. " FDZC ,FPU divide-by-zero interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x04 8. " FIOC ,FPU invalid operation interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " CWBER ,Cache write buffer error status" "No error,Error"
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "FADR,Store Buffer Fault Address Register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "FATR,Store Buffer Fault Attributes Register"
|
|
bitfld.long 0x00 31. " BEOVR ,Bus error overrun" "Not occurred,Ocurred"
|
|
bitfld.long 0x00 8.--11. " BEMN ,Bus error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " BEWT ,Bus error write" "Read,Write"
|
|
bitfld.long 0x00 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " BEMD ,Bus error privilege level" "User mode,Supervisor/privileged mode"
|
|
bitfld.long 0x00 0. " BEDA ,Bus error data access type" "Instruction,Data"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "FDR,Store Buffer Fault Data Register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PID,Process ID register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID And M1_PID For MPU"
|
|
else
|
|
if (((per.l(ad:0xF0003000+0x0C))&0xA000)==0x0000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes"
|
|
bitfld.long 0x00 14. " EFDS ,Enable flash data speculation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes"
|
|
bitfld.long 0x00 12. " DFCIC ,Disable flash controller instruction caching" "No,Yes"
|
|
bitfld.long 0x00 11. " DFCDA ,Disable flash controller data caching" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear"
|
|
elif (((per.l(ad:0xF0003000+0x0C))&0xA000)==0x4000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes"
|
|
bitfld.long 0x00 14. " EFDS ,Enable flash data speculation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear"
|
|
elif (((per.l(ad:0xF0003000+0x0C))&0xA000)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes"
|
|
bitfld.long 0x00 12. " DFCIC ,Disable flash controller instruction caching" "No,Yes"
|
|
bitfld.long 0x00 11. " DFCDA ,Disable flash controller data caching" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear"
|
|
endif
|
|
endif
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Wakeup"
|
|
rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Not completed,Acknowledge"
|
|
bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested"
|
|
endif
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LMDR0,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB"
|
|
rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..."
|
|
rbitfld.long 0x00 16. " RO ,Read-only" "Read/write,Read only"
|
|
rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,PC cache,PS cache,?..."
|
|
bitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [2] ,Control field 1 - PS parity fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [1] ,Control field 1 - PC parity miss enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [0] ,Control field 1 - PS parity miss enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CF0[3] ,Control field 0 - Parity Fault Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Control field 0 - ECC enable read check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "LMDR1,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB"
|
|
rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..."
|
|
rbitfld.long 0x00 16. " RO ,Read-only" "Read/write,Read only"
|
|
rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,PC cache,PS cache,?..."
|
|
bitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [2] ,Control field 1 - PS parity fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [1] ,Control field 1 - PC parity miss enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [0] ,Control field 1 - PS parity miss enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CF0[3] ,Control field 0 - Parity Fault Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Control field 0 - ECC enable read check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "LMDR2,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB"
|
|
rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..."
|
|
rbitfld.long 0x00 16. " RO ,Read-only" "Read/write,Read only"
|
|
rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,PC cache,PS cache,?..."
|
|
bitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [2] ,Control field 1 - PS parity fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [1] ,Control field 1 - PC parity miss enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [0] ,Control field 1 - PS parity miss enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CF0[3] ,Control field 0 - Parity Fault Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Control field 0 - ECC enable read check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "LMPECR,LMEM Parity And ECC Control Register"
|
|
bitfld.long 0x00 20. " ECPR ,Enable cache parity reporting" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " ERPR ,Enable RAM Parity Reporting" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ER1BR ,Enable RAM ECC 1 bit reporting" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ERNCR ,Enable RAM ECC noncorrectable reporting" "Enabled,Disabled"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "LMPEIR,LMEM Parity And ECC Interrupt Register"
|
|
rbitfld.long 0x00 31. " V ,Valid bit" "0,1"
|
|
bitfld.long 0x00 24.--28. " PEELOC ,Parity or ECC error location" "SRAM_L non-correct ECC,SRAM_U non-correct ECC,,,,,,,SRAM_L 1-bit correct ECC,SRAM_U 1-bit correct ECC,,,,,PC tag parity,PC data parity,?..."
|
|
bitfld.long 0x00 21. " PE[21] ,Parity error - PC data parity" "No error,Error"
|
|
bitfld.long 0x00 20. " [20] ,Parity error - PC tag parity" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " E1B[9] ,ECC 1-bit error - SRAM_U" "No error,Error"
|
|
bitfld.long 0x00 8. " [8] ,ECC 1-bit error - SRAM_L" "No error,Error"
|
|
bitfld.long 0x00 1. " ENC[1] ,ECC noncorrectable error - SRAM_U" "No error,Error"
|
|
bitfld.long 0x00 0. " [0] ,ECC noncorrectable error - SRAM_L" "No error,Error"
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "LMFAR,LMEM Fault Address Register"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "LMFATR,LMEM Fault Attribute Register"
|
|
rbitfld.long 0x00 31. " OVR ,Overrun" "No overrun,Overrun"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PEFMST ,Parity/ecc fault master number"
|
|
rbitfld.long 0x00 7. " PEFW ,Parity/ecc fault write" "0,1"
|
|
bitfld.long 0x00 4.--6. " PEFSIZE ,Parity/ecc fault master size" "8-bit,16-bit,32-bit,64-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEFPRT[3] ,Parity/ecc fault protection - cacheable" "Non-cacheable,Cacheable"
|
|
bitfld.long 0x00 2. " [2] ,Parity/ecc fault protection - bufferable" "Non-bufferable,Bufferable"
|
|
bitfld.long 0x00 1. " [1] ,Parity/ecc fault protection - mode" "User,Supervisor"
|
|
bitfld.long 0x00 0. " [0] ,Parity/ecc fault protection - type" "I-fetch,Data"
|
|
rgroup.long 0x4A0++0x07
|
|
line.long 0x00 "LMFDHR,LMEM Fault Data High Register"
|
|
line.long 0x04 "LMFDLR,LMEM Fault Data Low Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0x4000D000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CESR,Control/Error Status Register"
|
|
eventfld.long 0x00 31. " SPERR_[31] ,Slave port 0 error" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Slave port 1 error" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Slave port 2 error" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Slave port 3 error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8,12,16,?..."
|
|
bitfld.long 0x00 0. " VLD ,Global enable/disable for the MPU" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "EAR0,Error Address Register (Slave Port 0)"
|
|
line.long 0x04 "EDR0,Error Detail Register (Slave Port 0)"
|
|
hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..."
|
|
bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "EAR1,Error Address Register (Slave Port 1)"
|
|
line.long 0x04 "EDR1,Error Detail Register (Slave Port 1)"
|
|
hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..."
|
|
bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "EAR2,Error Address Register (Slave Port 2)"
|
|
line.long 0x04 "EDR2,Error Detail Register (Slave Port 2)"
|
|
hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..."
|
|
bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write"
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "EAR3,Error Address Register (Slave Port 3)"
|
|
line.long 0x04 "EDR3,Error Detail Register (Slave Port 3)"
|
|
hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..."
|
|
bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write"
|
|
textline " "
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "RGD0_WORD0,Region Descriptor 0 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD0_WORD1,Region Descriptor 0 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD0_WORD2,Region Descriptor 0 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD0_WORD3,Region Descriptor 0 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x410++0x0F
|
|
line.long 0x00 "RGD1_WORD0,Region Descriptor 1 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD1_WORD1,Region Descriptor 1 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD1_WORD2,Region Descriptor 1 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD1_WORD3,Region Descriptor 1 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x420++0x0F
|
|
line.long 0x00 "RGD2_WORD0,Region Descriptor 2 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD2_WORD1,Region Descriptor 2 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD2_WORD2,Region Descriptor 2 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD2_WORD3,Region Descriptor 2 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x430++0x0F
|
|
line.long 0x00 "RGD3_WORD0,Region Descriptor 3 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD3_WORD1,Region Descriptor 3 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD3_WORD2,Region Descriptor 3 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD3_WORD3,Region Descriptor 3 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x440++0x0F
|
|
line.long 0x00 "RGD4_WORD0,Region Descriptor 4 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD4_WORD1,Region Descriptor 4 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD4_WORD2,Region Descriptor 4 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD4_WORD3,Region Descriptor 4 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x450++0x0F
|
|
line.long 0x00 "RGD5_WORD0,Region Descriptor 5 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD5_WORD1,Region Descriptor 5 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD5_WORD2,Region Descriptor 5 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD5_WORD3,Region Descriptor 5 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x460++0x0F
|
|
line.long 0x00 "RGD6_WORD0,Region Descriptor 6 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD6_WORD1,Region Descriptor 6 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD6_WORD2,Region Descriptor 6 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD6_WORD3,Region Descriptor 6 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x470++0x0F
|
|
line.long 0x00 "RGD7_WORD0,Region Descriptor 7 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD7_WORD1,Region Descriptor 7 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
line.long 0x08 "RGD7_WORD2,Region Descriptor 7 Word 2"
|
|
bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
line.long 0x0C "RGD7_WORD3,Region Descriptor 7 Word 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed"
|
|
bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included"
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode"
|
|
bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AIPS-Lite (Peripheral Bridge)"
|
|
base ad:0x40000000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPRA,Master Privilege Register A"
|
|
bitfld.long 0x00 30. " MTR0 ,Master 0 trusted for read" "Not trusted,Trusted"
|
|
bitfld.long 0x00 29. " MTW0 ,Master 0 trusted for writes" "Not trusted,Trusted"
|
|
bitfld.long 0x00 28. " MPL0 ,Master 0 privilege level" "Forced,Not forced"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MTR1 ,Master 1 trusted for read" "Not trusted,Trusted"
|
|
bitfld.long 0x00 25. " MTW1 ,Master 1 trusted for writes" "Not trusted,Trusted"
|
|
bitfld.long 0x00 24. " MPL1 ,Master 1 privilege level" "Forced,Not forced"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MTR2 ,Master 2 trusted for read" "Not trusted,Trusted"
|
|
bitfld.long 0x00 21. " MTW2 ,Master 2 trusted for writes" "Not trusted,Trusted"
|
|
bitfld.long 0x00 20. " MPL2 ,Master 2 privilege level" "Forced,Not forced"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "PACRA,Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x04 "PACRB,Peripheral Access Control Register"
|
|
bitfld.long 0x04 30. " SP8 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 29. " WP8 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 28. " TP8 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 26. " SP9 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 25. " WP9 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 24. " TP9 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SP13 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 9. " WP13 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 8. " TP13 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SP15 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 1. " WP15 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 0. " TP15 ,Trusted protect" "Unprotected,Protected"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "OPACRA,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x04 "OPACRB,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x04 30. " SP8 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 29. " WP8 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 28. " TP8 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 26. " SP9 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 25. " WP9 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 24. " TP9 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SP13 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 9. " WP13 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 8. " TP13 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SP15 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 1. " WP15 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 0. " TP15 ,Trusted protect" "Unprotected,Protected"
|
|
group.long 0x50++0x2F
|
|
line.long 0x00 "OPACRE,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. " SP32 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 29. " WP32 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 28. " TP32 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SP33 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 25. " WP33 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 24. " TP33 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SP36 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 13. " WP36 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 12. " TP36 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SP37 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 9. " WP37 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 8. " TP37 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SP38 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 5. " WP38 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 4. " TP38 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SP39 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 1. " WP39 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 0. " TP39 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x04 "OPACRF,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x04 14. " SP44 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 13. " WP44 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 12. " TP44 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SP45 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 9. " WP45 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x04 8. " TP45 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x08 "OPACRG,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x08 26. " SP49 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 25. " WP49 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 24. " TP49 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SP50 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 21. " WP50 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 20. " TP50 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x08 18. " SP51 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 17. " WP51 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 16. " TP51 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SP54 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 5. " WP54 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 4. " TP54 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SP55 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 1. " WP55 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x08 0. " TP55 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x0C "OPACRH,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x0C 30. " SP56 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 29. " WP56 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 28. " TP56 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SP57 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 25. " WP57 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 24. " TP57 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " SP58 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 21. " WP58 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 20. " TP58 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " SP59 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 17. " WP59 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 16. " TP59 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " SP60 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 13. " WP60 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 12. " TP60 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " SP61 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 9. " WP61 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 8. " TP61 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SP63 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 1. " WP63 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x0C 0. " TP63 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x10 "OPACRI,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x10 30. " SP64 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x10 29. " WP64 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x10 28. " TP64 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x14 "OPACRJ,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x14 30. " SP72 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 29. " WP72 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 28. " TP72 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x14 26. " SP73 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 25. " WP73 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 24. " TP73 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x14 22. " SP74 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 21. " WP74 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 20. " TP74 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x14 18. " SP75 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 17. " WP75 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 16. " TP75 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x14 14. " SP76 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 13. " WP76 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 12. " TP76 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x14 10. " SP77 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 9. " WP77 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x14 8. " TP77 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x18 "OPACRK,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x18 22. " SP82 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x18 21. " WP82 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x18 20. " TP82 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x18 6. " SP86 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x18 5. " WP86 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x18 4. " TP86 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x1C "OPACRL,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x1C 22. " SP90 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x1C 21. " WP90 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x1C 20. " TP90 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x20 "OPACRM,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x20 30. " SP96 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 29. " WP96 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 28. " TP96 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 26. " SP97 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 25. " WP97 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 24. " TP97 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 22. " SP98 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 21. " WP98 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 20. " TP98 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 18. " SP99 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 17. " WP99 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 16. " TP99 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 14. " SP100 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 13. " WP100 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 12. " TP100 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 10. " SP101 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 9. " WP101 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 8. " TP101 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 6. " SP102 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 5. " WP102 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 4. " TP102 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x20 2. " SP103 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 1. " WP103 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x20 0. " TP103 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x24 "OPACRN,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x24 22. " SP106 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x24 21. " WP106 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x24 20. " TP106 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x24 18. " SP107 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x24 17. " WP107 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x24 16. " TP107 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x24 14. " SP108 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x24 13. " WP108 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x24 12. " TP108 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x28 "OPACRO,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x28 18. " SP115 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x28 17. " WP115 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x28 16. " TP115 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x28 14. " SP116 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x28 13. " WP116 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x28 12. " TP116 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x28 10. " SP117 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x28 9. " WP117 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x28 8. " TP117 ,Trusted protect" "Unprotected,Protected"
|
|
line.long 0x2C "OPACRP,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x2C 10. " SP125 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x2C 9. " WP125 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x2C 8. " TP125 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " SP126 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x2C 5. " WP126 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x2C 4. " TP126 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " SP127 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x2C 1. " WP127 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x2C 0. " TP127 ,Trusted protect" "Unprotected,Protected"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PACRU,Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected"
|
|
bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "TRGMUX (Trigger MUX Control)"
|
|
base ad:0x40062000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
width 12.
|
|
tree.open "TRGMUX1"
|
|
if (per.l(ad:0x40062000+0x1000)&0x80000000)==0x00000000
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "CTRL0,TRGMUX_CTRL0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
else
|
|
rgroup.long 0x1000++0x03
|
|
line.long 0x00 "CTRL0,TRGMUX_CTRL0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
endif
|
|
if ((per.l(ad:0x40062000+0x1004)&0x80000000)==0x00000000)
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "CTRL1,TRGMUX_CTRL1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
else
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "CTRL1,TRGMUX_CTRL1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_Pulse0,PDB0_Pulse1,?..."
|
|
endif
|
|
tree.end
|
|
tree.open "TRGMUX0"
|
|
if (per.l(ad:0x40062000)&0x80000000)==0x00000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DMAMUX0,TRGMUX_DMAMUX0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMAMUX0,TRGMUX_DMAMUX0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x04)&0x80000000)==0x00000000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EXTOUT0,TRGMUX_EXTOUT0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "EXTOUT0,TRGMUX_EXTOUT0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x08)&0x80000000)==0x00000000
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EXTOUT1,TRGMUX_EXTOUT1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EXTOUT1,TRGMUX_EXTOUT1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x0C)&0x80000000)==0x00000000
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC0,TRGMUX_ADC0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC0,TRGMUX_ADC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x10)&0x80000000)==0x00000000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADC1,TRGMUX_ADC1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC1,TRGMUX_ADC1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x1C)&0x80000000)==0x00000000
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMP0,TRGMUX_CMP0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CMP0,TRGMUX_CMP0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x20)&0x80000000)==0x00000000
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMP1,TRGMUX_CMP1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CMP1,TRGMUX_CMP1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x28)&0x80000000)==0x00000000
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FTM0,TRGMUX_FTM0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "FTM0,TRGMUX_FTM0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x2C)&0x80000000)==0x00000000
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FTM1,TRGMUX_FTM1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "FTM1,TRGMUX_FTM1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x30)&0x80000000)==0x00000000
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FTM2,TRGMUX_FTM2 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "FTM2,TRGMUX_FTM2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x38)&0x80000000)==0x00000000
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDB0,TRGMUX_PDB0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PDB0,TRGMUX_PDB0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x44)&0x80000000)==0x00000000
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FLEXIO,TRGMUX_FLEXIO Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "FLEXIO,TRGMUX_FLEXIO Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x48)&0x80000000)==0x00000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "LPIT0,TRGMUX_LPIT0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "LPIT0,TRGMUX_LPIT0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x4C)&0x80000000)==0x00000000
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "LPUART0,TRGMUX_LPUART0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "LPUART0,TRGMUX_LPUART0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x50)&0x80000000)==0x00000000
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "LPUART1,TRGMUX_LPUART1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "LPUART1,TRGMUX_LPUART1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x54)&0x80000000)==0x00000000
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LPI2C0,TRGMUX_LPI2C0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "LPI2C0,TRGMUX_LPI2C0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x58)&0x80000000)==0x00000000
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LPI2C1,TRGMUX_LPI2C1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LPI2C1,TRGMUX_LPI2C1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x5C)&0x80000000)==0x00000000
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "LPSPI0,TRGMUX_LPSPI0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LPSPI0,TRGMUX_LPSPI0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x60)&0x80000000)==0x00000000
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "LPSPI1,TRGMUX_LPSPI1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "LPSPI1,TRGMUX_LPSPI1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x64)&0x80000000)==0x00000000
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "LPTMR0,TRGMUX_LPTMR0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "LPTMR0,TRGMUX_LPTMR0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x68)&0x80000000)==0x00000000
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRGMUX_TSI,TRGMUX_LPTMR0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRGMUX_TSI,TRGMUX_LPTMR0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x6C)&0x80000000)==0x00000000
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PWT,TRGMUX_PWT Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "PWT,TRGMUX_PWT Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,TRGMUX1 Output 0,TRGMUX1 Output 1,TRGMUX1 Output 2,TRGMUX1 Output 3,TRGMUX1 Output 4,TRGMUX1 Output 5,TRGMUX1 Output 6,TRGMUX1 Output 7,?..."
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
width 9.
|
|
tree.open "TRGMUX0"
|
|
if (per.l(ad:0x40062000)&0x80000000)==0x00000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DMAMUX0,TRGMUX DMAMUX0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMAMUX0,TRGMUX DMAMUX0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x04)&0x80000000)==0x00000000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EXTOUT0,TRGMUX EXTOUT0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "EXTOUT0,TRGMUX EXTOUT0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x08)&0x80000000)==0x00000000
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EXTOUT1,TRGMUX_EXTOUT1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EXTOUT1,TRGMUX_EXTOUT1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x0C)&0x80000000)==0x00000000
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC0,TRGMUX_ADC0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC0,TRGMUX_ADC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x10)&0x80000000)==0x00000000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADC1,TRGMUX_ADC1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC1,TRGMUX_ADC1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x14)&0x80000000)==0x00000000
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADC2,TRGMUX_ADC2 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC2,TRGMUX_ADC2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x18)&0x80000000)==0x00000000
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DAC0,TRGMUX_DAC0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "DAC0,TRGMUX_DAC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x1C)&0x80000000)==0x00000000
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMP0,TRGMUX_CMP0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CMP0,TRGMUX_CMP0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x20)&0x80000000)==0x00000000
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMP1,TRGMUX_CMP1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CMP1,TRGMUX_CMP1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x24)&0x80000000)==0x00000000
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMP2,TRGMUX_CMP2 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CMP2,TRGMUX_CMP2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x28)&0x80000000)==0x00000000
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FTM0,TRGMUX_FTM0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "FTM0,TRGMUX_FTM0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x2C)&0x80000000)==0x00000000
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FTM1,TRGMUX_FTM1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "FTM1,TRGMUX_FTM1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x30)&0x80000000)==0x00000000
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FTM2,TRGMUX_FTM2 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "FTM2,TRGMUX_FTM2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x34)&0x80000000)==0x00000000
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FTM3,TRGMUX_FTM3 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "FTM3,TRGMUX_FTM3 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x38)&0x80000000)==0x00000000
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDB0,TRGMUX_PDB0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PDB0,TRGMUX_PDB0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x3C)&0x80000000)==0x00000000
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDB1,TRGMUX_PDB1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDB1,TRGMUX_PDB1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x40)&0x80000000)==0x00000000
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDB2,TRGMUX_PDB2 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PDB2,TRGMUX_PDB2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x44)&0x80000000)==0x00000000
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FLEXIO,TRGMUX_FLEXIO Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "FLEXIO,TRGMUX_FLEXIO Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x48)&0x80000000)==0x00000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "LPIT0,TRGMUX_LPIT0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "LPIT0,TRGMUX_LPIT0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x4C)&0x80000000)==0x00000000
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "LPUART0,TRGMUX_LPUART0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "LPUART0,TRGMUX_LPUART0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x50)&0x80000000)==0x00000000
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "LPUART1,TRGMUX_LPUART1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "LPUART1,TRGMUX_LPUART1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x54)&0x80000000)==0x00000000
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LPI2C0,TRGMUX_LPI2C0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "LPI2C0,TRGMUX_LPI2C0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x58)&0x80000000)==0x00000000
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LPI2C1,TRGMUX_LPI2C1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LPI2C1,TRGMUX_LPI2C1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x5C)&0x80000000)==0x00000000
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "LPSPI0,TRGMUX_LPSPI0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LPSPI0,TRGMUX_LPSPI0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x60)&0x80000000)==0x00000000
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "LPSPI1,TRGMUX_LPSPI1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "LPSPI1,TRGMUX_LPSPI1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x64)&0x80000000)==0x00000000
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "LPTMR0,TRGMUX_LPTMR0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "LPTMR0,TRGMUX_LPTMR0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
if (per.l(ad:0x40062000+0x6C)&0x80000000)==0x00000000
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PWT,TRGMUX_PWT Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "PWT,TRGMUX_PWT Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "TRGMUX IN0,TRGMUX IN1,TRGMUX IN2,TRGMUX IN3,RTC Seconds,RTC Alarm,LPTMR0,LPIT CH0,LPIT CH1,LPIT CH2,LPIT CH3,FTM0 Trigger,FTM1 Trigger,FTM2 Trigger,FTM3 Trigger,ADC0 COCOA,ADC0 COCOB,CMP0 Output,CMP1 Output,CMP2 Output,FLEXIO Trigger 0,FLEXIO Trigger 1,FLEXIO Trigger 2,FLEXIO Trigger 3,?..."
|
|
endif
|
|
tree.end
|
|
tree.open "TRGMUX1"
|
|
if (per.l(ad:0x40062000+0x1000)&0x80000000)==0x00000000
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "CTRL0,TRGMUX_CTRL0 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
else
|
|
rgroup.long 0x1000++0x03
|
|
line.long 0x00 "CTRL0,TRGMUX_CTRL0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
endif
|
|
if ((per.l(ad:0x40062000+0x1004)&0x80000000)==0x00000000)
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "CTRL1,TRGMUX_CTRL1 Register"
|
|
rbitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
else
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "CTRL1,TRGMUX_CTRL1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 source select" "Disabled,VDD,SIM,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,LPUART0 RX Data,LPUART0 TX Data,LPUART0 RX Idle,LPI2C0 Master STOP,LPI2C0 Slave STOP,LPSPI0 Frame,LPSPI0 RX data,LPUART1 RX Data,LPUART1 TX Data,LPUART1 RX Idle,LPI2C1 Master STOP,LPI2C1 Slave STOP,LPSPI1 Frame,LPSPI1 RX data,ADC1_COCOA,ADC1_COCOB,PDB0_DAC,PDB0_Pulse,PDB1_DAC,PDB1_Pulse,PDB2_DAC,PDB2_Pulse,ADC2_COCOA,ADC2_COCOB,?..."
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "EDMA (Enhanced Direct Memory Access)"
|
|
base ad:0x40008000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("S32D248*")||cpuis("S32S*"))
|
|
bitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " CX ,Cancel transfer" "Normal,Cancelled"
|
|
bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Normal,Cancelled"
|
|
bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CLM ,Continuous link mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Normal,Halt"
|
|
bitfld.long 0x00 4. " HOE ,Halt on error" "No,Yes"
|
|
bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Fixed priority,Round robin"
|
|
bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. " VLD ,Valid error" "Invalid,Valid"
|
|
bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled"
|
|
bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error"
|
|
bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error"
|
|
bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error"
|
|
bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error"
|
|
bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error"
|
|
bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error"
|
|
bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled"
|
|
wgroup.byte 0x18++0x01
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "Specified,All"
|
|
bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x01 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "Specified,All"
|
|
bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1A++0x01
|
|
line.byte 0x00 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x00 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x00 6. " CAER ,Clear all enable requests" "Specified,All"
|
|
bitfld.byte 0x00 0.--3. " CERQ ,Clear enable request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x01 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x01 6. " SAER ,Set all enable requests" "Specified,All"
|
|
bitfld.byte 0x01 0.--3. " SERQ ,Set enable request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1C++0x01
|
|
line.byte 0x00 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x00 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x00 6. " CADN ,Clears all DONE bits" "Specified,All"
|
|
bitfld.byte 0x00 0.--3. " CDNE ,Clear DONE bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x01 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x01 6. " SAST ,Set all START bits (Activates all channels)" "Specified,All"
|
|
bitfld.byte 0x01 0.--3. " SSRT ,Set START bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1E++0x01
|
|
line.byte 0x00 "CERR,Clear Error Register"
|
|
bitfld.byte 0x00 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x00 6. " CAEI ,Clear all error indicators" "Specified,All"
|
|
bitfld.byte 0x00 0.--3. " CERR ,Clear error indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x01 7. " NOP ,No op enable" "Normal op,No op"
|
|
bitfld.byte 0x01 6. " CAIR ,Clear all interrupt requests" "Specified,All"
|
|
bitfld.byte 0x01 0.--3. " CINT ,Clear interrupt request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt request 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Interrupt request 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt request 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Interrupt request 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt request 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt request 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt request 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Interrupt request 7" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 6. " [6] ,Interrupt request 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt request 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt request 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Interrupt request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt request 0" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error"
|
|
eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error"
|
|
else
|
|
eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error"
|
|
endif
|
|
eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error"
|
|
eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present"
|
|
bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present"
|
|
bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present"
|
|
bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present"
|
|
bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present"
|
|
bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present"
|
|
bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present"
|
|
else
|
|
bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present"
|
|
endif
|
|
bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present"
|
|
bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present"
|
|
bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present"
|
|
bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present"
|
|
bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request In Stop Register"
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
bitfld.long 0x00 15. " EDREQ_[15] ,Enable asynchronous DMA request in stop mode for channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop mode for channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop mode for channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop mode for channel 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop mode for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop mode for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop mode for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop mode for channel 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop mode for channel 7" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " EDREQ_[7] ,Enable asynchronous DMA request in stop mode for channel 7" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop mode for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop mode for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop mode for channel 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop mode for channel 3." "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop mode for channel 2." "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop mode for channel 1." "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop mode for channel 0." "Disabled,Enabled"
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "DCHPRI7,Channel 7 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "DCHPRI6,Channel 6 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "DCHPRI5,Channel 5 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "DCHPRI4,Channel 4 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("MKE14Z*")&&!cpuis("MKE15Z*"))
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "DCHPRI11,Channel 11 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "DCHPRI10,Channel 10 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "DCHPRI9,Channel 9 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "DCHPRI8,Channel 8 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "DCHPRI15,Channel 15 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "DCHPRI14,Channel 14 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "DCHPRI13,Channel 13 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "DCHPRI12,Channel 12 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
width 23.
|
|
sif !cpuis("MKE14Z*")&&!cpuis("MKE15Z*")
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1000+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID0,Channel 0 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x1000+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1000+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1000+0x0C)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x1000+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1000+0x16))&0x8000)==0x8000)
|
|
group.word (0x1000+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1000+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1000+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1000+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1000+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1000+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1000+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1020+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID1,Channel 1 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x1020+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1020+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1020+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1020+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1020+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1020+0x0C)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x1020+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1020+0x16))&0x8000)==0x8000)
|
|
group.word (0x1020+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1020+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1020+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1020+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1020+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1020+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1020+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1040+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID2,Channel 2 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x1040+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1040+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1040+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1040+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1040+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1040+0x0C)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x1040+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1040+0x16))&0x8000)==0x8000)
|
|
group.word (0x1040+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1040+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1040+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1040+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1040+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1040+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1040+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1060+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID3,Channel 3 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x1060+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1060+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1060+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1060+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1060+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1060+0x0C)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x1060+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1060+0x16))&0x8000)==0x8000)
|
|
group.word (0x1060+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1060+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1060+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1060+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1060+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1060+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1060+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1080+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID4,Channel 4 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
group.word (0x1080+0x04)++0x03
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1080+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1080+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1080+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1080+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1080+0x0C)++0x07
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD4_DADDR,TCD Destination Address"
|
|
group.word (0x1080+0x14)++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1080+0x16))&0x8000)==0x8000)
|
|
group.word (0x1080+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1080+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1080+0x18)++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1080+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1080+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1080+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1080+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x10A0+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID5,Channel 5 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
group.word (0x10A0+0x04)++0x03
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x10A0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x10A0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x10A0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x10A0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x10A0+0x0C)++0x07
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD5_DADDR,TCD Destination Address"
|
|
group.word (0x10A0+0x14)++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x10A0+0x16))&0x8000)==0x8000)
|
|
group.word (0x10A0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x10A0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x10A0+0x18)++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x10A0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x10A0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x10A0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x10A0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x10C0+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID6,Channel 6 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
group.word (0x10C0+0x04)++0x03
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x10C0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x10C0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x10C0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x10C0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x10C0+0x0C)++0x07
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD6_DADDR,TCD Destination Address"
|
|
group.word (0x10C0+0x14)++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x10C0+0x16))&0x8000)==0x8000)
|
|
group.word (0x10C0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x10C0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x10C0+0x18)++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x10C0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x10C0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x10C0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x10C0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x10E0+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID7,Channel 7 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
group.word (0x10E0+0x04)++0x03
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x10E0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x10E0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x10E0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x10E0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x10E0+0x0C)++0x07
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD7_DADDR,TCD Destination Address"
|
|
group.word (0x10E0+0x14)++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x10E0+0x16))&0x8000)==0x8000)
|
|
group.word (0x10E0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x10E0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x10E0+0x18)++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x10E0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x10E0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x10E0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x10E0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1100+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID8,Channel 8 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
group.word (0x1100+0x04)++0x03
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1100+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1100+0x0C)++0x07
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD8_DADDR,TCD Destination Address"
|
|
group.word (0x1100+0x14)++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1100+0x16))&0x8000)==0x8000)
|
|
group.word (0x1100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1100+0x18)++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1100+0x1C)++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1100+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1120+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID9,Channel 9 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
group.word (0x1120+0x04)++0x03
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1120+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1120+0x0C)++0x07
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD9_DADDR,TCD Destination Address"
|
|
group.word (0x1120+0x14)++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1120+0x16))&0x8000)==0x8000)
|
|
group.word (0x1120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1120+0x18)++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1120+0x1C)++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1120+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1140+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID10,Channel 10 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
group.word (0x1140+0x04)++0x03
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1140+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1140+0x0C)++0x07
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD10_DADDR,TCD Destination Address"
|
|
group.word (0x1140+0x14)++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1140+0x16))&0x8000)==0x8000)
|
|
group.word (0x1140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1140+0x18)++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1140+0x1C)++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1140+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1160+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID11,Channel 11 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
group.word (0x1160+0x04)++0x03
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1160+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1160+0x0C)++0x07
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD11_DADDR,TCD Destination Address"
|
|
group.word (0x1160+0x14)++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1160+0x16))&0x8000)==0x8000)
|
|
group.word (0x1160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1160+0x18)++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1160+0x1C)++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1160+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x1180+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID12,Channel 12 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
group.word (0x1180+0x04)++0x03
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1180+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1180+0x0C)++0x07
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD12_DADDR,TCD Destination Address"
|
|
group.word (0x1180+0x14)++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1180+0x16))&0x8000)==0x8000)
|
|
group.word (0x1180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1180+0x18)++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1180+0x1C)++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1180+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x11A0+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID13,Channel 13 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
group.word (0x11A0+0x04)++0x03
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x11A0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x11A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x11A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x11A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x11A0+0x0C)++0x07
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD13_DADDR,TCD Destination Address"
|
|
group.word (0x11A0+0x14)++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x11A0+0x16))&0x8000)==0x8000)
|
|
group.word (0x11A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x11A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x11A0+0x18)++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x11A0+0x1C)++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x11A0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x11A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x11A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x11C0+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID14,Channel 14 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
group.word (0x11C0+0x04)++0x03
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x11C0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x11C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x11C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x11C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x11C0+0x0C)++0x07
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD14_DADDR,TCD Destination Address"
|
|
group.word (0x11C0+0x14)++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x11C0+0x16))&0x8000)==0x8000)
|
|
group.word (0x11C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x11C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x11C0+0x18)++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x11C0+0x1C)++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x11C0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x11C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x11C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
group.byte (0x11E0+0x0140)++0x00
|
|
line.byte 0x00 "DCHMID15,Channel 15 Master ID Register"
|
|
bitfld.byte 0x00 7. " EMI ,Enable Master ID replication" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " PAL ,Privileged access level" "User,Privileged"
|
|
rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
group.word (0x11E0+0x04)++0x03
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S32D248*")||cpuis("S32S*")
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte burst,?..."
|
|
else
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
endif
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x11E0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x11E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x11E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x11E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x11E0+0x0C)++0x07
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD15_DADDR,TCD Destination Address"
|
|
group.word (0x11E0+0x14)++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x11E0+0x16))&0x8000)==0x8000)
|
|
group.word (0x11E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x11E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x11E0+0x18)++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x11E0+0x1C)++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x11E0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x11E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x11E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x1000+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1000+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1000+0x0C)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x1000+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1000+0x16))&0x8000)==0x8000)
|
|
group.word (0x1000+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1000+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1000+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1000+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1000+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1000+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1000+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x1020+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1020+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1020+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1020+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1020+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1020+0x0C)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x1020+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1020+0x16))&0x8000)==0x8000)
|
|
group.word (0x1020+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1020+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1020+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1020+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1020+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1020+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1020+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x1040+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1040+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1040+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1040+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1040+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1040+0x0C)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x1040+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1040+0x16))&0x8000)==0x8000)
|
|
group.word (0x1040+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1040+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1040+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1040+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1040+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1040+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1040+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x1060+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1060+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1060+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1060+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1060+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1060+0x0C)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x1060+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1060+0x16))&0x8000)==0x8000)
|
|
group.word (0x1060+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1060+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1060+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1060+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1060+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1060+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1060+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
group.word (0x1080+0x04)++0x03
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x1080+0x08))&0xC0000000)==0x00)
|
|
group.long (0x1080+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x1080+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1080+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x1080+0x0C)++0x07
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD4_DADDR,TCD Destination Address"
|
|
group.word (0x1080+0x14)++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x1080+0x16))&0x8000)==0x8000)
|
|
group.word (0x1080+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1080+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1080+0x18)++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x1080+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x1080+0x1E))&0x8000)==0x8000)
|
|
group.word (0x1080+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1080+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
group.word (0x10A0+0x04)++0x03
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x10A0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x10A0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x10A0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x10A0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x10A0+0x0C)++0x07
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD5_DADDR,TCD Destination Address"
|
|
group.word (0x10A0+0x14)++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x10A0+0x16))&0x8000)==0x8000)
|
|
group.word (0x10A0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x10A0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x10A0+0x18)++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x10A0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x10A0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x10A0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x10A0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
group.word (0x10C0+0x04)++0x03
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x10C0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x10C0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x10C0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x10C0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x10C0+0x0C)++0x07
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD6_DADDR,TCD Destination Address"
|
|
group.word (0x10C0+0x14)++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x10C0+0x16))&0x8000)==0x8000)
|
|
group.word (0x10C0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x10C0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x10C0+0x18)++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x10C0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x10C0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x10C0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x10C0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
group.word (0x10E0+0x04)++0x03
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte burst,32-byte burst,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40008000+0x10E0+0x08))&0xC0000000)==0x00)
|
|
group.long (0x10E0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif (((per.l(ad:0x40008000))&0x80)==0x80)
|
|
group.long (0x10E0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 1. " MLOFF ,Minor loop offset"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x10E0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count"
|
|
endif
|
|
group.long (0x10E0+0x0C)++0x07
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD7_DADDR,TCD Destination Address"
|
|
group.word (0x10E0+0x14)++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.w(ad:0x40008000+0x10E0+0x16))&0x8000)==0x8000)
|
|
group.word (0x10E0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x10E0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x10E0+0x18)++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x10E0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "None,,4 cycles,8 cycles"
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not done,Done"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Inactive,Active"
|
|
newline
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Normal,Scatter gather"
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.w(ad:0x40008000+0x10E0+0x1E))&0x8000)==0x8000)
|
|
group.word (0x10E0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x10E0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count"
|
|
bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAMUX (Direct Memory Access Multiplexer)"
|
|
base ad:0x40021000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
width 9.
|
|
if ((per.b(ad:0x40021000+0x0)&0x80)==0x00)
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x1)&0x80)==0x00)
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x2)&0x80)==0x00)
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x3)&0x80)==0x00)
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x4)&0x80)==0x00)
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG4,Channel 4 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG4,Channel 4 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x5)&0x80)==0x00)
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG5,Channel 5 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG5,Channel 5 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x6)&0x80)==0x00)
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG6,Channel 6 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG6,Channel 6 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x7)&0x80)==0x00)
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG7,Channel 7 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG7,Channel 7 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 9.
|
|
if ((per.b(ad:0x40021000+0x0)&0x80)==0x00)
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x1)&0x80)==0x00)
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x2)&0x80)==0x00)
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x3)&0x80)==0x00)
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x4)&0x80)==0x00)
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG4,Channel 4 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG4,Channel 4 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x5)&0x80)==0x00)
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG5,Channel 5 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG5,Channel 5 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x6)&0x80)==0x00)
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG6,Channel 6 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG6,Channel 6 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x7)&0x80)==0x00)
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG7,Channel 7 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG7,Channel 7 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x8)&0x80)==0x00)
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "CHCFG8,Channel 8 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "CHCFG8,Channel 8 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0x9)&0x80)==0x00)
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "CHCFG9,Channel 9 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "CHCFG9,Channel 9 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0xA)&0x80)==0x00)
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "CHCFG10,Channel 10 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "CHCFG10,Channel 10 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0xB)&0x80)==0x00)
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "CHCFG11,Channel 11 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "CHCFG11,Channel 11 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0xC)&0x80)==0x00)
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "CHCFG12,Channel 12 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "CHCFG12,Channel 12 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0xD)&0x80)==0x00)
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "CHCFG13,Channel 13 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "CHCFG13,Channel 13 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0xE)&0x80)==0x00)
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "CHCFG14,Channel 14 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "CHCFG14,Channel 14 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.b(ad:0x40021000+0xF)&0x80)==0x00)
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "CHCFG15,Channel 15 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,TSI,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive,LPI2C1_Transmit,,,,,,,ADC0,ADC1,,CMP0,CMP1,,PDB0,,,Port A,Port B,Port C,Port D,Port E,,,,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "Disabled,,LPUART0_Receive,LPUART0_Transmit,LPUART1_Receive,LPUART1_Transmit,LPUART2_Receive,LPUART2_Transmit,,,FlexIO_Shifter0,FlexIO_Shifter1,FlexIO_Shifter2,FlexIO_Shifter3,LPSPI0_Receive,LPSPI0_Transmit,LPSPI1_Receive,LPSPI1_Transmit,LPI2C0_Receive,LPI2C0_Transmit,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,LPI2C1_Receive/FTM3_CH0,LPI2C1_Transmit/FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,ADC0,ADC1,ADC2,CMP0,CMP1,CMP2,PDB0,PDB1,PDB2,Port A,Port B,Port C,Port D,Port E,FlexCAN0,FlexCAN1,DAC0,FTM1_OR,FTM2_OR,LPTMR0,DMAMUX,DMAMUX,DMAMUX,DMAMUX"
|
|
endif
|
|
else
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "CHCFG15,Channel 15 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA Channel Trigger Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x40052000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
width 7.
|
|
sif cpuis("S32MTV")
|
|
if (((per.l(ad:0x40052000))&0x800)==0x800)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control And Status Register"
|
|
bitfld.long 0x00 15. " WIN ,Watchdog window" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " CMD32EN ,Watchdog support for 32-bit refresh/unlock command write words" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRES ,Watchdog prescaler" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked"
|
|
rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "Not successful,Successful"
|
|
bitfld.long 0x00 8.--9. " CLK ,Watchdog clock" "Bus clock,LPO clock,Internal clock,External reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN ,Watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3.--4. " TST ,Watchdog test" "Disabled,User mode,Test mode (Low byte),Test mode (High byte)"
|
|
bitfld.long 0x00 2. " DBG ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WAIT ,Wait enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STOP ,Stop enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control And Status Register"
|
|
bitfld.long 0x00 15. " WIN ,Watchdog window" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 13. " CMD32EN ,Watchdog support for 32-bit refresh/unlock command write words" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRES ,Watchdog prescaler" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked"
|
|
rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "Not successful,Successful"
|
|
bitfld.long 0x00 8.--9. " CLK ,Watchdog clock" "Bus clock,LPO clock,Internal clock,External reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN ,Watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3.--4. " TST ,Watchdog test" "Disabled,User mode,Test mode (Low byte),Test mode (High byte)"
|
|
bitfld.long 0x00 2. " DBG ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WAIT ,Wait enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STOP ,Stop enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control And Status Register"
|
|
bitfld.long 0x00 15. " WIN ,Watchdog window" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " CMD32EN ,Watchdog support for 32-bit refresh/unlock command write words" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRES ,Watchdog prescaler" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked"
|
|
rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "Not successful,Successful"
|
|
bitfld.long 0x00 8.--9. " CLK ,Watchdog clock" "Bus clock,LPO clock,System oscillator clock,Slow internal reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN ,Watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3.--4. " TST ,Watchdog test" "Disabled,User mode,Test mode (Low byte),Test mode (High byte)"
|
|
bitfld.long 0x00 2. " DBG ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WAIT ,Wait enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STOP ,Stop enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TOVALHIGH ,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TOVALLOW ,Low byte of the timeout value"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("S32MTV"))
|
|
if (((per.l(ad:0x40052000+0x00))&0x08000)==0x08000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WINHIGH ,High byte of watchdog window"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WINLOW ,Low byte of watchdog window"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WINHIGH ,High byte of watchdog window"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WINLOW ,Low byte of watchdog window"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "WDOG_CS1,Watchdog Control and Status Register 1"
|
|
bitfld.byte 0x00 7. " EN ,Watchdog Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " INT ,Watchdog Interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " TST ,Watchdog Test" "Disabled,User mode,Test (WDOG_CNTL),Test (WDOG_CNTH)"
|
|
bitfld.byte 0x00 2. " DBG ,Debug Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " WAIT ,Wait Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " STOP ,Stop Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "WDOG_CS2,Watchdog Control and Status Register 2"
|
|
bitfld.byte 0x01 7. " WIN ,Watchdog Window" "Disabled,Enabled"
|
|
eventfld.byte 0x01 6. " FLG ,Watchdog Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " PRES ,Watchdog Prescaler (256)" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " CLK ,Watchdog Clock" "BUSclk,LPOCLK,ICSIRCLK,External"
|
|
rgroup.byte 0x02++0x01
|
|
line.byte 0x00 "WDOG_CNTH,Watchdog Counter Register: High"
|
|
line.byte 0x01 "WDOG_CNTL,Watchdog Counter Register: Low"
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "WDOG_TOVALH,Watchdog Timeout Value Register: High"
|
|
line.byte 0x01 "WDOG_TOVALL,Watchdog Timeout Value Register: Low"
|
|
if ((per.b(ad:0x40052000+0x01)&0x80)==0x80)
|
|
group.byte 0x06++0x01
|
|
line.byte 0x00 "WDOG_WINH,Watchdog Window Register: High"
|
|
line.byte 0x01 "WDOG_WINL,Watchdog Window Register: Low"
|
|
else
|
|
hgroup.byte 0x06++0x01
|
|
hide.byte 0x00 "WDOG_WINH,Watchdog Window Register: High"
|
|
hide.byte 0x01 "WDOG_WINL,Watchdog Window Register: Low"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "EWM (External Watchdog Monitor)"
|
|
base ad:0x40061000
|
|
width 14.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CTRL,Control Register"
|
|
bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " INEN ,Input enable" "Disable,Enable"
|
|
bitfld.byte 0x00 1. " ASSIN ,EWM_IN's assertion state select" "0,1"
|
|
bitfld.byte 0x00 0. " EWMEN ,EWM enable" "Disable,Enable"
|
|
wgroup.byte 0x01++0x00
|
|
line.byte 0x00 "SERV,Service Register"
|
|
group.byte 0x02++0x01
|
|
line.byte 0x00 "CMPL,Compare Low Register"
|
|
line.byte 0x01 "CMPH,Compare High Register"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "System Security"
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40032000
|
|
width 11.
|
|
if ((per.l(ad:0x40032000+0x08)&0x01000000)==0x01000000)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CRC_DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC High Upper Byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC High Lower Byte"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC Low Lower Byte"
|
|
line.long 0x04 "CRC_GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HIGH ,High Polynominal Half-word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOW ,Low Polynominal Half-word"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CRC_DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC Low Lower Byte"
|
|
line.long 0x04 "CRC_GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOW ,Low Polynominal Half-word"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_CTRL,CRC Control register"
|
|
bitfld.long 0x00 30.--31. " TOT ,Type Of Transpose For Writes" "No transposition,Only Bits,Bits and Bytes,Only Bytes"
|
|
bitfld.long 0x00 28.--29. " TOTR ,Type Of Transpose For Read" "No transposition,Only Bits,Bits and Bytes,Only Bytes"
|
|
bitfld.long 0x00 26. " FXOR ,Complement Read Of CRC Data Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WAS ,Write CRC Data Register As Seed" "Data,Seed"
|
|
bitfld.long 0x00 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "LMEM (Local Memory Controller)"
|
|
base ad:0xE0082000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCCCR,Cache Control Register"
|
|
bitfld.long 0x00 31. " GO ,Initiate Cache Command" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PUSHW1 ,Push Way 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INVW1 ,Invalidate Way 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PUSHW0 ,Push Way 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INVW0 ,Invalidate Way 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PCCR3 ,Force no allocation on cache misses" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCCR2 ,Force all cacheable spaces to write trough" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENWRBUF ,Enable Write Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled"
|
|
if (per.l(ad:0xE0082000+0x04)&0x110000)==0x110000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCLCR,Cache Line Control Register"
|
|
bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write"
|
|
bitfld.long 0x00 26. " LADSEL ,Line Address Select" "Cache,Physical"
|
|
bitfld.long 0x00 24.--25. " LCMD ,Line Command" "Search and read/write,Invalidate,Push,Clear"
|
|
rbitfld.long 0x00 22. " LCWAY ,Line Command Way" "Way 0,Way 1"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " LCIMB ,Line Command Initial Modified Bit" "0,1"
|
|
rbitfld.long 0x00 20. " LCIVB ,Line Command Initial Valid Bit" "0,1"
|
|
bitfld.long 0x00 16. " TDSEL ,Tag/Data Select" "Data,Tag"
|
|
bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 0x10 " CACHEADDR ,Tag array cache address"
|
|
bitfld.long 0x00 0. " LGO ,Initiate Cache Line Command" "Not active,Active"
|
|
elif (per.l(ad:0xE0082000+0x04)&0x110000)==0x010000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCLCR,Cache Line Control Register"
|
|
bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write"
|
|
bitfld.long 0x00 26. " LADSEL ,Line Address Select" "Cache,Physical"
|
|
bitfld.long 0x00 24.--25. " LCMD ,Line Command" "Search and read/write,Invalidate,Push,Clear"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " LCIMB ,Line Command Initial Modified Bit" "0,1"
|
|
rbitfld.long 0x00 20. " LCIVB ,Line Command Initial Valid Bit" "0,1"
|
|
bitfld.long 0x00 16. " TDSEL ,Tag/Data Select" "Data,Tag"
|
|
bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 0x10 " CACHEADDR ,Tag array cache address"
|
|
bitfld.long 0x00 0. " LGO ,Initiate Cache Line Command" "Not active,Active"
|
|
elif (per.l(ad:0xE0082000+0x04)&0x110000)==0x100000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCLCR,Cache Line Control Register"
|
|
bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write"
|
|
bitfld.long 0x00 26. " LADSEL ,Line Address Select" "Cache,Physical"
|
|
bitfld.long 0x00 24.--25. " LCMD ,Line Command" "Search and read/write,Invalidate,Push,Clear"
|
|
rbitfld.long 0x00 22. " LCWAY ,Line Command Way" "Way 0,Way 1"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " LCIMB ,Line Command Initial Modified Bit" "0,1"
|
|
rbitfld.long 0x00 20. " LCIVB ,Line Command Initial Valid Bit" "0,1"
|
|
bitfld.long 0x00 16. " TDSEL ,Tag/Data Select" "Data,Tag"
|
|
bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--11. 0x4 " CACHEADDR ,Tag array cache address"
|
|
bitfld.long 0x00 0. " LGO ,Initiate Cache Line Command" "Not active,Active"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCLCR,Cache Line Control Register"
|
|
bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write"
|
|
bitfld.long 0x00 26. " LADSEL ,Line Address Select" "Cache,Physical"
|
|
bitfld.long 0x00 24.--25. " LCMD ,Line Command" "Search and read/write,Invalidate,Push,Clear"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " LCIMB ,Line Command Initial Modified Bit" "0,1"
|
|
rbitfld.long 0x00 20. " LCIVB ,Line Command Initial Valid Bit" "0,1"
|
|
bitfld.long 0x00 16. " TDSEL ,Tag/Data Select" "Data,Tag"
|
|
bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--11. 0x4 " CACHEADDR ,Tag array cache address"
|
|
bitfld.long 0x00 0. " LGO ,Initiate Cache Line Command" "Not active,Active"
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PCCSAR,Cache Search Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " PHYADDR ,Physical Address"
|
|
bitfld.long 0x00 0. " LGO ,Initiate Cache Line Command" "0,1"
|
|
line.long 0x04 "PCCCVR,Cache Read/write Value Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCCRMR,Cache regions mode register"
|
|
bitfld.long 0x00 30.--31. " R0 ,Region 0 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back"
|
|
bitfld.long 0x00 26.--27. " R2 ,Region 2 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back"
|
|
bitfld.long 0x00 24.--25. " R3 ,Region 3 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " R4 ,Region 4 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back"
|
|
bitfld.long 0x00 20.--21. " R5 ,Region 5 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSCM (Flash Memory Module)"
|
|
base ad:0x40010000
|
|
width 11.
|
|
rgroup.long 0x00++0x3F
|
|
line.long 0x00 "CPXTYPE,Processor X Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PERSONALITY ,Processor x personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RYPZ ,Processor x revision"
|
|
line.long 0x04 "CPXNUM,Processor X Number Register"
|
|
bitfld.long 0x04 0. " CPN ,Processor x number" "0,1"
|
|
line.long 0x08 "CPXMASTER,Processor X Master Register"
|
|
bitfld.long 0x08 0.--5. " PPN ,Processor x physical port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CPXCOUNT,Processor X Count Register"
|
|
bitfld.long 0x0C 0.--1. " PCNT ,Processor x count" "Single core,1,2,3"
|
|
line.long 0x10 "CPXCFG0,Processor X Configuration Register 0"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
hexmask.long.byte 0x10 16.--23. 1. " ICWY ,Level 1 instruction cache ways"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DCSZ ,Level 1 data cache size"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCWY ,Level 1 data cache ways"
|
|
endif
|
|
line.long 0x14 "CPXCFG1,Processor X Configuration Register 1"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
hexmask.long.byte 0x14 24.--31. 1. " L2SZ ,Level 2 instruction cache size"
|
|
hexmask.long.byte 0x14 16.--23. 1. " L2WY ,Level 2 instruction cache ways"
|
|
else
|
|
hexmask.long.byte 0x14 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
endif
|
|
line.long 0x18 "CPXCFG2,Processor X Configuration Register 2"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
hexmask.long.byte 0x18 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size"
|
|
hexmask.long.byte 0x18 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size"
|
|
else
|
|
hexmask.long.byte 0x18 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
endif
|
|
line.long 0x1C "CPXCFG3,Processor X Configuration Register 3"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
bitfld.long 0x1C 8.--9. " SBP ,System bus ports" "0,1,2,3"
|
|
bitfld.long 0x1C 6. " BB ,Bit banding" "Not supported,Supported"
|
|
bitfld.long 0x1C 5. " CMP ,Core memory protection unit" "Not included,Included"
|
|
bitfld.long 0x1C 4. " TZ ,Trust zone" "Not included,Included"
|
|
newline
|
|
bitfld.long 0x1C 3. " MMU ,Memory management unit" "Not included,Included"
|
|
bitfld.long 0x1C 2. " JAZ ,Jazelle support" "Not included,Included"
|
|
bitfld.long 0x1C 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included"
|
|
bitfld.long 0x1C 0. " FPU ,Floating point unit" "Not included,Included"
|
|
else
|
|
hexmask.long.byte 0x1C 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
endif
|
|
line.long 0x20 "CP0TYPE,Processor 0 Type Register"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. " PERSONALITY ,Processor 0 personality"
|
|
hexmask.long.byte 0x20 0.--7. 1. " RYPZ ,Processor 0 revision"
|
|
line.long 0x24 "CP0NUM,Processor 0 Number Register"
|
|
bitfld.long 0x24 0. " CPN ,Processor 0 number" "0,1"
|
|
line.long 0x28 "CP0MASTER,Processor 0 Master Register"
|
|
bitfld.long 0x28 0.--5. " PPMN ,Processor 0 physical master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x2C "CP0COUNT,Processor 0 Count Register"
|
|
bitfld.long 0x2C 0.--1. " PCNT ,Processor count" "Single core,1,2,3"
|
|
line.long 0x30 "CP0CFG0,Processor 0 Configuration Register 0"
|
|
hexmask.long.byte 0x30 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
hexmask.long.byte 0x30 16.--23. 1. " ICWY ,Level 1 instruction cache ways"
|
|
hexmask.long.byte 0x30 8.--15. 1. " DCSZ ,Level 1 data cache size"
|
|
hexmask.long.byte 0x30 0.--7. 1. " DCWY ,Level 1 data cache ways"
|
|
endif
|
|
line.long 0x34 "CP0CFG1,Processor 0 Configuration Register 1"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
hexmask.long.byte 0x34 24.--31. 1. " L2SZ ,Level 2 instruction cache size"
|
|
hexmask.long.byte 0x34 16.--23. 1. " L2WY ,Level 2 instruction cache ways"
|
|
else
|
|
hexmask.long.byte 0x34 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
endif
|
|
line.long 0x38 "CP0CFG2,Processor 0 Configuration Register 2"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
hexmask.long.byte 0x38 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size"
|
|
hexmask.long.byte 0x38 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size"
|
|
else
|
|
hexmask.long.byte 0x38 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
endif
|
|
line.long 0x3C "CP0CFG3,Processor 0 Configuration Register 3"
|
|
sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")
|
|
bitfld.long 0x3C 8.--9. " SBP ,System bus ports" "0,1,2,3"
|
|
bitfld.long 0x3C 6. " BB ,Bit banding" "Not supported,Supported"
|
|
bitfld.long 0x3C 5. " CMP ,Core memory protection unit" "Not included,Included"
|
|
bitfld.long 0x3C 4. " TZ ,Trust zone" "Not included,Included"
|
|
newline
|
|
bitfld.long 0x3C 3. " MMU ,Memory management unit" "Not included,Included"
|
|
bitfld.long 0x3C 2. " JAZ ,Jazelle support" "Not included,Included"
|
|
bitfld.long 0x3C 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included"
|
|
bitfld.long 0x3C 0. " FPU ,Floating point unit" "Not included,Included"
|
|
else
|
|
hexmask.long.byte 0x3C 24.--31. 1. " ICSZ ,Level 1 instruction cache size"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40010000+0x400))&0x10000)==0x10000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..."
|
|
rbitfld.long 0x00 5. " OCMCDR0[5] ,Flash speculate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " OCMCDR0[4] ,Data prefetch enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
newline
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..."
|
|
bitfld.long 0x00 5. " OCMCDR0[5] ,Flash speculate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OCMCDR0[4] ,Data prefetch enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x404))&0x10000)==0x10000)
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..."
|
|
rbitfld.long 0x00 5. " OCMCDR1[5] ,Flash speculate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " OCMCDR1[4] ,Data prefetch enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
newline
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..."
|
|
bitfld.long 0x00 5. " OCMCDR1[5] ,Flash speculate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OCMCDR1[4] ,Data prefetch enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x408))&0x10000)==0x10000)
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..."
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
newline
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x400))&0x10000)==0x10000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x404))&0x10000)==0x10000)
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x408))&0x10000)==0x10000)
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x40C))&0x10000)==0x10000)
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "OCMDR3,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "OCMDR3,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present"
|
|
rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..."
|
|
bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..."
|
|
newline
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
tree "MTB (Micro Trace Buffer)"
|
|
tree "RAM (System RAM Controller)"
|
|
base ad:0xF0000000
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "MTB_POSITION,MTB Position Register"
|
|
hexmask.long 0x00 3.--31. 0x08 " POINTER ,Trace packet address pointer"
|
|
bitfld.long 0x00 2. " WRAP ,Pointer value wraps" "Low,High"
|
|
line.long 0x04 "MTB_MASTER,MTB Master Register"
|
|
bitfld.long 0x04 31. " EN ,Main trace enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " HALTREQ ,Halt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " RAMPRIV ,RAM privilege bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " SFRWPRIV ,Special function register write privilege bit" "Low,High"
|
|
bitfld.long 0x04 6. " TSTOPEN ,Trace stop input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " TSTARTEN ,Trace start input enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0.--4. " MASK ,Maximum size of the trace buffer in RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "MTB_FLOW,MTB Flow Register"
|
|
hexmask.long 0x08 3.--31. 0x08 " WATERMARK ,Watermark value"
|
|
bitfld.long 0x08 1. " AUTOHALT ,Autohalt" "Not halted,Halted"
|
|
bitfld.long 0x08 0. " AUTOSTOP ,Autostop" "Not stopped,Stopped"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "MTB_BASE,MTB Base Register"
|
|
rgroup.long 0xF00++0x03
|
|
line.long 0x00 "MTB_MODECTRL,Integration Mode Control Register"
|
|
rgroup.long 0xFA0++0x07
|
|
line.long 0x00 "MTB_TAGSET,Claim TAG Set Register"
|
|
line.long 0x04 "MTB_TAGCLEAR,Claim TAG Clear Register"
|
|
rgroup.long 0xFB0++0x0F
|
|
line.long 0x00 "MTB_LOCKACCESS,Lock Access Register"
|
|
line.long 0x04 "MTB_LOCKSTAT,Lock Status Register"
|
|
line.long 0x08 "MTB_AUTHSTAT,Authentication Status Register"
|
|
bitfld.long 0x08 2. " BIT2 ,It's hardwired to NIDEN or DBGEN signal" "Low,High"
|
|
bitfld.long 0x08 0. " BIT0 ,It's hardwired to DBGEN" "Low,High"
|
|
line.long 0x0C "MTB_DEVICEARCH,Device Architecture Register"
|
|
rgroup.long 0xFC8++0x07
|
|
line.long 0x00 "MTB_DEVICECFG,Device Configuration Register"
|
|
line.long 0x04 "MTB_DEVICETYPID,Device Type Identifier Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "MTB_PERIPHID4,Peripheral ID Register 4"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "MTB_PERIPHID5,Peripheral ID Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "MTB_PERIPHID6,Peripheral ID Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "MTB_PERIPHID7,Peripheral ID Register 7"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "MTB_PERIPHID0,Peripheral ID Register 0"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "MTB_PERIPHID1,Peripheral ID Register 1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "MTB_PERIPHID2,Peripheral ID Register 2"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "MTB_PERIPHID3,Peripheral ID Register 3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "MTB_COMPID0,Component ID Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "MTB_COMPID1,Component ID Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "MTB_COMPID2,Component ID Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "MTB_COMPID3,Component ID Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DWT (Data Watchpoint Trace)"
|
|
base ad:0xF0001000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MTBDWT_CTRL,MTB DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCMP ,Number of comparators" "0,1,?..."
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Trace sample and exception trace" "Supported,Not supported"
|
|
bitfld.long 0x00 26. " NOEXTTRIG ,External match signals" "Supported,Not supported"
|
|
newline
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Cycle counter" "Supported,Not supported"
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEBTENA ,POSTCNT underflow packets" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Folded instruction counter overflow events" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,LSU counter overflow events" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Sleep counter overflow events" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Exception overhead counter events" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,CPI counter overflow events" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Periodic PC sample packets" "Not generated,Generated"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Synchronization packets" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CYCTAP ,Cycle counter" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Cycle counter" "Not supported,Supported"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "MTBDWT_COMP0,MTB_DWT Comparator Register 0"
|
|
line.long 0x04 "MTBDWT_MASK0,MTB_DWT Comparator Mask Register 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "MTBDWT_FCT0,MTB_DWT Comparator Function Register 0"
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")
|
|
rbitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred"
|
|
else
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred"
|
|
endif
|
|
bitfld.long 0x08 12.--15. " DATAVADDR0 ,Data value address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 10.--11. " DATAVSIZE ,Data value size" "Byte,Halfword,Word,?..."
|
|
bitfld.long 0x08 8. " DATAVMATCH ,Data value match" "Address comparison,Data value comparison"
|
|
newline
|
|
bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,Read + write,?..."
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "MTBDWT_COMP1,MTB_DWT Comparator Register 1"
|
|
line.long 0x04 "MTBDWT_MASK1,MTB_DWT Comparator Mask Register 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "MTBDWT_FCT1,MTB_DWT Comparator Function Register 1"
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")
|
|
rbitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred"
|
|
else
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred"
|
|
endif
|
|
bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,Read + write,?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MTBDWT_TBCTRL,MTB_DWT Trace Buffer Control Register"
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" "0,1,?..."
|
|
else
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" "0,1,?..."
|
|
endif
|
|
bitfld.long 0x00 1. " ACOMP1 ,Action based on comparator 1 match" "Trigger TSTOP,Trigger TSTART"
|
|
newline
|
|
bitfld.long 0x00 0. " ACOMP0 ,Action based on comparator 0 match" "Trigger TSTOP,Trigger TSTART"
|
|
rgroup.long 0xFC8++0x07
|
|
line.long 0x00 "MTBDWT_DEVICECFG,Device Configuration Register"
|
|
line.long 0x04 "MTBDWT_DEVICETYPID,Device Type Identifier Register"
|
|
rgroup.long (0xFD0+0x0)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID4,Peripheral ID Register 4"
|
|
rgroup.long (0xFD0+0x4)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID5,Peripheral ID Register 5"
|
|
rgroup.long (0xFD0+0x8)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID6,Peripheral ID Register 6"
|
|
rgroup.long (0xFD0+0xC)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID7,Peripheral ID Register 7"
|
|
rgroup.long (0xFD0+0x10)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID0,Peripheral ID Register 0"
|
|
rgroup.long (0xFD0+0x14)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID1,Peripheral ID Register 1"
|
|
rgroup.long (0xFD0+0x18)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID2,Peripheral ID Register 2"
|
|
rgroup.long (0xFD0+0x1C)++0x03
|
|
line.long 0x00 "MTBDWT_PERIPHID3,Peripheral ID Register 3"
|
|
rgroup.long (0xFF0+0x0)++0x03
|
|
line.long 0x00 "MTBDWT_COMPID0,Component ID Register 0"
|
|
rgroup.long (0xFF0+0x4)++0x03
|
|
line.long 0x00 "MTBDWT_COMPID1,Component ID Register 1"
|
|
rgroup.long (0xFF0+0x8)++0x03
|
|
line.long 0x00 "MTBDWT_COMPID2,Component ID Register 2"
|
|
rgroup.long (0xFF0+0xC)++0x03
|
|
line.long 0x00 "MTBDWT_COMPID3,Component ID Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ROM (System ROM)"
|
|
base ad:0xF0002000
|
|
width 15.
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "ROM_ENTRY0,Entry Register 0"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "ROM_ENTRY1,Entry Register 1"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "ROM_ENTRY2,Entry Register 2"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ROM_TABLEMARK,End of Table Marker Register"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "ROM_SYSACCESS,System Access Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "ROM_PERIPHID4,Peripheral ID Register 4"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "ROM_PERIPHID5,Peripheral ID Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "ROM_PERIPHID6,Peripheral ID Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "ROM_PERIPHID7,Peripheral ID Register 7"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "ROM_PERIPHID0,Peripheral ID Register 0"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "ROM_PERIPHID1,Peripheral ID Register 1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "ROM_PERIPHID2,Peripheral ID Register 2"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "ROM_PERIPHID3,Peripheral ID Register 3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "ROM_COMPID0,Component ID Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "ROM_COMPID1,Component ID Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "ROM_COMPID2,Component ID Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ROM_COMPID3,Component ID Register 3"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R"))
|
|
tree "FTMRE (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "FCCOBIX,Flash CCOB Index Register"
|
|
bitfld.byte 0x00 0.--2. " CCOBIX ,Common Command Register Index" "0,1,2,3,4,5,6,7"
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor Key Security Enable Bits" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash Security Bits" "Secured,Secured,Unsecured,Secured"
|
|
if (((per.b(ad:0x40020000+0x05))&0x80)==0x00)
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
bitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,20.6-21.6,21.6-22.6,22.6-23.6,23.6-24.6,24.6-25.6,?..."
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
rbitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,20.6-21.6,21.6-22.6,22.6-23.6,23.6-24.6,24.6-25.6,?..."
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. " CCIF ,Command Complete Interrupt Flag" "In progress,Completed"
|
|
eventfld.byte 0x00 5. " ACCERR ,Flash Access Error Flag" "No error,Error"
|
|
eventfld.byte 0x00 4. " FPVIOL ,Flash Protection Violation Flag" "No violation,Violation"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " MGBUSY ,Memory Controller Busy Flag" "Idle,Busy"
|
|
rbitfld.byte 0x00 0.--1. " MGSTAT ,Memory Controller Command Completion Status Flag" "No error,Non-correctable error,Any error,Non-correctable/Any"
|
|
group.byte 0x07++0x02
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. " CCIE ,Command Complete Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " ERSAREQ ,Debugger Mass Erase Request" "Not requested,Requested"
|
|
line.byte 0x01 "FCCOBLO,Flash Common Command Object Register: Low"
|
|
line.byte 0x02 "FCCOBHI,Flash Common Command Object Register: High"
|
|
if ((per.b(ad:0x40020000+0x0B)&0x24)==0x24)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "00,01,10,11"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "00,01,10,11"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x24)==0x20)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "00,01,10,11"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x24)==0x04)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "00,01,10,11"
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
endif
|
|
rgroup.byte 0x0F++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
width 0xB
|
|
tree.end
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "FTFE (Miscellaneous System Control Module)"
|
|
base ad:0x40020000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed"
|
|
eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error"
|
|
eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error"
|
|
line.byte 0x01 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased"
|
|
bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended"
|
|
sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW??Z*")
|
|
sif (cpuis("MKV5*"))
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready"
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready"
|
|
elif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
textline " "
|
|
rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block"
|
|
rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..."
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available"
|
|
elif cpuis("K32W0?2S1M*")
|
|
rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000"
|
|
rbitfld.byte 0x01 2. " CRCRDY ,CRC ready" "Not available,Available"
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
else
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..."
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available"
|
|
endif
|
|
endif
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")||cpuis("MKW*")||cpuis("MKV5*")
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "FCCOB3,Flash Common Command Object Registers"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "FCCOB2,Flash Common Command Object Registers"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "FCCOB1,Flash Common Command Object Registers"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "FCCOB0,Flash Common Command Object Registers"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "FCCOB7,Flash Common Command Object Registers"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "FCCOB6,Flash Common Command Object Registers"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "FCCOB5,Flash Common Command Object Registers"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "FCCOB4,Flash Common Command Object Registers"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "FCCOBB,Flash Common Command Object Registers"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "FCCOBA,Flash Common Command Object Registers"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "FCCOB9,Flash Common Command Object Registers"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "FCCOB8,Flash Common Command Object Registers"
|
|
sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW*")&&!cpuis("MKV5*")
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte (0x10+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x11+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x12+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x13+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5"))
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROT1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROT0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROTH3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTH2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTH1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTH0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
elif (cpuis("MKW*"))
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROT1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROT0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
else
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "FPROTH3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTH2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTH1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTH0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte 0x1C++0x03
|
|
line.byte 0x00 "FPROTL3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTL2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTL1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTL0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
endif
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte 0x24++0x01
|
|
line.byte 0x00 "FPROTSL,Secondary Program Flash Protection Registers"
|
|
line.byte 0x01 "FPROTSH,Secondary Program Flash Protection Registers"
|
|
endif
|
|
sif (cpu()!="MK63FN1M0VLQ12")&&(cpu()!="MK63FN1M0VMD12")&&(cpu()!="MKV40F64VLH15")&&(cpu()!="MKV40F128VLH15")&&(cpu()!="MKV40F128VLL15")&&(cpu()!="MKV40F256VLH15")&&(cpu()!="MKV40F256VLL15")&&(cpu()!="MKV43F64VLH15")&&(cpu()!="MKV43F128VLH15")&&(cpu()!="MKV43F128VLL15")&&(cpu()!="MKV44F64VLH15")&&(cpu()!="MKV44F128VLH15")&&(cpu()!="MKV44F128VLL15")&&(cpu()!="MKV45F128VLH15")&&(cpu()!="MKV45F128VLL15")&&(cpu()!="MKV45F256VLH15")&&(cpu()!="MKV45F256VLL15")&&(cpu()!="MKV46F128VLH15")&&(cpu()!="MKV46F128VLL15")&&(cpu()!="MKV46F256VLH15")&&(cpu()!="MKV46F256VLL15")&&cpuis("MKV31F*")&&cpuis("MKV30F*")&&(cpu()=="MK64FN1M0VLQ12")&&(cpu()!="MK64FN1M0VMD12")&&(cpu()!="MK64FN1M0VLL12")&&(cpu()!="MK64FN1M0VDC12")&&(cpu()!="MK65FN2M0CAF18")&&(cpu()!="MK65FN2M0VMF18")&&(cpu()!="MK66FN2M0VLQ18")&&(cpu()!="MK66FN2M0VMD18")&&(!cpuis("K32W0?2S1M*")&&(!cpuis("MKW*")))
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
elif (cpuis("MKW21D*"))
|
|
if (((per.l(ad:0x40020000))&0x80)==0x80)
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected"
|
|
else
|
|
rgroup.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected"
|
|
endif
|
|
elif ((cpuis("MKW22D*"))||(cpuis("MKW24D*")))
|
|
hgroup.byte 0x16++0x01
|
|
hide.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
hide.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
endif
|
|
textline " "
|
|
sif ((cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x18++0x0F
|
|
line.byte 0x00 "XACCH3,Execute-only Access Register 3"
|
|
bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x01 "XACCH2,Execute-only Access Register 2"
|
|
bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x02 "XACCH1,Execute-only Access Register 1"
|
|
bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x03 "XACCH0,Execute-only Access Register 0"
|
|
bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x04 "XACCL3,Execute-only Access Register 3"
|
|
bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x05 "XACCL2,Execute-only Access Register 2"
|
|
bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x06 "XACCL1,Execute-only Access Register 1"
|
|
bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x07 "XACCL0,Execute-only Access Register 0"
|
|
bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x08 "SACCH3,Supervisor-only Access Register 3"
|
|
bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x09 "SACCH2,Supervisor-only Access Register 2"
|
|
bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0A "SACCH1,Supervisor-only Access Register 1"
|
|
bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0B "SACCH0,Supervisor-only Access Register 0"
|
|
bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0C "SACCL3,Supervisor-only Access Register 3"
|
|
bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0D "SACCL2,Supervisor-only Access Register 2"
|
|
bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0E "SACCL1,Supervisor-only Access Register 1"
|
|
bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0F "SACCL0,Supervisor-only Access Register 0"
|
|
bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x28++0x03
|
|
line.byte 0x00 "XACCSH,Secondary Execute-only Access Registers"
|
|
bitfld.byte 0x00 7. " XA_S[15] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 6. " [14] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 5. " [13] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [12] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 3. " [11] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 2. " [10] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [9] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 0. " [8] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x01 "XACCSL,Secondary Execute-only Access Registers"
|
|
bitfld.byte 0x01 7. " XA_S[7] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 6. " [6] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 5. " [5] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 3. " [3] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 2. " [2] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 0. " [0] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x02 "SACCSH,Secondary Supervisor-only Access Registers"
|
|
bitfld.byte 0x02 7. " SA_S[15] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 6. " [14] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 5. " [13] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [12] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 3. " [11] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 2. " [10] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [9] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 0. " [8] ,Secondary supervisor-only access control" "Yes,No"
|
|
line.byte 0x03 "SACCSL,Secondary Supervisor-only Access Registers"
|
|
bitfld.byte 0x03 7. " SA_S[7] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 6. " [6] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 5. " [5] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [4] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 3. " [3] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 2. " [2] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [1] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 0. " [0] ,Secondary supervisor-only access control" "Yes,No"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW2?Z*")||cpuis("MKW3?Z*")||cpuis("MKW4?Z*"))
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
elif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "FACSSS,Secondary Flash Access Segment Size Register"
|
|
rgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "FACSNS,Secondary Flash Access Segment Number Register"
|
|
group.byte 0x52++0x01
|
|
line.byte 0x00 "FSTDBYCTL,Flash Standby Control Register"
|
|
bitfld.byte 0x00 0. " STDBYDIS ,Standy mode disable" "Enabled,Disabled"
|
|
group.byte 0x53++0x01
|
|
line.byte 0x00 "FSTDBY,Flash Standby Register"
|
|
bitfld.byte 0x00 2. " STDBY2 ,Standy mode for flash block 2" "Enabled,Disabled"
|
|
bitfld.byte 0x00 1. " STDBY1 ,Standy mode for flash block 1" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0. " STDBY0 ,Standy mode for flash block 0" "Enabled,Disabled"
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rgroup.byte 0x2E++0x01
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
bitfld.byte 0x00 1. " DFDIF ,Double bit fault detect interrupt flag" "Not detected,Detected"
|
|
line.byte 0x01 "FERCNFG,Flash Error Configuration Register"
|
|
bitfld.byte 0x01 5. " FDFD ,Force double bit fault detect" "Not forced,Forced"
|
|
bitfld.byte 0x01 1. " DFDIE ,Double bit fault detect interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "FTMRH (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
rbitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,?..."
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor Key Security Enable Bits" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash Security Bits" "Secured,Secured,Unsecured,Secured"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "FCCOBIX,Flash CCOB Index Register"
|
|
bitfld.byte 0x00 0.--2. " CCOBIX ,Common Command Register Index" "FCMD[7:0]+Global addr[23:16],Global addr[15:0],Data 0[15:0],Data 1[15:0],Data 2[15:0],Data 3[15:0],?..."
|
|
group.byte 0x04++0x02
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. " CCIE ,Command Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " IGNSF ,Ignore Single Bit Fault" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FDFD ,Force Double Bit Fault Detect" "DFDIF,DFDIF+interrupt"
|
|
bitfld.byte 0x00 0. " FSFD ,Force Single Bit Fault Detect" "SFDIF,SFDIF+interrupt"
|
|
line.byte 0x01 "FERCNFG,Flash Error Configuration Register"
|
|
bitfld.byte 0x01 1. " DFDIE ,Double Bit Fault Detect Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SFDIE ,Single Bit Fault Detect Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "FSTAT,Flash Status Register"
|
|
bitfld.byte 0x02 7. " CCIF ,Command Complete Interrupt Flag" "In progress,Completed"
|
|
bitfld.byte 0x02 5. " ACCERR ,Flash Access Error Flag" "No error,Error"
|
|
bitfld.byte 0x02 4. " FPVIOL ,Flash Protection Violation Flag" "No violation,Violation"
|
|
textline " "
|
|
rbitfld.byte 0x02 3. " MGBUSY ,Memory Controller Busy Flag" "Idle,Busy"
|
|
rbitfld.byte 0x02 0.--1. " MGSTAT ,Memory Controller Command Completion Status Flag" "No error,Non-correctable error,Any error,Non-correctable/Any"
|
|
if ((per.b(ad:0x40020000+0x04)&0x10)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
bitfld.byte 0x00 1. " DFDIF ,Double Bit Fault Detect Interrupt Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " SFDIF ,Single Bit Fault Detect Interrupt Flag" "Not detected,Detected"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
bitfld.byte 0x00 1. " DFDIF ,Double Bit Fault Detect Interrupt Flag" "Not detected,Detected"
|
|
endif
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z16VLD2")||cpuis("MKE02Z16VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z16VLC2R"))
|
|
if ((per.b(ad:0x40020000+0x08)&0x24)==0x24)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "00,01,10,11"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "00,01,10,11"
|
|
elif ((per.b(ad:0x40020000+0x08)&0x24)==0x20)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "00,01,10,11"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
elif ((per.b(ad:0x40020000+0x08)&0x24)==0x04)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "00,01,10,11"
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40020000+0x08)&0x04)==0x04))
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
group.byte 0x09++0x02
|
|
line.byte 0x00 "EEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " DPOPEN ,EEPROM Protection Control" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " DPS ,EEPROM Protection Size" "32 bytes,64 bytes,96 bytes,128 bytes,160 bytes,192 bytes,224 bytes,256 bytes"
|
|
line.byte 0x01 "FCCOBHI,Flash Common Command Object Register:High"
|
|
line.byte 0x02 "FCCOBLO,Flash Common Command Object Register:Low"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.open "Clock Modules"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "SCG (System Clock Generator)"
|
|
base ad:0x40064000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
width 12.
|
|
rgroup.long 0x0++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 31. " DIVPRES_[4] ,DIVCORE divider present" "Absent,Present"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 29. " [2] ,DIVEXT divider present" "Absent,Present"
|
|
bitfld.long 0x04 28. " [1] ,DIVBUS divider present" "Absent,Present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 27. " [0] ,DIVSLOW divider present" "Absent,Present"
|
|
textline " "
|
|
bitfld.long 0x04 6. " CLKPRES_[5] ,Low Power FLL clock present" "Absent,Present"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 5. " [4] ,RTC OSC clock present" "Absent,Present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Fast IRC clock present" "Absent,Present"
|
|
bitfld.long 0x04 2. " [2] ,Slow IRC clock present" "Absent,Present"
|
|
bitfld.long 0x04 1. " [1] ,System OSC clock present" "Absent,Present"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,RTC_OSC,LPFLL_CLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,LPFLL_CLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow Clock Divide Ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,?..."
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 24.--26. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,RTC_OSC,LPFLL_CLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,LPFLL_CLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
line.long 0x04 "VCCR,VLPR Clock Control Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,,RTC OSC,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HCCR,HSRUN Clock Control Register"
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,RTC OSC,LPFLL_CLK,?..."
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG Clkout select" "SCG EXTERNAL Clock,System OSC,Slow IRC,Fast IRC,RTC OSC,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG Clkout select" "SCG SLOW Clock,System OSC,Slow IRC,Fast IRC,,LPFLL_CLK,?..."
|
|
endif
|
|
if (per.l(ad:0x40064000+0x100)&0x800000)==0x800000
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
rbitfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
rbitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
rbitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
eventfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
endif
|
|
if (per.l(ad:0x40064000+0x100)&0x1)==0x1
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
sif !cpuis("K32W0?2S1M*")
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz"
|
|
bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain"
|
|
bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal"
|
|
endif
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
sif !cpuis("K32W0?2S1M*")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz"
|
|
bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain"
|
|
bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40064000+0x200)&0x800000)==0x800000
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled"
|
|
endif
|
|
if (per.l(ad:0x40064000+0x200)&0x1)==0x1
|
|
rgroup.long 0x204++0x07
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " SIRCDIV3 ,Slow IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC Clock Divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SIRCCFG,Slow IRC Configuration Register"
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz"
|
|
else
|
|
group.long 0x204++0x07
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " SIRCDIV3 ,Slow IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SIRCCFG,Slow IRC Configuration Register"
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz"
|
|
endif
|
|
if (per.l(ad:0x40064000+0x300)&0x800000)==0x800000
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
rbitfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
rbitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
eventfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
endif
|
|
if (per.l(ad:0x40064000+0x300)&0x1)==0x1
|
|
rgroup.long 0x304++0x0B
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "FIRCCFG,Fast IRC Configuration Register"
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz"
|
|
line.long 0x08 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x08 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC OSC"
|
|
else
|
|
bitfld.long 0x08 0.--1. " TRIMSRC ,Trim source" ",,System OSC,?..."
|
|
endif
|
|
else
|
|
group.long 0x304++0x0B
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "FIRCCFG,Fast IRC Configuration Register"
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz"
|
|
line.long 0x08 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x08 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..."
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC OSC"
|
|
else
|
|
bitfld.long 0x08 0.--1. " TRIMSRC ,Trim source" ",,System OSC,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40064000+0x300)&0x100)==0x00
|
|
group.long 0x318++0x3
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status"
|
|
else
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status"
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")
|
|
if (per.l(ad:0x40064000+0x400)&0x800000)==0x800000
|
|
group.long 0x400++0x03
|
|
line.long 0x00 " ROSCCSR ,RTC OSC Control Status Register"
|
|
rbitfld.long 0x00 26. " ROSCERR ,RTC OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " ROSCSEL ,RTC OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " ROSCVLD ,RTC OSC valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Not locked,Locked"
|
|
rbitfld.long 0x00 17. " ROSCCMRE ,RTC OSC clock monitor reset enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " ROSCCM ,RTC OSC clock monitor" "Disabled,Enabled"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 " ROSCCSR ,RTC OSC Control Status Register"
|
|
eventfld.long 0x00 26. " ROSCERR ,RTC OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " ROSCSEL ,RTC OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " ROSCVLD ,RTC OSC valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " ROSCCMRE ,RTC OSC clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ROSCCM ,RTC OSC clock monitor" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40064000+0x500)&0x800000)==0x800000
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "LPFLLCSR,Low Power FLL Control Status Register"
|
|
rbitfld.long 0x00 26. " LPFLLERR ,LPFLL clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " LPFLLSEL ,LPFLL selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " LPFLLVLD ,LPFLL valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
rbitfld.long 0x00 17. " LPFLLCMRE ,LPFLL clock monitor reset Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " LPFLLCM ,LPFLL clock monitor" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " LPFLLTRMLOCK ,LPFLL trim LOCK" "Unlocked,Locked"
|
|
rbitfld.long 0x00 9. " LPFLLTRUP ,LPFLL trim update" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " LPFLLTREN ,LPFLL trim enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.long 0x00 1. " LPFLLSTEN ,LPFLL stop enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 0. " LPFLLEN ,LPFLL enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "LPFLLCSR,Low Power FLL Control Status Register"
|
|
eventfld.long 0x00 26. " LPFLLERR ,LPFLL clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " LPFLLSEL ,LPFLL selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " LPFLLVLD ,LPFLL valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 17. " LPFLLCMRE ,LPFLL clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LPFLLCM ,LPFLL clock monitor" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " LPFLLTRMLOCK ,LPFLL trim LOCK" "Unlocked,Locked"
|
|
bitfld.long 0x00 9. " LPFLLTRUP ,LPFLL trim update" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LPFLLTREN ,LPFLL trim enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 1. " LPFLLSTEN ,LPFLL stop enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " LPFLLEN ,LPFLL enable" "Disabled,Enabled"
|
|
endif
|
|
if (per.l(ad:0x40064000+0x500)&0x1)==0x1
|
|
rgroup.long 0x504++0x0B
|
|
line.long 0x00 "LPFLLDIV,Low Power FLL Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " LPFLLDIV3 ,LPFLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " LPFLLDIV2 ,LPFLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " LPFLLDIV1 ,LPFLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "LPFLLCFG,Low Power FLL Configuration Register"
|
|
bitfld.long 0x04 0.--1. " FSEL ,Frequency select" "48 MHz,72 MHz,?..."
|
|
line.long 0x08 "LPFLLTCFG,Low Power FLL Trim Configuration Register"
|
|
bitfld.long 0x08 16. " LOCKW2LSB ,Lock LPFLL with 2 LSBS" "1 LSB,2 LSB"
|
|
bitfld.long 0x08 8.--12. " TRIMDIV ,LPFLL trim predivide" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x08 0.--1. " TRIMSRC ,Trim source" "SIRC,FIRC,System OSC,RTC OSC"
|
|
else
|
|
group.long 0x504++0x0B
|
|
line.long 0x00 "LPFLLDIV,Low Power FLL Divide Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 16.--18. " LPFLLDIV3 ,LPFLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " LPFLLDIV2 ,LPFLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " LPFLLDIV1 ,LPFLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "LPFLLCFG,Low Power FLL Configuration Register"
|
|
bitfld.long 0x04 0.--1. " FSEL ,Frequency select" "48 MHz,72 MHz,?..."
|
|
line.long 0x08 "LPFLLTCFG,Low Power FLL Trim Configuration Register"
|
|
bitfld.long 0x08 16. " LOCKW2LSB ,Lock LPFLL with 2 LSBS" "1 LSB,2 LSB"
|
|
bitfld.long 0x08 8.--12. " TRIMDIV ,LPFLL trim predivide" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x08 0.--1. " TRIMSRC ,Trim Source" "SIRC,FIRC,System OSC,RTC OSC"
|
|
endif
|
|
if (per.l(ad:0x40064000+0x500)&0x100)==0x00
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTOTRIM ,Auto tune trim status"
|
|
else
|
|
rgroup.long 0x514++0x03
|
|
line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTOTRIM ,Auto tune trim status"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 12.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 31. " DIVPRES[31] ,DIVCORE divider present" "Absent,Present"
|
|
newline
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x04 30. " [30] ,DIVCORE divider present" "Absent,Present"
|
|
bitfld.long 0x04 29. " [29] ,DIVEXT divider present" "Absent,Present"
|
|
endif
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x04 28. " [28] ,DIVBUS divider present" "Absent,Present"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 27. " [27] ,DIVSLOW divider present" "Absent,Present"
|
|
newline
|
|
sif !cpuis("K32W*")
|
|
bitfld.long 0x04 6. " CLKPRES[6] ,System PLL clock present" "Absent,Present"
|
|
endif
|
|
newline
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x04 5. " [5] ,System PLL clock present" "Absent,Present"
|
|
bitfld.long 0x04 4. " [4] ,System PLL clock present" "Absent,Present"
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Fast IRC clock present" "Absent,Present"
|
|
bitfld.long 0x04 2. " [2] ,Slow IRC clock present" "Absent,Present"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,System OSC clock present" "Absent,Present"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
newline
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
line.long 0x04 "VCCR,VLPR Clock Control Register"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
elif cpuis("MKL28Z*")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
elif cpuis("S32MTV")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
elif (cpuis("K32W*"))
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,,ROSC_CLK,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
else
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 8.--11. " DIVEXT ,External Clock Divide Ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
sif (!cpuis("S32MTV"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HCCR,HSRUN Clock Control Register"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
elif (cpuis("K32W*"))
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG clkout select" "SCG_EXTERNAL_CLOCK,SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG clkout select" "SCG SLOW clock,System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x100))&0x800000)==0x800000)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
rbitfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))
|
|
newline
|
|
rbitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
elif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
eventfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))
|
|
newline
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
elif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x100))&0x01)==0x01)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
sif (!cpuis("K32W*"))
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 11. " SC2P ,Oscillator 2 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 10. " SC4P ,Oscillator 4 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 9. " SC8P ,Oscillator 8 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 8. " SC16P ,Oscillator 16 pF capacitor load" "0,1"
|
|
newline
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",,4 Mhz-8 Mhz,8 Mhz-40 Mhz"
|
|
else
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz"
|
|
endif
|
|
bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-gain,High-gain"
|
|
bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal"
|
|
endif
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
sif (!cpuis("K32W*"))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 11. " SC2P ,Oscillator 2 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 10. " SC4P ,Oscillator 4 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 9. " SC8P ,Oscillator 8 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 8. " SC16P ,Oscillator 16 pF capacitor load" "0,1"
|
|
newline
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",,4 Mhz-8 Mhz,8 Mhz-40 Mhz"
|
|
else
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz"
|
|
endif
|
|
bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-gain,High-gain"
|
|
bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x200))&0x800000)==0x800000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
rbitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x200))&0x01)==0x01)
|
|
rgroup.long 0x204++0x07
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SIRCCFG,Slow IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" ",8 MHz"
|
|
else
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz"
|
|
endif
|
|
else
|
|
group.long 0x204++0x07
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SIRCCFG,Slow IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" ",8 MHz"
|
|
else
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x300))&0x800000)==0x800000)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
rbitfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
sif (!cpuis("S32MTV"))
|
|
rbitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled"
|
|
endif
|
|
rbitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
eventfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
sif (!cpuis("S32MTV"))
|
|
bitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x300))&0x01)==0x01)
|
|
rgroup.long 0x304++0x07
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
sif cpuis("MKL28Z*")||cpuis("K32W*")
|
|
bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "FIRCCFG,Fast IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz"
|
|
endif
|
|
else
|
|
group.long 0x304++0x07
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
sif cpuis("MKL28Z*")||cpuis("K32W*")
|
|
bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "FIRCCFG,Fast IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz"
|
|
endif
|
|
endif
|
|
sif (!cpuis("S32MTV")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S"))
|
|
if (((per.l(ad:0x40064000+0x300))&0x01)==0x01)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x00 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..."
|
|
bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC_OSC"
|
|
else
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x00 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..."
|
|
bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC_OSC"
|
|
endif
|
|
endif
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
if (((per.l(ad:0x40064000+0x318))&0x200)==0x000)&&(((per.l(ad:0x40064000+0x318))&0x100)==0x000)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status"
|
|
else
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status"
|
|
endif
|
|
sif ((!cpuis("MKL28Z*"))&&!cpuis("S32MTV"))
|
|
group.long 0x400++0x0B
|
|
line.long 0x00 "ROSCCSR,RTC OSC Control Status Register"
|
|
bitfld.long 0x00 26. " ROSCERR ,RTC OSC clock error" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ROSCSEL ,RTC OSC selected" "Not the system,The system"
|
|
bitfld.long 0x00 24. " ROSCVLD ,RTC OSC valid" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 17. " ROSCCMRE ,RTC OSC clock monitor reset enable" "Interrupt,Reset"
|
|
bitfld.long 0x00 16. " ROSCCM ,RTC OSC clock monitor" "Disabled,Enabled"
|
|
line.long 0x04 "LPFLLCSR,Low Power FLL Control Status Register"
|
|
bitfld.long 0x04 26. " LPFLLERR ,LPFLL clock error" "Not detected,Detected"
|
|
bitfld.long 0x04 25. " LPFLLSEL ,LPFLL selected" "Not the system,The system"
|
|
bitfld.long 0x04 24. " LPFLLVLD ,LPFLL valid" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x04 17. " LPFLLCMRE ,LPFLL clock monitor reset enable" "Interrupt,Reset"
|
|
bitfld.long 0x04 16. " LPFLLCM ,LPFLL clock monitor" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LPFLLTRMLOCK ,LPFLL trim LOCK" "Not locked,Locked"
|
|
bitfld.long 0x04 9. " LPFLLVLD ,LPFLL trim update" "AUTOTRIM,Referenced"
|
|
bitfld.long 0x04 8. " LPFLLTREN ,LPFLL trim enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LPFLLSTEN ,LPFLL stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LPFLLEN ,LPFLL enable" "Disabled,Enabled"
|
|
line.long 0x08 "LPFLLDIV,Low Power FLL Divide Register"
|
|
bitfld.long 0x08 16.--18. " LPFLLDIV3 ,LPFLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x08 8.--10. " LPFLLDIV2 ,LPFLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x08 0.--2. " LPFLLDIV1 ,LPFLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "LPFLLCFG,Low Power FLL Configuration Register"
|
|
bitfld.long 0x00 0.--1. " FSEL ,Frequency select" "48 MHZ,72 MHZ,?..."
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "LPFLLTCFG,Low Power FLL Trim Configuration Register"
|
|
bitfld.long 0x00 16. " LOCKW2LSB ,Lock LPFLL with 2 LSBS" "1LSB,2LSB"
|
|
bitfld.long 0x00 8.--12. " TRIMDIV ,LPFLL trim predivide" "Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8,Divide by 9,Divide by 10,Divide by 11,Divide by 12,Divide by 13,Divide by 14,Divide by 15,Divide by 16,Divide by 17,Divide by 18,Divide by 19,Divide by 20,Divide by 21,Divide by 22,Divide by 23,Divide by 24,Divide by 25,Divide by 26,Divide by 27,Divide by 28,Divide by 29,Divide by 30,Divide by 31,Divide by 32"
|
|
bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" "SIRC,FIRC,System OSC,RTC OSC"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTOTRIM ,Auto tune trim status"
|
|
endif
|
|
endif
|
|
sif (!cpuis("K32W*"))
|
|
if (((per.l(ad:0x40064000+0x600))&0x800000)==0x800000)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPLLCSR,System PLL Control Status Register"
|
|
rbitfld.long 0x00 26. " SPLLERR ,System PLL clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SPLLSEL ,System PLL selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SPLLVLD ,System PLL valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 17. " SPLLCMRE ,System PLL clock monitor reset enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " SPLLCM ,System PLL clock monitor" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 1. " SPLLSTEN ,System PLL stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPLLCSR,System PLL Control Status Register"
|
|
eventfld.long 0x00 26. " SPLLERR ,System PLL clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SPLLSEL ,System PLL selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SPLLVLD ,System PLL valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 17. " SPLLCMRE ,System PLL clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SPLLCM ,System PLL clock monitor" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 1. " SPLLSTEN ,System PLL stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x600))&0x01)==0x01)
|
|
rgroup.long 0x604++0x07
|
|
line.long 0x00 "SPLLDIV,System PLL Divide Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SPLLDIV3 ,System PLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SPLLDIV2 ,System PLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SPLLDIV1 ,System PLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SPLLCFG,System PLL Configuration Register"
|
|
bitfld.long 0x04 16.--20. " MULT ,System PLL multiplier" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47"
|
|
bitfld.long 0x04 8.--10. " PREDIV ,PLL reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKL28Z*")||cpuis("S32MTV"))
|
|
bitfld.long 0x04 0. " SOURCE ,Clock source" "SOSC,FIRC"
|
|
endif
|
|
else
|
|
group.long 0x604++0x07
|
|
line.long 0x00 "SPLLDIV,System PLL Divide Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SPLLDIV3 ,System PLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SPLLDIV2 ,System PLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SPLLDIV1 ,System PLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SPLLCFG,System PLL Configuration Register"
|
|
bitfld.long 0x04 16.--20. " MULT ,System PLL multiplier" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47"
|
|
bitfld.long 0x04 8.--10. " PREDIV ,PLL reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKL28Z*")||cpuis("S32MTV"))
|
|
bitfld.long 0x04 0. " SOURCE ,Clock source" "SOSC,FIRC"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "OSC32 (RTC Oscillator)"
|
|
base ad:0x40060000
|
|
width 10.
|
|
if (((per.l(ad:0x40060000))&0x80)==0x80)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "OSC32_CR,RTC Oscillator Control Register"
|
|
bitfld.byte 0x00 7. " ROSCEN ,RTC 32k Oscillator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ROSCSTPEN ,RTC 32k Oscillator stop mode enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " ROSCSTB ,RTC 32k Oscillator stable flag" "Unstable,Stable"
|
|
bitfld.byte 0x00 4. " ROSCEREFS ,RTC 32k Oscillator external reference clcok selection" "Bypass mode,Crystal mode"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "OSC32_CR,RTC Oscillator Control Register"
|
|
bitfld.byte 0x00 7. " ROSCEN ,RTC 32k Oscillator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ROSCSTPEN ,RTC 32k Oscillator stop mode enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " ROSCSTB ,RTC 32k Oscillator stable flag" "Unstable,Stable"
|
|
bitfld.byte 0x00 4. " ROSCEREFS ,RTC 32k Oscillator external reference clcok selection" "Bypass mode,Crystal mode"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCC (Peripheral Clock Controller)"
|
|
base ad:0x40065000
|
|
width 10.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA0,DMA0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MPU,MPU Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "FLASH,FLASH Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "DMAMUX0,DMAMUX0 Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "FLEXCAN0,FLEXCAN0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "FLEXCAN1,FLEXCAN1 Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (per.l(ad:0x40065000+0x98)&0x40000000)==0x40000000
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FLEXTMR3,FLEXTMR3 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FLEXTMR3,FLEXTMR3 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0x9C)&0x40000000)==0x40000000
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "ADC1,ADC1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "ADC1,ADC1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0xB0)&0x40000000)==0x40000000
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "LPSPI0,LPSPI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "LPSPI0,LPSPI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0xB4)&0x40000000)==0x40000000
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "LPSPI1,LPSPI1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "LPSPI1,LPSPI1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PDB1,PDB1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRC,CRC Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "PDB2,PDB2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
endif
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PDB0,PDB0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (per.l(ad:0x40065000+0xDC)&0x40000000)==0x40000000
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "LPIT0,LPIT0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "LPIT0,LPIT0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0xE0)&0x40000000)==0x40000000
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "FLEXTMR0,FLEXTMR0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "FLEXTMR0,FLEXTMR0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0xE4)&0x40000000)==0x40000000
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FLEXTMR1,FLEXTMR1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FLEXTMR1,FLEXTMR1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0xE8)&0x40000000)==0x40000000
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "FLEXTMR2,FLEXTMR2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "FLEXTMR2,FLEXTMR2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0xEC)&0x40000000)==0x40000000
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "ADC0,ADC0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "ADC0,ADC0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
if (per.l(ad:0x40065000+0xF0)&0x40000000)==0x40000000
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "ADC2,ADC2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "ADC2,ADC2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
endif
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "RTC,RTC Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DAC0,DAC0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
endif
|
|
if (per.l(ad:0x40065000+0x100)&0x40000000)==0x40000000
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "LPTMR0,LPTMR0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "LPTMR0,LPTMR0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TSI,TSI Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
endif
|
|
group.long 0x124++0x13
|
|
line.long 0x00 "PORTA,PORTA Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "PORTB,PORTB Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x08 "PORTC,PORTC Register"
|
|
rbitfld.long 0x08 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x08 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x0C "PORTD,PORTD Register"
|
|
rbitfld.long 0x0C 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x0C 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x10 "PORTE,PORTE Register"
|
|
rbitfld.long 0x10 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x10 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x10 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "PWT,PWT Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (per.l(ad:0x40065000+0x168)&0x40000000)==0x40000000
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "FLEXIO,FLEXIO Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "FLEXIO,FLEXIO Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "OSC32,OSC32 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "EWM,EWM Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (per.l(ad:0x40065000+0x198)&0x40000000)==0x40000000
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "LPI2C0,LPI2C0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "LPI2C0,LPI2C0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0x19C)&0x40000000)==0x40000000
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "LPI2C1,LPI2C1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "LPI2C1,LPI2C1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0x1A8)&0x40000000)==0x40000000
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "LPUART0,LPUART0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "LPUART0,LPUART0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0x1AC)&0x40000000)==0x40000000
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "LPUART1,LPUART1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "LPUART1,LPUART1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40065000+0x1B0)&0x40000000)==0x40000000
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "LPUART2,LPUART2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
else
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "LPUART2,LPUART2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,LPFLLCLK,?..."
|
|
endif
|
|
endif
|
|
group.long 0x1CC++0x07
|
|
line.long 0x00 "CMP0,CMP0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "CMP1,CMP1 Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CMP2,CMP2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RCM (Reset Control Module)"
|
|
base ad:0x4007F000
|
|
width 11.
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "RCM_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "RCM_PARAM,Parameter Register"
|
|
bitfld.long 0x04 16. " ECORE1 ,Existence of SRS[CORE1] status indication feature" "Not available,Available"
|
|
bitfld.long 0x04 13. " ESACKERR ,Existence of SRS[SACKERR] status indication feature" "Not available,Available"
|
|
sif !cpuis("MKE1?F*")
|
|
bitfld.long 0x04 11. " EMDM_AP ,Existence of SRS[MDM_AP] status indication feature" "Not available,Available"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 10. " ESW ,Existence of SRS[SW] status indication feature" "Not available,Available"
|
|
bitfld.long 0x04 9. " ELOCKUP ,Existence of SRS[LOCKUP] status indication feature" "Not available,Available"
|
|
bitfld.long 0x04 7. " EPOR ,Existence of SRS[POR] status indication feature" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EPIN ,Existence of SRS[PIN] status indication feature" "Not available,Available"
|
|
bitfld.long 0x04 5. " EWDOG ,Existence of SRS[WDOG] status indication feature" "Not available,Available"
|
|
bitfld.long 0x04 3. " ELOL ,Existence of SRS[LOL] status indication feature" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ELOC ,Existence of SRS[LOC] status indication feature" "Not available,Available"
|
|
bitfld.long 0x04 1. " ELVD ,Existence of SRS[LVD] status indication feature" "Not available,Available"
|
|
line.long 0x08 "RCM_SRS,System Reset Status Register"
|
|
bitfld.long 0x08 13. " SACKERR ,Stop Acknowledge Error" "No reset,Reset"
|
|
bitfld.long 0x08 11. " MDM_AP ,MDM-AP System Reset Request" "No reset,Reset"
|
|
bitfld.long 0x08 10. " SW ,Software" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LOCKUP ,Core Lockup" "No reset,Reset"
|
|
sif cpuis("MKE1?F*")
|
|
textline " "
|
|
bitfld.long 0x08 8. " JTAG ,JTAG generated reset" "No reset,Reset"
|
|
bitfld.long 0x08 7. " POR ,Power-On Reset" "No reset,Reset"
|
|
bitfld.long 0x08 6. " PIN ,External Reset Pin" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x08 7. " POR ,Power-On Reset" "No reset,Reset"
|
|
bitfld.long 0x08 6. " PIN ,External Reset Pin" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 5. " WDOG ,Watchdog" "No reset,Reset"
|
|
bitfld.long 0x08 3. " LOL ,Loss-of-Lock Reset" "No reset,Reset"
|
|
bitfld.long 0x08 2. " LOC ,Loss-of-Clock Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LVD ,Low-Voltage/High-Voltage Detect or Power-On Reset" "No reset,Reset"
|
|
group.long 0x0C++0x13
|
|
line.long 0x00 "RCM_RPC,Reset Pin Control Register"
|
|
bitfld.long 0x00 8.--12. " RSTFLTSEL ,Reset Pin Filter Bus Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "Disabled,LPO clock"
|
|
bitfld.long 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "Disabled,Bus clock,LPO clock,?..."
|
|
textline " "
|
|
line.long 0x04 "RCM_MR,Mode Register"
|
|
eventfld.long 0x04 1.--2. " BOOTROM ,Boot ROM configuration" "Flash,ROM due to BOOTCFG0 pin assertion,ROM due to FOPT[7] configuration,ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration"
|
|
line.long 0x08 "RCM_FM,Force Mode Register"
|
|
bitfld.long 0x08 1.--2. " FORCEROM ,Force ROM boot" "No effect,Forced with RCM_MR[1],Forced with RCM_MR[2],Forced with RCM_MR[2:1]"
|
|
textline " "
|
|
line.long 0x0C "RCM_SSRS,Sticky System Reset Status Register"
|
|
eventfld.long 0x0C 13. " SSACKERR ,Sticky stop acknowledge error" "No reset,Reset"
|
|
eventfld.long 0x0C 11. " SMDM_AP ,Sticky MDM-AP system reset request" "No reset,Reset"
|
|
eventfld.long 0x0C 10. " SSW ,Sticky software" "No reset,Reset"
|
|
textline " "
|
|
sif cpuis("MKE1?F*")
|
|
eventfld.long 0x0C 9. " SLOCKUP ,Sticky core lockup" "No reset,Reset"
|
|
eventfld.long 0x0C 8. " SJTAG ,Sticky JTAG generated reset" "No reset,Reset"
|
|
else
|
|
eventfld.long 0x0C 9. " SLOCKUP ,Sticky core lockup" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x0C 7. " SPOR ,Sticky power-on reset" "No reset,Reset"
|
|
eventfld.long 0x0C 6. " SPIN ,Sticky external reset pin" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " SWDOG ,Sticky watchdog reset" "No reset,Reset"
|
|
eventfld.long 0x0C 3. " SLOL ,Sticky loss-of-lock reset" "No reset,Reset"
|
|
eventfld.long 0x0C 2. " SLOC ,Sticky loss-of-clock reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " SLVD ,Sticky low-voltage detect reset" "No reset,Reset"
|
|
line.long 0x10 "RCM_SRIE,System Reset Interrupt Enable Register"
|
|
bitfld.long 0x10 13. " SACKERR ,Stop acknowledge error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " MDM_AP ,MDM-AP system reset request interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " SW ,Software interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKE1?F*")
|
|
bitfld.long 0x10 9. " LOCKUP ,Core lockup interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " JTAG ,JTAG generated reset interrupt" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x10 9. " LOCKUP ,Core lockup interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 7. " GIE ,Global interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " PIN ,External reset pin interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " WDOG ,Watchdog interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " LOL ,Loss-of-lock interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " LOC ,Loss-of-clock interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " DELAY ,Reset delay time" "10 LPO cycles,34 LPO cycles,130 LPO cycles,514 LPO cycles"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "ICS (Internal Clock Source)"
|
|
base ad:0x40064000
|
|
width 8.
|
|
if ((per.b(ad:0x40065000)&0x04)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICS_C1,ICS Control Register 1"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock Source Select" "FLL,Internal,External,?..."
|
|
bitfld.byte 0x00 3.--5. " RDIV ,Reference Divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal Reference Clock as ICSIRCLK Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal Reference Stop Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICS_C1,ICS Control Register 1"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock Source Select" "FLL,Internal,External,?..."
|
|
bitfld.byte 0x00 3.--5. " RDIV ,Reference Divider" "/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.byte 0x00 2. " IREFS ,Internal Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal Reference Clock as ICSIRCLK Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal Reference Stop Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x01++0x03
|
|
line.byte 0x00 "ICS_C2,ICS Control Register 2"
|
|
bitfld.byte 0x00 5.--7. " BDIV ,Bus Frequency Divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 4. " LP ,Low Power Select" "FLL enabled,FLL disabled"
|
|
line.byte 0x01 "ICS_C3,ICS Control Register 3"
|
|
line.byte 0x02 "ICS_C4,ICS Control Register 4"
|
|
bitfld.byte 0x02 7. " LOLIE ,Loss of Lock Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x02 5. " CME ,Clock Monitor Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SCFTRIM ,Slow Internal Reference Clock Fine Trim" "Decrease,Increase"
|
|
line.byte 0x03 "ICS_S,ICS Status Register"
|
|
eventfld.byte 0x03 7. " LOLS ,Loss of Lock Status" "Not lost,Lost"
|
|
rbitfld.byte 0x03 6. " LOCK ,Lock Status" "Unlocked,Locked"
|
|
textline " "
|
|
rbitfld.byte 0x03 4. " IREFST ,Internal Reference Status" "External,Internal"
|
|
rbitfld.byte 0x03 2.--3. " CLKST ,Clock Mode Status" "FLL,Internal,External,?..."
|
|
width 0xB
|
|
tree.end
|
|
tree "OSC (Oscillator)"
|
|
base ad:0x40065000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "OSC_CR,OSC Control Register"
|
|
bitfld.byte 0x00 7. " OSCEN ,OSC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " OSCSTEN ,OSC Enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OSCOS ,OSC Output Select" "EXTAL,Oscillator"
|
|
textline " "
|
|
sif (cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z32VLD2R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
bitfld.byte 0x00 2. " RANGE ,Frequency Range Select" "32 kHz,4-20 MHz"
|
|
else
|
|
bitfld.byte 0x00 2. " RANGE ,Frequency Range Select" "32 kHz,4-24 MHz"
|
|
endif
|
|
bitfld.byte 0x00 1. " HGO ,High Gain Oscillator Select" "Low-power,High-gain"
|
|
rbitfld.byte 0x00 0. " OSCINIT ,OSC Initialization" "Not completed,Completed"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "ADC (Analog-to-digital converter)"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "ADC0"
|
|
base ad:0x4003B000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
width 10.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide Select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..."
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input Clock Select" "ADC_ALTCLK1,ADC_ALTCLK2,ADC_ALTCLK3,ADC_ALTCLK4"
|
|
line.long 0x04 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample Time Select"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RA,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "RB,ADC Data Result Register"
|
|
in
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x04 "CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x08 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x08 7. " ADACT ,Conversion Active" "Inactive,Active"
|
|
bitfld.long 0x08 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x08 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ACFGT ,Compare Function Greater Than Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ACREN ,Compare Function Range Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--1. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,VALTH/VALTL,?..."
|
|
line.long 0x0C "SC3,Status and Control Register 3"
|
|
bitfld.long 0x0C 7. " CAL ,Calibration" "No effect,Start"
|
|
bitfld.long 0x0C 3. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " AVGE ,Hardware Average Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " AVGS ,Hardware Average Select" "4 samples,8 samples,16 samples,32 samples"
|
|
group.long 0x98++0x53
|
|
line.long 0x00 "BASE_OFS,ADC Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BA_OFS ,Base Offset Error Correction Value"
|
|
line.long 0x04 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFS ,Offset Error Correction Value"
|
|
line.long 0x08 "USR_OFS,ADC USER Offset Correction Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " USR_OFS ,USER Offset Error Correction Value"
|
|
line.long 0x0C "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x0C 0.--5. " XOFS ,Offset Error Correction Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " YOFS ,Y Offset Error Correction Value"
|
|
line.long 0x14 "G,ADC Gain Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " G ,Gain"
|
|
line.long 0x18 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " UG ,User Gain"
|
|
line.long 0x1C "CLPS,ADC General Calibration Value Register"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " CLPS ,Calibration Value"
|
|
line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " CLP3 ,Calibration Value"
|
|
line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " CLP2 ,Calibration Value"
|
|
line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x28 0.--8. 1. " CLP1 ,Calibration Value"
|
|
line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CLP0 ,Calibration Value"
|
|
line.long 0x30 "CLPX,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x30 0.--6. 1. " CLPX ,Calibration Value"
|
|
line.long 0x34 "CLP9,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x34 0.--6. 1. " CLP9 ,Calibration Value"
|
|
line.long 0x38 "CLPS_OFS,ADC General Calibration Value Register"
|
|
bitfld.long 0x38 0.--3. " CLPS_OFS ,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "CLP3_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x3C 0.--3. " CLP3_OFS ,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "CLP2_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x40 0.--3. " CLP2_OFS ,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "CLP1_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x44 0.--3. " CLP1_OFS ,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "CLP0_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x48 0.--3. " CLP0_OFS ,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "CLPX_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x4C 0.--11. 1. " CLPX_OFS ,CLPX Offset"
|
|
line.long 0x50 "CLP9_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x50 0.--11. 1. " CLP9_OFS ,CLP9 Offset"
|
|
width 0x0B
|
|
else
|
|
width 10.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide Select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..."
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input Clock Select" "ADC_ALTCLK1,ADC_ALTCLK2,ADC_ALTCLK3,ADC_ALTCLK4"
|
|
line.long 0x04 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample Time Select"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RA,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "RB,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "RC,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "RD,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "RE,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "RF,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "RG,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "RH,ADC Data Result Register"
|
|
in
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x04 "CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x08 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x08 7. " ADACT ,Conversion Active" "Inactive,Active"
|
|
bitfld.long 0x08 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x08 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ACFGT ,Compare Function Greater Than Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ACREN ,Compare Function Range Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--1. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,VALTH/VALTL,?..."
|
|
line.long 0x0C "SC3,Status and Control Register 3"
|
|
bitfld.long 0x0C 7. " CAL ,Calibration" "No effect,Start"
|
|
bitfld.long 0x0C 3. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " AVGE ,Hardware Average Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " AVGS ,Hardware Average Select" "4 samples,8 samples,16 samples,32 samples"
|
|
group.long 0x98++0x53
|
|
line.long 0x00 "BASE_OFS,ADC Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BA_OFS ,Base Offset Error Correction Value"
|
|
line.long 0x04 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFS ,Offset Error Correction Value"
|
|
line.long 0x08 "USR_OFS,ADC USER Offset Correction Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " USR_OFS ,USER Offset Error Correction Value"
|
|
line.long 0x0C "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x0C 0.--5. " XOFS ,Offset Error Correction Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " YOFS ,Y Offset Error Correction Value"
|
|
line.long 0x14 "G,ADC Gain Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " G ,Gain"
|
|
line.long 0x18 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " UG ,User Gain"
|
|
line.long 0x1C "CLPS,ADC General Calibration Value Register"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " CLPS ,Calibration Value"
|
|
line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " CLP3 ,Calibration Value"
|
|
line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " CLP2 ,Calibration Value"
|
|
line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x28 0.--8. 1. " CLP1 ,Calibration Value"
|
|
line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CLP0 ,Calibration Value"
|
|
line.long 0x30 "CLPX,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x30 0.--6. 1. " CLPX ,Calibration Value"
|
|
line.long 0x34 "CLP9,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x34 0.--6. 1. " CLP9 ,Calibration Value"
|
|
line.long 0x38 "CLPS_OFS,ADC General Calibration Value Register"
|
|
bitfld.long 0x38 0.--3. " CLPS_OFS ,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "CLP3_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x3C 0.--3. " CLP3_OFS ,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "CLP2_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x40 0.--3. " CLP2_OFS ,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "CLP1_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x44 0.--3. " CLP1_OFS ,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "CLP0_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x48 0.--3. " CLP0_OFS ,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "CLPX_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x4C 0.--11. 1. " CLPX_OFS ,CLPX Offset"
|
|
line.long 0x50 "CLP9_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x50 0.--11. 1. " CLP9_OFS ,CLP9 Offset"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "ADC1"
|
|
base ad:0x40027000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
width 10.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide Select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..."
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input Clock Select" "ADC_ALTCLK1,ADC_ALTCLK2,ADC_ALTCLK3,ADC_ALTCLK4"
|
|
line.long 0x04 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample Time Select"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RA,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "RB,ADC Data Result Register"
|
|
in
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x04 "CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x08 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x08 7. " ADACT ,Conversion Active" "Inactive,Active"
|
|
bitfld.long 0x08 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x08 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ACFGT ,Compare Function Greater Than Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ACREN ,Compare Function Range Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--1. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,VALTH/VALTL,?..."
|
|
line.long 0x0C "SC3,Status and Control Register 3"
|
|
bitfld.long 0x0C 7. " CAL ,Calibration" "No effect,Start"
|
|
bitfld.long 0x0C 3. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " AVGE ,Hardware Average Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " AVGS ,Hardware Average Select" "4 samples,8 samples,16 samples,32 samples"
|
|
group.long 0x98++0x53
|
|
line.long 0x00 "BASE_OFS,ADC Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BA_OFS ,Base Offset Error Correction Value"
|
|
line.long 0x04 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFS ,Offset Error Correction Value"
|
|
line.long 0x08 "USR_OFS,ADC USER Offset Correction Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " USR_OFS ,USER Offset Error Correction Value"
|
|
line.long 0x0C "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x0C 0.--5. " XOFS ,Offset Error Correction Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " YOFS ,Y Offset Error Correction Value"
|
|
line.long 0x14 "G,ADC Gain Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " G ,Gain"
|
|
line.long 0x18 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " UG ,User Gain"
|
|
line.long 0x1C "CLPS,ADC General Calibration Value Register"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " CLPS ,Calibration Value"
|
|
line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " CLP3 ,Calibration Value"
|
|
line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " CLP2 ,Calibration Value"
|
|
line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x28 0.--8. 1. " CLP1 ,Calibration Value"
|
|
line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CLP0 ,Calibration Value"
|
|
line.long 0x30 "CLPX,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x30 0.--6. 1. " CLPX ,Calibration Value"
|
|
line.long 0x34 "CLP9,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x34 0.--6. 1. " CLP9 ,Calibration Value"
|
|
line.long 0x38 "CLPS_OFS,ADC General Calibration Value Register"
|
|
bitfld.long 0x38 0.--3. " CLPS_OFS ,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "CLP3_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x3C 0.--3. " CLP3_OFS ,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "CLP2_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x40 0.--3. " CLP2_OFS ,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "CLP1_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x44 0.--3. " CLP1_OFS ,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "CLP0_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x48 0.--3. " CLP0_OFS ,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "CLPX_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x4C 0.--11. 1. " CLPX_OFS ,CLPX Offset"
|
|
line.long 0x50 "CLP9_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x50 0.--11. 1. " CLP9_OFS ,CLP9 Offset"
|
|
width 0x0B
|
|
else
|
|
width 10.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?Z???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,,AD10,AD11,,,,,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide Select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..."
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input Clock Select" "ADC_ALTCLK1,ADC_ALTCLK2,ADC_ALTCLK3,ADC_ALTCLK4"
|
|
line.long 0x04 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample Time Select"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RA,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "RB,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "RC,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "RD,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "RE,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "RF,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "RG,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "RH,ADC Data Result Register"
|
|
in
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x04 "CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x08 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x08 7. " ADACT ,Conversion Active" "Inactive,Active"
|
|
bitfld.long 0x08 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x08 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ACFGT ,Compare Function Greater Than Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ACREN ,Compare Function Range Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--1. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,VALTH/VALTL,?..."
|
|
line.long 0x0C "SC3,Status and Control Register 3"
|
|
bitfld.long 0x0C 7. " CAL ,Calibration" "No effect,Start"
|
|
bitfld.long 0x0C 3. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " AVGE ,Hardware Average Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " AVGS ,Hardware Average Select" "4 samples,8 samples,16 samples,32 samples"
|
|
group.long 0x98++0x53
|
|
line.long 0x00 "BASE_OFS,ADC Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BA_OFS ,Base Offset Error Correction Value"
|
|
line.long 0x04 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFS ,Offset Error Correction Value"
|
|
line.long 0x08 "USR_OFS,ADC USER Offset Correction Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " USR_OFS ,USER Offset Error Correction Value"
|
|
line.long 0x0C "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x0C 0.--5. " XOFS ,Offset Error Correction Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " YOFS ,Y Offset Error Correction Value"
|
|
line.long 0x14 "G,ADC Gain Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " G ,Gain"
|
|
line.long 0x18 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " UG ,User Gain"
|
|
line.long 0x1C "CLPS,ADC General Calibration Value Register"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " CLPS ,Calibration Value"
|
|
line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " CLP3 ,Calibration Value"
|
|
line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " CLP2 ,Calibration Value"
|
|
line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x28 0.--8. 1. " CLP1 ,Calibration Value"
|
|
line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CLP0 ,Calibration Value"
|
|
line.long 0x30 "CLPX,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x30 0.--6. 1. " CLPX ,Calibration Value"
|
|
line.long 0x34 "CLP9,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x34 0.--6. 1. " CLP9 ,Calibration Value"
|
|
line.long 0x38 "CLPS_OFS,ADC General Calibration Value Register"
|
|
bitfld.long 0x38 0.--3. " CLPS_OFS ,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "CLP3_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x3C 0.--3. " CLP3_OFS ,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "CLP2_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x40 0.--3. " CLP2_OFS ,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "CLP1_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x44 0.--3. " CLP1_OFS ,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "CLP0_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x48 0.--3. " CLP0_OFS ,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "CLPX_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x4C 0.--11. 1. " CLPX_OFS ,CLPX Offset"
|
|
line.long 0x50 "CLP9_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x50 0.--11. 1. " CLP9_OFS ,CLP9 Offset"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
tree "ADC2"
|
|
base ad:0x4003C000
|
|
width 10.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("MKE1?F???VLH??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,,AD4,AD5,AD6,AD7,,,,,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
elif (cpuis("MKE1?F???VLL??"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,INT AD0,INT AD1,INT AD2,,,Temp Sensor,Band Gap,INT AD3,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide Select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..."
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input Clock Select" "ADC_ALTCLK1,ADC_ALTCLK2,ADC_ALTCLK3,ADC_ALTCLK4"
|
|
line.long 0x04 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample Time Select"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RA,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "RB,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "RC,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "RD,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "RE,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "RF,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "RG,ADC Data Result Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "RH,ADC Data Result Register"
|
|
in
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x04 "CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x08 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x08 7. " ADACT ,Conversion Active" "Inactive,Active"
|
|
bitfld.long 0x08 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x08 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ACFGT ,Compare Function Greater Than Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ACREN ,Compare Function Range Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--1. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,VALTH/VALTL,?..."
|
|
line.long 0x0C "SC3,Status and Control Register 3"
|
|
bitfld.long 0x0C 7. " CAL ,Calibration" "No effect,Start"
|
|
bitfld.long 0x0C 3. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " AVGE ,Hardware Average Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " AVGS ,Hardware Average Select" "4 samples,8 samples,16 samples,32 samples"
|
|
group.long 0x98++0x53
|
|
line.long 0x00 "BASE_OFS,ADC Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BA_OFS ,Base Offset Error Correction Value"
|
|
line.long 0x04 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFS ,Offset Error Correction Value"
|
|
line.long 0x08 "USR_OFS,ADC USER Offset Correction Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " USR_OFS ,USER Offset Error Correction Value"
|
|
line.long 0x0C "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x0C 0.--5. " XOFS ,Offset Error Correction Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " YOFS ,Y Offset Error Correction Value"
|
|
line.long 0x14 "G,ADC Gain Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " G ,Gain"
|
|
line.long 0x18 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " UG ,User Gain"
|
|
line.long 0x1C "CLPS,ADC General Calibration Value Register"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " CLPS ,Calibration Value"
|
|
line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " CLP3 ,Calibration Value"
|
|
line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " CLP2 ,Calibration Value"
|
|
line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x28 0.--8. 1. " CLP1 ,Calibration Value"
|
|
line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CLP0 ,Calibration Value"
|
|
line.long 0x30 "CLPX,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x30 0.--6. 1. " CLPX ,Calibration Value"
|
|
line.long 0x34 "CLP9,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x34 0.--6. 1. " CLP9 ,Calibration Value"
|
|
line.long 0x38 "CLPS_OFS,ADC General Calibration Value Register"
|
|
bitfld.long 0x38 0.--3. " CLPS_OFS ,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "CLP3_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x3C 0.--3. " CLP3_OFS ,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "CLP2_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x40 0.--3. " CLP2_OFS ,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "CLP1_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x44 0.--3. " CLP1_OFS ,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "CLP0_OFS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x48 0.--3. " CLP0_OFS ,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "CLPX_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x4C 0.--11. 1. " CLPX_OFS ,CLPX Offset"
|
|
line.long 0x50 "CLP9_OFS,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x50 0.--11. 1. " CLP9_OFS ,CLP9 Offset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
else
|
|
base ad:0x4003B000
|
|
width 12.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "ADC_SC1,Status and Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE02Z??VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,Vss,Vss,Vss,Vss,,,Tem. Sensor,Bandgap,,,,,,VREFH,VREFL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,Vss,Vss,Vss,Vss,,,Tem. Sensor,Bandgap,,,,,,VREFH,VREFL,Disabled"
|
|
endif
|
|
line.long 0x04 "ADC_SC2,Status and Control Register 2"
|
|
rbitfld.long 0x04 7. " ADACT ,Conversion Active" "No,Yes"
|
|
bitfld.long 0x04 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x04 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACFGT ,Compare Function Greater Than Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " FEMPTY ,Result FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 2. " FFULL ,Result FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,VDDA/VSSA,?..."
|
|
line.long 0x08 "ADC_SC3,Status and Control Register 3"
|
|
bitfld.long 0x08 7. " ADLPC ,Low-Power Configuration" "High speed,Low power"
|
|
bitfld.long 0x08 5.--6. " ADIV ,Clock Divide Select" "Clk,Clk/2,Clk/4,Clk/8"
|
|
bitfld.long 0x08 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit,?..."
|
|
bitfld.long 0x08 0.--1. " ADICLK ,Input Clock Select" "BusClk,BusClk/2,ALTCLK,ADACK"
|
|
line.long 0x0C "ADC_SC4,Status and Control Register 4"
|
|
sif (!cpuis("MKE02Z??VFM4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLD4R")&&!cpuis("MKE02Z64VLD4R")&&!cpuis("MKE02Z64VLH4R")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z32VLD2R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x0C 8. " HTRGME ,Hardware Trigger Multiple Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " ASCANE ,FIFO Scan Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ACFSEL ,Compare function select OR/AND" "OR,AND"
|
|
bitfld.long 0x0C 0.--2. " AFDEP ,FIFO Depth" "Disabled,2-level,3-level,4-level,5-level,6-level,7-level,8-level"
|
|
else
|
|
bitfld.long 0x0C 6. " ASCANE ,FIFO Scan Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ACFSEL ,Compare function select OR/AND" "OR,AND"
|
|
bitfld.long 0x0C 0.--2. " AFDEP ,FIFO Depth" "Disabled,2-level,3-level,4-level,5-level,6-level,7-level,8-level"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "ADC_R,Conversion Result Register"
|
|
in
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADC_CV,Compare Value Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare Value"
|
|
sif (cpuis("MKE02Z??VLC?")||cpuis("MKE02Z??VLD?")||cpuis("MKE02Z??VFM?")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z32VLD2R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_APCTL1,Pin Control 1 Register"
|
|
bitfld.long 0x00 11. " ADPC11 ,AD11 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " ADPC10 ,AD10 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " ADPC9 ,AD9 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADPC8 ,AD8 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " ADPC7 ,AD7 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ADPC6 ,AD6 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADPC5 ,AD5 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " ADPC4 ,AD4 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " ADPC3 ,AD3 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADPC2 ,AD2 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " ADPC1 ,AD1 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ADPC0 ,AD0 Pin I/O Control" "Enabled,Disabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_APCTL1,Pin Control 1 Register"
|
|
bitfld.long 0x00 15. " ADPC15 ,AD15 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " ADPC14 ,AD14 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " ADPC13 ,AD13 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ADPC12 ,AD12 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " ADPC11 ,AD11 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " ADPC10 ,AD10 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADPC9 ,AD9 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ADPC8 ,AD8 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " ADPC7 ,AD7 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADPC6 ,AD6 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " ADPC5 ,AD5 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " ADPC4 ,AD4 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADPC3 ,AD3 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " ADPC2 ,AD2 Pin I/O Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " ADPC1 ,AD1 Pin I/O Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADPC0 ,AD0 Pin I/O Control" "Enabled,Disabled"
|
|
endif
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
group.long 0x01C++0x03
|
|
line.long 0x00 "ADC_SC5,Status and Control Register 5"
|
|
bitfld.long 0x00 1. " HTRGMASKE ,Hardware Trigger Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HTRGMASKSEL ,Hardware Trigger Mask Mode Select" "HTRGMASKE,Automatically"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "CMP (Comparator)"
|
|
tree "Channel 0"
|
|
base ad:0x40073000
|
|
width 5.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "C0,CMP Control Register 0"
|
|
bitfld.long 0x00 30. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 25. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 24. " COUT ,Analog comparator output" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FPR ,Filter sample period"
|
|
bitfld.long 0x00 14.--15. " WE_SE ,Windowing/Sample enable" "None,Windowing mode,Sampling mode,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PMODE ,Power mode select" "Low speed,High speed"
|
|
bitfld.long 0x00 11. " INVT ,Comparator invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.long 0x00 9. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Filter disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.long 0x00 2. " OFFSET ,Comparator hard block offset control" "Level 0,Level 1"
|
|
bitfld.long 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3"
|
|
line.long 0x04 "C1,CMP Control Register 1"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 29. " DACOE ,DAC output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
else
|
|
bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 23. " CHN7 ,Channel 7 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CHN6 ,Channel 6 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CHN5 ,Channel 5 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CHN4 ,Channel 4 input enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 15. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,?..."
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,?..."
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
else
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " VOSEL ,DAC output voltage select"
|
|
line.long 0x08 "C2,CMP Control Register 2"
|
|
bitfld.long 0x08 31. " RRE ,Round-Robin enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RRIE ,Round-Robin interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " FXMP ,Fixed MUX port" "Plus fixed,Minus fixed"
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,?..."
|
|
newline
|
|
eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed"
|
|
else
|
|
bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
newline
|
|
eventfld.long 0x08 23. " CH7F ,Channel 7 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 22. " CH6F ,Channel 6 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 21. " CH5F ,Channel 5 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 20. " CH4F ,Channel 4 input changed flag" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 14.--15. " NSAM ,Number of sample clocks" "Same cycle,1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x08 8.--13. " INITMOD ,Comparator and DAC initialization delay modulus" "64,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1"
|
|
else
|
|
bitfld.long 0x08 7. " ACO7 ,The result of the input comparison for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " ACO6 ,The result of the input comparison for channel 6" "0,1"
|
|
bitfld.long 0x08 5. " ACO5 ,The result of the input comparison for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " ACO4 ,The result of the input comparison for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40074000
|
|
width 5.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "C0,CMP Control Register 0"
|
|
bitfld.long 0x00 30. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 25. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 24. " COUT ,Analog comparator output" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FPR ,Filter sample period"
|
|
bitfld.long 0x00 14.--15. " WE_SE ,Windowing/Sample enable" "None,Windowing mode,Sampling mode,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PMODE ,Power mode select" "Low speed,High speed"
|
|
bitfld.long 0x00 11. " INVT ,Comparator invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.long 0x00 9. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Filter disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.long 0x00 2. " OFFSET ,Comparator hard block offset control" "Level 0,Level 1"
|
|
bitfld.long 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3"
|
|
line.long 0x04 "C1,CMP Control Register 1"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 29. " DACOE ,DAC output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
else
|
|
bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 23. " CHN7 ,Channel 7 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CHN6 ,Channel 6 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CHN5 ,Channel 5 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CHN4 ,Channel 4 input enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 15. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,?..."
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,?..."
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
else
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " VOSEL ,DAC output voltage select"
|
|
line.long 0x08 "C2,CMP Control Register 2"
|
|
bitfld.long 0x08 31. " RRE ,Round-Robin enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RRIE ,Round-Robin interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " FXMP ,Fixed MUX port" "Plus fixed,Minus fixed"
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,?..."
|
|
newline
|
|
eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed"
|
|
else
|
|
bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
newline
|
|
eventfld.long 0x08 23. " CH7F ,Channel 7 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 22. " CH6F ,Channel 6 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 21. " CH5F ,Channel 5 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 20. " CH4F ,Channel 4 input changed flag" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 14.--15. " NSAM ,Number of sample clocks" "Same cycle,1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x08 8.--13. " INITMOD ,Comparator and DAC initialization delay modulus" "64,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1"
|
|
else
|
|
bitfld.long 0x08 7. " ACO7 ,The result of the input comparison for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " ACO6 ,The result of the input comparison for channel 6" "0,1"
|
|
bitfld.long 0x08 5. " ACO5 ,The result of the input comparison for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " ACO4 ,The result of the input comparison for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "Channel 2"
|
|
base ad:0x40075000
|
|
width 5.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "C0,CMP Control Register 0"
|
|
bitfld.long 0x00 30. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 25. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 24. " COUT ,Analog comparator output" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FPR ,Filter sample period"
|
|
bitfld.long 0x00 14.--15. " WE_SE ,Windowing/Sample enable" "None,Windowing mode,Sampling mode,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PMODE ,Power mode select" "Low speed,High speed"
|
|
bitfld.long 0x00 11. " INVT ,Comparator invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.long 0x00 9. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Filter disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.long 0x00 2. " OFFSET ,Comparator hard block offset control" "Level 0,Level 1"
|
|
bitfld.long 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3"
|
|
line.long 0x04 "C1,CMP Control Register 1"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 29. " DACOE ,DAC output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
else
|
|
bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 23. " CHN7 ,Channel 7 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CHN6 ,Channel 6 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CHN5 ,Channel 5 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CHN4 ,Channel 4 input enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 15. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,?..."
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,?..."
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
else
|
|
bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " VOSEL ,DAC output voltage select"
|
|
line.long 0x08 "C2,CMP Control Register 2"
|
|
bitfld.long 0x08 31. " RRE ,Round-Robin enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RRIE ,Round-Robin interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " FXMP ,Fixed MUX port" "Plus fixed,Minus fixed"
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,?..."
|
|
newline
|
|
eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed"
|
|
else
|
|
bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
newline
|
|
eventfld.long 0x08 23. " CH7F ,Channel 7 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 22. " CH6F ,Channel 6 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 21. " CH5F ,Channel 5 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 20. " CH4F ,Channel 4 input changed flag" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 14.--15. " NSAM ,Number of sample clocks" "Same cycle,1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x08 8.--13. " INITMOD ,Comparator and DAC initialization delay modulus" "64,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
sif (cpuis("S32MTV*"))
|
|
bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1"
|
|
else
|
|
bitfld.long 0x08 7. " ACO7 ,The result of the input comparison for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " ACO6 ,The result of the input comparison for channel 6" "0,1"
|
|
bitfld.long 0x08 5. " ACO5 ,The result of the input comparison for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " ACO4 ,The result of the input comparison for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "ACMP (Analog comparator)"
|
|
tree "Channel 0"
|
|
base ad:0x40073000
|
|
width 11.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "ACMP0_CS,ACMP0 Control and Status Register"
|
|
bitfld.byte 0x00 7. " ACE ,Analog Comparator Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " HYST ,Analog Comparator Hysterisis Selection" "20 mV,30 mV"
|
|
bitfld.byte 0x00 5. " ACF ,ACMP Interrupt Flag Bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ACIE ,ACMP Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " ACO ,ACMP Output" "Low,High"
|
|
bitfld.byte 0x00 2. " ACOPE ,ACMP Output Pin Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " ACMOD ,ACMP MOD" "Falling edge,Rising edge,Falling edge,Both edges"
|
|
line.byte 0x01 "ACMP0_C0,ACMP0 Control Register 0"
|
|
bitfld.byte 0x01 4.--5. " ACPSEL ,ACMP Positive Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
bitfld.byte 0x01 0.--1. " ACNSEL ,ACMP Negative Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
line.byte 0x02 "ACMP0_C1,ACMP0 Control Register 1"
|
|
bitfld.byte 0x02 7. " DACEN ,DAC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " DACREF ,DAC Reference Select" "Bandgap,VDDA"
|
|
bitfld.byte 0x02 0.--5. " DACVAL ,DAC Output Level Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ACMP0_C2,ACMP0 Control Register 2"
|
|
bitfld.byte 0x00 2. " ACIPE2 ,ACMP Input Pin 2 PTC4 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACIPE1 ,ACMP Input Pin 1 PTA1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACIPE0 ,ACMP Input Pin 0 PTA0 Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40074000
|
|
width 11.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "ACMP1_CS,ACMP1 Control and Status Register"
|
|
bitfld.byte 0x00 7. " ACE ,Analog Comparator Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " HYST ,Analog Comparator Hysterisis Selection" "20 mV,30 mV"
|
|
bitfld.byte 0x00 5. " ACF ,ACMP Interrupt Flag Bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ACIE ,ACMP Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " ACO ,ACMP Output" "Low,High"
|
|
bitfld.byte 0x00 2. " ACOPE ,ACMP Output Pin Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " ACMOD ,ACMP MOD" "Falling edge,Rising edge,Falling edge,Both edges"
|
|
line.byte 0x01 "ACMP1_C0,ACMP1 Control Register 0"
|
|
bitfld.byte 0x01 4.--5. " ACPSEL ,ACMP Positive Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
bitfld.byte 0x01 0.--1. " ACNSEL ,ACMP Negative Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
line.byte 0x02 "ACMP1_C1,ACMP1 Control Register 1"
|
|
bitfld.byte 0x02 7. " DACEN ,DAC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " DACREF ,DAC Reference Select" "Bandgap,VDDA"
|
|
bitfld.byte 0x02 0.--5. " DACVAL ,DAC Output Level Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ACMP1_C2,ACMP1 Control Register 2"
|
|
bitfld.byte 0x00 2. " ACIPE2 ,ACMP Input Pin 2 PTB4 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACIPE1 ,ACMP Input Pin 1 PTA7 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACIPE0 ,ACMP Input Pin 0 PTA6 Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x4003F000
|
|
width 10.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "DAT0,DAC Data 0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "DAT1,DAC Data 1 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "DAT2,DAC Data 2 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "DAT3,DAC Data 3 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DAT4,DAC Data 4 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAT5,DAC Data 5 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DAT6,DAC Data 6 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DAT7,DAC Data 7 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DATA1 ,DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA0 ,DATA0"
|
|
if (((per.l(ad:0x4003F000+0x20))&0x60000)==0x60000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "STATCTRL,DAC Status and Control Register"
|
|
bitfld.long 0x00 28.--31. " DACBFRP ,FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DACBFUP ,FIFO Write Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
bitfld.long 0x00 23. " DMAEN ,DMA Enable Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " BFOUTEN ,DAC output buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TESTOUTEN ,DAC test output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " DACBFWM ,FIFO watermark select" "2 or less words,Max/4 or less words,Max/2 or less words,Max-2 or less words"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " DACBFMD ,DAC Buffer Work Mode Select" "Normal mode,Swing mode,One-Time Scan mode,FIFO mode"
|
|
bitfld.long 0x00 16. " DACBFEN ,DAC Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DACEN ,DAC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DACRFS ,DAC Reference Select" "DACREF_1,DACREF_2"
|
|
bitfld.long 0x00 13. " DACTRGSEL ,DAC Trigger Select" "Hardware,Software"
|
|
bitfld.long 0x00 12. " DACSWTRG ,DAC Software Trigger" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LPEN ,DAC Low Power Control" "High-Power,Low-Power"
|
|
bitfld.long 0x00 10. " DACBWIEN ,DAC Buffer Watermark Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DACBTIEN ,DAC Buffer Read Pointer Top Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DACBBIEN ,DAC Buffer Read Pointer Bottom Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DACBFWMF ,FIFO Watermark Status Flag" "Not reached,Reached"
|
|
bitfld.long 0x00 1. " DACBFRPTF ,FIFO nearly empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DACBFRPBF ,FIFO FULL status Flag" "Not full,Full"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "STATCTRL,DAC Status and Control Register"
|
|
bitfld.long 0x00 28.--31. " DACBFRP ,DAC Buffer Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DACBFUP ,DAC Buffer Upper Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " DMAEN ,DMA Enable Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " BFOUTEN ,DAC output buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TESTOUTEN ,DAC test output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " DACBFWM ,DAC Buffer Watermark Select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " DACBFMD ,DAC Buffer Work Mode Select" "Normal mode,Swing mode,One-Time Scan mode,FIFO mode"
|
|
bitfld.long 0x00 16. " DACBFEN ,DAC Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DACEN ,DAC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DACRFS ,DAC Reference Select" "DACREF_1,DACREF_2"
|
|
bitfld.long 0x00 13. " DACTRGSEL ,DAC Trigger Select" "Hardware,Software"
|
|
bitfld.long 0x00 12. " DACSWTRG ,DAC Software Trigger" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LPEN ,DAC Low Power Control" "High-Power,Low-Power"
|
|
bitfld.long 0x00 10. " DACBWIEN ,DAC Buffer Watermark Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DACBTIEN ,DAC Buffer Read Pointer Top Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DACBBIEN ,DAC Buffer Read Pointer Bottom Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DACBFWMF ,DAC Buffer Watermark Flag" "Not reached,Reached"
|
|
bitfld.long 0x00 1. " DACBFRPTF ,DAC Buffer Read Pointer Top Position Flag" "Not zero,Zero"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DACBFRPBF ,DAC Buffer Read Pointer Bottom Position Flag" "Not equal,Equal"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "Timers"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "PDB (Programmable Delay Block)"
|
|
tree "PDB0"
|
|
base ad:0x40036000
|
|
width 18.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SC,Status And Control Register"
|
|
bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,When PDB counter reaches MOD value,When input event is detected,When PDB counter reaches MOD value/Input event"
|
|
newline
|
|
bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWTRIG ,Software trigger" "No effect,Clear"
|
|
bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger"
|
|
bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "*1,*10,*20,*40"
|
|
bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous"
|
|
bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated"
|
|
newline
|
|
line.long 0x04 "MOD,Modulus Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter"
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "IDLY,Interrupt Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay"
|
|
line.long 0x04 "CH0C1,Channel 0 Control Register 1"
|
|
bitfld.long 0x04 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x08 "CH0S,Channel 0 Status Register"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
bitfld.long 0x08 23. " CF[7] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 22. " [6] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 21. " [5] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 20. " [4] ,PDB channel flag" "Not matched,Matched"
|
|
newline
|
|
bitfld.long 0x08 19. " [3] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 18. " [2] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 17. " [1] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 16. " [0] ,PDB channel flag" "Not matched,Matched"
|
|
else
|
|
hexmask.long.byte 0x08 16.--23. 1. " CF ,PDB channel flags"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0DLY2,Channel 0 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DLY3,Channel 0 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH0DLY4,Channel 0 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH0DLY5,Channel 0 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH0DLY6,Channel 0 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0DLY7,Channel 0 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "DACINTC0,DAC External Trigger Input Enable"
|
|
bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "DACINT0,DAC External Trigger Input Enable"
|
|
hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval"
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "CH1C1,Channel 0 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH1S,Channel 0 Status Register"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 22. " [6] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 21. " [5] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 20. " [4] ,PDB channel flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 18. " [2] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 17. " [1] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 16. " [0] ,PDB channel flag" "No error,Error"
|
|
else
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH1DLY2,Channel 0 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH1DLY3,Channel 0 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1DLY4,Channel 0 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1DLY5,Channel 0 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH1DLY6,Channel 0 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH1DLY7,Channel 0 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S"))
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "CH2C1,Channel 0 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH2S,Channel 0 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH2DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH2DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH2DLY2,Channel 0 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH2DLY3,Channel 0 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CH2DLY4,Channel 0 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CH2DLY5,Channel 0 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2DLY6,Channel 0 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH2DLY7,Channel 0 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S"))
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "CH3C1,Channel 0 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH3S,Channel 0 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH3DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH3DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH3DLY2,Channel 0 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH3DLY3,Channel 0 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH3DLY4,Channel 0 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH3DLY5,Channel 0 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH3DLY6,Channel 0 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH3DLY7,Channel 0 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
group.long 0x190++0x07
|
|
line.long 0x00 "POEN,Pulse-Out 0 Enable Register"
|
|
bitfld.long 0x00 7. " POEN_[7] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
line.long 0x04 "PO0DLY,Pulse-Out 0 Delay Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PO1DLY,Pulse-Out 0 Delay Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "PDB1"
|
|
base ad:0x40031000
|
|
width 18.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SC,Status And Control Register"
|
|
bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,When PDB counter reaches MOD value,When input event is detected,When PDB counter reaches MOD value/Input event"
|
|
newline
|
|
bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWTRIG ,Software trigger" "No effect,Clear"
|
|
bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger"
|
|
bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "*1,*10,*20,*40"
|
|
bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous"
|
|
bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated"
|
|
newline
|
|
line.long 0x04 "MOD,Modulus Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter"
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "IDLY,Interrupt Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay"
|
|
line.long 0x04 "CH0C1,Channel 1 Control Register 1"
|
|
bitfld.long 0x04 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x08 "CH0S,Channel 1 Status Register"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
bitfld.long 0x08 23. " CF[7] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 22. " [6] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 21. " [5] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 20. " [4] ,PDB channel flag" "Not matched,Matched"
|
|
newline
|
|
bitfld.long 0x08 19. " [3] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 18. " [2] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 17. " [1] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 16. " [0] ,PDB channel flag" "Not matched,Matched"
|
|
else
|
|
hexmask.long.byte 0x08 16.--23. 1. " CF ,PDB channel flags"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0DLY2,Channel 1 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DLY3,Channel 1 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH0DLY4,Channel 1 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH0DLY5,Channel 1 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH0DLY6,Channel 1 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0DLY7,Channel 1 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "DACINTC0,DAC External Trigger Input Enable"
|
|
bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "DACINT0,DAC External Trigger Input Enable"
|
|
hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval"
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "CH1C1,Channel 1 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH1S,Channel 1 Status Register"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 22. " [6] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 21. " [5] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 20. " [4] ,PDB channel flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 18. " [2] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 17. " [1] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 16. " [0] ,PDB channel flag" "No error,Error"
|
|
else
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH1DLY2,Channel 1 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH1DLY3,Channel 1 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1DLY4,Channel 1 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1DLY5,Channel 1 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH1DLY6,Channel 1 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH1DLY7,Channel 1 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S"))
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "CH2C1,Channel 1 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH2S,Channel 1 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH2DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH2DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH2DLY2,Channel 1 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH2DLY3,Channel 1 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CH2DLY4,Channel 1 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CH2DLY5,Channel 1 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2DLY6,Channel 1 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH2DLY7,Channel 1 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S"))
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "CH3C1,Channel 1 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH3S,Channel 1 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH3DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH3DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH3DLY2,Channel 1 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH3DLY3,Channel 1 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH3DLY4,Channel 1 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH3DLY5,Channel 1 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH3DLY6,Channel 1 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH3DLY7,Channel 1 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
group.long 0x190++0x07
|
|
line.long 0x00 "POEN,Pulse-Out 1 Enable Register"
|
|
bitfld.long 0x00 7. " POEN_[7] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
line.long 0x04 "PO0DLY,Pulse-Out 1 Delay Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PDB2"
|
|
base ad:0x40033000
|
|
width 18.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SC,Status And Control Register"
|
|
bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,When PDB counter reaches MOD value,When input event is detected,When PDB counter reaches MOD value/Input event"
|
|
newline
|
|
bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWTRIG ,Software trigger" "No effect,Clear"
|
|
bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger"
|
|
bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "*1,*10,*20,*40"
|
|
bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous"
|
|
bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated"
|
|
newline
|
|
line.long 0x04 "MOD,Modulus Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter"
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "IDLY,Interrupt Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay"
|
|
line.long 0x04 "CH0C1,Channel 2 Control Register 1"
|
|
bitfld.long 0x04 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x04 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x08 "CH0S,Channel 2 Status Register"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
bitfld.long 0x08 23. " CF[7] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 22. " [6] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 21. " [5] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 20. " [4] ,PDB channel flag" "Not matched,Matched"
|
|
newline
|
|
bitfld.long 0x08 19. " [3] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 18. " [2] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 17. " [1] ,PDB channel flag" "Not matched,Matched"
|
|
bitfld.long 0x08 16. " [0] ,PDB channel flag" "Not matched,Matched"
|
|
else
|
|
hexmask.long.byte 0x08 16.--23. 1. " CF ,PDB channel flags"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x08 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel 2 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel 2 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel 2 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel 2 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0DLY2,Channel 2 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DLY3,Channel 2 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH0DLY4,Channel 2 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH0DLY5,Channel 2 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH0DLY6,Channel 2 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0DLY7,Channel 2 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "DACINTC0,DAC External Trigger Input Enable"
|
|
bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "DACINT0,DAC External Trigger Input Enable"
|
|
hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval"
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "CH1C1,Channel 2 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH1S,Channel 2 Status Register"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 22. " [6] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 21. " [5] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 20. " [4] ,PDB channel flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 18. " [2] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 17. " [1] ,PDB channel flag" "No error,Error"
|
|
bitfld.long 0x04 16. " [0] ,PDB channel flag" "No error,Error"
|
|
else
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel 2 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel 2 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel 2 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel 2 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH1DLY2,Channel 2 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH1DLY3,Channel 2 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1DLY4,Channel 2 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1DLY5,Channel 2 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH1DLY6,Channel 2 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH1DLY7,Channel 2 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S"))
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "CH2C1,Channel 2 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH2S,Channel 2 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH2DLY0,Channel 2 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH2DLY1,Channel 2 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH2DLY2,Channel 2 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH2DLY3,Channel 2 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CH2DLY4,Channel 2 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CH2DLY5,Channel 2 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2DLY6,Channel 2 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH2DLY7,Channel 2 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S"))
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "CH3C1,Channel 2 Control Register 1"
|
|
bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1"
|
|
bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH3S,Channel 2 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
newline
|
|
bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH3DLY0,Channel 2 Delay 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH3DLY1,Channel 2 Delay 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH3DLY2,Channel 2 Delay 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH3DLY3,Channel 2 Delay 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH3DLY4,Channel 2 Delay 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH3DLY5,Channel 2 Delay 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH3DLY6,Channel 2 Delay 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH3DLY7,Channel 2 Delay 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
group.long 0x190++0x07
|
|
line.long 0x00 "POEN,Pulse-Out 2 Enable Register"
|
|
bitfld.long 0x00 7. " POEN_[7] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PDB Pulse-Out enable" "Disabled,Enabled"
|
|
line.long 0x04 "PO0DLY,Pulse-Out 2 Delay Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PO1DLY,Pulse-Out 2 Delay Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "FTM (FlexTimer)"
|
|
tree "FTM0"
|
|
base ad:0x40038000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM0_SC,FTM0 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM0_CNT,FTM0 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM0_MOD,FTM0 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM0_C0V,FTM0 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM0_C1V,FTM0 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM0_C2V,FTM0 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM0_C3V,FTM0 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register"
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "FTM0_C4V,FTM0 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register"
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "FTM0_C5V,FTM0 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register"
|
|
group.long (0x3C+0x04)++0x03
|
|
line.long 0x00 "FTM0_C6V,FTM0 Channel 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register"
|
|
group.long (0x44+0x04)++0x03
|
|
line.long 0x00 "FTM0_C7V,FTM0 Channel 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM0 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM0_CONF,FTM0 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM0_INVCTRL,FTM0 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_SWOCTRL,FTM0 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM0_PWMLOAD,FTM0 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM0_HCR,FTM0 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM0_INVCTRL,FTM0 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_SWOCTRL,FTM0 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM0_PWMLOAD,FTM0 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM0_HCR,FTM0 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM0_INVCTRL,FTM0 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_SWOCTRL,FTM0 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM0_PWMLOAD,FTM0 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM0_HCR,FTM0 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM0_MOD_MIRROR,FTM0 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM0_C0V_MIRROR,FTM0 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM0_C1V_MIRROR,FTM0 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM0_C2V_MIRROR,FTM0 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM0_C3V_MIRROR,FTM0 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FTM0_C4V_MIRROR,FTM0 Mirror of Channel 4 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 4 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "FTM0_C5V_MIRROR,FTM0 Mirror of Channel 5 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 5 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "FTM0_C6V_MIRROR,FTM0 Mirror of Channel 6 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 6 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "FTM0_C7V_MIRROR,FTM0 Mirror of Channel 7 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 7 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM0_SC,Status And Control"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM0_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
line.long 0x04 "FTM0_MOD,Modulo"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo Value"
|
|
textline " "
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status and Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status and Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM0_CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM0_STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 1. " CH1F ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CH0F ,Channel 0 Flag" "Not occurred,Occurred"
|
|
if (((per.l(ad:0x40038000+0x54))&0x04)==0x04)
|
|
if (((per.l(ad:0x40038000+0x8C)&0x80)==0x80))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,Software:MOD/CnV Hardware:FTM/OUTMASK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40038000+0x8C)&0x80)==0x80))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,Software:MOD/CnV Hardware:FTM/OUTMASK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x8C)&0x80)==0x00))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FTM0_SYNC,Synchronization"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "Clk rising edges,PWM synch."
|
|
bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FTM0_SYNC,Synchronization"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "Clk rising edges,PWM synch."
|
|
textline " "
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "FTM0_OUTINIT,Initial State For Channels Output"
|
|
bitfld.long 0x00 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1"
|
|
bitfld.long 0x00 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1"
|
|
line.long 0x04 "FTM0_OUTMASK,Output Mask"
|
|
bitfld.long 0x04 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked"
|
|
if (((per.l(ad:0x40038000+0x54))&0x04)==0x04)
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
line.long 0x04 "FTM0_DEADTIME,Deadtime Insertion Control"
|
|
bitfld.long 0x04 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x04 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM0_DEADTIME,Deadtime Insertion Control"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM0_EXTTRIG,FTM External Trigger"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40038000+0x54))&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM0_POL,Channels Polarity"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM0_POL,Channels Polarity"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM0_FMS,Fault Mode Status"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "No fault,Fault"
|
|
bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Fault Inputs OR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "No fault,Fault"
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "No fault,Fault"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "No fault,Fault"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "No fault,Fault"
|
|
line.long 0x04 "FTM0_FILTER,Input Capture Filter Control"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40038000+0x54))&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM0_FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM0_FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM0_CONF,Configuration"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,Debug Mode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency - ratio of counter overflows : TOF bit is set" "Each overflow,Not next,Not 2 next,Not 3 next,Not 4 next,Not 5 next,Not 6 next,Not 7 next,Not 8 next,Not 9 next,Not 10 next,Not 11 next,Not 12 next,Not 13 next,Not 14 next,Not 15 next,Not 16 next,Not 17 next,Not 18 next,Not 19 next,Not 20 next,Not 21 next,Not 22 next,Not 23 next,Not 24 next,Not 25 next,Not 26 next,Not 27 next,Not 28 next,Not 29 next,Not 30 next,Not 31 next"
|
|
if (((per.l(ad:0x40038000+0x54))&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM0_FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active Low"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM0_FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active Low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM0_SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. " HWSOC ,SWOCTRL synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 19. " HWINVC ,INVCTRL synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " HWOM ,OUTMASK synchronization is activated by a hardware trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM synchronization is activated by a hardware trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSOC ,SWOCTRL synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 11. " SWINVC ,INVCTRL synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 10. " SWOM ,OUTMASK synchronization is activated by the software trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWOM ,MOD CNTIN and CV synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy PWM,Enhanced PWM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "All rising edges,PWM"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "All rising edges,PWM"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "All rising edges,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode - TRIGj bit clearing when the hardware trigger j is detected" "Enabled,Disabled"
|
|
line.long 0x04 "FTM0_INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x04 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM0_SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x08 9. " CH1OCV ,Channel 1 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 8. " CH0OCV ,Channel 0 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM0_PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x0C 9. " LDOK ,MOD CNTIN CV Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " CH1SEL ,Channel 1 Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 0. " CH0SEL ,Channel 0 Select" "Not selected,Selected"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "FTM1"
|
|
base ad:0x40039000
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM1_CNT,FTM1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM1_MOD,FTM1 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM1_C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM1_C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM1_C2SC,FTM1 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM1_C2V,FTM1 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM1_C3SC,FTM1 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM1_C3V,FTM1 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM1_C4SC,FTM1 Channel 4 Status And Control Register"
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "FTM1_C4V,FTM1 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM1_C5SC,FTM1 Channel 5 Status And Control Register"
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "FTM1_C5V,FTM1 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "FTM1_C6SC,FTM1 Channel 6 Status And Control Register"
|
|
group.long (0x3C+0x04)++0x03
|
|
line.long 0x00 "FTM1_C6V,FTM1 Channel 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "FTM1_C7SC,FTM1 Channel 7 Status And Control Register"
|
|
group.long (0x44+0x04)++0x03
|
|
line.long 0x00 "FTM1_C7V,FTM1 Channel 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM1 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
endif
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM1_CONF,FTM1 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM1_HCR,FTM1 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM1_HCR,FTM1 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM1_HCR,FTM1 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM1_MOD_MIRROR,FTM1 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM1_C0V_MIRROR,FTM1 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM1_C1V_MIRROR,FTM1 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM1_C2V_MIRROR,FTM1 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM1_C3V_MIRROR,FTM1 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FTM1_C4V_MIRROR,FTM1 Mirror of Channel 4 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 4 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "FTM1_C5V_MIRROR,FTM1 Mirror of Channel 5 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 5 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "FTM1_C6V_MIRROR,FTM1 Mirror of Channel 6 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 6 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "FTM1_C7V_MIRROR,FTM1 Mirror of Channel 7 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 7 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*"))
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM1_CNT,FTM1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM1_MOD,FTM1 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM1_C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM1_C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM1_C2SC,FTM1 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM1_C2V,FTM1 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM1_C3SC,FTM1 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM1_C3V,FTM1 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM1 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
endif
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM1_CONF,FTM1 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x40039000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM1_HCR,FTM1 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM1_HCR,FTM1 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM1_HCR,FTM1 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM1_MOD_MIRROR,FTM1 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM1_C0V_MIRROR,FTM1 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM1_C1V_MIRROR,FTM1 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM1_C2V_MIRROR,FTM1 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM1_C3V_MIRROR,FTM1 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM1_SC,Status And Control"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM1_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
line.long 0x04 "FTM1_MOD,Modulo"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo Value"
|
|
textline " "
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status and Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM1_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status and Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM1_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM1_CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM1_STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 1. " CH1F ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CH0F ,Channel 0 Flag" "Not occurred,Occurred"
|
|
if (((per.l(ad:0x40039000+0x54))&0x04)==0x04)
|
|
if (((per.l(ad:0x40039000+0x8C)&0x80)==0x80))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,Software:MOD/CnV Hardware:FTM/OUTMASK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40039000+0x8C)&0x80)==0x80))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,Software:MOD/CnV Hardware:FTM/OUTMASK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40039000+0x8C)&0x80)==0x00))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FTM1_SYNC,Synchronization"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "Clk rising edges,PWM synch."
|
|
bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FTM1_SYNC,Synchronization"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "Clk rising edges,PWM synch."
|
|
textline " "
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "FTM1_OUTINIT,Initial State For Channels Output"
|
|
bitfld.long 0x00 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1"
|
|
bitfld.long 0x00 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1"
|
|
line.long 0x04 "FTM1_OUTMASK,Output Mask"
|
|
bitfld.long 0x04 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked"
|
|
if (((per.l(ad:0x40039000+0x54))&0x04)==0x04)
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
line.long 0x04 "FTM1_DEADTIME,Deadtime Insertion Control"
|
|
bitfld.long 0x04 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x04 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,Deadtime Insertion Control"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM1_EXTTRIG,FTM External Trigger"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40039000+0x54))&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,Channels Polarity"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,Channels Polarity"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM1_FMS,Fault Mode Status"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "No fault,Fault"
|
|
bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Fault Inputs OR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "No fault,Fault"
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "No fault,Fault"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "No fault,Fault"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "No fault,Fault"
|
|
line.long 0x04 "FTM1_FILTER,Input Capture Filter Control"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40039000+0x54))&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM1_CONF,Configuration"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,Debug Mode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency - ratio of counter overflows : TOF bit is set" "Each overflow,Not next,Not 2 next,Not 3 next,Not 4 next,Not 5 next,Not 6 next,Not 7 next,Not 8 next,Not 9 next,Not 10 next,Not 11 next,Not 12 next,Not 13 next,Not 14 next,Not 15 next,Not 16 next,Not 17 next,Not 18 next,Not 19 next,Not 20 next,Not 21 next,Not 22 next,Not 23 next,Not 24 next,Not 25 next,Not 26 next,Not 27 next,Not 28 next,Not 29 next,Not 30 next,Not 31 next"
|
|
if (((per.l(ad:0x40039000+0x54))&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active Low"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active Low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM1_SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. " HWSOC ,SWOCTRL synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 19. " HWINVC ,INVCTRL synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " HWOM ,OUTMASK synchronization is activated by a hardware trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM synchronization is activated by a hardware trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSOC ,SWOCTRL synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 11. " SWINVC ,INVCTRL synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 10. " SWOM ,OUTMASK synchronization is activated by the software trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWOM ,MOD CNTIN and CV synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy PWM,Enhanced PWM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "All rising edges,PWM"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "All rising edges,PWM"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "All rising edges,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode - TRIGj bit clearing when the hardware trigger j is detected" "Enabled,Disabled"
|
|
line.long 0x04 "FTM1_INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x04 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x08 9. " CH1OCV ,Channel 1 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 8. " CH0OCV ,Channel 0 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM1_PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x0C 9. " LDOK ,MOD CNTIN CV Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " CH1SEL ,Channel 1 Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 0. " CH0SEL ,Channel 0 Select" "Not selected,Selected"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "FTM2"
|
|
base ad:0x4003A000
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,FTM2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM2_MOD,FTM2 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C2V,FTM2 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM2_C3V,FTM2 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status And Control Register"
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C4V,FTM2 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status And Control Register"
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "FTM2_C5V,FTM2 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "FTM2_C6SC,FTM2 Channel 6 Status And Control Register"
|
|
group.long (0x3C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C6V,FTM2 Channel 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "FTM2_C7SC,FTM2 Channel 7 Status And Control Register"
|
|
group.long (0x44+0x04)++0x03
|
|
line.long 0x00 "FTM2_C7V,FTM2 Channel 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM2_MOD_MIRROR,FTM2 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM2_C0V_MIRROR,FTM2 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM2_C1V_MIRROR,FTM2 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM2_C2V_MIRROR,FTM2 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM2_C3V_MIRROR,FTM2 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FTM2_C4V_MIRROR,FTM2 Mirror of Channel 4 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 4 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "FTM2_C5V_MIRROR,FTM2 Mirror of Channel 5 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 5 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "FTM2_C6V_MIRROR,FTM2 Mirror of Channel 6 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 6 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "FTM2_C7V_MIRROR,FTM2 Mirror of Channel 7 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 7 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
elif (cpuis("MKE1?F???VLH16"))
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,FTM2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM2_MOD,FTM2 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C2V,FTM2 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM2_C3V,FTM2 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status And Control Register"
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C4V,FTM2 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status And Control Register"
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "FTM2_C5V,FTM2 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM2_MOD_MIRROR,FTM2 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM2_C0V_MIRROR,FTM2 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM2_C1V_MIRROR,FTM2 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM2_C2V_MIRROR,FTM2 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM2_C3V_MIRROR,FTM2 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FTM2_C4V_MIRROR,FTM2 Mirror of Channel 4 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 4 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "FTM2_C5V_MIRROR,FTM2 Mirror of Channel 5 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 5 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
elif (cpuis("MKE1?Z*"))
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,FTM2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM2_MOD,FTM2 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C2V,FTM2 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM2_C3V,FTM2 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM2_HCR,FTM2 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM2_MOD_MIRROR,FTM2 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM2_C0V_MIRROR,FTM2 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM2_C1V_MIRROR,FTM2 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM2_C2V_MIRROR,FTM2 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM2_C3V_MIRROR,FTM2 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM2_SC,Status And Control"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
line.long 0x04 "FTM2_MOD,Modulo"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo Value"
|
|
textline " "
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM2_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM2_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM2_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "FTM2_C4V,Channel 4 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "FTM2_C5V,Channel 5 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM2_STATUS,Capture And Compare Status"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,Software:MOD/CnV Hardware:FTM/OUTMASK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Manual/even channels,Manual/all channels,Automatic/all channels"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,Software:MOD/CnV Hardware:FTM/OUTMASK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "None,OUTINIT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x8C)&0x80)==0x00))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FTM2_SYNC,Synchronization"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "Clk rising edges,PWM synch."
|
|
bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FTM2_SYNC,Synchronization"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "Clk rising edges,PWM synch."
|
|
textline " "
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "FTM2_OUTINIT,Initial State For Channels Output"
|
|
bitfld.long 0x00 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1"
|
|
bitfld.long 0x00 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1"
|
|
bitfld.long 0x00 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1"
|
|
bitfld.long 0x00 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1"
|
|
bitfld.long 0x00 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1"
|
|
line.long 0x04 "FTM2_OUTMASK,Output Mask"
|
|
bitfld.long 0x04 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04)
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "FTM2_COMBINE,Function For Linked Channels"
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For Registers C4V and C5V" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For Channel 4" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complement Of Channel 4 and 5" "Not complement,Complement"
|
|
textline " "
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For Channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For Registers C2V and C3V" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For Channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For Channel 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complement Of Channel 2 and 3" "Not complement,Complement"
|
|
textline " "
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For Channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For Registers C0V and C1V" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For Channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For Channel 0" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complement Of Channel 0 and 1" "Not complement,Complement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
line.long 0x04 "FTM2_DEADTIME,Deadtime Insertion Control"
|
|
bitfld.long 0x04 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x04 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,Function For Linked Channels"
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For Registers C4V and C5V" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For Channel 4" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complement Of Channel 4 and 5" "Not complement,Complement"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For Channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For Registers C2V and C3V" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For Channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For Channel 2" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For Channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complement Of Channel 2 and 3" "Not complement,Complement"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For Channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For Registers C0V and C1V" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For Channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For Channel 0" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For Channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complement Of Channel 0 and 1" "Not complement,Complement"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,Deadtime Insertion Control"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM2_EXTTRIG,FTM External Trigger"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,Channels Polarity"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,Channels Polarity"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM2_FMS,Fault Mode Status"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "No fault,Fault"
|
|
bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Fault Inputs OR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "No fault,Fault"
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "No fault,Fault"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "No fault,Fault"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "No fault,Fault"
|
|
line.long 0x04 "FTM2_FILTER,Input Capture Filter Control"
|
|
bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,Configuration"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,Debug Mode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency - ratio of counter overflows : TOF bit is set" "Each overflow,Not next,Not 2 next,Not 3 next,Not 4 next,Not 5 next,Not 6 next,Not 7 next,Not 8 next,Not 9 next,Not 10 next,Not 11 next,Not 12 next,Not 13 next,Not 14 next,Not 15 next,Not 16 next,Not 17 next,Not 18 next,Not 19 next,Not 20 next,Not 21 next,Not 22 next,Not 23 next,Not 24 next,Not 25 next,Not 26 next,Not 27 next,Not 28 next,Not 29 next,Not 30 next,Not 31 next"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active Low"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active Low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active Low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM2_SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. " HWSOC ,SWOCTRL synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 19. " HWINVC ,INVCTRL synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " HWOM ,OUTMASK synchronization is activated by a hardware trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV synchronization is activated by a hardware trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM synchronization is activated by a hardware trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSOC ,SWOCTRL synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 11. " SWINVC ,INVCTRL synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 10. " SWOM ,OUTMASK synchronization is activated by the software trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWOM ,MOD CNTIN and CV synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM synchronization is activated by the software trigger" "No,Yes"
|
|
bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy PWM,Enhanced PWM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "All rising edges,PWM"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "All rising edges,PWM"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "All rising edges,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode - TRIGj bit clearing when the hardware trigger j is detected" "Enabled,Disabled"
|
|
line.long 0x04 "FTM2_INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x04 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x08 13. " CH5OCV ,Channel 5 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 12. " CH4OCV ,Channel 4 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 11. " CH3OCV ,Channel 3 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 10. " CH2OCV ,Channel 2 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 9. " CH1OCV ,Channel 1 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 8. " CH0OCV ,Channel 0 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM2_PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x0C 9. " LDOK ,MOD CNTIN CV Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " CH5SEL ,Channel 5 Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 4. " CH4SEL ,Channel 4 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CH3SEL ,Channel 3 Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 2. " CH2SEL ,Channel 2 Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 1. " CH1SEL ,Channel 1 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CH0SEL ,Channel 0 Select" "Not selected,Selected"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "FTM3"
|
|
base ad:0x40026000
|
|
; Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0.
|
|
width 16.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM3_SC,FTM3 Status And Control Register"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM3_CNT,FTM3 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM3_MOD,FTM3 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register"
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "FTM3_C0V,FTM3 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register"
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "FTM3_C1V,FTM3 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register"
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "FTM3_C2V,FTM3 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register"
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "FTM3_C3V,FTM3 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register"
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "FTM3_C4V,FTM3 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register"
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "FTM3_C5V,FTM3 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register"
|
|
group.long (0x3C+0x04)++0x03
|
|
line.long 0x00 "FTM3_C6V,FTM3 Channel 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register"
|
|
group.long (0x44+0x04)++0x03
|
|
line.long 0x00 "FTM3_C7V,FTM3 Channel 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM3_CNTIN,FTM3 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register"
|
|
if ((per.l(ad:0x40026000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Automatic enabled"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM3_SYNC,FTM3 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM3_OUTINIT,FTM3 Initial State For Channels Output Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM3_OUTMASK,FTM3 Output Mask Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if ((per.l(ad:0x40026000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register"
|
|
sif cpuis("MKE1?F???VLL16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v,c7v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v,c5v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v,c3v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v,c1v)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x40026000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "FTM3_EXTTRIG,FTM3 External Trigger Register"
|
|
if ((per.l(ad:0x40026000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
elif cpuis("MKE1?F???VLH16")
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
else
|
|
endif
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "FTM3_FMS,FTM3 Fault Mode Status Register"
|
|
in
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,FTM3 Input Capture Filter Control Register"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
endif
|
|
if ((per.l(ad:0x40026000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control"
|
|
bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control"
|
|
rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM3_CONF,FTM3 Configuration Register"
|
|
bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " LDFQ ,Load Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x40026000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
sif (cpuis("MKE1?F???VLL16")||cpuis("MKE1?F???VLH16"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FTM3_SYNCONF,FTM3 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear"
|
|
sif (cpuis("MKE1?F???VLL16"))
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM3_INVCTRL,FTM3 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM3_SWOCTRL,FTM3 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM3_PWMLOAD,FTM3 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM3_HCR,FTM3 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
elif cpuis("MKE1?F???VLH16")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM3_INVCTRL,FTM3 Inverting Control Register"
|
|
bitfld.long 0x00 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM3_SWOCTRL,FTM3 Software Output Control Register"
|
|
bitfld.long 0x04 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x04 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x04 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x04 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM3_PWMLOAD,FTM3 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x08 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x08 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
bitfld.long 0x08 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM3_HCR,FTM3 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "FTM3_INVCTRL,FTM3 Inverting Control Register"
|
|
bitfld.long 0x00 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM3_SWOCTRL,FTM3 Software Output Control Register"
|
|
bitfld.long 0x04 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x04 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x04 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x04 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM3_PWMLOAD,FTM3 PWM Load Register"
|
|
eventfld.long 0x08 11. " GLDOK ,Global load OK" "No action,LDOK"
|
|
bitfld.long 0x08 10. " GLEN ,Global load enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x08 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x08 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
bitfld.long 0x08 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
line.long 0x0C "FTM3_HCR,FTM3 Half Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HCVAL ,Half cycle value"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FTM3_MOD_MIRROR,FTM3 Mirror of Modulo Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACMOD ,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FTM3_C0V_MIRROR,FTM3 Mirror of Channel 0 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 0 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "FTM3_C1V_MIRROR,FTM3 Mirror of Channel 1 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 1 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FTM3_C2V_MIRROR,FTM3 Mirror of Channel 2 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 2 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FTM3_C3V_MIRROR,FTM3 Mirror of Channel 3 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 3 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FTM3_C4V_MIRROR,FTM3 Mirror of Channel 4 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 4 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "FTM3_C5V_MIRROR,FTM3 Mirror of Channel 5 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 5 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "FTM3_C6V_MIRROR,FTM3 Mirror of Channel 6 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 6 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "FTM3_C7V_MIRROR,FTM3 Mirror of Channel 7 Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the Channel 7 Match Integer Value"
|
|
bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "LPIT (Low-power Periodic Interrupt Timer)"
|
|
base ad:0x40037000
|
|
width 22.
|
|
endian.be
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EXT_TRIG ,Number of external trigger inputs"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHANNEL ,Number of timer channels"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. " DBG_EN ,Debug enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SW_RST ,Software reset bit" "No reset,Reset"
|
|
bitfld.long 0x00 0. " M_CEN ,Module clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "MSR,Module Status Register"
|
|
eventfld.long 0x04 3. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x08 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x08 3. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TVAL0,Timer Value Register"
|
|
rgroup.long (0x20+0x04)++0x03
|
|
line.long 0x00 "CVAL0,Current Timer Value"
|
|
if (((per.l.be(ad:0x40031000+0x20+0x08))&0x01)==0x00)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCTRL0,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCTRL0,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TVAL1,Timer Value Register"
|
|
rgroup.long (0x30+0x04)++0x03
|
|
line.long 0x00 "CVAL1,Current Timer Value"
|
|
if (((per.l.be(ad:0x40031000+0x30+0x08))&0x01)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "TCTRL1,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "TCTRL1,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TVAL2,Timer Value Register"
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CVAL2,Current Timer Value"
|
|
if (((per.l.be(ad:0x40031000+0x40+0x08))&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCTRL2,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCTRL2,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TVAL3,Timer Value Register"
|
|
rgroup.long (0x50+0x04)++0x03
|
|
line.long 0x00 "CVAL3,Current Timer Value"
|
|
if (((per.l.be(ad:0x40031000+0x50+0x08))&0x01)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "TCTRL3,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "TCTRL3,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4"))
|
|
tree "PWT (Pulse Width Timer)"
|
|
base ad:0x40033000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWT_R1,Pulse Width Timer Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " PPW ,Positive Pulse Width"
|
|
bitfld.long 0x00 15. " PCLKS ,PWT Clock Source Selection" "Bus clk,Alternative clk"
|
|
bitfld.long 0x00 13.--14. " PINSEL ,PWT Pulse Inputs Selection" "PWTIN[0],PWTIN[1],PWTIN[2],PWTIN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " EDGE ,PWT input edge sensitivity (first edge,all subsequent edges) " "Falling/Falling,Rising/All edges,Falling/All edges,Rising/Rising"
|
|
bitfld.long 0x00 8.--10. " PRE ,PWT Clock Pre-scaler(CLKPRE) Setting" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 7. " PWTEN ,PWT Module Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWTIE ,PWT module interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRDYIE ,PWT Pulse Width Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " POVIE ,PWT counter overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWTSR ,PWT Soft Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " PWTRDY ,PWT pulse width valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " PWTOV ,PWT counter overflow" "No overflow,Overflow"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PWT_R2,Pulse Width Timer Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " PWTC ,PWT counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " NPW ,Negative Pulse Width"
|
|
width 0xB
|
|
tree.end
|
|
elif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
tree "PWT (Pulse Width Timer)"
|
|
base ad:0x40056000
|
|
width 10.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "PWT_CS,Pulse Width Timer Control and Status Register"
|
|
bitfld.byte 0x00 7. " PWTEN ,PWT Module Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PWTIE ,PWT Module Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PRDYIE ,PWT Pulse Width Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " POVIE ,PWT Counter Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PWTSR ,PWT Soft Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 2. " FCTLE ,First counter load enable after enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PWTRDY ,PWT Pulse Width Valid" "Not updated,Updated"
|
|
bitfld.byte 0x00 0. " PWTOV ,PWT Counter Overflow" "Not overflowed,Overflowed"
|
|
line.byte 0x01 "PWT_CR,Pulse Width Timer Control Register"
|
|
bitfld.byte 0x01 7. " PCLKS ,PWT Clock Source Selection" "BUS_CLK,Alternative clk"
|
|
bitfld.byte 0x01 5.--6. " PINSEL ,PWT Pulse Inputs Selection" "PWTIN[0],PWTIN[1],PWTIN[2],PWTIN[3]"
|
|
eventfld.byte 0x01 4. " TGL ,PWTIN states Toggled from last state" "Not toggled,Toggled"
|
|
rbitfld.byte 0x01 3. " LVL ,PWTIN Level when Overflows" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x01 0.--2. " PRE ,PWT Clock Prescaler (CLKPRE) Setting" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
rgroup.byte 0x02++0x05
|
|
line.byte 0x00 "PWT_PPH,Pulse Width Timer Positive Pulse Width Register: High"
|
|
line.byte 0x01 "PWT_PPL,Pulse Width Timer Positive Pulse Width Register: Low"
|
|
line.byte 0x02 "PWT_NPH,Pulse Width Timer Negative Pulse Width Register: High"
|
|
line.byte 0x03 "PWT_NPL,Pulse Width Timer Negative Pulse Width Register: Low"
|
|
line.byte 0x04 "PWT_CNTH,Pulse Width Timer Counter Register: High"
|
|
line.byte 0x05 "PWT_CNTL,Pulse Width Timer Counter Register: Low"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPTMR (Low Power Timer)"
|
|
base ad:0x40040000
|
|
width 5.
|
|
if (((per.l(ad:0x40040000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equal,Equal"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active-high/Rising-edge,Active-low/Falling-edge"
|
|
bitfld.long 0x00 2. " TFC ,Timer Free-Running counter" "Reset whenever TCF is set,Reset on overflow"
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equal,Equal"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active-high/rising-edge,Active-low/falling-edge"
|
|
rbitfld.long 0x00 2. " TFC ,Timer Free-Running counter" "Reset whenever TCF is set,Reset on overflow"
|
|
rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40040000))&0x03)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Enabled,Bypassed"
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "0,1,2,3"
|
|
elif (((per.l(ad:0x40040000))&0x03)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
rbitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
rbitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Enabled,Bypassed"
|
|
else
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Enabled,Bypassed"
|
|
endif
|
|
rbitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "0,1,2,3"
|
|
elif (((per.l(ad:0x40040000))&0x03)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Glitch filter value" "Disabled,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Enabled,Bypassed"
|
|
bitfld.long 0x00 0.--1. " PCS ,Glitch filter clock select" "0,1,2,3"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S"))
|
|
rbitfld.long 0x00 3.--6. " PRESCALE ,Glitch filter value" "Disabled,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
rbitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Enabled,Bypassed"
|
|
else
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Glitch filter value" "Disabled,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Enabled,Bypassed"
|
|
endif
|
|
rbitfld.long 0x00 0.--1. " PCS ,Glitch filter clock select" "0,1,2,3"
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
line.long 0x04 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNTER ,Counter value"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
tree "PIT (Periodic Interrupt Timer)"
|
|
base ad:0x40037000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PIT_MCR,PIT Module Control Register"
|
|
bitfld.long 0x00 1. " MDIS ,Module Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Do not freeze,Freeze"
|
|
group.long 0x100++0x03 "PIT0 Registers"
|
|
line.long 0x00 "PIT_LDVAL0,PIT0 Timer Load Value Register"
|
|
rgroup.long (0x100+0x4)++0x03
|
|
line.long 0x00 "PIT_CVAL0,PIT0 Current Timer Value Register"
|
|
group.long (0x100+0x8)++0x03
|
|
line.long 0x00 "PIT_TCTRL0,PIT0 Timer Control Register"
|
|
bitfld.long 0x00 1. " TIE ,Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer Enable" "Disabled,Enabled"
|
|
group.long (0x100+0xC)++0x03
|
|
line.long 0x00 "PIT_TFLG0,PIT0 Timer Flag Register"
|
|
eventfld.long 0x00 0. " TIF ,Timer Interrupt Flag" "No timeout,Timeout"
|
|
group.long 0x110++0x03 "PIT1 Registers"
|
|
line.long 0x00 "PIT_LDVAL1,PIT1 Timer Load Value Register"
|
|
rgroup.long (0x110+0x4)++0x03
|
|
line.long 0x00 "PIT_CVAL1,PIT1 Current Timer Value Register"
|
|
group.long (0x110+0x8)++0x03
|
|
line.long 0x00 "PIT_TCTRL1,PIT1 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain Mode" "Not chained,Chained"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIE ,Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer Enable" "Disabled,Enabled"
|
|
group.long (0x110+0xC)++0x03
|
|
line.long 0x00 "PIT_TFLG1,PIT1 Timer Flag Register"
|
|
eventfld.long 0x00 0. " TIF ,Timer Interrupt Flag" "No timeout,Timeout"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "RTC (Real-Time Counter)"
|
|
base ad:0x4003D000
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
width 5.
|
|
if ((per.l(ad:0x4003D000+0x800)&0x01)==0x01)&&((per.l(ad:0x4003D000+0x804)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x01)==0x01)&&((per.l(ad:0x4003D000+0x804)&0x01)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x01)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x01)==0x01)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "TSR,RTC Time Seconds Register"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x02)==0x02)&&((per.l(ad:0x4003D000+0x804)&0x02)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TPR ,Time prescaler register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x02)==0x02)&&((per.l(ad:0x4003D000+0x804)&0x02)==0x00)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TPR ,Time prescaler register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x02)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x02)==0x02)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TPR ,Time prescaler register"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x04)==0x04)&&((per.l(ad:0x4003D000+0x804)&0x04)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x04)==0x04)&&((per.l(ad:0x4003D000+0x804)&0x04)==0x00)
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x04)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x04)==0x04)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "TAR,RTC Time Alarm Register"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x08)==0x08)&&((per.l(ad:0x4003D000+0x804)&0x08)==0x08)&&((per.l(ad:0x4003D000+0x18)&0x08)==0x08)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CIC ,Compensation interval counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCV ,Time compensation value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CIR ,Compensation interval register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCR ,Time compensation register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x08)==0x08)&&((per.l(ad:0x4003D000+0x804)&0x08)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x08)==0x08)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CIC ,Compensation interval counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCV ,Time compensation value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CIR ,Compensation interval register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCR ,Time compensation register"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x08)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x08)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x08)==0x00)
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x00 "TCR,RTC Time Compensation Register"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CIC ,Compensation interval counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCV ,Time compensation value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CIR ,Compensation interval register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCR ,Time compensation register"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x10)==0x10)&&((per.l(ad:0x4003D000+0x804)&0x10)==0x10)&&((per.l(ad:0x4003D000+0x18)&0x10)==0x10)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24.--25. " CPE ,Clock pin enable" "Disabled,Enabled,?..."
|
|
bitfld.long 0x00 9. " CLKO ,Clock Output" "Allowed,Not allowed"
|
|
bitfld.long 0x00 8. " OSCE ,Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LPOS ,LPO select" "32khz crystal,1khz lpo/prescaler bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32khz crystal"
|
|
bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x10)==0x10)&&((per.l(ad:0x4003D000+0x804)&0x10)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x10)==0x10)
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24.--25. " CPE ,Clock pin enable" "Disabled,Enabled,?..."
|
|
bitfld.long 0x00 9. " CLKO ,Clock Output" "Allowed,Not allowed"
|
|
bitfld.long 0x00 8. " OSCE ,Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LPOS ,LPO select" "32khz crystal,1khz lpo/prescaler bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32khz crystal"
|
|
bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x10)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x10)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x10)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CR,RTC Control Register"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24.--25. " CPE ,Clock pin enable" "Disabled,Enabled,?..."
|
|
bitfld.long 0x00 9. " CLKO ,Clock Output" "Allowed,Not allowed"
|
|
bitfld.long 0x00 8. " OSCE ,Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LPOS ,LPO select" "32khz crystal,1khz lpo/prescaler bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32khz crystal"
|
|
bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x20)==0x20)&&((per.l(ad:0x4003D000+0x804)&0x20)==0x20)&&((per.l(ad:0x4003D000+0x18)&0x20)==0x20)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SR,RTC Status Register"
|
|
bitfld.long 0x00 4. " TCE ,Time Counter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " TAF ,Time Alarm Flag" "No alarm,Alarm"
|
|
rbitfld.long 0x00 1. " TOF ,Time Overflow Flag" "No overflow,Overflow"
|
|
rbitfld.long 0x00 0. " TIF ,Time Invalid Flag" "Valid,Invalid"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x20)==0x20)&&((per.l(ad:0x4003D000+0x804)&0x20)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x20)==0x20)
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "SR,RTC Status Register"
|
|
bitfld.long 0x00 4. " TCE ,Time Counter Enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x20)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x20)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x20)==0x00)
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SR,RTC Status Register"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SR,RTC Status Register"
|
|
bitfld.long 0x00 4. " TCE ,Time Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAF ,Time Alarm Flag" "No alarm,Alarm"
|
|
bitfld.long 0x00 1. " TOF ,Time Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 0. " TIF ,Time Invalid Flag" "Valid,Invalid"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x40)==0x40)&&((per.l(ad:0x4003D000+0x804)&0x40)==0x40)&&((per.l(ad:0x4003D000+0x18)&0x40)==0x40)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LR,RTC Lock Register"
|
|
bitfld.long 0x00 6. " LRL ,Lock Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " SRL ,Status Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " CRL ,Control Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " TCL ,Time Compensation Lock" "Locked,Unlocked"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x40)==0x40)&&((per.l(ad:0x4003D000+0x804)&0x40)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x40)==0x40)
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "LR,RTC Lock Register"
|
|
bitfld.long 0x00 6. " LRL ,Lock Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " SRL ,Status Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " CRL ,Control Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " TCL ,Time Compensation Lock" "Locked,Unlocked"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x40)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x40)==0x00)&&((per.l(ad:0x4003D000+0x18)&0x40)==0x00)
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x00 "LR,RTC Lock Register"
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "LR,RTC Lock Register"
|
|
bitfld.long 0x00 6. " LRL ,Lock Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " SRL ,Status Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " CRL ,Control Register Lock" "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " TCL ,Time Compensation Lock" "Locked,Unlocked"
|
|
endif
|
|
if ((per.l(ad:0x4003D000+0x800)&0x80)==0x80)&&((per.l(ad:0x4003D000+0x804)&0x80)==0x80)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 16.--18. " TSIC ,Timer Seconds Interrupt Configuration" "1 Hz,2 Hz,4 Hz,8 Hz,16 Hz,32 Hz,64 Hz,128 Hz"
|
|
bitfld.long 0x00 4. " TSIE ,Time Seconds Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAIE ,Time Alarm Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TOIE ,Time Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIIE ,Time Invalid Interrupt Enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x80)==0x80)&&((per.l(ad:0x4003D000+0x804)&0x80)==0x00)
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 16.--18. " TSIC ,Timer Seconds Interrupt Configuration" "1 Hz,2 Hz,4 Hz,8 Hz,16 Hz,32 Hz,64 Hz,128 Hz"
|
|
bitfld.long 0x00 4. " TSIE ,Time Seconds Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAIE ,Time Alarm Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TOIE ,Time Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIIE ,Time Invalid Interrupt Enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003D000+0x800)&0x80)==0x00)&&((per.l(ad:0x4003D000+0x804)&0x80)==0x80)
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 16.--18. " TSIC ,Timer Seconds Interrupt Configuration" "1 Hz,2 Hz,4 Hz,8 Hz,16 Hz,32 Hz,64 Hz,128 Hz"
|
|
bitfld.long 0x00 4. " TSIE ,Time Seconds Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAIE ,Time Alarm Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TOIE ,Time Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIIE ,Time Invalid Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
endif
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "WAR,RTC Write Access Register"
|
|
bitfld.long 0x00 7. " IERW ,Interrupt Enable Register Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LRW ,Lock Register Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SRW ,Status Register Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CRW ,Control Register Write" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TCRW ,Time Compensation Register Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TARW ,Time Alarm Register Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TPRW ,Time Prescaler Register Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TSRW ,Time Seconds Register Write" "Disabled,Enabled"
|
|
line.long 0x04 "RAR,RTC Read Access Register"
|
|
bitfld.long 0x04 7. " IERR ,Interrupt Enable Register Read" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LRR ,Lock Register Read" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " SRR ,Status Register Read" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CRR ,Control Register Read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TCRR ,Time Compensation Register Read" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TARR ,Time Alarm Register Read" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TPRR ,Time Prescaler Register Read" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TSRR ,Time Seconds Register Read" "Disabled,Enabled"
|
|
width 0x0B
|
|
else
|
|
width 9.
|
|
if ((per.l(ad:0x4003D000)&0x4000)==0x0000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_SC,RTC Status and Control Register"
|
|
bitfld.long 0x00 14.--15. " RTCLKS ,Real-Time Clock Source Select" "External,LPOCLK,ICSIRCLK,BUSCLK"
|
|
bitfld.long 0x00 8.--10. " RTCPS ,Real-Time Clock Prescaler Select" "Off,/1,/2,/4,/8,/16,/32,/64"
|
|
eventfld.long 0x00 7. " RTIF ,Real-Time Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIE ,Real-Time Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTCO ,Real-Time Counter Output" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_SC,RTC Status and Control Register"
|
|
bitfld.long 0x00 14.--15. " RTCLKS ,Real-Time Clock Source Select" "External,LPOCLK,ICSIRCLK,BUSCLK"
|
|
bitfld.long 0x00 8.--10. " RTCPS ,Real-Time Clock Prescaler Select" "Off,/128,/256,/512,/1024,/2048,/100,/1000"
|
|
eventfld.long 0x00 7. " RTIF ,Real-Time Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIE ,Real-Time Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTCO ,Real-Time Counter Output" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_MOD,RTC Modulo Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MOD ,RTC Modulo"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RTC_CNT,RTC Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,RTC Count"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree.open "Communication interfaces"
|
|
sif (!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x40076000
|
|
width 9.
|
|
if ((per.b(ad:0x40076000+0x1)&0x10)==0x10)&&((per.b(ad:0x40076000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000+0x1)&0x10)==0x0)&&((per.b(ad:0x40076000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
if ((per.b(ad:0x40076000)&0x10)==0x10)&&((per.b(ad:0x40076000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x10)&&((per.b(ad:0x40076000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x0)&&((per.b(ad:0x40076000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x0)&&((per.b(ad:0x40076000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR ,SPI Baud Rate Prescale Divisor" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.byte 0x00 0.--3. " SPR ,SPI baud rate divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..."
|
|
hgroup.byte 0x03++0x00
|
|
hide.byte 0x00 "SPI0_S,SPI Status Register"
|
|
in
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SPI0_D,SPI Data Register"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SPI0_M,SPI Match Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40077000
|
|
width 9.
|
|
if ((per.b(ad:0x40077000+0x1)&0x10)==0x10)&&((per.b(ad:0x40077000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000+0x1)&0x10)==0x0)&&((per.b(ad:0x40077000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
if ((per.b(ad:0x40077000)&0x10)==0x10)&&((per.b(ad:0x40077000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x10)&&((per.b(ad:0x40077000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x0)&&((per.b(ad:0x40077000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x0)&&((per.b(ad:0x40077000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal,Bidirectional"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR ,SPI Baud Rate Prescale Divisor" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.byte 0x00 0.--3. " SPR ,SPI baud rate divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..."
|
|
hgroup.byte 0x03++0x00
|
|
hide.byte 0x00 "SPI1_S,SPI Status Register"
|
|
in
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SPI1_D,SPI Data Register"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SPI1_M,SPI Match Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C0"
|
|
base ad:0x40066000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "I2C0_A1,I2C Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,I2C Primary Slave Address"
|
|
line.byte 0x01 "I2C0_F,I2C Frequency Divider register"
|
|
bitfld.byte 0x01 6.--7. " MULT ,I2C Multiplier Factor" "1,2,4,?..."
|
|
bitfld.byte 0x01 0.--5. " ICR ,I2C ClockRate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.b(ad:0x40066000+0x08))&0x80)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C0_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Following Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C0_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Current Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "I2C0_S,I2C Status register"
|
|
rbitfld.byte 0x00 7. " TCF ,Transfer Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 6. " IAAS ,Addressed As A Slave" "Not addressed,Addressed"
|
|
rbitfld.byte 0x00 5. " BUSY ,Bus Busy" "Idle,Busy"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " ARBL ,Arbitration Lost" "Not lost,Lost"
|
|
bitfld.byte 0x00 3. " RAM ,Range Address Match" "Not matched,Matched"
|
|
rbitfld.byte 0x00 2. " SRW ,Slave Read/Write" "Write,Read"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " IICIF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "I2C0_D,I2C Data I/O register"
|
|
IN
|
|
if ((per.b(ad:0x40066000+0x05)&0x40)==0x40)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C0_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif (!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z32VLD2R"))
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C0_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif (!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z32VLD2R"))
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master,Independent"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "I2C0_FLT,I2C Programmable Input Glitch Filter Register"
|
|
bitfld.byte 0x00 7. " SHEN ,Stop Hold Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C Bus Stop Detect Flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C Bus Stop Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " STARTF ,I2C Bus Start Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.b((ad:0x40066000+0x05)))&0x40)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "I2C0_RA,I2C Range Address register"
|
|
hexmask.byte 0x00 1.--7. 0x2 " RAD ,Range slave address"
|
|
else
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "I2C0_RA,I2C Range Address register"
|
|
endif
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "I2C0_SMB,I2C SMBus Control and Status Register"
|
|
bitfld.byte 0x00 7. " FACK ,Fast NACK/ACK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " SIICAEN ,Second I2C address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TCKSEL , Timeout counter clock select" "I2C_clk/64,I2C_clk"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "I2C0_A2,I2C Address Register 2"
|
|
hexmask.byte 0x01 1.--7. 0x2 " SAD ,SMBus address"
|
|
line.byte 0x02 "I2C0_SLTH,I2C SCL Low Timeout Register High"
|
|
line.byte 0x03 "I2C0_SLTL,I2C SCL Low Timeout Register Low"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R")
|
|
tree "I2C1"
|
|
base ad:0x40067000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "I2C1_A1,I2C Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,I2C Primary Slave Address"
|
|
line.byte 0x01 "I2C1_F,I2C Frequency Divider register"
|
|
bitfld.byte 0x01 6.--7. " MULT ,I2C Multiplier Factor" "1,2,4,?..."
|
|
bitfld.byte 0x01 0.--5. " ICR ,I2C ClockRate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.b(ad:0x40067000+0x08))&0x80)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C1_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Following Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C1_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Current Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "I2C1_S,I2C Status register"
|
|
rbitfld.byte 0x00 7. " TCF ,Transfer Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 6. " IAAS ,Addressed As A Slave" "Not addressed,Addressed"
|
|
rbitfld.byte 0x00 5. " BUSY ,Bus Busy" "Idle,Busy"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " ARBL ,Arbitration Lost" "Not lost,Lost"
|
|
bitfld.byte 0x00 3. " RAM ,Range Address Match" "Not matched,Matched"
|
|
rbitfld.byte 0x00 2. " SRW ,Slave Read/Write" "Write,Read"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " IICIF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "I2C1_D,I2C Data I/O register"
|
|
IN
|
|
if ((per.b(ad:0x40067000+0x05)&0x40)==0x40)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C1_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif (!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z32VLD2R"))
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C1_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif (!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z32VLD2R"))
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master,Independent"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "I2C1_FLT,I2C Programmable Input Glitch Filter Register"
|
|
bitfld.byte 0x00 7. " SHEN ,Stop Hold Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C Bus Stop Detect Flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C Bus Stop Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " STARTF ,I2C Bus Start Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.b((ad:0x40067000+0x05)))&0x40)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "I2C1_RA,I2C Range Address register"
|
|
hexmask.byte 0x00 1.--7. 0x2 " RAD ,Range slave address"
|
|
else
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "I2C1_RA,I2C Range Address register"
|
|
endif
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "I2C1_SMB,I2C SMBus Control and Status Register"
|
|
bitfld.byte 0x00 7. " FACK ,Fast NACK/ACK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " SIICAEN ,Second I2C address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TCKSEL , Timeout counter clock select" "I2C_clk/64,I2C_clk"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "I2C1_A2,I2C Address Register 2"
|
|
hexmask.byte 0x01 1.--7. 0x2 " SAD ,SMBus address"
|
|
line.byte 0x02 "I2C1_SLTH,I2C SCL Low Timeout Register High"
|
|
line.byte 0x03 "I2C1_SLTL,I2C SCL Low Timeout Register Low"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
tree "MSCAN (Freescale's Scalable Controller Area Network)"
|
|
base ad:0x40024000
|
|
width 16.
|
|
if ((per.b(ad:0x40024000)&0x01)==0x00)&&((per.b(ad:0x40024000+0x01)&0x21)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL0,MSCAN Control Register 0"
|
|
eventfld.byte 0x00 7. " RXFRM ,Received Frame Flag" "No valid,Valid"
|
|
rbitfld.byte 0x00 6. " RXACT ,Receiver Active Status" "Transmitting/Idle,Receiving"
|
|
bitfld.byte 0x00 5. " CSWAI ,CAN Stops in Wait Mode" "No,Yes"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized"
|
|
bitfld.byte 0x00 3. " TIME ,Timer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WUPE ,WakeUp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SLPRQ ,Sleep Mode Request" "Normal,Sleep mode"
|
|
bitfld.byte 0x00 0. " INITRQ ,Initialization Mode Request" "Normal,Initialization"
|
|
elif ((per.b(ad:0x40024000)&0x01)==0x00)&&((per.b(ad:0x40024000+0x01)&0x21)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL0,MSCAN Control Register 0"
|
|
bitfld.byte 0x00 5. " CSWAI ,CAN Stops in Wait Mode" "No,Yes"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized"
|
|
bitfld.byte 0x00 3. " TIME ,Timer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WUPE ,WakeUp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SLPRQ ,Sleep Mode Request" "Normal,Sleep mode"
|
|
bitfld.byte 0x00 0. " INITRQ ,Initialization Mode Request" "Normal,Initialization"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL0,MSCAN Control Register 0"
|
|
rbitfld.byte 0x00 7. " RXFRM ,Received Frame Flag" "No valid,Valid"
|
|
rbitfld.byte 0x00 6. " RXACT ,Receiver Active Status" "Transmitting/Idle,Receiving"
|
|
rbitfld.byte 0x00 5. " CSWAI ,CAN Stops in Wait Mode" "No,Yes"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized"
|
|
rbitfld.byte 0x00 3. " TIME ,Timer Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " WUPE ,WakeUp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SLPRQ ,Sleep Mode Request" "Normal,Sleep mode"
|
|
bitfld.byte 0x00 0. " INITRQ ,Initialization Mode Request" "Normal,Initialization"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x05)==0x05)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL1,MSCAN Control Register 1"
|
|
bitfld.byte 0x00 7. " CANE ,MSCAN Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CLKSRC ,MSCAN Clock Source" "Oscillator,Bus"
|
|
bitfld.byte 0x00 5. " LOOPB ,Loopback Self Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LISTEN ,Listen Only Mode" "Normal,Activated"
|
|
bitfld.byte 0x00 3. " BORM ,Bus-Off Recovery Mode" "Automatic,Manual"
|
|
bitfld.byte 0x00 2. " WUPM ,WakeUp Mode" "Any level,T_wup"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SLPAK ,Sleep Mode Acknowledge" "Not acknowledge,Acknowledged"
|
|
bitfld.byte 0x00 0. " INITAK ,Initialization Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
elif ((per.b(ad:0x40024000)&0x05)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL1,MSCAN Control Register 1"
|
|
bitfld.byte 0x00 7. " CANE ,MSCAN Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CLKSRC ,MSCAN Clock Source" "Oscillator,Bus"
|
|
bitfld.byte 0x00 5. " LOOPB ,Loopback Self Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LISTEN ,Listen Only Mode" "Normal,Activated"
|
|
bitfld.byte 0x00 3. " BORM ,Bus-Off Recovery Mode" "Automatic,Manual"
|
|
bitfld.byte 0x00 1. " SLPAK ,Sleep Mode Acknowledge" "Not acknowledge,Acknowledged"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " INITAK ,Initialization Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL1,MSCAN Control Register 1"
|
|
bitfld.byte 0x00 7. " CANE ,MSCAN Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CLKSRC ,MSCAN Clock Source" "Oscillator,Bus"
|
|
bitfld.byte 0x00 5. " LOOPB ,Loopback Self Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LISTEN ,Listen Only Mode" "Normal,Activated"
|
|
bitfld.byte 0x00 3. " BORM ,Bus-Off Recovery Mode" "Automatic,Manual"
|
|
bitfld.byte 0x00 2. " WUPM ,WakeUp Mode" "Any level,T_wup"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SLPAK ,Sleep Mode Acknowledge" "Not acknowledge,Acknowledged"
|
|
bitfld.byte 0x00 0. " INITAK ,Initialization Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR0,MSCAN Bus Timing Register 0"
|
|
bitfld.byte 0x00 6.--7. " SJW ,Synchronization Jump Width" "1 Tq cycle,2 Tq cycles,3 Tq cycles,4 Tq cycles"
|
|
bitfld.byte 0x00 0.--5. " BRP ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
else
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR0,MSCAN Bus Timing Register 0"
|
|
bitfld.byte 0x00 6.--7. " SJW ,Synchronization Jump Width" "1 Tq cycle,2 Tq cycles,3 Tq cycles,4 Tq cycles"
|
|
bitfld.byte 0x00 0.--5. " BRP ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR1,MSCAN Bus Timing Register 1"
|
|
bitfld.byte 0x00 7. " SAMP ,Sampling" "1 sample,3 samples"
|
|
bitfld.byte 0x00 4.--6. " TSEG2 ,Time Segment 2" ",2 Tq cycles,3 Tq cycles,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles"
|
|
bitfld.byte 0x00 0.--3. " TSEG1 ,Time Segment 1" ",,,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles,9 Tq cycles,10 Tq cycles,11 Tq cycles,12 Tq cycles,13 Tq cycles,14 Tq cycles,15 Tq cycles,16 Tq cycles"
|
|
else
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR1,MSCAN Bus Timing Register 1"
|
|
bitfld.byte 0x00 7. " SAMP ,Sampling" "1 sample,3 samples"
|
|
bitfld.byte 0x00 4.--6. " TSEG2 ,Time Segment 2" ",2 Tq cycles,3 Tq cycles,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles"
|
|
bitfld.byte 0x00 0.--3. " TSEG1 ,Time Segment 1" ",,,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles,9 Tq cycles,10 Tq cycles,11 Tq cycles,12 Tq cycles,13 Tq cycles,14 Tq cycles,15 Tq cycles,16 Tq cycles"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "MSCAN_CANRFLG,MSCAN Receiver Flag Register"
|
|
bitfld.byte 0x00 7. " WUPIF ,Wake-Up Interrupt Flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 6. " CSCIF ,CAN Status Change Interrupt Flag" "No occurred,Occurred"
|
|
bitfld.byte 0x00 4.--5. " RSTAT ,Receiver Status" "RxOK,RxWRN,RxERR,Bus-off"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTAT ,Transmitter Status" "TxOK,TxWRN,TxERR,Bus-off"
|
|
bitfld.byte 0x00 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 0. " RXF ,Receive Buffer Full Flag" "Empty,Not empty"
|
|
elif ((per.b(ad:0x40024000)&0x04)==0x04)&&((per.b(ad:0x40024000)&0x02)==0x02)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "MSCAN_CANRFLG,MSCAN Receiver Flag Register"
|
|
bitfld.byte 0x00 7. " WUPIF ,Wake-Up Interrupt Flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 6. " CSCIF ,CAN Status Change Interrupt Flag" "No occurred,Occurred"
|
|
bitfld.byte 0x00 4.--5. " RSTAT ,Receiver Status" "RxOK,RxWRN,RxERR,Bus-off"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTAT ,Transmitter Status" "TxOK,TxWRN,TxERR,Bus-off"
|
|
bitfld.byte 0x00 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 0. " RXF ,Receive Buffer Full Flag" "Empty,Not empty"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "MSCAN_CANRFLG,MSCAN Receiver Flag Register"
|
|
bitfld.byte 0x00 6. " CSCIF ,CAN Status Change Interrupt Flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 4.--5. " RSTAT ,Receiver Status" "RxOK,RxWRN,RxERR,Bus-off"
|
|
bitfld.byte 0x00 2.--3. " TSTAT ,Transmitter Status" "TxOK,TxWRN,TxERR,Bus-off"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 0. " RXF ,Receive Buffer Full Flag" "Empty,Not empty"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x05++0x00
|
|
line.byte 0x00 "MSCAN_CANRIER,MSCAN Receiver Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " WUPIE ,WakeUp Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CSCIE ,CAN Status Change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " RSTATE ,Receiver Status Change Enable" "Not generated,Bus-off,RxErr/Bus-off,All"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTATE ,Transmitter Status Change Enable" "Not generated,Bus-off,TxErr/Bus-off,All"
|
|
bitfld.byte 0x00 1. " OVRIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXFIE ,Receiver Full Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MSCAN_CANRIER,MSCAN Receiver Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " WUPIE ,WakeUp Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CSCIE ,CAN Status Change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " RSTATE ,Receiver Status Change Enable" "Not generated,Bus-off,RxErr/Bus-off,All"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTATE ,Transmitter Status Change Enable" "Not generated,Bus-off,TxErr/Bus-off,All"
|
|
bitfld.byte 0x00 1. " OVRIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXFIE ,Receiver Full Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "MSCAN_CANTFLG,MSCAN Transmitter Flag Register"
|
|
bitfld.byte 0x00 2. " TXE2 ,Transmitter Buffer 2 Empty" "Full,Empty"
|
|
bitfld.byte 0x00 1. " TXE1 ,Transmitter Buffer 1 Empty" "Full,Empty"
|
|
bitfld.byte 0x00 0. " TXE0 ,Transmitter Buffer 0 Empty" "Full,Empty"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "MSCAN_CANTFLG,MSCAN Transmitter Flag Register"
|
|
bitfld.byte 0x00 2. " TXE2 ,Transmitter Buffer 2 Empty" "Full,Empty"
|
|
bitfld.byte 0x00 1. " TXE1 ,Transmitter Buffer 1 Empty" "Full,Empty"
|
|
bitfld.byte 0x00 0. " TXE0 ,Transmitter Buffer 0 Empty" "Full,Empty"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "MSCAN_CANTIER,MSCAN Transmitter Interrupt Enable Register"
|
|
bitfld.byte 0x00 2. " TXEIE2 ,Transmitter 2 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TXEIE1 ,Transmitter 1 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXEIE0 ,Transmitter 0 Empty Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "MSCAN_CANTIER,MSCAN Transmitter Interrupt Enable Register"
|
|
bitfld.byte 0x00 2. " TXEIE2 ,Transmitter 2 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TXEIE1 ,Transmitter 1 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXEIE0 ,Transmitter 0 Empty Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "MSCAN_CANTARQ,MSCAN Transmitter Message Abort Request Register"
|
|
bitfld.byte 0x00 2. " ABTRQ2 ,Abort 2 Request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " ABTRQ1 ,Abort 1 Request" "Not requested,Requested"
|
|
bitfld.byte 0x00 0. " ABTRQ0 ,Abort 0 Request" "Not requested,Requested"
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "MSCAN_CANTARQ,MSCAN Transmitter Message Abort Request Register"
|
|
bitfld.byte 0x00 2. " ABTRQ2 ,Abort 2 Request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " ABTRQ1 ,Abort 1 Request" "Not requested,Requested"
|
|
bitfld.byte 0x00 0. " ABTRQ0 ,Abort 0 Request" "Not requested,Requested"
|
|
endif
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "MSCAN_CANTAAK,MSCAN Transmitter Message Abort Acknowledge Register"
|
|
bitfld.byte 0x00 2. " ABTAK2 ,Abort Acknowledge" "Not aborted,Aborted"
|
|
bitfld.byte 0x00 1. " ABTAK1 ,Abort Acknowledge" "Not aborted,Aborted"
|
|
bitfld.byte 0x00 0. " ABTAK0 ,Abort Acknowledge" "Not aborted,Aborted"
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x0A++0x01
|
|
line.byte 0x00 "MSCAN_CANTBSEL,MSCAN Transmit Buffer Selection Register"
|
|
bitfld.byte 0x00 2. " TX2 ,Transmit Buffer 2 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 1. " TX1 ,Transmit Buffer 1 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " TX0 ,Transmit Buffer 0 Select" "Not selected,Selected"
|
|
else
|
|
group.byte 0x0A++0x01
|
|
line.byte 0x00 "MSCAN_CANTBSEL,MSCAN Transmit Buffer Selection Register"
|
|
bitfld.byte 0x00 2. " TX2 ,Transmit Buffer 2 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 1. " TX1 ,Transmit Buffer 1 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " TX0 ,Transmit Buffer 0 Select" "Not selected,Selected"
|
|
endif
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAC,MSCAN Identifier Acceptance Control Register"
|
|
bitfld.byte 0x00 4.--5. " IDAM ,Identifier Acceptance Mode" "2x(32-bit) filters,4x(16-bit) filters,8x(8-bit) filters,Filter closed"
|
|
rbitfld.byte 0x00 0.--2. " IDHIT ,Identifier Acceptance Hit Indicator" "0,1,2,3,4,5,6,7"
|
|
if ((per.b(ad:0x40024000+0x01)&0x08)==0x08)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "MSCAN_CANMISC,MSCAN Miscellaneous Register"
|
|
eventfld.byte 0x00 0. " BOHOLD ,Bus-off State Hold Until User Request" "Not bus-off/Recovery,Bus-off & Others state"
|
|
else
|
|
rgroup.byte 0x0D++0x00
|
|
line.byte 0x00 "MSCAN_CANMISC,MSCAN Miscellaneous Register"
|
|
eventfld.byte 0x00 0. " BOHOLD ,Bus-off State Hold Until User Request" "Not bus-off/Recovery,Bus-off & Others state"
|
|
endif
|
|
width 16.
|
|
if (((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01))||(((per.b(ad:0x40024000)&0x02)==0x02)&&((per.b(ad:0x40024000+0x01)&0x02)==0x02))
|
|
rgroup.byte 0x0E++0x01
|
|
line.byte 0x00 "MSCAN_CANRXERR,MSCAN Receive Error Counter"
|
|
line.byte 0x01 "MSCAN_CANTXERR,MSCAN Transmit Error Counter"
|
|
else
|
|
hgroup.byte 0x0E++0x01
|
|
hide.byte 0x00 "MSCAN_CANRXERR,MSCAN Receive Error Counter"
|
|
hide.byte 0x01 "MSCAN_CANTXERR,MSCAN Transmit Error Counter"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR0,MSCAN Identifier Acceptance Register 0 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR1,MSCAN Identifier Acceptance Register 1 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR2,MSCAN Identifier Acceptance Register 2 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR3,MSCAN Identifier Acceptance Register 3 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR4,MSCAN Identifier Mask Register 4 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR5,MSCAN Identifier Mask Register 5 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR6,MSCAN Identifier Mask Register 6 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR7,MSCAN Identifier Mask Register 7 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR0,MSCAN Identifier Acceptance Register 0 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR1,MSCAN Identifier Acceptance Register 1 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR2,MSCAN Identifier Acceptance Register 2 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR3,MSCAN Identifier Acceptance Register 3 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "No,Yes"
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "No,Yes"
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "No,Yes"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR4,MSCAN Identifier Mask Register 4 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR5,MSCAN Identifier Mask Register 5 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR6,MSCAN Identifier Mask Register 6 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR7,MSCAN Identifier Mask Register 7 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
width 14.
|
|
if ((per.b(ad:0x40024000+0x21)&0x08)==0x08)
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MSCAN_REIDR0,Receive Extended Identifier Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MSCAN_REIDR1,Receive Extended Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " REID20_REID18 ,Extended Format Identifier 20-18" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RSRR ,Substitute Remote Request" "None,Transmission buffers"
|
|
bitfld.byte 0x00 3. " REIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
bitfld.byte 0x00 0.--2. " REID17_REID15 ,Extended Format Identifier 17-15" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "MSCAN_REIDR2,Receive Extended Identifier Register 2"
|
|
line.byte 0x01 "MSCAN_REIDR3,Receive Extended Identifier Register 3"
|
|
hexmask.byte 0x01 1.--7. 0x01 " REID6_REID0 ,Extended Format Identifier 6-0"
|
|
bitfld.byte 0x01 0. " RERTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
elif ((per.b(ad:0x40024000+0x21)&0x08)==0x00)
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MSCAN_RSIDR0,Receive Standard Identifier Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MSCAN_RSIDR1,Receive Standard Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " RSID2_RSID0 ,Standard Format Identifier 2-0" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RSRTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
bitfld.byte 0x00 3. " RSIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
endif
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR0,Receive Extended Data Segment Register 0"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR1,Receive Extended Data Segment Register 1"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR2,Receive Extended Data Segment Register 2"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR3,Receive Extended Data Segment Register 3"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR4,Receive Extended Data Segment Register 4"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR5,Receive Extended Data Segment Register 5"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR6,Receive Extended Data Segment Register 6"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR7,Receive Extended Data Segment Register 7"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "MSCAN_RDLR,Receive Data Length Register"
|
|
bitfld.byte 0x00 0.--3. " RDLC ,Data Length Code Bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
rgroup.byte 0x2E++0x01
|
|
line.byte 0x00 "MSCAN_RTSRH,Receive Time Stamp Register High"
|
|
line.byte 0x01 "MSCAN_RTSRL,Receive Time Stamp Register Low"
|
|
if ((per.b(ad:0x40024000+0x31)&0x08)==0x08)
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "MSCAN_TEIDR0,Transmit Extended Identifier Register 0"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "MSCAN_TEIDR1,Transmit Extended Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " TEID20_TEID18 ,Extended Format Identifier 20-18" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " TSRR ,Substitute Remote Request" "None,Transmission buffers"
|
|
bitfld.byte 0x00 3. " TEIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
bitfld.byte 0x00 0.--2. " TEID17_TEID15 ,Extended Format Identifier 17-15" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x32++0x01
|
|
line.byte 0x00 "MSCAN_TEIDR2,Transmit Extended Identifier Register 2"
|
|
line.byte 0x01 "MSCAN_TEIDR3,Transmit Extended Identifier Register 3"
|
|
hexmask.byte 0x01 1.--7. 0x01 " TEID6_TEID0 ,Extended Format Identifier 6-0"
|
|
bitfld.byte 0x01 0. " TERTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
elif ((per.b(ad:0x40024000+0x31)&0x08)==0x00)
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "MSCAN_TSIDR0,Transmit Standard Identifier Register 0"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "MSCAN_TSIDR1,Transmit Standard Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " TSID2_TSID0 ,Standard Format Identifier 2-0" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " TSRTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
bitfld.byte 0x00 3. " TSIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
endif
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR0,Transmit Extended Data Segment Register 0"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR1,Transmit Extended Data Segment Register 1"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR2,Transmit Extended Data Segment Register 2"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR3,Transmit Extended Data Segment Register 3"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR4,Transmit Extended Data Segment Register 4"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR5,Transmit Extended Data Segment Register 5"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR6,Transmit Extended Data Segment Register 6"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR7,Transmit Extended Data Segment Register 7"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "MSCAN_TDLR,Transmit Data Length Register"
|
|
bitfld.byte 0x00 0.--3. " DLC ,Data Length Code Bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
if ((((per.b(ad:0x40024000+0x06))&0x04)==0x04)&&(((per.b(ad:0x40024000+0x0A))&0x04)==0x04)||(((per.b(ad:0x40024000+0x06))&0x02)==0x02)&&(((per.b(ad:0x40024000+0x0A))&0x02)==0x02)||(((per.b(ad:0x40024000+0x06))&0x01)==0x01)&&(((per.b(ad:0x40024000+0x0A))&0x01)==0x01))
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "MSCAN_TBPR,Transmit Buffer Priority Register"
|
|
group.byte 0x3E++0x01
|
|
line.byte 0x00 "MSCAN_TTSRH,Transmit Time Stamp Register High"
|
|
line.byte 0x01 "MSCAN_TTSRL,Transmit Time Stamp Register Low"
|
|
else
|
|
hgroup.byte 0x3D++0x00
|
|
hide.byte 0x00 "MSCAN_TBPR,Transmit Buffer Priority Register"
|
|
hgroup.byte 0x3E++0x01
|
|
hide.byte 0x00 "MSCAN_TTSRH,Transmit Time Stamp Register High"
|
|
hide.byte 0x01 "MSCAN_TTSRL,Transmit Time Stamp Register Low"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z64VLH4")||cpuis("MKE04Z64VLD4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z128VLK4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z64VQH4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z??VFM4")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z??VFM4R"))
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x4006A000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "UART0_BDH,UART Baud Rate Register: High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0.--4. " SBR ,Baud Rate Modulo Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART0_BDL,UART Baud Rate Register: Low"
|
|
if (((per.b(ad:0x4006A000+0x02))&0x82)==0x82)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " RSRC ,Receiver Source Select" "Loop-back,Single-wire"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PT ,Parity Type" "Even,Odd"
|
|
elif (((per.b(ad:0x4006A000+0x02))&0x82)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " RSRC ,Receiver Source Select" "Loop-back,Single-wire"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x4006A000+0x02))&0x82)==0x02)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PT ,Parity Type" "Even,Odd"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "UART0_C2,UART Control Register 2"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-up"
|
|
bitfld.byte 0x00 0. " SBK ,Send Break" "Normal,Break"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " TC ,Transmission Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "No noise,Noise"
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "No error,Error"
|
|
if (((per.b(ad:0x4006A000)&0x20)==0)&&((per.b(ad:0x4006A000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "10-bit,13-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006A000)&0x20)==0x20)&&((per.b(ad:0x4006A000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "12-bit,15-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "11-bit,14-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
if (((per.b(ad:0x4006A000+0x02))&0xB0)==0xB0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART0_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x4006A000+0x02))&0x10)==0x10)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART0_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART0_C3,UART Control Register 3"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART0_D,UART Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x4006B000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "UART1_BDH,UART Baud Rate Register: High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0.--4. " SBR ,Baud Rate Modulo Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART1_BDL,UART Baud Rate Register: Low"
|
|
if (((per.b(ad:0x4006B000+0x02))&0x82)==0x82)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " RSRC ,Receiver Source Select" "Loop-back,Single-wire"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PT ,Parity Type" "Even,Odd"
|
|
elif (((per.b(ad:0x4006B000+0x02))&0x82)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " RSRC ,Receiver Source Select" "Loop-back,Single-wire"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x4006B000+0x02))&0x82)==0x02)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PT ,Parity Type" "Even,Odd"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "UART1_C2,UART Control Register 2"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-up"
|
|
bitfld.byte 0x00 0. " SBK ,Send Break" "Normal,Break"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " TC ,Transmission Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "No noise,Noise"
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "No error,Error"
|
|
if (((per.b(ad:0x4006B000)&0x20)==0)&&((per.b(ad:0x4006B000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "10-bit,13-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006B000)&0x20)==0x20)&&((per.b(ad:0x4006B000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "12-bit,15-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "11-bit,14-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
if (((per.b(ad:0x4006B000+0x02))&0xB0)==0xB0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART1_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x4006B000+0x02))&0x10)==0x10)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART1_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART1_C3,UART Control Register 3"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART1_D,UART Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("MKE02Z??VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VFM4R")&&!cpuis("MKE02Z16VLC2R"))
|
|
tree "UART2"
|
|
base ad:0x4006C000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "UART2_BDH,UART Baud Rate Register: High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0.--4. " SBR ,Baud Rate Modulo Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART2_BDL,UART Baud Rate Register: Low"
|
|
if (((per.b(ad:0x4006C000+0x02))&0x82)==0x82)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " RSRC ,Receiver Source Select" "Loop-back,Single-wire"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PT ,Parity Type" "Even,Odd"
|
|
elif (((per.b(ad:0x4006C000+0x02))&0x82)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " RSRC ,Receiver Source Select" "Loop-back,Single-wire"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x4006C000+0x02))&0x82)==0x02)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PT ,Parity Type" "Even,Odd"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. " LOOPS ,Loop Mode Select" "Normal,Loop/Single-wire"
|
|
bitfld.byte 0x00 6. " UARTSWAI ,UART Stops in Wait Mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " M ,9-Bit or 8-Bit Mode Select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x00 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
bitfld.byte 0x00 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "UART2_C2,UART Control Register 2"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-up"
|
|
bitfld.byte 0x00 0. " SBK ,Send Break" "Normal,Break"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " TC ,Transmission Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "No noise,Noise"
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "No error,Error"
|
|
if (((per.b(ad:0x4006C000)&0x20)==0)&&((per.b(ad:0x4006C000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "10-bit,13-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006C000)&0x20)==0x20)&&((per.b(ad:0x4006C000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "12-bit,15-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "No detected,Detected"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wake Up Idle Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Character Generation Length" "11-bit,14-bit"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12-bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
if (((per.b(ad:0x4006C000+0x02))&0xB0)==0xB0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART2_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x4006C000+0x02))&0x10)==0x10)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART2_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART2_C3,UART Control Register 3"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART2_D,UART Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x4006A000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART0_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "One,Two"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop Mode Select" "Not selected,Selected"
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART Stops in Wait Mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver Source Select" "Internal loop-back mode,Single-wire UART"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit Mode Select" "Start+8 data bits+stop,Start+9 data bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity Type" "Even,Odd"
|
|
line.byte 0x03 "UART0_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-Up"
|
|
bitfld.byte 0x03 0. " SBK ,Send Break" "Normal,Break"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||CPUIS("S9KEAZN8AMTG")||CPUIS("S9KEAZN8ACTG")||CPUIS("S9KEAZN8AMFK")||CPUIS("S9KEAZN8ACFK")||CPUIS("S9KEAZ128AMLH")||CPUIS("S9KEAZ64AMLH")||CPUIS("S9KEAZ128ACLH")||CPUIS("S9KEAZ128AVLH")||CPUIS("S9KEAZ64ACLH")||CPUIS("S9KEAZ64AVLH")||CPUIS("S9KEAZN64ACLH")||CPUIS("S9KEAZ128AVLHR")||CPUIS("S9KEAZ64AMLK")||CPUIS("S9KEAZ128AMLK")||CPUIS("S9KEAZ128ACLK")||CPUIS("S9KEAZ128AVLK")||CPUIS("S9KEAZ64ACLK")||CPUIS("S9KEAZ64AVLK")||CPUIS("S9KEAZN16AMLC")||CPUIS("S9KEAZN32AMLC")||CPUIS("S9KEAZN64AMLC")||CPUIS("S9KEAZN64ACLC")||CPUIS("S9KEAZN16ACLC")||CPUIS("S9KEAZN32ACLC")||CPUIS("S9KEAZN32AVLC")||CPUIS("S9KEAZN16ACLH")||CPUIS("S9KEAZN32ACLH")||CPUIS("S9KEAZN16AMLH")||CPUIS("S9KEAZN32AMLH")||CPUIS("S9KEAZN64AMLH")||CPUIS("S9KEAZN8AMFKR")||CPUIS("S9KEAZN8AVTG")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
in
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit Complete Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.b(ad:0x4006A000)&0x20)==0)&&((per.b(ad:0x4006A000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "10 bit,13 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006A000)&0x20)==0x20)&&((per.b(ad:0x4006A000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "12 bit,15 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "11 bit,14 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART0_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART0_D,UART Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x4006B000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART1_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "One,Two"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop Mode Select" "Not selected,Selected"
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART Stops in Wait Mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver Source Select" "Internal loop-back mode,Single-wire UART"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit Mode Select" "Start+8 data bits+stop,Start+9 data bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity Type" "Even,Odd"
|
|
line.byte 0x03 "UART1_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-Up"
|
|
bitfld.byte 0x03 0. " SBK ,Send Break" "Normal,Break"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||CPUIS("S9KEAZN8AMTG")||CPUIS("S9KEAZN8ACTG")||CPUIS("S9KEAZN8AMFK")||CPUIS("S9KEAZN8ACFK")||CPUIS("S9KEAZ128AMLH")||CPUIS("S9KEAZ64AMLH")||CPUIS("S9KEAZ128ACLH")||CPUIS("S9KEAZ128AVLH")||CPUIS("S9KEAZ64ACLH")||CPUIS("S9KEAZ64AVLH")||CPUIS("S9KEAZN64ACLH")||CPUIS("S9KEAZ128AVLHR")||CPUIS("S9KEAZ64AMLK")||CPUIS("S9KEAZ128AMLK")||CPUIS("S9KEAZ128ACLK")||CPUIS("S9KEAZ128AVLK")||CPUIS("S9KEAZ64ACLK")||CPUIS("S9KEAZ64AVLK")||CPUIS("S9KEAZN16AMLC")||CPUIS("S9KEAZN32AMLC")||CPUIS("S9KEAZN64AMLC")||CPUIS("S9KEAZN64ACLC")||CPUIS("S9KEAZN16ACLC")||CPUIS("S9KEAZN32ACLC")||CPUIS("S9KEAZN32AVLC")||CPUIS("S9KEAZN16ACLH")||CPUIS("S9KEAZN32ACLH")||CPUIS("S9KEAZN16AMLH")||CPUIS("S9KEAZN32AMLH")||CPUIS("S9KEAZN64AMLH")||CPUIS("S9KEAZN8AMFKR")||CPUIS("S9KEAZN8AVTG")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
in
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit Complete Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.b(ad:0x4006B000)&0x20)==0)&&((per.b(ad:0x4006B000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "10 bit,13 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006B000)&0x20)==0x20)&&((per.b(ad:0x4006B000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "12 bit,15 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "11 bit,14 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART1_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART1_D,UART Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x4006C000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART2_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "One,Two"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop Mode Select" "Not selected,Selected"
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART Stops in Wait Mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver Source Select" "Internal loop-back mode,Single-wire UART"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit Mode Select" "Start+8 data bits+stop,Start+9 data bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity Type" "Even,Odd"
|
|
line.byte 0x03 "UART2_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-Up"
|
|
bitfld.byte 0x03 0. " SBK ,Send Break" "Normal,Break"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||CPUIS("S9KEAZN8AMTG")||CPUIS("S9KEAZN8ACTG")||CPUIS("S9KEAZN8AMFK")||CPUIS("S9KEAZN8ACFK")||CPUIS("S9KEAZ128AMLH")||CPUIS("S9KEAZ64AMLH")||CPUIS("S9KEAZ128ACLH")||CPUIS("S9KEAZ128AVLH")||CPUIS("S9KEAZ64ACLH")||CPUIS("S9KEAZ64AVLH")||CPUIS("S9KEAZN64ACLH")||CPUIS("S9KEAZ128AVLHR")||CPUIS("S9KEAZ64AMLK")||CPUIS("S9KEAZ128AMLK")||CPUIS("S9KEAZ128ACLK")||CPUIS("S9KEAZ128AVLK")||CPUIS("S9KEAZ64ACLK")||CPUIS("S9KEAZ64AVLK")||CPUIS("S9KEAZN16AMLC")||CPUIS("S9KEAZN32AMLC")||CPUIS("S9KEAZN64AMLC")||CPUIS("S9KEAZN64ACLC")||CPUIS("S9KEAZN16ACLC")||CPUIS("S9KEAZN32ACLC")||CPUIS("S9KEAZN32AVLC")||CPUIS("S9KEAZN16ACLH")||CPUIS("S9KEAZN32ACLH")||CPUIS("S9KEAZN16AMLH")||CPUIS("S9KEAZN32AMLH")||CPUIS("S9KEAZN64AMLH")||CPUIS("S9KEAZN8AMFKR")||CPUIS("S9KEAZN8AVTG")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
in
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit Complete Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.b(ad:0x4006C000)&0x20)==0)&&((per.b(ad:0x4006C000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "10 bit,13 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006C000)&0x20)==0x20)&&((per.b(ad:0x4006C000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "12 bit,15 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "11 bit,14 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART2_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART2_D,UART Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
else
|
|
tree.open "LPSPI (Low Power Serial Peripheral Interface)"
|
|
tree "LPSPI0"
|
|
base ad:0x4002C000
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled"
|
|
line.long 0x04 "SR,Status Register"
|
|
rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy"
|
|
eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched"
|
|
eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error"
|
|
eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed"
|
|
eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
newline
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "DER,DMA Enable Register"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
line.long 0x10 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only"
|
|
bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" ",Input trigger"
|
|
newline
|
|
elif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "LPSPI_HREQ pin,Input trigger"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high"
|
|
bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4002C000+0x10))&0x01)==0x01)
|
|
if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
endif
|
|
endif
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
line.long 0x04 "DMR1,Data Match Register 1"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")
|
|
if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01)
|
|
if (((per.l(ad:0x4002C000+0x10))&0x01)==0x01)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
endif
|
|
endif
|
|
elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01)
|
|
if (((per.l(ad:0x4002C000+0x10))&0x01)==0x01)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "CCR,Clock Configuration Register"
|
|
in
|
|
newline
|
|
endif
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count"
|
|
endif
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture"
|
|
bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first"
|
|
bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture"
|
|
bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first"
|
|
bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size"
|
|
endif
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture"
|
|
bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first"
|
|
bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size"
|
|
endif
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data"
|
|
sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S")
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPSPI1"
|
|
base ad:0x4002D000
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled"
|
|
line.long 0x04 "SR,Status Register"
|
|
rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy"
|
|
eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched"
|
|
eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error"
|
|
eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed"
|
|
eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
newline
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "DER,DMA Enable Register"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
line.long 0x10 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only"
|
|
bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" ",Input trigger"
|
|
newline
|
|
elif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "LPSPI_HREQ pin,Input trigger"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high"
|
|
bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4002D000+0x10))&0x01)==0x01)
|
|
if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled"
|
|
bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated"
|
|
bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output"
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode"
|
|
endif
|
|
endif
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
line.long 0x04 "DMR1,Data Match Register 1"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")
|
|
if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01)
|
|
if (((per.l(ad:0x4002D000+0x10))&0x01)==0x01)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
endif
|
|
endif
|
|
elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01)
|
|
if (((per.l(ad:0x4002D000+0x10))&0x01)==0x01)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "CCR,Clock Configuration Register"
|
|
in
|
|
newline
|
|
endif
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider"
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count"
|
|
endif
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture"
|
|
bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first"
|
|
bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture"
|
|
bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first"
|
|
bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size"
|
|
endif
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture"
|
|
bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first"
|
|
bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size"
|
|
endif
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data"
|
|
sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S")
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "LPI2C (Low Power Inter-Integrated Circuit)"
|
|
tree "LPI2C0"
|
|
base ad:0x40066000
|
|
width 8.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled"
|
|
line.long 0x04 "MSR,Master Status Register"
|
|
rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy"
|
|
eventfld.long 0x04 14. " DMF ,Data match flag" "No match,Match"
|
|
newline
|
|
eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "No timeout,Timeout"
|
|
eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost"
|
|
newline
|
|
eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected"
|
|
eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " EPF ,End packet flag" "Not end packet,End packet"
|
|
newline
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
line.long 0x10 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Matched only"
|
|
bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "LPI2C_HREQ pin,Input trigger"
|
|
newline
|
|
bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high"
|
|
bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40066000+0x10))&0x01)==0x00)
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
else
|
|
rgroup.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40066000+0x10))&0x01)==0x00)||(((per.l(ad:0x40066000+0x14))&0x1000000)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
endif
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
endif
|
|
if (((per.l(ad:0x40066000+0x10))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count"
|
|
endif
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit DATA[7:0],Receive (Data[7:0] + 1) bytes,Generate STOP condition,Receive and discard (Data[7:0] + 1) bytes,Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode,Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data"
|
|
newline
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "MRDR,Master Receive Data Register"
|
|
in
|
|
newline
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40066000+0x110))&0x01)==0x00)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
rbitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x114++0x0B
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x00 24. " SBF ,Slave busy flag" "Idle,Busy"
|
|
rbitfld.long 0x00 15. " SARF ,SMBus alert response flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 14. " GCF ,General call flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 13. " AM1F ,Address match 1 flag" "No match,Match"
|
|
rbitfld.long 0x00 12. " AM0F ,Address match 0 flag" "No match,Match"
|
|
eventfld.long 0x00 11. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x00 10. " BEF ,Bit error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RSF ,Repeated start flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 3. " TAF ,Transmit ACK flag" "Not required,Required"
|
|
rbitfld.long 0x00 2. " AVF ,Address valid flag" "Invalid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x04 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x04 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " GCIE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x08 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
sif cpuis("IMX8DV*")||cpuis("K32W0?2S1M*")||cpuis("MKL28*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
line.long 0x04 "SSR,Slave Status Register"
|
|
rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected"
|
|
rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "No match,Match"
|
|
rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "No match,Match"
|
|
newline
|
|
eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected"
|
|
rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required"
|
|
rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid"
|
|
newline
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40066000+0x110))&0x01)==0x00)
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40066000+0x110))&0x01)==0x00)
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
else
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
endif
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
endif
|
|
newline
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("S32K1*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "SASR,Slave Address Status Register"
|
|
in
|
|
newline
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. " ANV ,Address not valid" "Valid,Invalid"
|
|
hexmask.long.word 0x00 0.--10. 1. " RADDR ,Received address"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40066000+0x124))&0x08)==0x08)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
else
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
endif
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
endif
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
wgroup.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data"
|
|
newline
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "SRDR,Slave Receive Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPI2C1"
|
|
base ad:0x40067000
|
|
width 8.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled"
|
|
line.long 0x04 "MSR,Master Status Register"
|
|
rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy"
|
|
eventfld.long 0x04 14. " DMF ,Data match flag" "No match,Match"
|
|
newline
|
|
eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "No timeout,Timeout"
|
|
eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost"
|
|
newline
|
|
eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected"
|
|
eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " EPF ,End packet flag" "Not end packet,End packet"
|
|
newline
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
line.long 0x10 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Matched only"
|
|
bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "LPI2C_HREQ pin,Input trigger"
|
|
newline
|
|
bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high"
|
|
bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40067000+0x10))&0x01)==0x00)
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
else
|
|
rgroup.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40067000+0x10))&0x01)==0x00)||(((per.l(ad:0x40067000+0x14))&0x1000000)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
endif
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
endif
|
|
if (((per.l(ad:0x40067000+0x10))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count"
|
|
endif
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit DATA[7:0],Receive (Data[7:0] + 1) bytes,Generate STOP condition,Receive and discard (Data[7:0] + 1) bytes,Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode,Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data"
|
|
newline
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "MRDR,Master Receive Data Register"
|
|
in
|
|
newline
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40067000+0x110))&0x01)==0x00)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
rbitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x114++0x0B
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x00 24. " SBF ,Slave busy flag" "Idle,Busy"
|
|
rbitfld.long 0x00 15. " SARF ,SMBus alert response flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 14. " GCF ,General call flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 13. " AM1F ,Address match 1 flag" "No match,Match"
|
|
rbitfld.long 0x00 12. " AM0F ,Address match 0 flag" "No match,Match"
|
|
eventfld.long 0x00 11. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x00 10. " BEF ,Bit error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RSF ,Repeated start flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 3. " TAF ,Transmit ACK flag" "Not required,Required"
|
|
rbitfld.long 0x00 2. " AVF ,Address valid flag" "Invalid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x04 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x04 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " GCIE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x08 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
sif cpuis("IMX8DV*")||cpuis("K32W0?2S1M*")||cpuis("MKL28*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
line.long 0x04 "SSR,Slave Status Register"
|
|
rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected"
|
|
rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "No match,Match"
|
|
rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "No match,Match"
|
|
newline
|
|
eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected"
|
|
rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required"
|
|
rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid"
|
|
newline
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40067000+0x110))&0x01)==0x00)
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40067000+0x110))&0x01)==0x00)
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
else
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
endif
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
endif
|
|
newline
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("S32K1*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "SASR,Slave Address Status Register"
|
|
in
|
|
newline
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. " ANV ,Address not valid" "Valid,Invalid"
|
|
hexmask.long.word 0x00 0.--10. 1. " RADDR ,Received address"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40067000+0x124))&0x08)==0x08)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
else
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
endif
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
endif
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
wgroup.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data"
|
|
newline
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "SRDR,Slave Receive Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)"
|
|
tree "LPUART0"
|
|
base ad:0x4006A000
|
|
width 8.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x04 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation"
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
if (per.l(ad:0x4006A000+0x10)&0x20002000)==0x20002000
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif (per.l(ad:0x4006A000+0x10)&0x20002000)==0x20000000
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006A000+0x18)&0x10)==0x10)&&((per.l(ad:0x4006A000+0x10)&0x2000)==0x2000)
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006A000+0x18)&0x10)==0x10)&&((per.l(ad:0x4006A000+0x10)&0x2000)==0x00)
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006A000+0x18)&0x10)==0x00)&&((per.l(ad:0x4006A000+0x10)&0x2000)==0x2000)
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x4006A000+0x18)&0x80)==0x80
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loopback,TX pin"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loopback,TX pin"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
endif
|
|
endif
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DATAR,LPUART Data Read Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "DATAW,LPUART Data Write Register"
|
|
bitfld.long 0x00 13. " TSC ,Transmit special character" "Normal,Special"
|
|
hexmask.long.word 0x00 0.--9. 1. " T ,Transmit data"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1"
|
|
line.long 0x04 "MODIR,LPUART Modem Irda Register"
|
|
bitfld.long 0x04 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS pin,Inverted receiver match result"
|
|
bitfld.long 0x04 4. " TXCTSC ,Transmit CTS configuration" "At each character start,On transmitter idle"
|
|
bitfld.long 0x04 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.long 0x04 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TXFLUSH ,Transmit fifo/buffer flush" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " RXFLUSH ,Receive fifo/buffer flush" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled/fifo idle,Enabled/fifo idle 1,Enabled/fifo idle 2,Enabled/fifo idle 4,Enabled/fifo idle 8,Enabled/fifo idle 16,Enabled/fifo idle 32,Enabled/fifo idle 64"
|
|
bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TXFLUSH ,Transmit fifo/buffer flush" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " RXFLUSH ,Receive fifo/buffer flush" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled/fifo idle,Enabled/fifo idle 1,Enabled/fifo idle 2,Enabled/fifo idle 4,Enabled/fifo idle 8,Enabled/fifo idle 16,Enabled/fifo idle 32,Enabled/fifo idle 64"
|
|
bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
endif
|
|
if (((per.l(ad:0x4006A000+0x18))&0x80000)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPUART1"
|
|
base ad:0x4006B000
|
|
width 8.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x04 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation"
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
if (per.l(ad:0x4006B000+0x10)&0x20002000)==0x20002000
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif (per.l(ad:0x4006B000+0x10)&0x20002000)==0x20000000
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006B000+0x18)&0x10)==0x10)&&((per.l(ad:0x4006B000+0x10)&0x2000)==0x2000)
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006B000+0x18)&0x10)==0x10)&&((per.l(ad:0x4006B000+0x10)&0x2000)==0x00)
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006B000+0x18)&0x10)==0x00)&&((per.l(ad:0x4006B000+0x10)&0x2000)==0x2000)
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x4006B000+0x18)&0x80)==0x80
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loopback,TX pin"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loopback,TX pin"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
endif
|
|
endif
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DATAR,LPUART Data Read Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "DATAW,LPUART Data Write Register"
|
|
bitfld.long 0x00 13. " TSC ,Transmit special character" "Normal,Special"
|
|
hexmask.long.word 0x00 0.--9. 1. " T ,Transmit data"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1"
|
|
line.long 0x04 "MODIR,LPUART Modem Irda Register"
|
|
bitfld.long 0x04 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS pin,Inverted receiver match result"
|
|
bitfld.long 0x04 4. " TXCTSC ,Transmit CTS configuration" "At each character start,On transmitter idle"
|
|
bitfld.long 0x04 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.long 0x04 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TXFLUSH ,Transmit fifo/buffer flush" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " RXFLUSH ,Receive fifo/buffer flush" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled/fifo idle,Enabled/fifo idle 1,Enabled/fifo idle 2,Enabled/fifo idle 4,Enabled/fifo idle 8,Enabled/fifo idle 16,Enabled/fifo idle 32,Enabled/fifo idle 64"
|
|
bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TXFLUSH ,Transmit fifo/buffer flush" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " RXFLUSH ,Receive fifo/buffer flush" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled/fifo idle,Enabled/fifo idle 1,Enabled/fifo idle 2,Enabled/fifo idle 4,Enabled/fifo idle 8,Enabled/fifo idle 16,Enabled/fifo idle 32,Enabled/fifo idle 64"
|
|
bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
endif
|
|
if (((per.l(ad:0x4006B000+0x18))&0x80000)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPUART2"
|
|
base ad:0x4006C000
|
|
width 8.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x04 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation"
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8/9-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " OSR ,Oversampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match wakeup,Idle match wakeup,Match on/off,Data match RWU enable/cts input match on/off"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
if (per.l(ad:0x4006C000+0x10)&0x20002000)==0x20002000
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif (per.l(ad:0x4006C000+0x10)&0x20002000)==0x20000000
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006C000+0x18)&0x10)==0x10)&&((per.l(ad:0x4006C000+0x10)&0x2000)==0x2000)
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006C000+0x18)&0x10)==0x10)&&((per.l(ad:0x4006C000+0x10)&0x2000)==0x00)
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
elif ((per.l(ad:0x4006C000+0x18)&0x10)==0x00)&&((per.l(ad:0x4006C000+0x10)&0x2000)==0x2000)
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x40000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x0x80000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Not completed,Completed"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Not full,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error"
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x4006C000+0x18)&0x80)==0x80
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loopback,TX pin"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loopback,TX pin"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "0,1"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "0,1"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "No effect,Wait for wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "No effect,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " M7 ,7-Bit mode select" "Receiver and transmitter use 8-bit to 10-bit,Receiver and transmitter use 7-bit"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line wakeup,Address-mark wakeup"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even parity,Odd parity"
|
|
endif
|
|
endif
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DATAR,LPUART Data Read Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "DATAW,LPUART Data Write Register"
|
|
bitfld.long 0x00 13. " TSC ,Transmit special character" "Normal,Special"
|
|
hexmask.long.word 0x00 0.--9. 1. " T ,Transmit data"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1"
|
|
line.long 0x04 "MODIR,LPUART Modem Irda Register"
|
|
bitfld.long 0x04 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS pin,Inverted receiver match result"
|
|
bitfld.long 0x04 4. " TXCTSC ,Transmit CTS configuration" "At each character start,On transmitter idle"
|
|
bitfld.long 0x04 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.long 0x04 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TXFLUSH ,Transmit fifo/buffer flush" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " RXFLUSH ,Receive fifo/buffer flush" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled/fifo idle,Enabled/fifo idle 1,Enabled/fifo idle 2,Enabled/fifo idle 4,Enabled/fifo idle 8,Enabled/fifo idle 16,Enabled/fifo idle 32,Enabled/fifo idle 64"
|
|
bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TXFLUSH ,Transmit fifo/buffer flush" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " RXFLUSH ,Receive fifo/buffer flush" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled/fifo idle,Enabled/fifo idle 1,Enabled/fifo idle 2,Enabled/fifo idle 4,Enabled/fifo idle 8,Enabled/fifo idle 16,Enabled/fifo idle 32,Enabled/fifo idle 64"
|
|
bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
endif
|
|
if (((per.l(ad:0x4006C000+0x18))&0x80000)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXIO"
|
|
base ad:0x4005A000
|
|
width 14.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TRIGGER ,Trigger number"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIN ,Pin number"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TIMER ,Timer number"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SHIFTER ,Shifter number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,FlexIO Control Register"
|
|
bitfld.long 0x00 31. " DOZEN ,Doze enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FASTACC ,Fast access" "Normal,Fast"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWRST ,Software reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLEXEN ,FlexIO enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PIN,Pin State Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PDI ,Pin data input"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
eventfld.long 0x00 3. " SSF_[3] ,Shifter status flag" "Cleared,Set"
|
|
eventfld.long 0x00 2. " [2] ,Shifter status flag" "Cleared,Set"
|
|
eventfld.long 0x00 1. " [1] ,Shifter status flag" "Cleared,Set"
|
|
eventfld.long 0x00 0. " [0] ,Shifter status flag" "Cleared,Set"
|
|
line.long 0x04 "SHIFTERR,Shifter Error Register"
|
|
eventfld.long 0x04 3. " SEF_[3] ,Shifter error flags" "Cleared,Set"
|
|
eventfld.long 0x04 2. " [2] ,Shifter error flags" "Cleared,Set"
|
|
eventfld.long 0x04 1. " [1] ,Shifter error flags" "Cleared,Set"
|
|
eventfld.long 0x04 0. " [0] ,Shifter error flags" "Cleared,Set"
|
|
line.long 0x08 "TIMSTAT,Timer Status Register"
|
|
eventfld.long 0x08 3. " TSF_[3] ,Timer status flags" "Cleared,Set"
|
|
eventfld.long 0x08 2. " [2] ,Timer status flags" "Cleared,Set"
|
|
eventfld.long 0x08 1. " [1] ,Timer status flags" "Cleared,Set"
|
|
eventfld.long 0x08 0. " [0] ,Timer status flags" "Cleared,Set"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
|
|
bitfld.long 0x00 3. " SSIE_[3] ,Shifter status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Shifter status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Shifter status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Shifter status interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "SHIFTEIEN,Shifter Error Interrupt Enable"
|
|
bitfld.long 0x04 3. " SEIE_[3] ,Shifter error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Shifter error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Shifter error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Shifter error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "TIMIEN,Timer Interrupt Enable Register"
|
|
bitfld.long 0x08 3. " TEIE_[3] ,Timer status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Timer status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Timer status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Timer status interrupt enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
|
|
bitfld.long 0x00 3. " SSDE_[3] ,Shifter status DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Shifter status DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Shifter status DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Shifter status DMA enable" "Disabled,Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SHIFTCTL0,Shifter Control 0 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..."
|
|
group.long (0x80+0x80)++0x03
|
|
line.long 0x00 "SHIFTCFG0x80,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0,1"
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled,Disabled,0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "SHIFTCTL1,Shifter Control 1 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..."
|
|
group.long (0x84+0x80)++0x03
|
|
line.long 0x00 "SHIFTCFG0x84,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0,1"
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled,Disabled,0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SHIFTCTL2,Shifter Control 2 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..."
|
|
group.long (0x88+0x80)++0x03
|
|
line.long 0x00 "SHIFTCFG0x88,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0,1"
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled,Disabled,0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SHIFTCTL3,Shifter Control 3 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..."
|
|
group.long (0x8C+0x80)++0x03
|
|
line.long 0x00 "SHIFTCFG0x8C,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0,1"
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled,Disabled,0,1"
|
|
hgroup.long 0x200++0x0F
|
|
hide.long 0x00 "SHIFTBUF0,Shifter Buffer 0 Register"
|
|
in
|
|
hide.long 0x04 "SHIFTBUF1,Shifter Buffer 1 Register"
|
|
in
|
|
hide.long 0x08 "SHIFTBUF2,Shifter Buffer 2 Register"
|
|
in
|
|
hide.long 0x0C "SHIFTBUF3,Shifter Buffer 3 Register"
|
|
in
|
|
group.long 0x280++0x0F
|
|
line.long 0x00 "SHIFTBUFBIS0,Shifter Buffer 0 Bit Swapped Register"
|
|
line.long 0x04 "SHIFTBUFBIS1,Shifter Buffer 1 Bit Swapped Register"
|
|
line.long 0x08 "SHIFTBUFBIS2,Shifter Buffer 2 Bit Swapped Register"
|
|
line.long 0x0C "SHIFTBUFBIS3,Shifter Buffer 3 Bit Swapped Register"
|
|
group.long 0x300++0x0F
|
|
line.long 0x00 "SHIFTBUFBYS0,Shifter Buffer 0 Byte Swapped Register"
|
|
line.long 0x04 "SHIFTBUFBYS1,Shifter Buffer 1 Byte Swapped Register"
|
|
line.long 0x08 "SHIFTBUFBYS2,Shifter Buffer 2 Byte Swapped Register"
|
|
line.long 0x0C "SHIFTBUFBYS3,Shifter Buffer 3 Byte Swapped Register"
|
|
group.long 0x380++0x0F
|
|
line.long 0x00 "SHIFTBUFBBS0,Shifter Buffer 0 Bit Byte Swapped Register"
|
|
line.long 0x04 "SHIFTBUFBBS1,Shifter Buffer 1 Bit Byte Swapped Register"
|
|
line.long 0x08 "SHIFTBUFBBS2,Shifter Buffer 2 Bit Byte Swapped Register"
|
|
line.long 0x0C "SHIFTBUFBBS3,Shifter Buffer 3 Bit Byte Swapped Register"
|
|
sif (cpuis("S32MTV"))
|
|
if (((per.l(ad:0x4005A000+0x400))&0x400000)==0x400000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "TIMCTL0,Timer Control 0 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "TIMCTL0,Timer Control 0 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "TIMCTL0,Timer Control 0 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
group.long (0x400+0x80)++0x03
|
|
line.long 0x00 "TIMCFG0,Timer Configuration 0 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "1/No reset,0/No reset,1/On reset,0/On reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement (Source of the shift clock)" "Flexio clock (Timer),Trigger input (Timer),Pin input (Pin),Trigger input (Trigger)"
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "No reset,,Timer pin=timer output,Timer trigger=timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Never disabled,Timer N-1 disable,Timer compare,Timer compare/trigger low,Pin rising/falling edge,Pin rising/falling edge,Trigger falling edge,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Timer N-1 enable,Trigger high,Trigger high and pin high,Pin rising edge,Pin rising edge and trigger high,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Timer compare,Timer disable,Both"
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled"
|
|
group.long (0x400+0x100)++0x03
|
|
line.long 0x00 "TIMCMP0,Timer Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value"
|
|
sif (cpuis("S32MTV"))
|
|
if (((per.l(ad:0x4005A000+0x404))&0x400000)==0x400000)
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "TIMCTL1,Timer Control 1 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "TIMCTL1,Timer Control 1 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "TIMCTL1,Timer Control 1 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
group.long (0x404+0x80)++0x03
|
|
line.long 0x00 "TIMCFG1,Timer Configuration 1 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "1/No reset,0/No reset,1/On reset,0/On reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement (Source of the shift clock)" "Flexio clock (Timer),Trigger input (Timer),Pin input (Pin),Trigger input (Trigger)"
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "No reset,,Timer pin=timer output,Timer trigger=timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Never disabled,Timer N-1 disable,Timer compare,Timer compare/trigger low,Pin rising/falling edge,Pin rising/falling edge,Trigger falling edge,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Timer N-1 enable,Trigger high,Trigger high and pin high,Pin rising edge,Pin rising edge and trigger high,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Timer compare,Timer disable,Both"
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled"
|
|
group.long (0x404+0x100)++0x03
|
|
line.long 0x00 "TIMCMP1,Timer Compare 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value"
|
|
sif (cpuis("S32MTV"))
|
|
if (((per.l(ad:0x4005A000+0x408))&0x400000)==0x400000)
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "TIMCTL2,Timer Control 2 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "TIMCTL2,Timer Control 2 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "TIMCTL2,Timer Control 2 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
group.long (0x408+0x80)++0x03
|
|
line.long 0x00 "TIMCFG2,Timer Configuration 2 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "1/No reset,0/No reset,1/On reset,0/On reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement (Source of the shift clock)" "Flexio clock (Timer),Trigger input (Timer),Pin input (Pin),Trigger input (Trigger)"
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "No reset,,Timer pin=timer output,Timer trigger=timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Never disabled,Timer N-1 disable,Timer compare,Timer compare/trigger low,Pin rising/falling edge,Pin rising/falling edge,Trigger falling edge,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Timer N-1 enable,Trigger high,Trigger high and pin high,Pin rising edge,Pin rising edge and trigger high,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Timer compare,Timer disable,Both"
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled"
|
|
group.long (0x408+0x100)++0x03
|
|
line.long 0x00 "TIMCMP2,Timer Compare 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value"
|
|
sif (cpuis("S32MTV"))
|
|
if (((per.l(ad:0x4005A000+0x40C))&0x400000)==0x400000)
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "TIMCTL3,Timer Control 3 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "TIMCTL3,Timer Control 3 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "TIMCTL3,Timer Control 3 Register"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low"
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/Bidirectional,Bidirectional output data,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit counters baud/bit mode,Dual 8-bit counters PWM mode,Single 16-bit counter mode"
|
|
endif
|
|
group.long (0x40C+0x80)++0x03
|
|
line.long 0x00 "TIMCFG3,Timer Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "1/No reset,0/No reset,1/On reset,0/On reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement (Source of the shift clock)" "Flexio clock (Timer),Trigger input (Timer),Pin input (Pin),Trigger input (Trigger)"
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "No reset,,Timer pin=timer output,Timer trigger=timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Never disabled,Timer N-1 disable,Timer compare,Timer compare/trigger low,Pin rising/falling edge,Pin rising/falling edge,Trigger falling edge,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Timer N-1 enable,Trigger high,Trigger high and pin high,Pin rising edge,Pin rising edge and trigger high,Trigger rising edge,Trigger rising/falling edge"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Timer compare,Timer disable,Both"
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled"
|
|
group.long (0x40C+0x100)++0x03
|
|
line.long 0x00 "TIMCMP3,Timer Compare 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
tree "CAN (FlexCAN)"
|
|
tree "CAN0"
|
|
base ad:0x40024000
|
|
width 16.
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,Module Disable" "No,Yes"
|
|
bitfld.long 0x00 30. " FRZ ,Freeze Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " NOTRDY ,FlexCAN Not Ready" "Ready,Not ready"
|
|
bitfld.long 0x00 26. " WAKMSK ,Wake Up Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " SOFTRST ,Soft Reset" "No reset,Reset"
|
|
rbitfld.long 0x00 24. " FRZACK ,Freeze Mode Acknowledge" "Not freezed,Freezed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SUPV ,Supervisor Mode" "User mode,Supervisor mode"
|
|
bitfld.long 0x00 22. " SLFWAK ,Self Wake Up" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WRNEN ,Warning Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " LPMACK ,Low-Power Mode Acknowledge" "Not low-power,Low-power"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAKSRC ,Wake Up Source" "Unfiltered Rx input,Filtered Rx input"
|
|
bitfld.long 0x00 17. " SRXDIS ,Self Reception Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " IRMQ ,Individual Rx Masking And Queue Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DMA ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LPRIOEN ,Local Priority Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AEN ,Abort Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "Format A,Format B,Format C,Format D"
|
|
hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number Of The Last Message Buffer"
|
|
if (per.l(ad:0x40024000+0x00)&0x200000)==0x200000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
bitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
bitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
bitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
bitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,Module Disable" "No,Yes"
|
|
bitfld.long 0x00 30. " FRZ ,Freeze Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " NOTRDY ,FlexCAN Not Ready" "Ready,Not ready"
|
|
bitfld.long 0x00 26. " WAKMSK ,Wake Up Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " SOFTRST ,Soft Reset" "No reset,Reset"
|
|
rbitfld.long 0x00 24. " FRZACK ,Freeze Mode Acknowledge" "Not freezed,Freezed"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " SUPV ,Supervisor Mode" "User mode,Supervisor mode"
|
|
bitfld.long 0x00 22. " SLFWAK ,Self Wake Up" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21. " WRNEN ,Warning Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " LPMACK ,Low-Power Mode Acknowledge" "Not low-power,Low-power"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " WAKSRC ,Wake Up Source" "Unfiltered Rx input,Filtered Rx input"
|
|
rbitfld.long 0x00 17. " SRXDIS ,Self Reception Disable" "No,Yes"
|
|
rbitfld.long 0x00 16. " IRMQ ,Individual Rx Masking And Queue Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 15. " DMA ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " LPRIOEN ,Local Priority Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " AEN ,Abort Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "Format A,Format B,Format C,Format D"
|
|
hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number Of The Last Message Buffer"
|
|
if (per.l(ad:0x40024000+0x00)&0x200000)==0x200000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
rbitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
rbitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
rbitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
rbitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
rbitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
rbitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
rbitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
rbitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
rbitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
rbitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
endif
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer Value"
|
|
if (per.l(ad:0x40024000+0x34)&0x30000)==(0x30000||0x10000)
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
else
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit Error Counter"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit Error Counter"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "ESR1,Error and Status 1 register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
bitfld.long 0x00 31. " BUFM[31] ,Message Buffer 31 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,Message Buffer 30 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,Message Buffer 29 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,Message Buffer 28 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Message Buffer 27 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,Message Buffer 26 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,Message Buffer 25 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,Message Buffer 24 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Message Buffer 23 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,Message Buffer 22 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,Message Buffer 21 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,Message Buffer 20 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Message Buffer 19 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,Message Buffer 18 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,Message Buffer 17 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,Message Buffer 16 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Message Buffer 15 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,Message Buffer 14 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,Message Buffer 13 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,Message Buffer 12 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Message Buffer 11 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,Message Buffer 10 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,Message Buffer 9 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,Message Buffer 8 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Message Buffer 7 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,Message Buffer 6 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,Message Buffer 5 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,Message Buffer 4 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Message Buffer 3 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,Message Buffer 2 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " [1] ,Message Buffer 1 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,Message Buffer 0 Interrupt Mask" "Masked,Not masked"
|
|
if (per.l(ad:0x40024000)&0x20000000)==0x20000000
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
eventfld.long 0x00 31. " BUFM[31] ,Message Buffer 31 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Message Buffer 30 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Message Buffer 29 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Message Buffer 28 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Message Buffer 27 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Message Buffer 26 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Message Buffer 25 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Message Buffer 24 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Message Buffer 23 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Message Buffer 22 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Message Buffer 21 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Message Buffer 20 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Message Buffer 19 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Message Buffer 18 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Message Buffer 17 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Message Buffer 16 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Message Buffer 15 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Message Buffer 14 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Message Buffer 13 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Message Buffer 12 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Message Buffer 11 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Message Buffer 10 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Message Buffer 9 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Message Buffer 8 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Rx FIFO Overflow Flag" "No overflow,Overflow"
|
|
eventfld.long 0x00 6. " [6] ,Rx FIFO Warning Flag" "No warning,Warning"
|
|
eventfld.long 0x00 5. " [5] ,Frames available in Rx FIFO Flag" "No frames,Frames available"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
eventfld.long 0x00 31. " BUFM[31] ,Message Buffer 31 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Message Buffer 30 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Message Buffer 29 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Message Buffer 28 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Message Buffer 27 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Message Buffer 26 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Message Buffer 25 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Message Buffer 24 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Message Buffer 23 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Message Buffer 22 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Message Buffer 21 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Message Buffer 20 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Message Buffer 19 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Message Buffer 18 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Message Buffer 17 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Message Buffer 16 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Message Buffer 15 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Message Buffer 14 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Message Buffer 13 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Message Buffer 12 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Message Buffer 11 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Message Buffer 10 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Message Buffer 9 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Message Buffer 8 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Message Buffer 7 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Message Buffer 6 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Message Buffer 5 in Rx FIFO Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Message Buffer 4 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Message Buffer 3 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Message Buffer 2 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Message Buffer 1 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Message Buffer 0 Interrupt Flag" "No interrupt,Interrupt"
|
|
endif
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,Bus Off Done Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 24.--27. " RFFN ,Number Of Rx FIFO Filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128"
|
|
bitfld.long 0x00 19.--23. " TASD ,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,Mailboxes Reception Priority" "Rx FIFO first,Mailboxes first"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Remote Response generated,Remote Request stored"
|
|
bitfld.long 0x00 16. " EACEN ,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,Timer Source" "CAN bit clock,External time tick"
|
|
bitfld.long 0x00 14. " PREXCEN ,Protocol Exception Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,Edge Filter Disable" "No,Yes"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,Bus Off Done Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 24.--27. " RFFN ,Number Of Rx FIFO Filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128"
|
|
rbitfld.long 0x00 19.--23. " TASD ,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 18. " MRP ,Mailboxes Reception Priority" "Rx FIFO first,Mailboxes first"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " RRS ,Remote Request Storing" "Remote Response generated,Remote Request stored"
|
|
rbitfld.long 0x00 16. " EACEN ,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "Disabled,Enabled"
|
|
rbitfld.long 0x00 15. " TIMER_SRC ,Timer Source" "CAN bit clock,External time tick"
|
|
bitfld.long 0x00 14. " PREXCEN ,Protocol Exception Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,Edge Filter Disable" "No,Yes"
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. " VPS ,Valid Priority Status" "Invalid,Valid"
|
|
bitfld.long 0x00 13. " IMB ,Inactive Mailbox" "Not inactive,Inactive"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value"
|
|
if (per.l(ad:0x40024000)&0x300)==0x00
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
elif (per.l(ad:0x40024000)&0x300)==0x100
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 13. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 13. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
elif (per.l(ad:0x40024000)&0x300)==0x200
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 30. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 29. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 30. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 29. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
endif
|
|
if (per.l(ad:0x40024000+0x30)&0x10)==0x10
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,identifier acceptance filter hit indicator"
|
|
endif
|
|
if (per.l(ad:0x40024000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,Bit Timing Format Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--20. " ERJW ,Extended Resync Jump Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 10.--15. " EPROPSEG ,Extended Propagation Segment" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. " EPSEG1 ,Extended Phase Segment 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,Extended Phase Segment 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "RXIMR0,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "RXIMR1,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "RXIMR2,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "RXIMR3,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "RXIMR4,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "RXIMR5,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "RXIMR6,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "RXIMR7,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "RXIMR8,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "RXIMR9,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "RXIMR10,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "RXIMR11,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "RXIMR12,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "RXIMR13,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "RXIMR14,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "RXIMR15,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,Bit Timing Format Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--20. " ERJW ,Extended Resync Jump Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 10.--15. " EPROPSEG ,Extended Propagation Segment" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. " EPSEG1 ,Extended Phase Segment 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,Extended Phase Segment 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "RXIMR0,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x884++0x03
|
|
line.long 0x00 "RXIMR1,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "RXIMR2,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x88C++0x03
|
|
line.long 0x00 "RXIMR3,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "RXIMR4,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x894++0x03
|
|
line.long 0x00 "RXIMR5,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "RXIMR6,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x89C++0x03
|
|
line.long 0x00 "RXIMR7,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "RXIMR8,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8A4++0x03
|
|
line.long 0x00 "RXIMR9,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "RXIMR10,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8AC++0x03
|
|
line.long 0x00 "RXIMR11,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "RXIMR12,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8B4++0x03
|
|
line.long 0x00 "RXIMR13,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "RXIMR14,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8BC++0x03
|
|
line.long 0x00 "RXIMR15,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x40025000
|
|
width 16.
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,Module Disable" "No,Yes"
|
|
bitfld.long 0x00 30. " FRZ ,Freeze Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " NOTRDY ,FlexCAN Not Ready" "Ready,Not ready"
|
|
bitfld.long 0x00 26. " WAKMSK ,Wake Up Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " SOFTRST ,Soft Reset" "No reset,Reset"
|
|
rbitfld.long 0x00 24. " FRZACK ,Freeze Mode Acknowledge" "Not freezed,Freezed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SUPV ,Supervisor Mode" "User mode,Supervisor mode"
|
|
bitfld.long 0x00 22. " SLFWAK ,Self Wake Up" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WRNEN ,Warning Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " LPMACK ,Low-Power Mode Acknowledge" "Not low-power,Low-power"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAKSRC ,Wake Up Source" "Unfiltered Rx input,Filtered Rx input"
|
|
bitfld.long 0x00 17. " SRXDIS ,Self Reception Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " IRMQ ,Individual Rx Masking And Queue Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DMA ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LPRIOEN ,Local Priority Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AEN ,Abort Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "Format A,Format B,Format C,Format D"
|
|
hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number Of The Last Message Buffer"
|
|
if (per.l(ad:0x40025000+0x00)&0x200000)==0x200000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
bitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
bitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
bitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
bitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MDIS ,Module Disable" "No,Yes"
|
|
bitfld.long 0x00 30. " FRZ ,Freeze Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " NOTRDY ,FlexCAN Not Ready" "Ready,Not ready"
|
|
bitfld.long 0x00 26. " WAKMSK ,Wake Up Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " SOFTRST ,Soft Reset" "No reset,Reset"
|
|
rbitfld.long 0x00 24. " FRZACK ,Freeze Mode Acknowledge" "Not freezed,Freezed"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " SUPV ,Supervisor Mode" "User mode,Supervisor mode"
|
|
bitfld.long 0x00 22. " SLFWAK ,Self Wake Up" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21. " WRNEN ,Warning Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " LPMACK ,Low-Power Mode Acknowledge" "Not low-power,Low-power"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " WAKSRC ,Wake Up Source" "Unfiltered Rx input,Filtered Rx input"
|
|
rbitfld.long 0x00 17. " SRXDIS ,Self Reception Disable" "No,Yes"
|
|
rbitfld.long 0x00 16. " IRMQ ,Individual Rx Masking And Queue Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 15. " DMA ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " LPRIOEN ,Local Priority Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " AEN ,Abort Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "Format A,Format B,Format C,Format D"
|
|
hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number Of The Last Message Buffer"
|
|
if (per.l(ad:0x40025000+0x00)&0x200000)==0x200000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
rbitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
rbitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
rbitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
rbitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
rbitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler Division Factor"
|
|
rbitfld.long 0x00 22.--23. " RJW ,Resync Jump Width" "1,2,3,4"
|
|
rbitfld.long 0x00 19.--21. " PSEG1 ,Phase Segment 1" "1,2,3,4,5,6,7,8"
|
|
rbitfld.long 0x00 16.--18. " PSEG2 ,Phase Segment 2" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BOFFMSK ,Bus Off Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ERRMSK ,Error Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 13. " CLKSRC ,CAN Engine Clock Source" "Oscillator clock,Peripheral clock"
|
|
rbitfld.long 0x00 12. " LPB ,Loop Back Mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " TWRNMSK ,Tx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 10. " RWRNMSK ,Rx Warning Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 7. " SMP ,CAN Bit Sampling" "1 sample,3 samples"
|
|
bitfld.long 0x00 6. " BOFFREC ,Bus Off Recovery" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TSYN ,Timer Sync" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " LBUF ,Lowest Buffer Transmitted First" "Highest first,Lowest first"
|
|
rbitfld.long 0x00 3. " LOM ,Listen-Only Mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation Segment" "1,2,3,4,5,6,7,8"
|
|
endif
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer Value"
|
|
if (per.l(ad:0x40025000+0x34)&0x30000)==(0x30000||0x10000)
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 31. " RTR ,RTR bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 30. " IDE ,IDE bit mask" "Not checked,Checked"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
else
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
bitfld.long 0x00 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x04 "RX14MASK,Rx 14 Mask register"
|
|
bitfld.long 0x04 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x04 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x04 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x04 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x04 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x04 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x04 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x04 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x04 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x04 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x04 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x04 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x04 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x04 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x04 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x04 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x04 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x04 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x04 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x04 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x04 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x04 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x04 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x04 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x04 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x04 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x04 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x04 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x04 0. ",ID bit 0 mask" "0,1"
|
|
line.long 0x08 "RX15MASK,Rx 15 Mask register"
|
|
bitfld.long 0x08 28. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x08 27. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x08 26. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x08 25. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x08 24. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x08 23. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x08 22. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x08 21. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x08 20. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x08 19. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x08 18. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x08 17. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x08 16. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x08 15. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x08 14. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x08 13. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x08 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x08 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x08 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x08 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x08 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x08 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x08 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x08 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x08 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x08 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x08 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x08 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x08 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
endif
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit Error Counter"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit Error Counter"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "ESR1,Error and Status 1 register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
bitfld.long 0x00 31. " BUFM[31] ,Message Buffer 31 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,Message Buffer 30 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,Message Buffer 29 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,Message Buffer 28 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Message Buffer 27 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,Message Buffer 26 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,Message Buffer 25 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,Message Buffer 24 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Message Buffer 23 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,Message Buffer 22 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,Message Buffer 21 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,Message Buffer 20 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Message Buffer 19 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,Message Buffer 18 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,Message Buffer 17 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,Message Buffer 16 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Message Buffer 15 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,Message Buffer 14 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,Message Buffer 13 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,Message Buffer 12 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Message Buffer 11 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,Message Buffer 10 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,Message Buffer 9 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,Message Buffer 8 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Message Buffer 7 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,Message Buffer 6 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,Message Buffer 5 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,Message Buffer 4 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Message Buffer 3 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,Message Buffer 2 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " [1] ,Message Buffer 1 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,Message Buffer 0 Interrupt Mask" "Masked,Not masked"
|
|
if (per.l(ad:0x40025000)&0x20000000)==0x20000000
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
eventfld.long 0x00 31. " BUFM[31] ,Message Buffer 31 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Message Buffer 30 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Message Buffer 29 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Message Buffer 28 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Message Buffer 27 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Message Buffer 26 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Message Buffer 25 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Message Buffer 24 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Message Buffer 23 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Message Buffer 22 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Message Buffer 21 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Message Buffer 20 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Message Buffer 19 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Message Buffer 18 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Message Buffer 17 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Message Buffer 16 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Message Buffer 15 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Message Buffer 14 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Message Buffer 13 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Message Buffer 12 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Message Buffer 11 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Message Buffer 10 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Message Buffer 9 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Message Buffer 8 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Rx FIFO Overflow Flag" "No overflow,Overflow"
|
|
eventfld.long 0x00 6. " [6] ,Rx FIFO Warning Flag" "No warning,Warning"
|
|
eventfld.long 0x00 5. " [5] ,Frames available in Rx FIFO Flag" "No frames,Frames available"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
eventfld.long 0x00 31. " BUFM[31] ,Message Buffer 31 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Message Buffer 30 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Message Buffer 29 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Message Buffer 28 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Message Buffer 27 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Message Buffer 26 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Message Buffer 25 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Message Buffer 24 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Message Buffer 23 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Message Buffer 22 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Message Buffer 21 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Message Buffer 20 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Message Buffer 19 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Message Buffer 18 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Message Buffer 17 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Message Buffer 16 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Message Buffer 15 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Message Buffer 14 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Message Buffer 13 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Message Buffer 12 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Message Buffer 11 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Message Buffer 10 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Message Buffer 9 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Message Buffer 8 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Message Buffer 7 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Message Buffer 6 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Message Buffer 5 in Rx FIFO Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Message Buffer 4 Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Message Buffer 3 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Message Buffer 2 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Message Buffer 1 Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Message Buffer 0 Interrupt Flag" "No interrupt,Interrupt"
|
|
endif
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,Bus Off Done Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 24.--27. " RFFN ,Number Of Rx FIFO Filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128"
|
|
bitfld.long 0x00 19.--23. " TASD ,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " MRP ,Mailboxes Reception Priority" "Rx FIFO first,Mailboxes first"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Remote Response generated,Remote Request stored"
|
|
bitfld.long 0x00 16. " EACEN ,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMER_SRC ,Timer Source" "CAN bit clock,External time tick"
|
|
bitfld.long 0x00 14. " PREXCEN ,Protocol Exception Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,Edge Filter Disable" "No,Yes"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 30. " BOFFDONEMSK ,Bus Off Done Interrupt Mask" "Masked,Not masked"
|
|
rbitfld.long 0x00 24.--27. " RFFN ,Number Of Rx FIFO Filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128"
|
|
rbitfld.long 0x00 19.--23. " TASD ,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 18. " MRP ,Mailboxes Reception Priority" "Rx FIFO first,Mailboxes first"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " RRS ,Remote Request Storing" "Remote Response generated,Remote Request stored"
|
|
rbitfld.long 0x00 16. " EACEN ,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "Disabled,Enabled"
|
|
rbitfld.long 0x00 15. " TIMER_SRC ,Timer Source" "CAN bit clock,External time tick"
|
|
bitfld.long 0x00 14. " PREXCEN ,Protocol Exception Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDFLTDIS ,Edge Filter Disable" "No,Yes"
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. " VPS ,Valid Priority Status" "Invalid,Valid"
|
|
bitfld.long 0x00 13. " IMB ,Inactive Mailbox" "Not inactive,Inactive"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value"
|
|
if (per.l(ad:0x40025000)&0x300)==0x00
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 28 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 27 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 26 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 25 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 24 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 23 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 22 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 21 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 20 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 19 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 18 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 17 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 16 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 15 mask" "0,1"
|
|
bitfld.long 0x00 15. ",ID bit 14 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
elif (per.l(ad:0x40025000)&0x300)==0x100
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 13. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 29. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 23. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked"
|
|
bitfld.long 0x00 13. " ID ,ID bit 13 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 12 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 11 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 10 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 9 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 8 mask" "0,1"
|
|
bitfld.long 0x00 7. ",ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
elif (per.l(ad:0x40025000)&0x300)==0x200
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 30. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 29. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
bitfld.long 0x00 31. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 30. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 29. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 28. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 27. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 26. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 25. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 24. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 22. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 21. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 20. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 19. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 18. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 17. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 16. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 14. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 13. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 12. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 11. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 10. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 9. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 8. ",ID bit 0 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ID ,ID bit 7 mask" "0,1"
|
|
bitfld.long 0x00 6. ",ID bit 6 mask" "0,1"
|
|
bitfld.long 0x00 5. ",ID bit 5 mask" "0,1"
|
|
bitfld.long 0x00 4. ",ID bit 4 mask" "0,1"
|
|
bitfld.long 0x00 3. ",ID bit 3 mask" "0,1"
|
|
bitfld.long 0x00 2. ",ID bit 2 mask" "0,1"
|
|
bitfld.long 0x00 1. ",ID bit 1 mask" "0,1"
|
|
bitfld.long 0x00 0. ",ID bit 0 mask" "0,1"
|
|
endif
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
endif
|
|
if (per.l(ad:0x40025000+0x30)&0x10)==0x10
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " IDHIT ,identifier acceptance filter hit indicator"
|
|
endif
|
|
if (per.l(ad:0x40025000+0x00)&0x40000000)==0x40000000
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,Bit Timing Format Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--20. " ERJW ,Extended Resync Jump Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 10.--15. " EPROPSEG ,Extended Propagation Segment" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. " EPSEG1 ,Extended Phase Segment 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,Extended Phase Segment 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "RXIMR0,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "RXIMR1,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "RXIMR2,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "RXIMR3,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "RXIMR4,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "RXIMR5,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "RXIMR6,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "RXIMR7,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "RXIMR8,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "RXIMR9,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "RXIMR10,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "RXIMR11,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "RXIMR12,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "RXIMR13,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "RXIMR14,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "RXIMR15,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. " BTF ,Bit Timing Format Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--20. " ERJW ,Extended Resync Jump Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 10.--15. " EPROPSEG ,Extended Propagation Segment" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. " EPSEG1 ,Extended Phase Segment 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0.--4. " EPSEG2 ,Extended Phase Segment 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "RXIMR0,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x884++0x03
|
|
line.long 0x00 "RXIMR1,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "RXIMR2,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x88C++0x03
|
|
line.long 0x00 "RXIMR3,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "RXIMR4,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x894++0x03
|
|
line.long 0x00 "RXIMR5,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "RXIMR6,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x89C++0x03
|
|
line.long 0x00 "RXIMR7,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "RXIMR8,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8A4++0x03
|
|
line.long 0x00 "RXIMR9,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "RXIMR10,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8AC++0x03
|
|
line.long 0x00 "RXIMR11,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "RXIMR12,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8B4++0x03
|
|
line.long 0x00 "RXIMR13,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "RXIMR14,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
rgroup.long 0x8BC++0x03
|
|
line.long 0x00 "RXIMR15,Rx Individual Mask Registers"
|
|
bitfld.long 0x00 31. " MI ,Mask bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Mask bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Mask bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Mask bit 0" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.open "Human-machine interface"
|
|
tree.open "GPIO (General-Purpose Input/Output)"
|
|
tree.open "GPIO"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
base ad:0x400FF000
|
|
width 12.
|
|
tree "GPIOA"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_PDOR,Port Data Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTA17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTA16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTA15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTA14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTA13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTA12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTA11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTA10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTA9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTA8" "Low,High"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 13. " PDO[13] ,Port Data Output PTA13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTA12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTA11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTA10" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTA7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTA6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTA5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTA4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTA3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTA2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTA1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTA0" "Low,High"
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "GPIOA_PSOR,Port Set Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTA17" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTA16" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTA15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTA14" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTA13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTA12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTA11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTA10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTA9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTA8" "No effect,Set"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 13. " PTSO[13] ,Port Set Output PTA13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTA12" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTA11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTA10" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTA6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTA5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTA4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTA2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTA0" "No effect,Set"
|
|
line.long 0x04 "GPIOA_PCOR,Port Clear Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTA17" "No effect,Clear"
|
|
bitfld.long 0x04 16. " [16] ,Port Clear Output PTA16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [15] ,Port Clear Output PTA15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Port Clear Output PTA14" "No effect,Clear"
|
|
bitfld.long 0x04 13. " [13] ,Port Clear Output PTA13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTA12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,Port Clear Output PTA11" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTA10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Port Clear Output PTA9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Port Clear Output PTA8" "No effect,Clear"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 13. " PTCO[13] ,Port Clear Output PTA13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTA12" "No effect,Clear"
|
|
bitfld.long 0x04 11. " [11] ,Port Clear Output PTA11" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTA10" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
line.long 0x08 "GPIOA_PTOR,Port Toggle Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTA17" "No effect,Toggle"
|
|
bitfld.long 0x08 16. " [16] ,Port Toggle Output PTA16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Port Toggle Output PTA15" "No effect,Toggle"
|
|
bitfld.long 0x08 14. " [14] ,Port Toggle Output PTA14" "No effect,Toggle"
|
|
bitfld.long 0x08 13. " [13] ,Port Toggle Output PTA13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTA12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Port Toggle Output PTA11" "No effect,Toggle"
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTA10" "No effect,Toggle"
|
|
bitfld.long 0x08 9. " [9] ,Port Toggle Output PTA9" "No effect,Toggle"
|
|
bitfld.long 0x08 8. " [8] ,Port Toggle Output PTA8" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x08 13. " PTTO[13] ,Port Toggle Output PTA13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTA12" "No effect,Toggle"
|
|
bitfld.long 0x08 11. " [11] ,Port Toggle Output PTA11" "No effect,Toggle"
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTA10" "No effect,Toggle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Port Toggle Output PTA7" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [6] ,Port Toggle Output PTA6" "No effect,Toggle"
|
|
bitfld.long 0x08 5. " [5] ,Port Toggle Output PTA5" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [4] ,Port Toggle Output PTA4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Port Toggle Output PTA3" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [2] ,Port Toggle Output PTA2" "No effect,Toggle"
|
|
bitfld.long 0x08 1. " [1] ,Port Toggle Output PTA1" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [0] ,Port Toggle Output PTA0" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_PDIR,Port Data Input Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTA17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTA16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTA15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTA14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTA13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTA12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTA11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTA10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTA9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTA8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " PDI[13] ,Port Data Input PTA13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTA12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTA11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTA10" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTA7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTA6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTA5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTA4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTA3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTA2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTA1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTA0" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_PDDR,Port Data Direction Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTA17" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTA16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTA15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTA14" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTA13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTA12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTA11" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTA10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTA9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTA8" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 13. " PDD[13] ,Port Data Direction PTA13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTA12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTA11" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTA10" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTA6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTA5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTA4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTA2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTA0" "Input,Output"
|
|
tree.end
|
|
tree "GPIOB"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIOB_PDOR,Port Data Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTB17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTB16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTB15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTB14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTB13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTB12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTB11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTB10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTB9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTB8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " PDO[13] ,Port Data Output PTB13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTB12" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTB7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTB6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTB5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTB4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTB3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTB2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTB1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTB0" "Low,High"
|
|
wgroup.long 0x44++0x0B
|
|
line.long 0x00 "GPIOB_PSOR,Port Set Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTB17" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTB16" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTB15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTB14" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTB13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTB12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTB11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTB10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTB9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTB8" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 13. " PTSO[13] ,Port Set Output PTB13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTB12" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTB6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTB4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTB0" "No effect,Set"
|
|
line.long 0x04 "GPIOB_PCOR,Port Clear Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTB17" "No effect,Clear"
|
|
bitfld.long 0x04 16. " [16] ,Port Clear Output PTB16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [15] ,Port Clear Output PTB15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Port Clear Output PTB14" "No effect,Clear"
|
|
bitfld.long 0x04 13. " [13] ,Port Clear Output PTB13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTB12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,Port Clear Output PTB11" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTB10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Port Clear Output PTB9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Port Clear Output PTB8" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 13. " PTCO[13] ,Port Clear Output PTB13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTB12" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Port Clear Output PTB6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,Port Clear Output PTB4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Port Clear Output PTB3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Port Clear Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [1] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Port Clear Output PTB0" "No effect,Clear"
|
|
line.long 0x08 "GPIOB_PTOR,Port Toggle Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTB17" "No effect,Toggle"
|
|
bitfld.long 0x08 16. " [16] ,Port Toggle Output PTB16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Port Toggle Output PTB15" "No effect,Toggle"
|
|
bitfld.long 0x08 14. " [14] ,Port Toggle Output PTB14" "No effect,Toggle"
|
|
bitfld.long 0x08 13. " [13] ,Port Toggle Output PTB13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTB12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Port Toggle Output PTB11" "No effect,Toggle"
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTB10" "No effect,Toggle"
|
|
bitfld.long 0x08 9. " [9] ,Port Toggle Output PTB9" "No effect,Toggle"
|
|
bitfld.long 0x08 8. " [8] ,Port Toggle Output PTB8" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x08 13. " PTTO[13] ,Port Toggle Output PTB13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTB12" "No effect,Toggle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Port Toggle Output PTB7" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [6] ,Port Toggle Output PTB6" "No effect,Toggle"
|
|
bitfld.long 0x08 5. " [5] ,Port Toggle Output PTB5" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [4] ,Port Toggle Output PTB4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Port Toggle Output PTB3" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [2] ,Port Toggle Output PTB2" "No effect,Toggle"
|
|
bitfld.long 0x08 1. " [1] ,Port Toggle Output PTB1" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [0] ,Port Toggle Output PTB0" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIOB_PDIR,Port Data Input Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTB17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTB16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTB15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTB14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTB13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTB12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTB11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTB10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTB9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTB8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " PDI[13] ,Port Data Input PTB13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTB12" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTB7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTB6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTB5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTB4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTB3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTB2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTB1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTB0" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIOB_PDDR,Port Data Direction Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTB17" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTB16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTB15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTB14" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTB13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTB12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTB11" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTB10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTB9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTB8" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 13. " PDD[13] ,Port Data Direction PTB13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTB12" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTB6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTB4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTB3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTB0" "Input,Output"
|
|
tree.end
|
|
tree "GPIOC"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIOC_PDOR,Port Data Output Register"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTC17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTC16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTC15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTC14" "Low,High"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTC13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTC12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTC11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTC10" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTC9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTC8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTC7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTC6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTC5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTC4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTC3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTC2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTC1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTC0" "Low,High"
|
|
wgroup.long 0x84++0x0B
|
|
line.long 0x00 "GPIOC_PSOR,Port Set Output Register"
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTC17" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTC16" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTC15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTC14" "No effect,Set"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTC13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTC12" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTC11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTC10" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTC9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTC8" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTC7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTC6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTC4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTC2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTC1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTC0" "No effect,Set"
|
|
line.long 0x04 "GPIOC_PCOR,Port Clear Output Register"
|
|
bitfld.long 0x04 17. " PTSO[17] ,Port Clear Output PTC17" "No effect,Clear"
|
|
bitfld.long 0x04 16. " [16] ,Port Clear Output PTC16" "No effect,Clear"
|
|
bitfld.long 0x04 15. " [15] ,Port Clear Output PTC15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Port Clear Output PTC14" "No effect,Clear"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x04 13. " [13] ,Port Clear Output PTC13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTC12" "No effect,Clear"
|
|
bitfld.long 0x04 11. " [11] ,Port Clear Output PTC11" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTC10" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Port Clear Output PTC9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Port Clear Output PTC8" "No effect,Clear"
|
|
bitfld.long 0x04 7. " [7] ,Port Clear Output PTC7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Port Clear Output PTC6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [5] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,Port Clear Output PTC4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " [3] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Port Clear Output PTC2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [1] ,Port Clear Output PTC1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Port Clear Output PTC0" "No effect,Clear"
|
|
line.long 0x08 "GPIOC_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTC17" "No effect,Toggle"
|
|
bitfld.long 0x08 16. " [16] ,Port Toggle Output PTC16" "No effect,Toggle"
|
|
bitfld.long 0x08 15. " [15] ,Port Toggle Output PTC15" "No effect,Toggle"
|
|
bitfld.long 0x08 14. " [14] ,Port Toggle Output PTC14" "No effect,Toggle"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x08 13. " [13] ,Port Toggle Output PTC13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTC12" "No effect,Toggle"
|
|
bitfld.long 0x08 11. " [11] ,Port Toggle Output PTC11" "No effect,Toggle"
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTC10" "No effect,Toggle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 9. " [9] ,Port Toggle Output PTC9" "No effect,Toggle"
|
|
bitfld.long 0x08 8. " [8] ,Port Toggle Output PTC8" "No effect,Toggle"
|
|
bitfld.long 0x08 7. " [7] ,Port Toggle Output PTC7" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [6] ,Port Toggle Output PTC6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 5. " [5] ,Port Toggle Output PTC5" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [4] ,Port Toggle Output PTC4" "No effect,Toggle"
|
|
bitfld.long 0x08 3. " [3] ,Port Toggle Output PTC3" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [2] ,Port Toggle Output PTC2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 1. " [1] ,Port Toggle Output PTC1" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [0] ,Port Toggle Output PTC0" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIOC_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTC17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTC16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTC15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTC14" "Low,High"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTC13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTC12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTC11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTC10" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTC9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTC8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTC7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTC6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTC5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTC4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTC3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTC2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTC1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTC0" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIOC_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Direction PTC17" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTC16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTC15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTC14" "Input,Output"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTC13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTC12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTC11" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTC10" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTC9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTC8" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTC7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTC6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTC4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTC2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTC1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTC0" "Input,Output"
|
|
tree.end
|
|
tree "GPIOD"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIOD_PDOR,Port Data Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTD17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTD16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTD15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTD14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTD13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTD12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTD11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTD10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTD9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTD8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 16. " PDO[16] ,Port Data Output PTD16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTD15" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTD7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTD6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTD5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTD4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTD3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTD2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTD1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTD0" "Low,High"
|
|
wgroup.long 0xC4++0x0B
|
|
line.long 0x00 "GPIOD_PSOR,Port Set Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTD17" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTD16" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTD15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTD14" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTD13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTD12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTD11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTD10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTD9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTD8" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 16. " PTSO[16] ,Port Set Output PTD16" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTD15" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTD6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTD4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTD3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTD2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTD0" "No effect,Set"
|
|
line.long 0x04 "GPIOD_PCOR,Port Clear Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTD17" "No effect,Clear"
|
|
bitfld.long 0x04 16. " [16] ,Port Clear Output PTD16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [15] ,Port Clear Output PTD15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Port Clear Output PTD14" "No effect,Clear"
|
|
bitfld.long 0x04 13. " [13] ,Port Clear Output PTD13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTD12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,Port Clear Output PTD11" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTD10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Port Clear Output PTD9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Port Clear Output PTD8" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 16. " PTCO[16] ,Port Clear Output PTD16" "No effect,Clear"
|
|
bitfld.long 0x04 15. " [15] ,Port Clear Output PTD15" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Port Clear Output PTD6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,Port Clear Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Port Clear Output PTD3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Port Clear Output PTD2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [1] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Port Clear Output PTD0" "No effect,Clear"
|
|
line.long 0x08 "GPIOD_PTOR,Port Toggle Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTD17" "No effect,Toggle"
|
|
bitfld.long 0x08 16. " [16] ,Port Toggle Output PTD16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Port Toggle Output PTD15" "No effect,Toggle"
|
|
bitfld.long 0x08 14. " [14] ,Port Toggle Output PTD14" "No effect,Toggle"
|
|
bitfld.long 0x08 13. " [13] ,Port Toggle Output PTD13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTD12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Port Toggle Output PTD11" "No effect,Toggle"
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTD10" "No effect,Toggle"
|
|
bitfld.long 0x08 9. " [9] ,Port Toggle Output PTD9" "No effect,Toggle"
|
|
bitfld.long 0x08 8. " [8] ,Port Toggle Output PTD8" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x08 16. " PTTO[16] ,Port Toggle Output PTD16" "No effect,Toggle"
|
|
bitfld.long 0x08 15. " [15] ,Port Toggle Output PTD15" "No effect,Toggle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Port Toggle Output PTD7" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [6] ,Port Toggle Output PTD6" "No effect,Toggle"
|
|
bitfld.long 0x08 5. " [5] ,Port Toggle Output PTD5" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [4] ,Port Toggle Output PTD4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Port Toggle Output PTD3" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [2] ,Port Toggle Output PTD2" "No effect,Toggle"
|
|
bitfld.long 0x08 1. " [1] ,Port Toggle Output PTD1" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [0] ,Port Toggle Output PTD0" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIOD_PDIR,Port Data Input Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTD17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTD16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTD15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTD14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTD13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTD12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTD11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTD10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTD9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTD8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 16. " PDI[16] ,Port Data Input PTD16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTD15" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTD7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTD6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTD5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTD4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTD3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTD2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTD1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTD0" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIOD_PDDR,Port Data Direction Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTD17" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTD16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTD15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTD14" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTD13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTD12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTD11" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTD10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTD9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTD8" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 16. " PDD[16] ,Port Data Direction PTD16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTD15" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTD6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTD4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTD3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTD2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTD0" "Input,Output"
|
|
tree.end
|
|
tree "GPIOE"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIOE_PDOR,Port Data Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 16. " PDO[16] ,Port Data Output PTE16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTE15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTE14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTE13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTE12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTE11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTE10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTE9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTE8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 11. " PDO[11] ,Port Data Output PTE11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTE10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTE9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTE8" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTE6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTE5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTE4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTE3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low,High"
|
|
wgroup.long 0x104++0x0B
|
|
line.long 0x00 "GPIOE_PSOR,Port Set Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 16. " PTSO[16] ,Port Set Output PTE16" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTE15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTE14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTE13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTE12" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTE11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTE10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTE9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTE8" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 11. " PTSO[11] ,Port Set Output PTE11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTE10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTE9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTE8" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTE5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTE4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
line.long 0x04 "GPIOE_PCOR,Port Clear Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x04 16. " PTCO[16] ,Port Clear Output PTE16" "No effect,Clear"
|
|
bitfld.long 0x04 15. " [15] ,Port Clear Output PTE15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Port Clear Output PTE14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [13] ,Port Clear Output PTE13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Port Clear Output PTE12" "No effect,Clear"
|
|
bitfld.long 0x04 11. " [11] ,Port Clear Output PTE11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTE10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Port Clear Output PTE9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Port Clear Output PTE8" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 11. " PTCO[11] ,Port Clear Output PTE11" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,Port Clear Output PTE10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Port Clear Output PTE9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Port Clear Output PTE8" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
line.long 0x08 "GPIOE_PTOR,Port Toggle Output Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x08 16. " PTTO[16] ,Port Toggle Output PTE16" "No effect,Toggle"
|
|
bitfld.long 0x08 15. " [15] ,Port Toggle Output PTE15" "No effect,Toggle"
|
|
bitfld.long 0x08 14. " [14] ,Port Toggle Output PTE14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 13. " [13] ,Port Toggle Output PTE13" "No effect,Toggle"
|
|
bitfld.long 0x08 12. " [12] ,Port Toggle Output PTE12" "No effect,Toggle"
|
|
bitfld.long 0x08 11. " [11] ,Port Toggle Output PTE11" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTE10" "No effect,Toggle"
|
|
bitfld.long 0x08 9. " [9] ,Port Toggle Output PTE9" "No effect,Toggle"
|
|
bitfld.long 0x08 8. " [8] ,Port Toggle Output PTE8" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x08 11. " PTTO[11] ,Port Toggle Output PTE11" "No effect,Toggle"
|
|
bitfld.long 0x08 10. " [10] ,Port Toggle Output PTE10" "No effect,Toggle"
|
|
bitfld.long 0x08 9. " [9] ,Port Toggle Output PTE9" "No effect,Toggle"
|
|
bitfld.long 0x08 8. " [8] ,Port Toggle Output PTE8" "No effect,Toggle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [6] ,Port Toggle Output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x08 5. " [5] ,Port Toggle Output PTE5" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [4] ,Port Toggle Output PTE4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Port Toggle Output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x08 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIOE_PDIR,Port Data Input Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 16. " PDI[16] ,Port Data Input PTE16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTE15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTE14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTE13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTE12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTE11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTE10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTE9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTE8" "Low,High"
|
|
else
|
|
bitfld.long 0x00 11. " PDI[11] ,Port Data Input PTE11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTE10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTE9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTE8" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTE6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTE5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTE4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTE3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIOE_PDDR,Port Data Direction Register"
|
|
sif (cpuis("MKE14Z???VLL7")||cpuis("MKE15Z???VLL7")||cpuis("MKE14F???VLL16")||cpuis("MKE16F???VLL16")||cpuis("MKE18F???VLL16"))
|
|
bitfld.long 0x00 16. " PDD[16] ,Port Data Direction PTE16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTE15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTE14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTE13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTE12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTE11" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTE10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTE9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTE8" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 11. " PDD[11] ,Port Data Direction PTE11" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTE10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTE9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTE8" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTE5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTE4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
tree "GPIOA"
|
|
base ad:0x400FF000
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "GPIOA_PDOR,Port Data Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Output PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Output PTD3" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTD3" "Low level,High level"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTD0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Output PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Output PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Output PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Output PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTC0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTA4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTA2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTA0" "Low level,High level"
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "GPIOA_PSOR,Port Set Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTD6" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Set Output PTD3" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTD3" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTD2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTD0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Set Output PTC7" "No effect,Set"
|
|
bitfld.long 0x00 22. " [22] ,Port Set Output PTC6" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] ,Port Set Output PTC4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTC2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTC1" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTC0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTB6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTB4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTB0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTA6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTA5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTA4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTA2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTA0" "No effect,Set"
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "GPIOA_PCOR,Port Clear Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTCO[31] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTD6" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 27. " PTCO[27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTD0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Clear Output PTC7" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,Port Clear Output PTC6" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,Port Clear Output PTC4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTC2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTC1" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTC0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTB6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTB4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTB3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTB0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "GPIOA_PTOR,Port Toggle Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggled Output PTD7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggled Output PTD6" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " [29] ,Port Toggled Output PTD5" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Toggled Output PTD3" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 27. " PTTO[27] ,Port Toggled Output PTD3" "No effect,Toggle"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Toggled Output PTD2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggled Output PTD1" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " [24] ,Port Toggled Output PTD0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Toggled Output PTC7" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " [22] ,Port Toggled Output PTC6" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " [21] ,Port Toggled Output PTC5" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " [20] ,Port Toggled Output PTC4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Toggled Output PTC3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggled Output PTC2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggled Output PTC1" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " [16] ,Port Toggled Output PTC0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Toggled Output PTB7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggled Output PTB6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggled Output PTB5" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Port Toggled Output PTB4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Toggled Output PTB3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggled Output PTB2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggled Output PTB1" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Port Toggled Output PTB0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Toggled Output PTA7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggled Output PTA6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggled Output PTA5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggled Output PTA4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggled Output PTA3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggled Output PTA2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggled Output PTA1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggled Output PTA0" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "GPIOA_PDIR,Port Data Input Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Input PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Input PTD3" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTD3" "Low level,High level"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTD0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Input PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Input PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Input PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Input PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTC0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTA4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTA2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTA0" "Low level,High level"
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "GPIOA_PDDR,Port Data Direction Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTD6" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Direction PTD3" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTD3" "Input,Output"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTD2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTD0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Direction PTC7" "Input,Output"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Direction PTC6" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Direction PTC4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTC2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTC1" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTC0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTB6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTB4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTB3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTB0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTA6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTA5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTA4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTA2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTA0" "Input,Output"
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "GPIOA_PIDR,Port Input Disable Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTD7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTD6" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Port Input Disable PTD5" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Input Disable PTD3" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 27. " PID[27] ,Port Input Disable PTD3" "No,Yes"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTD2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTD1" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTD0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Input Disable PTC7" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Port Input Disable PTC6" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Port Input Disable PTC5" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Port Input Disable PTC4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTC3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTC2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTC1" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTC0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTB7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTB6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTB5" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTB4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTB3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTB2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTB1" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTB0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTA7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTA6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTA5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTA4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTA3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTA2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTA1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTA0" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x400FF040
|
|
sif (cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLD4R"))
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "GPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port data output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port data output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port data output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port data output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port data output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port data output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port data output PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port data output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port data output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port data output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port data output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port data output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port data output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port data output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port data output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port data output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data output PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 26. " PDO[26] ,Port data output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data output PTE0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "GPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port set output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port set output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port set output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port set output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port set output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " [19] ,Port set output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port set output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port set output PTG1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port set output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port set output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port set output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port set output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port set output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port set output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port set output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port set output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port set output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port set output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port set output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port set output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port set output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port set output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port set output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port set output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port set output PTE0" "No effect,Set"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port set output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port set output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port set output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port set output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port set output PTE0" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "GPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port clear output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port clear output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port clear output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port clear output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port clear output PTH0" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,Port clear output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port clear output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port clear output PTG1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port clear output PTG0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port clear output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port clear output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port clear output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port clear output PTF4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port clear output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port clear output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port clear output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port clear output PTF0" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port clear output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port clear output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port clear output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port clear output PTE4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port clear output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port clear output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port clear output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port clear output PTE0" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTGO[26] ,Port clear output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port clear output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port clear output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port clear output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTGO[0] ,Port clear output PTE0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "GPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port toggle output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port toggle output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port toggle output PTH1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port toggle output PTH0" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " [19] ,Port toggle output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port toggle output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port toggle output PTG1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port toggle output PTG0" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " [15] ,Port toggle output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port toggle output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port toggle output PTF5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port toggle output PTF4" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Port toggle output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port toggle output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port toggle output PTF1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port toggle output PTF0" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port toggle output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port toggle output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port toggle output PTE5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port toggle output PTE4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Port toggle output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port toggle output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port toggle output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port toggle output PTE0" "No effect,Toggle"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port toggle output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port toggle output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port toggle output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port toggle output PTE0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "GPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port data input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port data input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port data input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port data input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port data input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port data input PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port data input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port data input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port data input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port data input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port data input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port data input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port data input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port data input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port data input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data input PTE0" "Low level,High level"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data input PTE0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "GPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port data direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port data direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port data direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " [19] ,Port data direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port data direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port data direction PTG1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port data direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port data direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port data direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port data direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port data direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port data direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port data direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port data direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port data direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port data direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port data direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port data direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data direction PTE0" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port data direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port data direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port data direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data direction PTE0" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PDIR"
|
|
line.long 0x00 "GPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PID[31] ,Port input disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port input disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port input disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port input disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port input disable PTH0" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Port input disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port input disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port input disable PTG1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port input disable PTG0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port input disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port input disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port input disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port input disable PTF4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port input disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port input disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port input disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port input disable PTF0" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port input disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port input disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port input disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port input disable PTE4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port input disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port input disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port input disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port input disable PTE0" "No,Yes"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PID[26] ,Port input disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port input disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port input disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port input disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port input disable PTE0" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
elif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R"))
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "GPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Output PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Output PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Output PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Output PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Output PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Output PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTG1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTG0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTF5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTF4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTF1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTF0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTE5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTE4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "GPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] ,Port Set Output PTH5" "No effect,Set"
|
|
bitfld.long 0x00 28. " [28] ,Port Set Output PTH4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Set Output PTH3" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTH1" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTH0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Set Output PTG7" "No effect,Set"
|
|
bitfld.long 0x00 22. " [22] ,Port Set Output PTG6" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] ,Port Set Output PTG5" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] ,Port Set Output PTG4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTG1" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTG0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTF5" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTF4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTF1" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTF0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTE5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTE4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTG1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "GPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,Port Clear Output PTH5" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,Port Clear Output PTH4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Clear Output PTH3" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Clear Output PTG7" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,Port Clear Output PTG6" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,Port Clear Output PTG5" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,Port Clear Output PTG4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PTGO[26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "GPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggle Output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggle Output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " [29] ,Port Toggle Output PTH5" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " [28] ,Port Toggle Output PTH4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Toggle Output PTH3" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggle Output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggle Output PTH1" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " [24] ,Port Toggle Output PTH0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Toggle Output PTG7" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " [22] ,Port Toggle Output PTG6" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " [21] ,Port Toggle Output PTG5" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " [20] ,Port Toggle Output PTG4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Toggle Output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggle Output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggle Output PTG1" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " [16] ,Port Toggle Output PTG0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Toggle Output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggle Output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggle Output PTF5" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Port Toggle Output PTF4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Toggle Output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggle Output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggle Output PTF1" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Port Toggle Output PTF0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggle Output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTE5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTE4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggle Output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggle Output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggle Output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggle Output PTH1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Toggle Output PTH0" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " [19] ,Port Toggle Output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggle Output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggle Output PTG1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Toggle Output PTG0" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " [15] ,Port Toggle Output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggle Output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggle Output PTF5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Toggle Output PTF4" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Port Toggle Output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggle Output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggle Output PTF1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Toggle Output PTF0" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggle Output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTE5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTE4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "GPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Input PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Input PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Input PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Input PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Input PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Input PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Input PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTG1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTG0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTF5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTF4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTF1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTF0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTE5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTE4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "GPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Direction PTH5" "Input,Output"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Direction PTH4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Direction PTH3" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTH1" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTH0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Direction PTG7" "Input,Output"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Direction PTG6" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Direction PTG5" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Direction PTG4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTG1" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTG0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTF5" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTF4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTF1" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTF0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTE5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTE4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTG1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "GPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Port Input Disable PTH5" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Port Input Disable PTH4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Input Disable PTH3" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTH1" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTH0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Input Disable PTG7" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Port Input Disable PTG6" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Port Input Disable PTG5" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Port Input Disable PTG4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTG1" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTG0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTF5" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTF4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTF1" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTF0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTE5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTE4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTH0" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTG1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTG0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTF4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTF0" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTE4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
elif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "GPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port data output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port data output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port data output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port data output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port data output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port data output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port data output PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port data output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port data output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port data output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port data output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port data output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port data output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port data output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port data output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port data output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data output PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 26. " PDO[26] ,Port data output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data output PTE0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "GPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port set output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port set output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port set output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port set output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port set output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " [19] ,Port set output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port set output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port set output PTG1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port set output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port set output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port set output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port set output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port set output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port set output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port set output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port set output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port set output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port set output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port set output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port set output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port set output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port set output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port set output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port set output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port set output PTE0" "No effect,Set"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port set output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port set output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port set output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port set output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port set output PTE0" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "GPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port clear output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port clear output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port clear output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port clear output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port clear output PTH0" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,Port clear output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port clear output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port clear output PTG1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port clear output PTG0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port clear output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port clear output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port clear output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port clear output PTF4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port clear output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port clear output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port clear output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port clear output PTF0" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port clear output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port clear output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port clear output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port clear output PTE4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port clear output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port clear output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port clear output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port clear output PTE0" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTGO[26] ,Port clear output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port clear output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port clear output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port clear output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTGO[0] ,Port clear output PTE0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "GPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port toggle output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port toggle output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port toggle output PTH1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port toggle output PTH0" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " [19] ,Port toggle output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port toggle output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port toggle output PTG1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port toggle output PTG0" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " [15] ,Port toggle output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port toggle output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port toggle output PTF5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port toggle output PTF4" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Port toggle output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port toggle output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port toggle output PTF1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port toggle output PTF0" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port toggle output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port toggle output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port toggle output PTE5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port toggle output PTE4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Port toggle output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port toggle output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port toggle output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port toggle output PTE0" "No effect,Toggle"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port toggle output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port toggle output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port toggle output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port toggle output PTE0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "GPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port data input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port data input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port data input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port data input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port data input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port data input PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port data input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port data input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port data input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port data input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port data input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port data input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port data input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port data input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port data input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data input PTE0" "Low level,High level"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data input PTE0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "GPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port data direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port data direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port data direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " [19] ,Port data direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port data direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port data direction PTG1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port data direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port data direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port data direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port data direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port data direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port data direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port data direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port data direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port data direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port data direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port data direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port data direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data direction PTE0" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port data direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port data direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port data direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data direction PTE0" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PDIR"
|
|
line.long 0x00 "GPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PID[31] ,Port input disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port input disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port input disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port input disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port input disable PTH0" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Port input disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port input disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port input disable PTG1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port input disable PTG0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port input disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port input disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port input disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port input disable PTF4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port input disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port input disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port input disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port input disable PTF0" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port input disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port input disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port input disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port input disable PTE4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port input disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port input disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port input disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port input disable PTE0" "No,Yes"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PID[26] ,Port input disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port input disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port input disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port input disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port input disable PTE0" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R"))
|
|
tree "GPIOC"
|
|
base ad:0x400FF080
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "GPIOC_PDOR,Port Data Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTI4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTI3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTI2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTI0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTI4" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "GPIOC_PSOR,Port Set Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTI6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTI5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTI4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTI3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTI2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTI1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTI0" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTI4" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "GPIOC_PCOR,Port Clear Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTGO[6] ,Port Clear Output PTI6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTI5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTI3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTI2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTI1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTI0" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 4. " PTGO[4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "GPIOC_PTOR,Port Toggle Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output PTI6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTI5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTI4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTI3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTI2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTI1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTI0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output PTI4" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "GPIOC_PDIR,Port Data Input Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTI4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTI3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTI2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTI0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTI4" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "GPIOC_PDDR,Port Data Direction Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTI6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTI5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTI4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTI3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTI2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTI1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTI0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTI4" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "GPIOC_PIDR,Port Input Disable Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PID[6] ,Port Input Disable PTI6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTI5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTI4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTI3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTI2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTI1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTI0" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 4. " PID[4] ,Port Input Disable PTI4" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLH4R")
|
|
tree.open "FGPIO"
|
|
tree "FGPIOA"
|
|
base ad:0xF8000000
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOA_PDOR,Port Data Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Output PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Output PTD3" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTD3" "Low level,High level"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTD0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Output PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Output PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Output PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Output PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTC0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTA4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTA2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTA0" "Low level,High level"
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOA_PSOR,Port Set Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTD6" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Set Output PTD3" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTD3" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTD2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTD0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Set Output PTC7" "No effect,Set"
|
|
bitfld.long 0x00 22. " [22] ,Port Set Output PTC6" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] ,Port Set Output PTC4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTC2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTC1" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTC0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTB6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTB4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTB0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTA6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTA5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTA4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTA2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTA0" "No effect,Set"
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOA_PCOR,Port Clear Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTCO[31] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTD6" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 27. " PTCO[27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTD0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Clear Output PTC7" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,Port Clear Output PTC6" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,Port Clear Output PTC4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTC2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTC1" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTC0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTB6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTB4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTB3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTB0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOA_PTOR,Port Toggle Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggled Output PTD7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggled Output PTD6" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " [29] ,Port Toggled Output PTD5" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Toggled Output PTD3" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 27. " PTTO[27] ,Port Toggled Output PTD3" "No effect,Toggle"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Toggled Output PTD2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggled Output PTD1" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " [24] ,Port Toggled Output PTD0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Toggled Output PTC7" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " [22] ,Port Toggled Output PTC6" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " [21] ,Port Toggled Output PTC5" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " [20] ,Port Toggled Output PTC4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Toggled Output PTC3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggled Output PTC2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggled Output PTC1" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " [16] ,Port Toggled Output PTC0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Toggled Output PTB7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggled Output PTB6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggled Output PTB5" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Port Toggled Output PTB4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Toggled Output PTB3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggled Output PTB2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggled Output PTB1" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Port Toggled Output PTB0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Toggled Output PTA7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggled Output PTA6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggled Output PTA5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggled Output PTA4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggled Output PTA3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggled Output PTA2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggled Output PTA1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggled Output PTA0" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOA_PDIR,Port Data Input Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Input PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Input PTD3" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTD3" "Low level,High level"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTD0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Input PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Input PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Input PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Input PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTC0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTA4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTA2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTA0" "Low level,High level"
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOA_PDDR,Port Data Direction Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTD6" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Direction PTD3" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTD3" "Input,Output"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTD2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTD0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Direction PTC7" "Input,Output"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Direction PTC6" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Direction PTC4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTC2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTC1" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTC0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTB6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTB4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTB3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTB0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTA6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTA5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTA4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTA2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTA0" "Input,Output"
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "FGPIOA_PIDR,Port Input Disable Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTD7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTD6" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Port Input Disable PTD5" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Input Disable PTD3" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 27. " PID[27] ,Port Input Disable PTD3" "No,Yes"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTD2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTD1" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTD0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Input Disable PTC7" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Port Input Disable PTC6" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Port Input Disable PTC5" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Port Input Disable PTC4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTC3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTC2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTC1" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTC0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTB7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTB6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTB5" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTB4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTB3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTB2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTB1" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTB0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTA7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTA6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTA5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTA4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTA3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTA2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTA1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTA0" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FGPIOB"
|
|
base ad:0xF8000040
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Output PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Output PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Output PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Output PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Output PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Output PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTG1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTG0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTF5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTF4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTF1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTF0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTE5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTE4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] ,Port Set Output PTH5" "No effect,Set"
|
|
bitfld.long 0x00 28. " [28] ,Port Set Output PTH4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Set Output PTH3" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTH1" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTH0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Set Output PTG7" "No effect,Set"
|
|
bitfld.long 0x00 22. " [22] ,Port Set Output PTG6" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] ,Port Set Output PTG5" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] ,Port Set Output PTG4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTG1" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTG0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTF5" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTF4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTF1" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTF0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTE5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTE4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTG1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,Port Clear Output PTH5" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,Port Clear Output PTH4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Clear Output PTH3" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Clear Output PTG7" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,Port Clear Output PTG6" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,Port Clear Output PTG5" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,Port Clear Output PTG4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PTGO[26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggle Output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggle Output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " [29] ,Port Toggle Output PTH5" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " [28] ,Port Toggle Output PTH4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Toggle Output PTH3" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggle Output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggle Output PTH1" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " [24] ,Port Toggle Output PTH0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Toggle Output PTG7" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " [22] ,Port Toggle Output PTG6" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " [21] ,Port Toggle Output PTG5" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " [20] ,Port Toggle Output PTG4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Toggle Output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggle Output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggle Output PTG1" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " [16] ,Port Toggle Output PTG0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Toggle Output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggle Output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggle Output PTF5" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Port Toggle Output PTF4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Toggle Output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggle Output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggle Output PTF1" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Port Toggle Output PTF0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggle Output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTE5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTE4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggle Output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggle Output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggle Output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggle Output PTH1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Toggle Output PTH0" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " [19] ,Port Toggle Output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggle Output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggle Output PTG1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Toggle Output PTG0" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " [15] ,Port Toggle Output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggle Output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggle Output PTF5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Toggle Output PTF4" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Port Toggle Output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggle Output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggle Output PTF1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Toggle Output PTF0" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggle Output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTE5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTE4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Input PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Input PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Input PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Input PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Input PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Input PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Input PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTG1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTG0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTF5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTF4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTF1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTF0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTE5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTE4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Direction PTH5" "Input,Output"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Direction PTH4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Direction PTH3" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTH1" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTH0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Direction PTG7" "Input,Output"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Direction PTG6" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Direction PTG5" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Direction PTG4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTG1" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTG0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTF5" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTF4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTF1" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTF0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTE5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTE4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTG1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "FGPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("MKE04Z64VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Port Input Disable PTH5" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Port Input Disable PTH4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Input Disable PTH3" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTH1" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTH0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Input Disable PTG7" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Port Input Disable PTG6" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Port Input Disable PTG5" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Port Input Disable PTG4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTG1" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTG0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTF5" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTF4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTF1" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTF0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTE5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTE4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
elif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTH0" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTG1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTG0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTF4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTF0" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTE4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "FGPIOC"
|
|
base ad:0xF8000080
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOC_PDOR,Port Data Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTI4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTI3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTI2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTI0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTI4" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOC_PSOR,Port Set Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTI6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTI5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTI4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTI3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTI2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTI1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTI0" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTI4" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOC_PCOR,Port Clear Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTGO[6] ,Port Clear Output PTI6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTI5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTI3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTI2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTI1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTI0" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 4. " PTGO[4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOC_PTOR,Port Toggle Output Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output PTI6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTI5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTI4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTI3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTI2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTI1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTI0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output PTI4" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOC_PDIR,Port Data Input Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTI4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTI3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTI2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTI0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTI4" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOC_PDDR,Port Data Direction Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTI6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTI5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTI4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTI3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTI2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTI1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTI0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTI4" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "FGPIOC_PIDR,Port Input Disable Register"
|
|
sif (cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE04Z64VLK4R")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4"))
|
|
bitfld.long 0x00 6. " PID[6] ,Port Input Disable PTI6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTI5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTI4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTI3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTI2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTI1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTI0" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 4. " PID[4] ,Port Input Disable PTI4" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
elif (cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z16VLD4")||cpuis("MKE02Z32VLD4")||cpuis("MKE02Z64VLD4")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VFM4R"))
|
|
tree.open "FGPIO"
|
|
tree "FGPIOA"
|
|
base ad:0xF8000000
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOA_PDOR,Port Data Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Output PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Output PTD3" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTD3" "Low level,High level"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTD0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Output PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Output PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Output PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Output PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTC0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTA4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTA2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTA0" "Low level,High level"
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOA_PSOR,Port Set Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTD6" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Set Output PTD3" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTD3" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTD2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTD0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Set Output PTC7" "No effect,Set"
|
|
bitfld.long 0x00 22. " [22] ,Port Set Output PTC6" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] ,Port Set Output PTC4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTC2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTC1" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTC0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTB6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTB4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTB0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTA6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTA5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTA4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTA2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTA0" "No effect,Set"
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOA_PCOR,Port Clear Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTCO[31] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTD6" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 27. " PTCO[27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTD0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Clear Output PTC7" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,Port Clear Output PTC6" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,Port Clear Output PTC4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTC2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTC1" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTC0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTB6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTB4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTB3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTB0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOA_PTOR,Port Toggle Output Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggled Output PTD7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggled Output PTD6" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " [29] ,Port Toggled Output PTD5" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Toggled Output PTD3" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 27. " PTTO[27] ,Port Toggled Output PTD3" "No effect,Toggle"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Toggled Output PTD2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggled Output PTD1" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " [24] ,Port Toggled Output PTD0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Toggled Output PTC7" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " [22] ,Port Toggled Output PTC6" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " [21] ,Port Toggled Output PTC5" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " [20] ,Port Toggled Output PTC4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Toggled Output PTC3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggled Output PTC2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggled Output PTC1" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " [16] ,Port Toggled Output PTC0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Toggled Output PTB7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggled Output PTB6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggled Output PTB5" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Port Toggled Output PTB4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Toggled Output PTB3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggled Output PTB2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggled Output PTB1" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Port Toggled Output PTB0" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Toggled Output PTA7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggled Output PTA6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggled Output PTA5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Port Toggled Output PTA4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Toggled Output PTA3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggled Output PTA2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggled Output PTA1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggled Output PTA0" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOA_PDIR,Port Data Input Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Input PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Input PTD3" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTD3" "Low level,High level"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTD0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Input PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Input PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Input PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Input PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTC0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTA4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTA2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTA0" "Low level,High level"
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOA_PDDR,Port Data Direction Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTD6" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Direction PTD3" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTD3" "Input,Output"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTD2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTD0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Data Direction PTC7" "Input,Output"
|
|
bitfld.long 0x00 22. " [22] ,Port Data Direction PTC6" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Direction PTC4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTC2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTC1" "Input,Output"
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTC0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTB6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTB4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTB3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTB0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTA6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTA5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTA4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTA2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTA0" "Input,Output"
|
|
group.long 0x18++0x03 "PIDR"
|
|
line.long 0x00 "FGPIOA_PIDR,Port Input Disable Register"
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VLC2R")&&!cpuis("MKE02Z32VFM4R"))
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTD7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTD6" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Port Input Disable PTD5" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Input Disable PTD3" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 27. " PID[27] ,Port Input Disable PTD3" "No,Yes"
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTD2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTD1" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTD0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Port Input Disable PTC7" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Port Input Disable PTC6" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Port Input Disable PTC5" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Port Input Disable PTC4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTC3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTC2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTC1" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTC0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTB7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTB6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTB5" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTB4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTB3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTB2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTB1" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTB0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTA7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTA6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTA5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTA4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTA3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTA2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTA1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTA0" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("MKE02Z16VLC4")&&!cpuis("MKE02Z32VLC4")&&!cpuis("MKE02Z64VLC4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z16VFM4")&&!cpuis("MKE02Z32VFM4")&&!cpuis("MKE02Z64VFM4")&&!cpuis("MKE02Z32VLC4R")&&!cpuis("MKE02Z32VFM4R"))
|
|
tree "FGPIOB"
|
|
base ad:0xF8000040
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port data output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port data output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port data output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port data output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port data output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port data output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port data output PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port data output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port data output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port data output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port data output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port data output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port data output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port data output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port data output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port data output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data output PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 26. " PDO[26] ,Port data output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data output PTE0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port set output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port set output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port set output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port set output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port set output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " [19] ,Port set output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port set output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port set output PTG1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port set output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port set output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port set output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port set output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port set output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port set output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port set output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port set output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port set output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port set output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port set output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port set output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port set output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port set output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port set output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port set output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port set output PTE0" "No effect,Set"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port set output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port set output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port set output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port set output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port set output PTE0" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port clear output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port clear output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port clear output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port clear output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port clear output PTH0" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,Port clear output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port clear output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port clear output PTG1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port clear output PTG0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port clear output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port clear output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port clear output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port clear output PTF4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port clear output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port clear output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port clear output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port clear output PTF0" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port clear output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port clear output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port clear output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port clear output PTE4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port clear output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port clear output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port clear output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port clear output PTE0" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTGO[26] ,Port clear output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port clear output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port clear output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port clear output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTGO[0] ,Port clear output PTE0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output PTH7" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Port toggle output PTH6" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Port toggle output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " [25] ,Port toggle output PTH1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port toggle output PTH0" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " [19] ,Port toggle output PTG3" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Port toggle output PTG2" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Port toggle output PTG1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port toggle output PTG0" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " [15] ,Port toggle output PTF7" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Port toggle output PTF6" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Port toggle output PTF5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port toggle output PTF4" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Port toggle output PTF3" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Port toggle output PTF2" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Port toggle output PTF1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port toggle output PTF0" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port toggle output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Port toggle output PTE6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Port toggle output PTE5" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port toggle output PTE4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Port toggle output PTE3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port toggle output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port toggle output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port toggle output PTE0" "No effect,Toggle"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output PTH2" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Port toggle output PTE7" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Port toggle output PTE2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Port toggle output PTE1" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port toggle output PTE0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port data input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port data input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port data input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port data input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port data input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port data input PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port data input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port data input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port data input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port data input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port data input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port data input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port data input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port data input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port data input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data input PTE0" "Low level,High level"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port data input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port data input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port data input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data input PTE0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port data direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port data direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port data direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port data direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " [19] ,Port data direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port data direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port data direction PTG1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port data direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port data direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port data direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port data direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port data direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port data direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port data direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port data direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port data direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port data direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port data direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port data direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port data direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port data direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port data direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port data direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data direction PTE0" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port data direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port data direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port data direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port data direction PTE0" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")||cpuis("MKE02Z32VLH4")||cpuis("MKE02Z64VLH4")||cpuis("MKE02Z32VQH4")||cpuis("MKE02Z64VQH4")||cpuis("MKE02Z64VLH4R")
|
|
bitfld.long 0x00 31. " PID[31] ,Port input disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port input disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port input disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port input disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port input disable PTH0" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Port input disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port input disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port input disable PTG1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port input disable PTG0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port input disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port input disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port input disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port input disable PTF4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port input disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port input disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port input disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port input disable PTF0" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port input disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port input disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port input disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port input disable PTE4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port input disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port input disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port input disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port input disable PTE0" "No,Yes"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PID[26] ,Port input disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port input disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port input disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port input disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port input disable PTE0" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
elif (!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
tree.open "FGPIO"
|
|
tree "FGPIOA"
|
|
base ad:0xF8000000
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOA_PDOR,Port Data Output Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTD6" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Data Output PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Output PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTD2" "Low level,High level"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTD2" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTD0" "Low level,High level"
|
|
bitfld.long 0x00 23. " [23] ,Port Data Output PTC7" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Data Output PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Output PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Output PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTC1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTC0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTB6" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTB4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTB3" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTA5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTA4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTA2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTA0" "Low level,High level"
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOA_PSOR,Port Set Output Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTD6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 28. " [28] ,Port Set Output PTD4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Set Output PTD3" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTD2" "No effect,Set"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTD3" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTD2" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTD0" "No effect,Set"
|
|
bitfld.long 0x00 23. " [23] ,Port Set Output PTC7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Set Output PTC6" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] ,Port Set Output PTC4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTC2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTC1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTC0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTB6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTB4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTB3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTB0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTA6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTA5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTA4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTA2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTA0" "No effect,Set"
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOA_PCOR,Port Clear Output Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PTCO[31] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTD6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,Port Clear Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PTCO[27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTD0" "No effect,Clear"
|
|
bitfld.long 0x00 23. " [23] ,Port Clear Output PTC7" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Clear Output PTC6" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,Port Clear Output PTC4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTC2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTC1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTC0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTB6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTB4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTB3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTB0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOA_PTOR,Port Toggle Output Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggled Output PTD7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggled Output PTD6" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Toggled Output PTD5" "Not toggled,Toggled"
|
|
bitfld.long 0x00 28. " [28] ,Port Toggled Output PTD4" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Toggled Output PTD3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggled Output PTD2" "Not toggled,Toggled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PTTO[27] ,Port Toggled Output PTD3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggled Output PTD2" "Not toggled,Toggled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Toggled Output PTD1" "Not toggled,Toggled"
|
|
bitfld.long 0x00 24. " [24] ,Port Toggled Output PTD0" "Not toggled,Toggled"
|
|
bitfld.long 0x00 23. " [23] ,Port Toggled Output PTC7" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Toggled Output PTC6" "Not toggled,Toggled"
|
|
bitfld.long 0x00 21. " [21] ,Port Toggled Output PTC5" "Not toggled,Toggled"
|
|
bitfld.long 0x00 20. " [20] ,Port Toggled Output PTC4" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Toggled Output PTC3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggled Output PTC2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggled Output PTC1" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Toggled Output PTC0" "Not toggled,Toggled"
|
|
bitfld.long 0x00 15. " [15] ,Port Toggled Output PTB7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggled Output PTB6" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Toggled Output PTB5" "Not toggled,Toggled"
|
|
bitfld.long 0x00 12. " [12] ,Port Toggled Output PTB4" "Not toggled,Toggled"
|
|
bitfld.long 0x00 11. " [11] ,Port Toggled Output PTB3" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Toggled Output PTB2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggled Output PTB1" "Not toggled,Toggled"
|
|
bitfld.long 0x00 8. " [8] ,Port Toggled Output PTB0" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Toggled Output PTA7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggled Output PTA6" "Not toggled,Toggled"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggled Output PTA5" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Toggled Output PTA4" "Not toggled,Toggled"
|
|
bitfld.long 0x00 3. " [3] ,Port Toggled Output PTA3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggled Output PTA2" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Toggled Output PTA1" "Not toggled,Toggled"
|
|
bitfld.long 0x00 0. " [0] ,Port Toggled Output PTA0" "Not toggled,Toggled"
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOA_PDIR,Port Data Input Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTD6" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Data Input PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Input PTD4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Input PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTD2" "Low level,High level"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTD2" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTD0" "Low level,High level"
|
|
bitfld.long 0x00 23. " [23] ,Port Data Input PTC7" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Data Input PTC6" "Low level,High level"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Input PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Input PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTC1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTC0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTB6" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTB4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTB3" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTB0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTA6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTA5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTA4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTA2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTA0" "Low level,High level"
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOA_PDDR,Port Data Direction Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTD6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 28. " [28] ,Port Data Direction PTD4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Data Direction PTD3" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTD2" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTD3" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTD2" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTD0" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Port Data Direction PTC7" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Data Direction PTC6" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Port Data Direction PTC4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTC2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTC1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTC0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTB6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTB4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTB3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTB0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTA6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTA5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTA4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTA2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTA0" "Input,Output"
|
|
group.long 0x18++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOA_PIDR,Port Input Disable Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VLC2R"))
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTD7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTD6" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " [29] ,Port Input Disable PTD5" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Port Input Disable PTD4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Port Input Disable PTD3" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTD2" "No,Yes"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 27. " PID[27] ,Port Input Disable PTD3" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTD2" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTD1" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTD0" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Port Input Disable PTC7" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] ,Port Input Disable PTC6" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Port Input Disable PTC5" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Port Input Disable PTC4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTC3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTC2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTC1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTC0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTB7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTB6" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTB5" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTB4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTB3" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTB2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTB1" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTB0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTA7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTA6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTA5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTA4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTA3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTA2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTA1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTA0" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("MKE02Z16VLC2")&&!cpuis("MKE02Z32VLC2")&&!cpuis("MKE02Z64VLC2")&&!cpuis("MKE02Z32VLC2R")&&!cpuis("MKE02Z16VLC2R"))
|
|
tree "FGPIOB"
|
|
base ad:0xF8000040
|
|
width 13.
|
|
group.long 0x00++0x03 "PDOR"
|
|
line.long 0x00 "FGPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Output PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Output PTE0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x03 "PSOR"
|
|
line.long 0x00 "FGPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")||cpuis("MKE02Z64VQH2")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " [25] ,Port Set Output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Set Output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " [19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,Port Set Output PTG1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Set Output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] ,Port Set Output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,Port Set Output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,Port Set Output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Set Output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] ,Port Set Output PTF3" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,Port Set Output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,Port Set Output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Set Output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Port Set Output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Set Output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] ,Port Set Output PTE3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 7. " [7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Set Output PTE0" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x08++0x03 "PCOR"
|
|
line.long 0x00 "FGPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")
|
|
bitfld.long 0x00 31. " PTGO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [11] ,Port Clear Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,Port Clear Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 26. " PTGO[26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x0C++0x03 "PTOR"
|
|
line.long 0x00 "FGPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port Toggle Output PTH7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 30. " [30] ,Port Toggle Output PTH6" "Not toggled,Toggled"
|
|
bitfld.long 0x00 26. " [26] ,Port Toggle Output PTH2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 25. " [25] ,Port Toggle Output PTH1" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Toggle Output PTH0" "Not toggled,Toggled"
|
|
bitfld.long 0x00 19. " [19] ,Port Toggle Output PTG3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 18. " [18] ,Port Toggle Output PTG2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 17. " [17] ,Port Toggle Output PTG1" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Toggle Output PTG0" "Not toggled,Toggled"
|
|
bitfld.long 0x00 15. " [15] ,Port Toggle Output PTF7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 14. " [14] ,Port Toggle Output PTF6" "Not toggled,Toggled"
|
|
bitfld.long 0x00 13. " [13] ,Port Toggle Output PTF5" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Toggle Output PTF4" "Not toggled,Toggled"
|
|
bitfld.long 0x00 11. " [11] ,Port Toggle Output PTF3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 10. " [10] ,Port Toggle Output PTF2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 9. " [9] ,Port Toggle Output PTF1" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Toggle Output PTF0" "Not toggled,Toggled"
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 6. " [6] ,Port Toggle Output PTE6" "Not toggled,Toggled"
|
|
bitfld.long 0x00 5. " [5] ,Port Toggle Output PTE5" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Toggle Output PTE4" "Not toggled,Toggled"
|
|
bitfld.long 0x00 3. " [3] ,Port Toggle Output PTE3" "Not toggled,Toggled"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "Not toggled,Toggled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output PTH2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 7. " [7] ,Port Toggle Output PTE7" "Not toggled,Toggled"
|
|
bitfld.long 0x00 2. " [2] ,Port Toggle Output PTE2" "Not toggled,Toggled"
|
|
bitfld.long 0x00 1. " [1] ,Port Toggle Output PTE1" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Toggle Output PTE0" "Not toggled,Toggled"
|
|
endif
|
|
rgroup.long 0x10++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Input PTG1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Input PTE0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x03 "PDDR"
|
|
line.long 0x00 "FGPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " [25] ,Port Data Direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Data Direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " [19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Port Data Direction PTG1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Data Direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " [13] ,Port Data Direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Data Direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Port Data Direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Data Direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Port Data Direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Data Direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 7. " [7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Data Direction PTE0" "Input,Output"
|
|
endif
|
|
group.long 0x18++0x03 "PDIR"
|
|
line.long 0x00 "FGPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("MKE02Z32VLH2")||cpuis("MKE02Z64VLH2")||cpuis("MKE02Z32VQH2")
|
|
bitfld.long 0x00 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Port Input Disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Port Input Disable PTH0" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Port Input Disable PTG1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Port Input Disable PTG0" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Port Input Disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Port Input Disable PTF4" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Port Input Disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Port Input Disable PTF0" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Port Input Disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Port Input Disable PTE4" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Port Input Disable PTE0" "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*"))
|
|
tree.open "KBI (Keyboard Interrupts)"
|
|
tree "KBI0"
|
|
base ad:0x40079000
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R"))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "KBI0_PE,KBI0 Pin Enable Register"
|
|
bitfld.long 0x00 31. " KBIPE[31] ,KBI Pin PTD7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,KBI Pin PTD6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,KBI Pin PTD5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,KBI Pin PTD4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,KBI Pin PTD3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,KBI Pin PTD2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,KBI Pin PTD1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,KBI Pin PTD0 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,KBI Pin PTC7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,KBI Pin PTC6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,KBI Pin PTC5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,KBI Pin PTC4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,KBI Pin PTC3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,KBI Pin PTC2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,KBI Pin PTC1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,KBI Pin PTC0 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Pin PTB7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,KBI Pin PTB6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,KBI Pin PTB5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,KBI Pin PTB4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Pin PTB3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,KBI Pin PTB2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,KBI Pin PTB1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,KBI Pin PTB0 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTA7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,KBI Pin PTA6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,KBI Pin PTA5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,KBI Pin PTA4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Pin PTA3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTA2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTA1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTA0 Interrupt Enables" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40079000+0x08))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI Pin PTD7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 30. " [30] ,KBI Pin PTD6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 29. " [29] ,KBI Pin PTD5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 28. " [28] ,KBI Pin PTD4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,KBI Pin PTD3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 26. " [26] ,KBI Pin PTD2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 25. " [25] ,KBI Pin PTD1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 24. " [24] ,KBI Pin PTD0 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,KBI Pin PTC7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 22. " [22] ,KBI Pin PTC6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 21. " [21] ,KBI Pin PTC5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 20. " [20] ,KBI Pin PTC4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,KBI Pin PTC3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 18. " [18] ,KBI Pin PTC2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 17. " [17] ,KBI Pin PTC1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 16. " [16] ,KBI Pin PTC0 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Pin PTB7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 14. " [14] ,KBI Pin PTB6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 13. " [13] ,KBI Pin PTB5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 12. " [12] ,KBI Pin PTB4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Pin PTB3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 10. " [10] ,KBI Pin PTB2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 9. " [9] ,KBI Pin PTB1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 8. " [8] ,KBI Pin PTB0 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTA7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 6. " [6] ,KBI Pin PTA6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 5. " [5] ,KBI Pin PTA5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 4. " [4] ,KBI Pin PTA4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Pin PTA3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTA2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTA1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTA0 Edge Select [Edge]" "Falling,Rising"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI Pin PTD7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 30. " [30] ,KBI Pin PTD6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 29. " [29] ,KBI Pin PTD5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 28. " [28] ,KBI Pin PTD4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,KBI Pin PTD3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 26. " [26] ,KBI Pin PTD2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 25. " [25] ,KBI Pin PTD1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 24. " [24] ,KBI Pin PTD0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,KBI Pin PTC7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 22. " [22] ,KBI Pin PTC6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 21. " [21] ,KBI Pin PTC5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 20. " [20] ,KBI Pin PTC4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,KBI Pin PTC3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 18. " [18] ,KBI Pin PTC2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 17. " [17] ,KBI Pin PTC1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 16. " [16] ,KBI Pin PTC0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Pin PTB7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 14. " [14] ,KBI Pin PTB6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 13. " [13] ,KBI Pin PTB5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 12. " [12] ,KBI Pin PTB4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Pin PTB3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 10. " [10] ,KBI Pin PTB2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 9. " [9] ,KBI Pin PTB1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 8. " [8] ,KBI Pin PTB0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTA7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 6. " [6] ,KBI Pin PTA6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 5. " [5] ,KBI Pin PTA5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 4. " [4] ,KBI Pin PTA4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Pin PTA3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTA2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTA1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTA0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
endif
|
|
sif (cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z8VFK4R")||cpuis("MKE04Z8VTG4R")||cpuis("MKE04Z8VWJ4R"))
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "KBI0_SC,KBI Status and Control Register"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "KBI0_SC,KBI Status and Control Register"
|
|
bitfld.long 0x00 5. " RSTKBSP ,Reset KBI_SP register" "Not reset,Reset"
|
|
bitfld.long 0x00 4. " KBSPEN ,Real KBI_SP register enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " KBF ,KBI Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Edges/Levels"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "KBI0_SP,KBI Source Pin Register"
|
|
bitfld.long 0x00 31. " SP[31] ,KBI Source Pin 31 - PTD7" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,KBI Source Pin 30 - PTD6" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,KBI Source Pin 29 - PTD5" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,KBI Source Pin 28 - PTD4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,KBI Source Pin 27 - PTD3" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,KBI Source Pin 26 - PTD2" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,KBI Source Pin 25 - PTD1" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,KBI Source Pin 24 - PTD0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,KBI Source Pin 23 - PTC7" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,KBI Source Pin 22 - PTC6" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,KBI Source Pin 21 - PTC5" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,KBI Source Pin 20 - PTC4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,KBI Source Pin 19 - PTC3" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,KBI Source Pin 18 - PTC2" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,KBI Source Pin 17 - PTC1" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,KBI Source Pin 16 - PTC0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Source Pin 15 - PTB7" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,KBI Source Pin 14 - PTB6" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,KBI Source Pin 13 - PTB5" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,KBI Source Pin 12 - PTB4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Source Pin 11 - PTB3" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,KBI Source Pin 10 - PTB2" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,KBI Source Pin 9 - PTB1" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,KBI Source Pin 8 - PTB0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Source Pin 7 - PTA7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,KBI Source Pin 6 - PTA6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,KBI Source Pin 5 - PTA5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,KBI Source Pin 4 - PTA4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Source Pin 3 - PTA3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,KBI Source Pin 2 - PTA2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,KBI Source Pin 1 - PTA1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,KBI Source Pin 0 - PTA0" "Low,High"
|
|
width 0xB
|
|
else
|
|
width 10.
|
|
sif (cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R"))
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "KBI0_SC,KBI Status and Control Register"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "KBI0_SC,KBI Status and Control Register"
|
|
rbitfld.byte 0x00 3. " KBF ,KBI Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " KBACK ,KBI Acknowledge" "No effect,KBF cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Edges/Levels"
|
|
endif
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "KBI0_PE,KBI0 Pin Enable Register"
|
|
bitfld.byte 0x00 7. " KBIPE[7] ,KBI Pin PTB3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " [6] ,KBI Pin PTB2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " [5] ,KBI Pin PTB1 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,KBI Pin PTB0 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " [3] ,KBI Pin PTA3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " [2] ,KBI Pin PTA2 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,KBI Pin PTA1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " [0] ,KBI Pin PTA0 Interrupt Enables" "Disabled,Enabled"
|
|
if (((per.b(ad:0x40079000))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.byte 0x00 7. " KBEDG[7] ,KBI Pin PTB3 Edge Selects [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 6. " [6] ,KBI Pin PTB2 Edge Selects [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 5. " [5] ,KBI Pin PTB1 Edge Selects [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,KBI Pin PTB0 Edge Selects [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 3. " [3] ,KBI Pin PTA3 Edge Selects [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 2. " [2] ,KBI Pin PTA2 Edge Selects [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,KBI Pin PTA1 Edge Selects [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 0. " [0] ,KBI Pin PTA0 Edge Selects [Edge]" "Falling,Rising"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.byte 0x00 7. " KBEDG[7] ,KBI Pin PTB3 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 6. " [6] ,KBI Pin PTB2 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 5. " [5] ,KBI Pin PTB1 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,KBI Pin PTB0 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 3. " [3] ,KBI Pin PTA3 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 2. " [2] ,KBI Pin PTA2 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,KBI Pin PTA1 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 0. " [0] ,KBI Pin PTA0 Edge Selects [Edge/Level]" "Falling/Low,Rising/High"
|
|
endif
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "KBI1"
|
|
base ad:0x4007A000
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE06Z64VLK4")||cpuis("MKE06Z128VLK4")||cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R"))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "KBI1_PE,KBI1 Pin Enable Register"
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4"))
|
|
bitfld.long 0x00 26. " KBIPE[26] ,KBI Pin PTH2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTE7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTE2 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTE1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTE0 Interrupt Enables" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 31. " KBIPE[31] ,KBI Pin PTH7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,KBI Pin PTH6 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!(cpuis("MKE06Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 29. " [29] ,KBI Pin PTH5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,KBI Pin PTH4 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,KBI Pin PTH3 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,KBI Pin PTH2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,KBI Pin PTH1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,KBI Pin PTH0 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!(cpuis("MKE06Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 23. " [23] ,KBI Pin PTG7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,KBI Pin PTG6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,KBI Pin PTG5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,KBI Pin PTG4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " [19] ,KBI Pin PTG3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,KBI Pin PTG2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,KBI Pin PTG1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,KBI Pin PTG0 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Pin PTF7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,KBI Pin PTF6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,KBI Pin PTF5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,KBI Pin PTF4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Pin PTF3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,KBI Pin PTF2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,KBI Pin PTF1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,KBI Pin PTF0 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTE7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,KBI Pin PTE6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,KBI Pin PTE5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,KBI Pin PTE4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Pin PTE3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTE2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTE1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTE0 Interrupt Enables" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x08))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI1_ES,KBI1 Edge Select Register"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " KBEDG[26] ,KBI Pin PTH2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTE7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTE2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTE1 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTE0 Edge Select [Edge]" "Falling,Rising"
|
|
else
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI Pin PTH7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 30. " [30] ,KBI Pin PTH6 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
sif (!(cpuis("MKE06Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 29. " [29] ,KBI Pin PTH5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 28. " [28] ,KBI Pin PTH4 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 27. " [27] ,KBI Pin PTH3 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,KBI Pin PTH2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 25. " [25] ,KBI Pin PTH1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 24. " [24] ,KBI Pin PTH0 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
sif (!(cpuis("MKE06Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 23. " [23] ,KBI Pin PTG7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 22. " [22] ,KBI Pin PTG6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 21. " [21] ,KBI Pin PTG5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 20. " [20] ,KBI Pin PTG4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " [19] ,KBI Pin PTG3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 18. " [18] ,KBI Pin PTG2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 17. " [17] ,KBI Pin PTG1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 16. " [16] ,KBI Pin PTG0 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Pin PTF7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 14. " [14] ,KBI Pin PTF6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 13. " [13] ,KBI Pin PTF5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 12. " [12] ,KBI Pin PTF4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Pin PTF3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 10. " [10] ,KBI Pin PTF2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 9. " [9] ,KBI Pin PTF1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 8. " [8] ,KBI Pin PTF0 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTE7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 6. " [6] ,KBI Pin PTE6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 5. " [5] ,KBI Pin PTE5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 4. " [4] ,KBI Pin PTE4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Pin PTE3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTE2 Edge/Level Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTE1 Edge/Level Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTE0 Edge/Level Select [Edge]" "Falling,Rising"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI1_ES,KBI1 Edge Select Register"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4")
|
|
bitfld.long 0x00 26. " KBEDG[26] ,KBI Pin PTH2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTE7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTE2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTE1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTE0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
else
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI Pin PTH7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 30. " [30] ,KBI Pin PTH6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
sif (!(cpuis("MKE06Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 29. " [29] ,KBI Pin PTH5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 28. " [28] ,KBI Pin PTH4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 27. " [27] ,KBI Pin PTH3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,KBI Pin PTH2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 25. " [25] ,KBI Pin PTH1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 24. " [24] ,KBI Pin PTH0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
sif (!(cpuis("MKE06Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE06Z64VQH4")||cpuis("MKE06Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE06Z64VLH4")||cpuis("MKE06Z128VLH4")||cpuis("MKE04Z128VLH4R")))
|
|
bitfld.long 0x00 23. " [23] ,KBI Pin PTG7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 22. " [22] ,KBI Pin PTG6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 21. " [21] ,KBI Pin PTG5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 20. " [20] ,KBI Pin PTG4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " [19] ,KBI Pin PTG3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 18. " [18] ,KBI Pin PTG2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 17. " [17] ,KBI Pin PTG1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 16. " [16] ,KBI Pin PTG0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Pin PTF7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 14. " [14] ,KBI Pin PTF6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 13. " [13] ,KBI Pin PTF5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 12. " [12] ,KBI Pin PTF4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Pin PTF3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 10. " [10] ,KBI Pin PTF2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 9. " [9] ,KBI Pin PTF1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 8. " [8] ,KBI Pin PTF0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Pin PTE7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 6. " [6] ,KBI Pin PTE6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 5. " [5] ,KBI Pin PTE5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 4. " [4] ,KBI Pin PTE4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Pin PTE3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 2. " [2] ,KBI Pin PTE2 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 1. " [1] ,KBI Pin PTE1 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 0. " [0] ,KBI Pin PTE0 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE04Z128VLH4R")||cpuis("MKE04Z64VLK4R")||cpuis("MKE04Z8VFK4R")||cpuis("MKE04Z8VTG4R")||cpuis("MKE04Z8VWJ4R"))
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "KBI1_SC,KBI Status and Control Register"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "KBI1_SC,KBI Status and Control Register"
|
|
bitfld.long 0x00 5. " RSTKBSP ,Reset KBI_SP register" "Not reset,Reset"
|
|
bitfld.long 0x00 4. " KBSPEN ,Real KBI_SP register enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " KBF ,KBI Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Edges/Levels"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "KBI1_SP,KBI Source Pin Register"
|
|
sif (cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE06Z64VLD4")||cpuis("MKE06Z128VLD4"))
|
|
bitfld.long 0x00 26. " SP[26] ,KBI Source Pin 26 - PTH2" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,KBI Source Pin 7 - PTE7" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,KBI Source Pin 2 - PTE2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,KBI Source Pin 1 - PTE1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,KBI Source Pin 0 - PTE0" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " SP[31] ,KBI Source Pin 31 - PTH7" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,KBI Source Pin 30 - PTH6" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("MKE06Z128VLD4")&&!cpuis("MKE04Z64VQH4")&&!cpuis("MKE04Z128VQH4")&&!cpuis("MKE06Z64VQH4")&&!cpuis("MKE06Z128VQH4")&&!cpuis("MKE04Z64VLH4")&&!cpuis("MKE04Z128VLH4")&&!cpuis("MKE06Z64VLH4")&&!cpuis("MKE06Z128VLH4")&&!cpuis("MKE04Z128VLH4R"))
|
|
bitfld.long 0x00 29. " [29] ,KBI Source Pin 29 - PTH5" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,KBI Source Pin 28 - PTH4" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,KBI Source Pin 27 - PTH3" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " [26] ,KBI Source Pin 26 - PTH2" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,KBI Source Pin 25 - PTH1" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,KBI Source Pin 24 - PTH0" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("MKE06Z128VLD4")&&!cpuis("MKE04Z64VQH4")&&!cpuis("MKE04Z128VQH4")&&!cpuis("MKE06Z64VQH4")&&!cpuis("MKE06Z128VQH4")&&!cpuis("MKE04Z64VLH4")&&!cpuis("MKE04Z128VLH4")&&!cpuis("MKE06Z64VLH4")&&!cpuis("MKE06Z128VLH4")&&!cpuis("MKE04Z128VLH4R"))
|
|
bitfld.long 0x00 23. " [23] ,KBI Source Pin 23 - PTG7" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,KBI Source Pin 22 - PTG6" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,KBI Source Pin 21 - PTG5" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,KBI Source Pin 20 - PTG4" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " [19] ,KBI Source Pin 19 - PTG3" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,KBI Source Pin 18 - PTG2" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,KBI Source Pin 17 - PTG1" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,KBI Source Pin 16 - PTG0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,KBI Source Pin 15 - PTF7" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,KBI Source Pin 14 - PTF6" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,KBI Source Pin 13 - PTF5" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,KBI Source Pin 12 - PTF4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,KBI Source Pin 11 - PTF3" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,KBI Source Pin 10 - PTF2" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,KBI Source Pin 9 - PTF1" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,KBI Source Pin 8 - PTF0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,KBI Source Pin 7 - PTE7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,KBI Source Pin 6 - PTE6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,KBI Source Pin 5 - PTE5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,KBI Source Pin 4 - PTE4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,KBI Source Pin 3 - PTE3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,KBI Source Pin 2 - PTE2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,KBI Source Pin 1 - PTE1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,KBI Source Pin 0 - PTE0" "Low,High"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 10.
|
|
sif (cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R"))
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "KBI1_SC,KBI Status and Control Register"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "KBI1_SC,KBI Status and Control Register"
|
|
rbitfld.byte 0x00 3. " KBF ,KBI Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Edges/Levels"
|
|
endif
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "KBI1_PE,KBI1 Pin Enable Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLD2R")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
bitfld.byte 0x00 7. " KBIPE[7] ,KBI Pin PTD7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " [6] ,KBI Pin PTD6 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " [5] ,KBI Pin PTD5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " [4] ,KBI Pin PTD4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " [3] ,KBI Pin PTD3 Interrupt Enables" "Disabled,Enabled"
|
|
else
|
|
bitfld.byte 0x00 3. " KBIPE[3] ,KBI Pin PTD3 Interrupt Enables" "Disabled,Enabled"
|
|
endif
|
|
bitfld.byte 0x00 2. " [2] ,KBI Pin PTD2 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,KBI Pin PTD1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " [0] ,KBI Pin PTD0 Interrupt Enables" "Disabled,Enabled"
|
|
if (((per.b(ad:0x4007A000))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "KBI1_ES,KBI1 Edge Select Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLD2R")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
bitfld.byte 0x00 7. " KBEDG[7] ,KBI Pin PTD7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 6. " [6] ,KBI Pin PTD6 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " [5] ,KBI Pin PTD5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 4. " [4] ,KBI Pin PTD4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " [3] ,KBI Pin PTD3 Edge Select [Edge]" "Falling,Rising"
|
|
else
|
|
bitfld.byte 0x00 3. " KBEDG[3] ,KBI Pin PTD3 Edge Select [Edge]" "Falling,Rising"
|
|
endif
|
|
bitfld.byte 0x00 2. " [2] ,KBI Pin PTD2 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,KBI Pin PTD1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.byte 0x00 0. " [0] ,KBI Pin PTD0 Edge Select [Edge]" "Falling,Rising"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "KBI1_ES,KBI1 Edge Select Register"
|
|
sif !(cpuis("MKE02Z16VLC2")||cpuis("MKE02Z32VLC2")||cpuis("MKE02Z64VLC2")||cpuis("MKE02Z16VLC4")||cpuis("MKE02Z32VLC4")||cpuis("MKE02Z64VLC4")||cpuis("MKE02Z32VLD4R")||cpuis("MKE02Z64VLD4R")||cpuis("MKE02Z64VLH4R")||cpuis("MKE02Z32VLD2R")||cpuis("MKE02Z32VLC2R")||cpuis("MKE02Z16VFM4")||cpuis("MKE02Z32VFM4")||cpuis("MKE02Z64VFM4")||cpuis("MKE02Z32VLC4R")||cpuis("MKE02Z16VLC2R")||cpuis("MKE02Z32VFM4R"))
|
|
bitfld.byte 0x00 7. " KBEDG[7] ,KBI Pin PTD7 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 6. " [6] ,KBI Pin PTD6 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " [5] ,KBI Pin PTD5 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 4. " [4] ,KBI Pin PTD4 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " [3] ,KBI Pin PTD3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
else
|
|
bitfld.byte 0x00 3. " KBEDG[3] ,KBI Pin PTD3 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
endif
|
|
bitfld.byte 0x00 2. " [2] ,KBI Pin PTD2 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,KBI Pin PTD1 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.byte 0x00 0. " [0] ,KBI Pin PTD0 Edge Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
endif
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "IRQ (Interrupt)"
|
|
base ad:0x40031000
|
|
width 8.
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "IRQ_SC,Interrupt Pin Request Status and Control Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKE15Z*"))
|
|
tree "TSI (Touch Sensing Input)"
|
|
base ad:0x40045000
|
|
width 11.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TSI_GENCS,TSI General Control and Status Register"
|
|
eventfld.long 0x00 31. " OUTRGF ,Out of range flag" "No,Yes"
|
|
bitfld.long 0x00 28. " ESOR ,End-of-scan or out-of-range interrupt selection" "Out-of-range,End-of-scan"
|
|
bitfld.long 0x00 19.--20. " DVOLT ,Comparator Vm/Vp/dvolt select" "0.3/1.3/1.0 V,0.3/1.6/1.3 V,0.3/1.9/1.6 V,0.3/2.3/2.0 V"
|
|
bitfld.long 0x00 7. " TSIEN ,Touch Sensing Input Module Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TSIIEN ,Touch Sensing Input Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STPE ,TSI STOP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " STM ,Scan Trigger Mode" "Software,Hardware"
|
|
rbitfld.long 0x00 3. " SCNIP ,Scan In Progress Status" "Not in progress,In progress"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EOSF ,End of Scan Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " EOSDMEO ,End-of-Scan DMA Transfer Request Enable Only" "Disabled,Enabled"
|
|
line.long 0x04 "TSI_DATA,TSI DATA Register"
|
|
bitfld.long 0x04 27.--31. " TSICH ,Current channel to be measured for self-cap mode select" "CH 0,CH 1,CH 2,CH 3,CH 4,CH 5,CH 6,CH 7,CH 8,CH 9,CH 10,CH 11,CH 12,CH 13,CH 14,CH 15,CH 16,CH 17,CH 18,CH 19,CH 20,CH 21,CH 22,CH 23,CH 24,?..."
|
|
bitfld.long 0x04 23. " DMAEN ,DMA Transfer Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SWTS ,Software Trigger Start" "No effect,Scan"
|
|
hexmask.long.word 0x04 0.--15. 1. " TSICNT ,TSI Conversion Counter Value"
|
|
line.long 0x08 "TSI_TSHD,TSI Threshold Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " THRESH ,TSI Wakeup Channel High-threshold"
|
|
hexmask.long.word 0x08 0.--15. 1. " THRESL ,TSI Wakeup Channel Low-threshold"
|
|
if (per.l(ad:0x40045000+0x0C)&0x400002)==0x400000
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TSI_MODE,TSI MODE Register"
|
|
bitfld.long 0x00 28.--30. " S_XDN ,S_XDN adjust sensitivity" "1/16,1/8,1/4,1/2,?..."
|
|
bitfld.long 0x00 23. " S_W_SHIELD ,Shield switch control" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 22. " S_SEN ,Sensitivity boost mode of self-cap" "OFF,ON"
|
|
bitfld.long 0x00 19.--21. " S_CTRIM ,Capacitor trim setting" "2.5p,5.0p,7.5p,10p,12.5p,15p,17.5p,20p"
|
|
bitfld.long 0x00 18. " S_XIN ,Input current multiple" "1/8,1/4"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " S_XCH ,Charge/Discharge current multiple" "1/16,1/8,1/4,1/2,?..."
|
|
bitfld.long 0x00 5.--6. " SETCLK ,Set main clock frequency" "20.72,16.65,13.87,11.91"
|
|
bitfld.long 0x00 1. " MODE ,Sensing mod select" "Self-cap mode,Mutual-cap mode"
|
|
bitfld.long 0x00 0. " S_NOISE ,Noise cancellation mode of self-cap" "OFF,ON"
|
|
elif (per.l(ad:0x40045000+0x0C)&0x400002)==0x400002
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TSI_MODE,TSI MODE Register"
|
|
bitfld.long 0x00 28.--30. " S_XDN ,S_XDN adjust sensitivity" "1/16,1/8,1/4,1/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " S_SEN ,Sensitivity boost mode of self-cap" "OFF,ON"
|
|
bitfld.long 0x00 19.--21. " S_CTRIM ,Capacitor trim setting" "2.5p,5.0p,7.5p,10p,12.5p,15p,17.5p,20p"
|
|
bitfld.long 0x00 18. " S_XIN ,Input current multiple" "1/8,1/4"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " S_XCH ,Charge/Discharge current multiple" "1/16,1/8,1/4,1/2,?..."
|
|
bitfld.long 0x00 5.--6. " SETCLK ,Set main clock frequency" "20.72,16.65,13.87,11.91"
|
|
bitfld.long 0x00 1. " MODE ,Sensing mod select" "Self-cap mode,Mutual-cap mode"
|
|
bitfld.long 0x00 0. " S_NOISE ,Noise cancellation mode of self-cap" "OFF,ON"
|
|
elif (per.l(ad:0x40045000+0x0C)&0x400002)==0x000002
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TSI_MODE,TSI MODE Register"
|
|
textline " "
|
|
bitfld.long 0x00 22. " S_SEN ,Sensitivity boost mode of self-cap" "OFF,ON"
|
|
bitfld.long 0x00 18. " S_XIN ,Input current multiple" "1/8,1/4"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " S_XCH ,Charge/Discharge current multiple" "1/16,1/8,1/4,1/2,?..."
|
|
bitfld.long 0x00 5.--6. " SETCLK ,Set main clock frequency" "20.72,16.65,13.87,11.91"
|
|
bitfld.long 0x00 1. " MODE ,Sensing mod select" "Self-cap mode,Mutual-cap mode"
|
|
bitfld.long 0x00 0. " S_NOISE ,Noise cancellation mode of self-cap" "OFF,ON"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TSI_MODE,TSI MODE Register"
|
|
bitfld.long 0x00 23. " S_W_SHIELD ,Shield switch control" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 22. " S_SEN ,Sensitivity boost mode of self-cap" "OFF,ON"
|
|
bitfld.long 0x00 18. " S_XIN ,Input current multiple" "1/8,1/4"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " S_XCH ,Charge/Discharge current multiple" "1/16,1/8,1/4,1/2,?..."
|
|
bitfld.long 0x00 5.--6. " SETCLK ,Set main clock frequency" "20.72,16.65,13.87,11.91"
|
|
bitfld.long 0x00 1. " MODE ,Sensing mod select" "Self-cap mode,Mutual-cap mode"
|
|
bitfld.long 0x00 0. " S_NOISE ,Noise cancellation mode of self-cap" "OFF,ON"
|
|
endif
|
|
if (per.l(ad:0x40045000+0x0C)&0x02)==0x02
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TSI_MUL0,TSI MUTUAL-CAP Register 0"
|
|
bitfld.long 0x00 29.--31. " M_PRE_CURRENT ,Vref generator current choose" "1uA,2uA,3uA,4uA,5uA,6uA,7uA,8uA"
|
|
bitfld.long 0x00 13.--15. " M_PRE_RES ,Pre-charged resistor choose" "1k,2k,3k,4k,5k,6k,7k,8k"
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bitfld.long 0x00 8.--11. " M_SEN_RES ,I_sense generator resistor choose" "2.5k,5k,7.5k,10k,12.5k,15k,17.5k,20k,22.5k,25k,27.5k,30k,32.5k,35k,37.5k,40k"
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bitfld.long 0x00 4.--6. " M_SEL_TX ,TX channel selection" "CH 0 as tx0,CH 1 as tx1,CH 2 as tx2,CH 3 as tx3,CH 4 as tx4,CH 5 as tx5,?..."
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textline " "
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bitfld.long 0x00 0.--2. " M_SEL_RX ,RX channel selection" "CH 6 as rx6,CH 7 as rx7,CH 8 as rx8,CH 9 as rx9,CH 10 as rx10,CH 11 as rx11,?..."
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else
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group.long 0x10++0x03
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line.long 0x00 "TSI_MUL0,TSI MUTUAL-CAP Register 0"
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bitfld.long 0x00 29.--31. " M_PRE_CURRENT ,Vref generator current choose" "1uA,2uA,3uA,4uA,5uA,6uA,7uA,8uA"
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bitfld.long 0x00 13.--15. " M_PRE_RES ,Pre-charged resistor choose" "1k,2k,3k,4k,5k,6k,7k,8k"
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bitfld.long 0x00 8.--11. " M_SEN_RES ,I_sense generator resistor choose" "2.5k,5k,7.5k,10k,12.5k,15k,17.5k,20k,22.5k,25k,27.5k,30k,32.5k,35k,37.5k,40k"
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endif
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group.long 0x14++0x07
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line.long 0x00 "TSI_MUL1,TSI MUTUAL-CAP Register 1"
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bitfld.long 0x00 19.--23. " M_SEN_BOOST ,Sensitivity boost current choose" "0u,2u,4u,6u,8u,10u,12u,14u,16u,18u,20u,22u,24u,26u,28u,30u,32u,34u,36u,38u,40u,42u,44u,46u,48u,50u,52u,54u,56u,58u,60u,62u"
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bitfld.long 0x00 18. " M_MODE ,TX drive mode control" "-5V~+5V,0V~+5V"
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bitfld.long 0x00 16. " M_VPRE_CHOOSE ,Digital control signal for pre-voltage choose" "Internal 1.2V voltage,1.2V PMC output"
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bitfld.long 0x00 14. " M_TRIM2[6] ,Vmid choose" "Vp-0.1V,Vp-0.4V"
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textline " "
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bitfld.long 0x00 8. " M_TRIM2[0] ,Vp/Vm/Vmid source choose" "Vref,Vpre in mutual AFE"
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bitfld.long 0x00 5.--7. " M_PMIRRORL ,PMOS current mirror on the left side" "4,8,12,16,20,24,28,32"
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bitfld.long 0x00 3.--4. " M_PMIRRORR ,PMOS current mirror on the right side" "1,2,3,4"
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bitfld.long 0x00 1.--2. " M_NMIRROR ,NMOS current mirror" "1,2,3,4"
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textline " "
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bitfld.long 0x00 0. " M_NMIR_CTRL ,NMOS mirror control signal" "Disabled,Enabled"
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line.long 0x04 "TSI_SINC,TSI SINC Filter Register"
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bitfld.long 0x04 24.--27. " CUTOFF ,Shifting out lower bits of counter value" "1,2,4,8,16,32,64,128,?..."
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bitfld.long 0x04 21. " ORDER ,Order of SINC filter select" "1,2"
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bitfld.long 0x04 16.--20. " DECIMATION ,Decimation value of the SINC filter choose" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
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rbitfld.long 0x04 3. " SWITCH_ENABLE ,SSC function enable" "Disabled,Enabled"
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textline " "
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rbitfld.long 0x04 2. " SINC_OVERFLOW_FLAG ,Counter result in TSI_DATA[TSICNT] overflow occurrence" "Not occurred,Occurred"
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rbitfld.long 0x04 1. " SINC_VALID ,SINC filter for digital testing state" "Disabled,Enabled"
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rbitfld.long 0x04 0. " SSC_CONTROL_OUT ,SSC output value" "0,1"
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if (per.l(ad:0x40045000+0x1C)&0x06000000)==0x00
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group.long 0x1C++0x03
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line.long 0x00 "TSI_SSC0,TSI SSC Register 0"
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bitfld.long 0x00 28.--31. " PRBS_OUTSEL ,PRBS method length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 25.--26. " SSC_MODE ,SSC mode choose" "PRBS,Up-down counter,SSC disabled,?..."
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bitfld.long 0x00 24. " SSC_CONTROL_REVERSE ,SSC output bit's polarity reverse" "Not reversed,Reversed"
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hexmask.long.byte 0x00 0.--7. 1. " SSC_PRESCALE_NUM ,Divider ratio for the clock used for generating the SSC output bit"
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elif (per.l(ad:0x40045000+0x1C)&0x06000000)==0x02000000
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group.long 0x1C++0x03
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line.long 0x00 "TSI_SSC0,TSI SSC Register 0"
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|
bitfld.long 0x00 28.--31. " PRBS_OUTSEL ,PRBS method length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 25.--26. " SSC_MODE ,SSC mode choose" "PRBS,Up-down counter,SSC disabled,?..."
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bitfld.long 0x00 24. " SSC_CONTROL_REVERSE ,SSC output bit's polarity reverse" "Not reversed,Reversed"
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bitfld.long 0x00 20.--23. " CHARGE_NUM ,SSC output bit 0's period choose" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
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textline " "
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bitfld.long 0x00 16.--19. " BASE_NOCHARGE_NUM ,SSC output bit 1's period choose" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
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hexmask.long.byte 0x00 0.--7. 1. " SSC_PRESCALE_NUM ,Divider ratio for the clock used for generating the SSC output bit"
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else
|
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group.long 0x1C++0x03
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|
line.long 0x00 "TSI_SSC0,TSI SSC Register 0"
|
|
textline " "
|
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bitfld.long 0x00 25.--26. " SSC_MODE ,SSC mode choose" "PRBS,Up-down counter,SSC disabled,?..."
|
|
bitfld.long 0x00 24. " SSC_CONTROL_REVERSE ,SSC output bit's polarity reverse" "Not reversed,Reversed"
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|
hexmask.long.byte 0x00 0.--7. 1. " SSC_PRESCALE_NUM ,Divider ratio for the clock used for generating the SSC output bit"
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|
endif
|
|
if (per.l(ad:0x40045000+0x1C)&0x06000000)==0x00
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|
group.long 0x20++0x03
|
|
line.long 0x00 "TSI_SSC1,TSI SSC Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRBS_WEIGHT_HI ,PRBS WEIGHT HI"
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|
hexmask.long.byte 0x00 16.--23. 1. " PRBS_WEIGHT_LO ,PRBS WEIGHT LO"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRBS_SPEED_HI ,PRBS SEED HI"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRBS_SPEED_LO ,PRBS SEED LO"
|
|
endif
|
|
if (per.l(ad:0x40045000+0x1C)&0x06000000)==0x02000000
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TSI_SSC2,TSI SSC Register 2"
|
|
bitfld.long 0x00 28.--31. " MOVE_NOCHARGE_MIN ,MOVE NOCHARGE MIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--21. " MOVE_NOCHARGE_MAX ,MOVE NOCHARGE MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--10. " MOVE_STEPS_NUM ,MOVE STEPS NUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " MOVE_REPEAT_NUM ,MOVE REPEAT NUM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
textline ""
|