6493 lines
405 KiB
Plaintext
6493 lines
405 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: GD32E23X On-Chip Peripherals
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; @Props: Released
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; @Author: PIW
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; @Changelog: 2022-05-10 PIW
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; @Manufacturer: GigaDevice - GigaDevice Semiconductor Inc.
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; @Doc: SVD generated (SVD2PER 1.8.0), based on:
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; GD32E230.svd (Rev. 1.0), GD32E231.svd (Rev. 1.0)
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; @Core: Cortex-M23
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; @Chip: GD32E230C4, GD32E230C6, GD32E230C8, GD32E230F4, GD32E230F6, GD32E230F8,
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; GD32E230G4, GD32E230G6, GD32E230G8, GD32E230K4, GD32E230K6, GD32E230K8,
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; GD32E231C4, GD32E231C6, GD32E231C8
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pergd32e23x.per 14807 2022-05-19 11:32:45Z kwisniewski $
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main extension,Reserved,Reserved,ARMv8-M w/ Main extension"
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newline
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
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bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ADC (Analog to digital converter)"
|
|
base ad:0x40012400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "STAT,status register"
|
|
bitfld.long 0x00 4. "STRC,Start flag of regular channel group" "0,1"
|
|
bitfld.long 0x00 3. "STIC,Start flag of inserted channel group" "0,1"
|
|
bitfld.long 0x00 2. "EOIC,End of inserted group conversion flag" "0,1"
|
|
bitfld.long 0x00 1. "EOC,End of group conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "WDE,Analog watchdog event flag" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 24.--25. "DRES,ADC resolution" "0,1,2,3"
|
|
bitfld.long 0x00 23. "RWDEN,Regular channel analog watchdog enable" "0,1"
|
|
bitfld.long 0x00 22. "IWDEN,Inserted channel analog watchdog enable" "0,1"
|
|
bitfld.long 0x00 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "DISIC,Discontinuous mode on injected channels" "0,1"
|
|
bitfld.long 0x00 11. "DISRC,Discontinuous mode on regular channels" "0,1"
|
|
bitfld.long 0x00 10. "ICA,Inserted channel group convert automatically" "0,1"
|
|
bitfld.long 0x00 9. "WDSC,When in scan mode analog watchdog is effective on a single channel" "0,1"
|
|
bitfld.long 0x00 8. "SM,Scan mode" "0,1"
|
|
bitfld.long 0x00 7. "EOICIE,Interrupt enable for EOIC" "0,1"
|
|
bitfld.long 0x00 6. "WDEIE,Interrupt enable for WDE" "0,1"
|
|
bitfld.long 0x00 5. "EOCIE,Interrupt enable for EOC" "0,1"
|
|
bitfld.long 0x00 0.--4. "WDCHSEL,Analog watchdog channel select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 23. "TSVREN,Channel 16 and 17 enable of ADC" "0,1"
|
|
bitfld.long 0x00 22. "SWRCST,Start on regular channel" "0,1"
|
|
bitfld.long 0x00 21. "SWICST,Start on inserted channel" "0,1"
|
|
bitfld.long 0x00 20. "ETERC,External trigger enable for regular channel" "0,1"
|
|
bitfld.long 0x00 17.--19. "ETSRC,External trigger select for regular channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "ETEIC,External trigger enable for inserted channels" "0,1"
|
|
bitfld.long 0x00 12.--14. "ETSIC,External trigger select for inserted channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "DAL,Data alignment" "0,1"
|
|
bitfld.long 0x00 8. "DMA,DMA request enable" "0,1"
|
|
bitfld.long 0x00 3. "RSTCLB,Reset calibration" "0,1"
|
|
bitfld.long 0x00 2. "CLB,ADC calibration" "0,1"
|
|
bitfld.long 0x00 1. "CTN,Continuous mode" "0,1"
|
|
bitfld.long 0x00 0. "ADCON,ADC ON" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SAMPT0,Sampling time register 0"
|
|
bitfld.long 0x00 21.--23. "SPT17,Channel 17 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SPT16,Channel 16 sample time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SAMPT1,Sampling time register 1"
|
|
bitfld.long 0x00 27.--29. "SPT9,Channel 9 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "SPT8,Channel 8 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. "SPT7,Channel 7 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SPT6,Channel 6 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "SPT5,Channel 5 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SPT4,Channel 4 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "SPT3,Channel 3 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. "SPT2,Channel 2 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. "SPT1,Channel 1 sample time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SPT0,Channel 0 sample time selection" "0,1,2,3,4,5,6,7"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "IOFF$1,Inserted channel data offset register $1"
|
|
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for injected channel x"
|
|
repeat.end
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "WDHT,watchdog higher threshold register"
|
|
hexmask.long.word 0x00 0.--11. 1. "WDHT,Analog watchdog high threshold"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "WDLT,watchdog low threshold register"
|
|
hexmask.long.word 0x00 0.--11. 1. "WDLT,Analog watchdog lower threshold"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RSQ0,regular sequence register 0"
|
|
bitfld.long 0x00 20.--23. "RL,Regular channel sequence length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15.--19. "RSQ15,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. "RSQ14,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. "RSQ13,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "RSQ12,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSQ1,regular sequence register 1"
|
|
bitfld.long 0x00 25.--29. "RSQ11,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--24. "RSQ10,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15.--19. "RSQ9,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. "RSQ8,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. "RSQ7,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "RSQ6,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RSQ2,regular sequence register 2"
|
|
bitfld.long 0x00 25.--29. "RSQ5,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--24. "RSQ4,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15.--19. "RSQ3,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. "RSQ2,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. "RSQ1,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "RSQ0,conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ISQ,injected sequence register"
|
|
bitfld.long 0x00 20.--21. "IL,Injected sequence length" "0,1,2,3"
|
|
bitfld.long 0x00 15.--19. "ISQ3,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. "ISQ2,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. "ISQ1,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "ISQ0,conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0x3C)++0x03
|
|
line.long 0x00 "IDATA$1,injected data register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDATAn,Injected data"
|
|
repeat.end
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RDATA,regular data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDATA,Regular data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "OVSAMPCTL,ADC oversample control register"
|
|
bitfld.long 0x00 9. "TOVS,Triggered Oversampling" "0,1"
|
|
bitfld.long 0x00 5.--8. "OVSS,Oversampling shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--4. "OVSR,Oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "OVSEN,Oversampler Enable" "0,1"
|
|
tree.end
|
|
tree "COMPARATOR (Comparator)"
|
|
base ad:0x4001001C
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,control and status register"
|
|
bitfld.long 0x00 15. "CMPLK,Comparator 0 lock" "0,1"
|
|
rbitfld.long 0x00 14. "CMPO,Comparator 0 output" "0,1"
|
|
bitfld.long 0x00 12.--13. "CMPHST,Comparator hysteresis" "0,1,2,3"
|
|
bitfld.long 0x00 11. "CMPPL,Polarity of comparator output" "0,1"
|
|
bitfld.long 0x00 8.--10. "CMPOSEL,Comparator output selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "CMPMSEL,Comparator input selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "CMPM,Comparator mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. "CMPSW,Comparator switch" "0,1"
|
|
bitfld.long 0x00 0. "CMPEN,Comparator enable" "0,1"
|
|
tree.end
|
|
tree "CRC (Cyclic redundancy check calculation unit)"
|
|
base ad:0x40023000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Data register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC calculation result bits"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FDATA,Free data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FDATA,General-purpose 8-bit data register bits"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL,Control register"
|
|
bitfld.long 0x00 7. "REV_O,Reverse output data" "0,1"
|
|
bitfld.long 0x00 5.--6. "REV_I,Reverse input data" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "PS,Size of polynomial" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RST,reset bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IDATA,Initialization Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "IDATA,CRC calculation initial value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "POLY,Polynomial register"
|
|
hexmask.long 0x00 0.--31. 1. "POLY,User configurable polynomial value"
|
|
tree.end
|
|
tree "DBGMCU (Debug support)"
|
|
base ad:0x40015800
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,MCU Device ID Code Register"
|
|
hexmask.long 0x00 0.--31. 1. "ID_CODE,DBG ID code register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL0,Debug Control Register 0"
|
|
bitfld.long 0x00 27. "TIMER13_HOLD,Timer 13 hold register" "0,1"
|
|
bitfld.long 0x00 19. "TIMER5_HOLD,Timer 5 hold register" "0,1"
|
|
bitfld.long 0x00 16. "I2C1_HOLD,I2C1 hold register" "0,1"
|
|
bitfld.long 0x00 15. "I2C0_HOLD,I2C0 hold register" "0,1"
|
|
bitfld.long 0x00 12. "TIMER2_HOLD,Timer 2 hold register" "0,1"
|
|
bitfld.long 0x00 10. "TIMER0_HOLD,Timer 0 hold register" "0,1"
|
|
bitfld.long 0x00 9. "WWDGT_HOLD,WWDGT hold register" "0,1"
|
|
bitfld.long 0x00 8. "FWDGT_HOLD,FWDGT hold register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "STB_HOLD,Standby mode hold Mode" "0,1"
|
|
bitfld.long 0x00 1. "DSLP_HOLD,DEEPSLEEP mode hold Mode" "0,1"
|
|
bitfld.long 0x00 0. "SLP_HOLD,Sleep mode hold register" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL1,Debug Control Register 1"
|
|
bitfld.long 0x00 18. "TIMER16_HOLD,Timer 16 hold register" "0,1"
|
|
bitfld.long 0x00 17. "TIMER15_HOLD,Timer 15 hold register" "0,1"
|
|
bitfld.long 0x00 16. "TIMER14_HOLD,Timer 14 hold register" "0,1"
|
|
bitfld.long 0x00 10. "RTC_HOLD,RTC hold register" "0,1"
|
|
tree.end
|
|
tree "DMA (DMA controller)"
|
|
base ad:0x40020000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTF,DMA interrupt flag register (DMA_INTF)"
|
|
bitfld.long 0x00 19. "ERRIF4,Channel 4 Error flag" "0,1"
|
|
bitfld.long 0x00 18. "HTFIF4,Channel 4 Half Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 17. "FTFIF4,Channel 4 Full Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 16. "GIF4,Channel 4 Global interrupt flag" "0,1"
|
|
bitfld.long 0x00 15. "ERRIF3,Channel 3 Error flag" "0,1"
|
|
bitfld.long 0x00 14. "HTFIF3,Channel 3 Half Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 13. "FTFIF3,Channel 3 Full Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 12. "GIF3,Channel 3 Global interrupt flag" "0,1"
|
|
bitfld.long 0x00 11. "ERRIF2,Channel 2 Error flag" "0,1"
|
|
bitfld.long 0x00 10. "HTFIF2,Channel 2 Half Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 9. "FTFIF2,Channel 2 Full Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 8. "GIF2,Channel 2 Global interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ERRIF1,Channel 1 Error flag" "0,1"
|
|
bitfld.long 0x00 6. "HTFIF1,Channel 1 Half Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 5. "FTFIF1,Channel 1 Full Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 4. "GIF1,Channel 1 Global interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "ERRIF0,Channel 0 Error flag" "0,1"
|
|
bitfld.long 0x00 2. "HTFIF0,Channel 0 Half Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 1. "FTFIF0,Channel 0 Full Transfer Finish flag" "0,1"
|
|
bitfld.long 0x00 0. "GIF0,Channel 0 Global interrupt flag" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "INTC,DMA interrupt flag clear register (DMA_INTC)"
|
|
bitfld.long 0x00 19. "ERRIFC4,Channel 4 Error clear" "0,1"
|
|
bitfld.long 0x00 18. "HTFIFC4,Channel 4 Half Transfer clear" "0,1"
|
|
bitfld.long 0x00 17. "FTFIFC4,Channel 4 Full Transfer Finish clear" "0,1"
|
|
bitfld.long 0x00 16. "GIFC4,Channel 4 Global interrupt flag clear" "0,1"
|
|
bitfld.long 0x00 15. "ERRIFC3,Channel 3 Error clear" "0,1"
|
|
bitfld.long 0x00 14. "HTFIFC3,Channel 3 Half Transfer clear" "0,1"
|
|
bitfld.long 0x00 13. "FTFIFC3,Channel 3 Full Transfer Finish clear" "0,1"
|
|
bitfld.long 0x00 12. "GIFC3,Channel 3 Global interrupt flag clear" "0,1"
|
|
bitfld.long 0x00 11. "ERRIFC2,Channel 2 Error clear" "0,1"
|
|
bitfld.long 0x00 10. "HTFIFC2,Channel 2 Half Transfer clear" "0,1"
|
|
bitfld.long 0x00 9. "FTFIFC2,Channel 2 Full Transfer Finish clear" "0,1"
|
|
bitfld.long 0x00 8. "GIFC2,Channel 2 Global interrupt flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ERRIFC1,Channel 1 Error clear" "0,1"
|
|
bitfld.long 0x00 6. "HTFIFC1,Channel 1 Half Transfer clear" "0,1"
|
|
bitfld.long 0x00 5. "FTFIFC1,Channel 1 Full Transfer Finish clear" "0,1"
|
|
bitfld.long 0x00 4. "GIFC1,Channel 1 Global interrupt flag clear" "0,1"
|
|
bitfld.long 0x00 3. "ERRIFC0,Channel 0 Error clear" "0,1"
|
|
bitfld.long 0x00 2. "HTFIFC0,Channel 0 Half Transfer clear" "0,1"
|
|
bitfld.long 0x00 1. "FTFIFC0,Channel 0 Full Transfer Finish clear" "0,1"
|
|
bitfld.long 0x00 0. "GIFC0,Channel 0 Global interrupt flag clear" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CH0CTL,DMA channel configuration register (DMA_CH0CTL)"
|
|
bitfld.long 0x00 14. "M2M,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PRIO,Priority Level of this channel" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "ERRIE,Transfer access error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTFIE,Half Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "FTFIE,Full Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CH0CNT,DMA channel 0 counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0PADDR,DMA channel 0 peripheral base address register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0MADDR,DMA channel 0 memory base address register"
|
|
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH1CTL,DMA channel configuration register (DMA_CH1CTL)"
|
|
bitfld.long 0x00 14. "M2M,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PRIO,Priority Level of this channel" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTFIE,Half Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "FTFIE,Full Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH1CNT,DMA channel 1 counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH1PADDR,DMA channel 1 peripheral base address register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH1MADDR,DMA channel 1 memory base address register"
|
|
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH2CTL,DMA channel configuration register (DMA_CH2CTL)"
|
|
bitfld.long 0x00 14. "M2M,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PRIO,Priority Level of this channel" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTFIE,Half Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "FTFIE,Full Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH2CNT,DMA channel 2 counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH2PADDR,DMA channel 2 peripheral base address register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CH2MADDR,DMA channel 2 memory base address register"
|
|
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH3CTL,DMA channel configuration register (DMA_CH3CTL)"
|
|
bitfld.long 0x00 14. "M2M,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PRIO,Priority Level of this channel" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTFIE,Half Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "FTFIE,Full Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH3CNT,DMA channel 3 counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH3PADDR,DMA channel 3 peripheral base address register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH3MADDR,DMA channel 3 memory base address register"
|
|
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH4CTL,DMA channel configuration register (DMA_CH4CTL)"
|
|
bitfld.long 0x00 14. "M2M,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PRIO,Priority Level of this channel" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTFIE,Half Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "FTFIE,Full Transfer Finish interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH4CNT,DMA channel 4 counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CH4PADDR,DMA channel 4 peripheral base address register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CH4MADDR,DMA channel 4 memory base address register"
|
|
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address"
|
|
tree.end
|
|
tree "EXTI (External interrupt/event controller)"
|
|
base ad:0x40010400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INTEN,Interrupt enable register (EXTI_INTEN)"
|
|
bitfld.long 0x00 27. "INTEN27,Enable Interrupt on line 27" "0,1"
|
|
bitfld.long 0x00 26. "INTEN26,Enable Interrupt on line 26" "0,1"
|
|
bitfld.long 0x00 25. "INTEN25,Enable Interrupt on line 25" "0,1"
|
|
bitfld.long 0x00 24. "INTEN24,Enable Interrupt on line 24" "0,1"
|
|
bitfld.long 0x00 23. "INTEN23,Enable Interrupt on line 23" "0,1"
|
|
bitfld.long 0x00 22. "INTEN22,Enable Interrupt on line 22" "0,1"
|
|
bitfld.long 0x00 21. "INTEN21,Enable Interrupt on line 21" "0,1"
|
|
bitfld.long 0x00 20. "INTEN20,Enable Interrupt on line 20" "0,1"
|
|
bitfld.long 0x00 19. "INTEN19,Enable Interrupt on line 19" "0,1"
|
|
bitfld.long 0x00 18. "INTEN18,Enable Interrupt on line 18" "0,1"
|
|
bitfld.long 0x00 17. "INTEN17,Enable Interrupt on line 17" "0,1"
|
|
bitfld.long 0x00 16. "INTEN16,Enable Interrupt on line 16" "0,1"
|
|
bitfld.long 0x00 15. "INTEN15,Enable Interrupt on line 15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "INTEN14,Enable Interrupt on line 14" "0,1"
|
|
bitfld.long 0x00 13. "INTEN13,Enable Interrupt on line 13" "0,1"
|
|
bitfld.long 0x00 12. "INTEN12,Enable Interrupt on line 12" "0,1"
|
|
bitfld.long 0x00 11. "INTEN11,Enable Interrupt on line 11" "0,1"
|
|
bitfld.long 0x00 10. "INTEN10,Enable Interrupt on line 10" "0,1"
|
|
bitfld.long 0x00 9. "INTEN9,Enable Interrupt on line 9" "0,1"
|
|
bitfld.long 0x00 8. "INTEN8,Enable Interrupt on line 8" "0,1"
|
|
bitfld.long 0x00 7. "INTEN7,Enable Interrupt on line 7" "0,1"
|
|
bitfld.long 0x00 6. "INTEN6,Enable Interrupt on line 6" "0,1"
|
|
bitfld.long 0x00 5. "INTEN5,Enable Interrupt on line 5" "0,1"
|
|
bitfld.long 0x00 4. "INTEN4,Enable Interrupt on line 4" "0,1"
|
|
bitfld.long 0x00 3. "INTEN3,Enable Interrupt on line 3" "0,1"
|
|
bitfld.long 0x00 2. "INTEN2,Enable Interrupt on line 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INTEN1,Enable Interrupt on line 1" "0,1"
|
|
bitfld.long 0x00 0. "INTEN0,Enable Interrupt on line 0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVEN,Event enable register (EXTI_EVEN)"
|
|
bitfld.long 0x00 27. "EVEN27,Enable Event on line 27" "0,1"
|
|
bitfld.long 0x00 26. "EVEN26,Enable Event on line 26" "0,1"
|
|
bitfld.long 0x00 25. "EVEN25,Enable Event on line 25" "0,1"
|
|
bitfld.long 0x00 24. "EVEN24,Enable Event on line 24" "0,1"
|
|
bitfld.long 0x00 23. "EVEN23,Enable Event on line 23" "0,1"
|
|
bitfld.long 0x00 22. "EVEN22,Enable Event on line 22" "0,1"
|
|
bitfld.long 0x00 21. "EVEN21,Enable Event on line 21" "0,1"
|
|
bitfld.long 0x00 20. "EVEN20,Enable Event on line 20" "0,1"
|
|
bitfld.long 0x00 19. "EVEN19,Enable Event on line 19" "0,1"
|
|
bitfld.long 0x00 18. "EVEN18,Enable Event on line 18" "0,1"
|
|
bitfld.long 0x00 17. "EVEN17,Enable Event on line 17" "0,1"
|
|
bitfld.long 0x00 16. "EVEN16,Enable Event on line 16" "0,1"
|
|
bitfld.long 0x00 15. "EVEN15,Enable Event on line 15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "EVEN14,Enable Event on line 14" "0,1"
|
|
bitfld.long 0x00 13. "EVEN13,Enable Event on line 13" "0,1"
|
|
bitfld.long 0x00 12. "EVEN12,Enable Event on line 12" "0,1"
|
|
bitfld.long 0x00 11. "EVEN11,Enable Event on line 11" "0,1"
|
|
bitfld.long 0x00 10. "EVEN10,Enable Event on line 10" "0,1"
|
|
bitfld.long 0x00 9. "EVEN9,Enable Event on line 9" "0,1"
|
|
bitfld.long 0x00 8. "EVEN8,Enable Event on line 8" "0,1"
|
|
bitfld.long 0x00 7. "EVEN7,Enable Event on line 7" "0,1"
|
|
bitfld.long 0x00 6. "EVEN6,Enable Event on line 6" "0,1"
|
|
bitfld.long 0x00 5. "EVEN5,Enable Event on line 5" "0,1"
|
|
bitfld.long 0x00 4. "EVEN4,Enable Event on line 4" "0,1"
|
|
bitfld.long 0x00 3. "EVEN3,Enable Event on line 3" "0,1"
|
|
bitfld.long 0x00 2. "EVEN2,Enable Event on line 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EVEN1,Enable Event on line 1" "0,1"
|
|
bitfld.long 0x00 0. "EVEN0,Enable Event on line 0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTEN,Rising Edge Trigger Enable register (EXTI_RTEN)"
|
|
bitfld.long 0x00 21. "RTEN21,Rising trigger event configuration of line 21" "0,1"
|
|
bitfld.long 0x00 19. "RTEN19,Rising trigger event configuration of line 19" "0,1"
|
|
bitfld.long 0x00 17. "RTEN17,Rising trigger event configuration of line 17" "0,1"
|
|
bitfld.long 0x00 16. "RTEN16,Rising trigger event configuration of line 16" "0,1"
|
|
bitfld.long 0x00 15. "RTEN15,Rising trigger event configuration of line 15" "0,1"
|
|
bitfld.long 0x00 14. "RTEN14,Rising trigger event configuration of line 14" "0,1"
|
|
bitfld.long 0x00 13. "RTEN13,Rising trigger event configuration of line 13" "0,1"
|
|
bitfld.long 0x00 12. "RTEN12,Rising trigger event configuration of line 12" "0,1"
|
|
bitfld.long 0x00 11. "RTEN11,Rising trigger event configuration of line 11" "0,1"
|
|
bitfld.long 0x00 10. "RTEN10,Rising trigger event configuration of line 10" "0,1"
|
|
bitfld.long 0x00 9. "RTEN9,Rising trigger event configuration of line 9" "0,1"
|
|
bitfld.long 0x00 8. "RTEN8,Rising trigger event configuration of line 8" "0,1"
|
|
bitfld.long 0x00 7. "RTEN7,Rising trigger event configuration of line 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTEN6,Rising trigger event configuration of line 6" "0,1"
|
|
bitfld.long 0x00 5. "RTEN5,Rising trigger event configuration of line 5" "0,1"
|
|
bitfld.long 0x00 4. "RTEN4,Rising trigger event configuration of line 4" "0,1"
|
|
bitfld.long 0x00 3. "RTEN3,Rising trigger event configuration of line 3" "0,1"
|
|
bitfld.long 0x00 2. "RTEN2,Rising trigger event configuration of line 2" "0,1"
|
|
bitfld.long 0x00 1. "RTEN1,Rising trigger event configuration of line 1" "0,1"
|
|
bitfld.long 0x00 0. "RTEN0,Rising trigger event configuration of line 0" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FTEN,Falling Egde Trigger Enable register (EXTI_FTEN)"
|
|
bitfld.long 0x00 21. "FTEN21,Falling trigger event configuration of line 21" "0,1"
|
|
bitfld.long 0x00 19. "FTEN19,Falling trigger event configuration of line 19" "0,1"
|
|
bitfld.long 0x00 17. "FTEN17,Falling trigger event configuration of line 17" "0,1"
|
|
bitfld.long 0x00 16. "FTEN16,Falling trigger event configuration of line 16" "0,1"
|
|
bitfld.long 0x00 15. "FTEN15,Falling trigger event configuration of line 15" "0,1"
|
|
bitfld.long 0x00 14. "FTEN14,Falling trigger event configuration of line 14" "0,1"
|
|
bitfld.long 0x00 13. "FTEN13,Falling trigger event configuration of line 13" "0,1"
|
|
bitfld.long 0x00 12. "FTEN12,Falling trigger event configuration of line 12" "0,1"
|
|
bitfld.long 0x00 11. "FTEN11,Falling trigger event configuration of line 11" "0,1"
|
|
bitfld.long 0x00 10. "FTEN10,Falling trigger event configuration of line 10" "0,1"
|
|
bitfld.long 0x00 9. "FTEN9,Falling trigger event configuration of line 9" "0,1"
|
|
bitfld.long 0x00 8. "FTEN8,Falling trigger event configuration of line 8" "0,1"
|
|
bitfld.long 0x00 7. "FTEN7,Falling trigger event configuration of line 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FTEN6,Falling trigger event configuration of line 6" "0,1"
|
|
bitfld.long 0x00 5. "FTEN5,Falling trigger event configuration of line 5" "0,1"
|
|
bitfld.long 0x00 4. "FTEN4,Falling trigger event configuration of line 4" "0,1"
|
|
bitfld.long 0x00 3. "FTEN3,Falling trigger event configuration of line 3" "0,1"
|
|
bitfld.long 0x00 2. "FTEN2,Falling trigger event configuration of line 2" "0,1"
|
|
bitfld.long 0x00 1. "FTEN1,Falling trigger event configuration of line 1" "0,1"
|
|
bitfld.long 0x00 0. "FTEN0,Falling trigger event configuration of line 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SWIEV,Software interrupt event register (EXTI_SWIEV)"
|
|
bitfld.long 0x00 21. "SWIEV21,Software Interrupt on line 21" "0,1"
|
|
bitfld.long 0x00 19. "SWIEV19,Software Interrupt on line 19" "0,1"
|
|
bitfld.long 0x00 17. "SWIEV17,Software Interrupt on line 17" "0,1"
|
|
bitfld.long 0x00 16. "SWIEV16,Software Interrupt on line 16" "0,1"
|
|
bitfld.long 0x00 15. "SWIEV15,Software Interrupt on line 15" "0,1"
|
|
bitfld.long 0x00 14. "SWIEV14,Software Interrupt on line 14" "0,1"
|
|
bitfld.long 0x00 13. "SWIEV13,Software Interrupt on line 13" "0,1"
|
|
bitfld.long 0x00 12. "SWIEV12,Software Interrupt on line 12" "0,1"
|
|
bitfld.long 0x00 11. "SWIEV11,Software Interrupt on line 11" "0,1"
|
|
bitfld.long 0x00 10. "SWIEV10,Software Interrupt on line 10" "0,1"
|
|
bitfld.long 0x00 9. "SWIEV9,Software Interrupt on line 9" "0,1"
|
|
bitfld.long 0x00 8. "SWIEV8,Software Interrupt on line 8" "0,1"
|
|
bitfld.long 0x00 7. "SWIEV7,Software Interrupt on line 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SWIEV6,Software Interrupt on line 6" "0,1"
|
|
bitfld.long 0x00 5. "SWIEV5,Software Interrupt on line 5" "0,1"
|
|
bitfld.long 0x00 4. "SWIEV4,Software Interrupt on line 4" "0,1"
|
|
bitfld.long 0x00 3. "SWIEV3,Software Interrupt on line 3" "0,1"
|
|
bitfld.long 0x00 2. "SWIEV2,Software Interrupt on line 2" "0,1"
|
|
bitfld.long 0x00 1. "SWIEV1,Software Interrupt on line 1" "0,1"
|
|
bitfld.long 0x00 0. "SWIEV0,Software Interrupt on line 0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PD,Pending register (EXTI_PD)"
|
|
bitfld.long 0x00 21. "PD21,Pending bit 21" "0,1"
|
|
bitfld.long 0x00 19. "PD19,Pending bit 19" "0,1"
|
|
bitfld.long 0x00 17. "PD17,Pending bit 17" "0,1"
|
|
bitfld.long 0x00 16. "PD16,Pending bit 16" "0,1"
|
|
bitfld.long 0x00 15. "PD15,Pending bit 15" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Pending bit 14" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Pending bit 13" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Pending bit 12" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Pending bit 11" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Pending bit 10" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Pending bit 9" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Pending bit 8" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Pending bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PD6,Pending bit 6" "0,1"
|
|
bitfld.long 0x00 5. "PD5,Pending bit 5" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Pending bit 4" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Pending bit 3" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Pending bit 2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Pending bit 1" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Pending bit 0" "0,1"
|
|
tree.end
|
|
tree "FMC"
|
|
base ad:0x40022000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WS,wait state register"
|
|
bitfld.long 0x00 15. "PGW,Program width to flash memory" "0,1"
|
|
bitfld.long 0x00 4. "PFEN,Pre-fetch enable" "0,1"
|
|
bitfld.long 0x00 0.--2. "WSCNT,wait state counter register" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "KEY,Unlock key register"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,FMC_CTL unlock register"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "OBKEY,Option byte unlock key register"
|
|
hexmask.long 0x00 0.--31. 1. "OBKEY,FMC_ CTL option bytes operation unlock register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STAT,Status register"
|
|
bitfld.long 0x00 5. "ENDF,End of operation flag bit" "0,1"
|
|
bitfld.long 0x00 4. "WPERR,Erase/Program protection error flag bit" "0,1"
|
|
bitfld.long 0x00 3. "PGAERR,Program alignment error flag bit" "0,1"
|
|
bitfld.long 0x00 2. "PGERR,Program error flag bit" "0,1"
|
|
rbitfld.long 0x00 0. "BUSY,The flash is busy bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTL,Control register"
|
|
bitfld.long 0x00 13. "OBRLD,Option byte reload bit" "0,1"
|
|
bitfld.long 0x00 12. "ENDIE,End of operation interrupt enable bit" "0,1"
|
|
bitfld.long 0x00 10. "ERRIE,Error interrupt enable bit" "0,1"
|
|
bitfld.long 0x00 9. "OBWEN,Option byte erase/program enable bit" "0,1"
|
|
bitfld.long 0x00 7. "LK,FMC_CTL lock bit" "0,1"
|
|
bitfld.long 0x00 6. "START,Send erase command to FMC bit" "0,1"
|
|
bitfld.long 0x00 5. "OBER,Option bytes erase command bit" "0,1"
|
|
bitfld.long 0x00 4. "OBPG,Option bytes program command bit" "0,1"
|
|
bitfld.long 0x00 2. "MER,Main flash mass erase for bank0 command bit" "0,1"
|
|
bitfld.long 0x00 1. "PER,Main flash page erase for bank0 command bit" "0,1"
|
|
bitfld.long 0x00 0. "PG,Main flash program for bank0 command bit" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADDR,Address register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Flash erase/program command address bits"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "OBSTAT,Option byte control register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DATA,Store DATA[15:0] of option bytes block after system reset"
|
|
hexmask.long.byte 0x00 8.--15. 1. "USER,Store USER of option bytes block after system reset"
|
|
bitfld.long 0x00 1.--2. "PLEVEL,Option bytes security protection level" "0,1,2,3"
|
|
bitfld.long 0x00 0. "OBERR,Option bytes read error bit" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "WP,Erase/Program Protection register"
|
|
hexmask.long.word 0x00 0.--15. 1. "WP,Store WP[15:0] of option bytes block after system reset"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PID,Product ID register"
|
|
hexmask.long 0x00 0.--31. 1. "PID,Product reserved ID code register"
|
|
tree.end
|
|
tree "FWDGT (Free watchdog timer)"
|
|
base ad:0x40003000
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMD,Key value"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSC,Prescaler register"
|
|
bitfld.long 0x00 0.--2. "PSC,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLD,Reload register"
|
|
hexmask.long.word 0x00 0.--11. 1. "RLD,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "STAT,Status register"
|
|
bitfld.long 0x00 2. "WUD,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x00 1. "RUD,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x00 0. "PUD,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WND,Window register"
|
|
hexmask.long.word 0x00 0.--11. 1. "WND,Watchdog counter window value"
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
tree "GPIOA"
|
|
base ad:0x48000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,GPIO port control register"
|
|
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CTL14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "CTL13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CTL12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "CTL11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CTL10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "CTL9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CTL8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "CTL7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CTL6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "CTL5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CTL4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CTL3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CTL2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "CTL1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CTL0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OMODE,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OM15,Port x configuration bit 15" "0,1"
|
|
bitfld.long 0x00 14. "OM14,Port x configuration bit 14" "0,1"
|
|
bitfld.long 0x00 13. "OM13,Port x configuration bit 13" "0,1"
|
|
bitfld.long 0x00 12. "OM12,Port x configuration bit 12" "0,1"
|
|
bitfld.long 0x00 11. "OM11,Port x configuration bit 11" "0,1"
|
|
bitfld.long 0x00 10. "OM10,Port x configuration bit 10" "0,1"
|
|
bitfld.long 0x00 9. "OM9,Port x configuration bit 9" "0,1"
|
|
bitfld.long 0x00 8. "OM8,Port x configuration bit 8" "0,1"
|
|
bitfld.long 0x00 7. "OM7,Port x configuration bit 7" "0,1"
|
|
bitfld.long 0x00 6. "OM6,Port x configuration bit 6" "0,1"
|
|
bitfld.long 0x00 5. "OM5,Port x configuration bit 5" "0,1"
|
|
bitfld.long 0x00 4. "OM4,Port x configuration bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OM3,Port x configuration bit 3" "0,1"
|
|
bitfld.long 0x00 2. "OM2,Port x configuration bit 2" "0,1"
|
|
bitfld.long 0x00 1. "OM1,Port x configuration bit 1" "0,1"
|
|
bitfld.long 0x00 0. "OM0,Port x configuration bit 0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPD,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "OSPD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OSPD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUD,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "PUD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PUD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ISTAT,GPIO port input data register"
|
|
bitfld.long 0x00 15. "ISTAT15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ISTAT14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ISTAT13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ISTAT12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ISTAT11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ISTAT10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ISTAT9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ISTAT8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ISTAT7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ISTAT6,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "ISTAT5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ISTAT4,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ISTAT3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ISTAT2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ISTAT1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ISTAT0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OCTL,GPIO port output data register"
|
|
bitfld.long 0x00 15. "OCTL15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OCTL14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OCTL13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OCTL12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OCTL11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OCTL10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OCTL9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OCTL8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OCTL7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OCTL6,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "OCTL5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OCTL4,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OCTL3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OCTL2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OCTL1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OCTL0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BOP,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "CR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "CR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "CR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "CR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "CR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "CR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "CR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "CR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "CR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "CR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 21. "CR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "CR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "CR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "CR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "CR0,Port x reset bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BOP15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BOP14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BOP13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BOP12,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "BOP11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BOP10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BOP9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BOP8,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BOP7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BOP6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BOP5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BOP4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BOP3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BOP2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "BOP1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BOP0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LOCK,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LKK,Port x lock bit y" "0,1"
|
|
bitfld.long 0x00 15. "LK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "LK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFSEL0,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "SEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFSEL1,GPIO alternate function register 1"
|
|
bitfld.long 0x00 28.--31. "SEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BC,Port bit reset register"
|
|
bitfld.long 0x00 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 5. "CR5,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 4. "CR4,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 0. "CR0,Port cleat bit" "0,1"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "TG,Port bit toggle register"
|
|
bitfld.long 0x00 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 5. "TG5,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 4. "TG4,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 0. "TG0,Port toggle bit" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x48000400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,GPIO port control register"
|
|
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CTL14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "CTL13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CTL12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "CTL11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CTL10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "CTL9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CTL8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "CTL7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CTL6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "CTL5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CTL4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CTL3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CTL2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "CTL1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CTL0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OMODE,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OM15,Port x configuration bit 15" "0,1"
|
|
bitfld.long 0x00 14. "OM14,Port x configuration bit 14" "0,1"
|
|
bitfld.long 0x00 13. "OM13,Port x configuration bit 13" "0,1"
|
|
bitfld.long 0x00 12. "OM12,Port x configuration bit 12" "0,1"
|
|
bitfld.long 0x00 11. "OM11,Port x configuration bit 11" "0,1"
|
|
bitfld.long 0x00 10. "OM10,Port x configuration bit 10" "0,1"
|
|
bitfld.long 0x00 9. "OM9,Port x configuration bit 9" "0,1"
|
|
bitfld.long 0x00 8. "OM8,Port x configuration bit 8" "0,1"
|
|
bitfld.long 0x00 7. "OM7,Port x configuration bit 7" "0,1"
|
|
bitfld.long 0x00 6. "OM6,Port x configuration bit 6" "0,1"
|
|
bitfld.long 0x00 5. "OM5,Port x configuration bit 5" "0,1"
|
|
bitfld.long 0x00 4. "OM4,Port x configuration bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OM3,Port x configuration bit 3" "0,1"
|
|
bitfld.long 0x00 2. "OM2,Port x configuration bit 2" "0,1"
|
|
bitfld.long 0x00 1. "OM1,Port x configuration bit 1" "0,1"
|
|
bitfld.long 0x00 0. "OM0,Port x configuration bit 0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPD,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "OSPD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OSPD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUD,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "PUD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PUD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ISTAT,GPIO port input data register"
|
|
bitfld.long 0x00 15. "ISTAT15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ISTAT14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ISTAT13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ISTAT12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ISTAT11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ISTAT10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ISTAT9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ISTAT8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ISTAT7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ISTAT6,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "ISTAT5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ISTAT4,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ISTAT3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ISTAT2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ISTAT1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ISTAT0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OCTL,GPIO port output data register"
|
|
bitfld.long 0x00 15. "OCTL15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OCTL14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OCTL13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OCTL12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OCTL11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OCTL10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OCTL9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OCTL8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OCTL7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OCTL6,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "OCTL5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OCTL4,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OCTL3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OCTL2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OCTL1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OCTL0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BOP,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "CR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "CR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "CR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "CR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "CR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "CR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "CR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "CR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "CR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "CR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 21. "CR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "CR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "CR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "CR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "CR0,Port x reset bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BOP15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BOP14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BOP13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BOP12,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "BOP11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BOP10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BOP9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BOP8,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BOP7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BOP6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BOP5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BOP4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BOP3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BOP2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "BOP1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BOP0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LOCK,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LKK,Port x lock bit y" "0,1"
|
|
bitfld.long 0x00 15. "LK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "LK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFSEL0,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "SEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFSEL1,GPIO alternate function register 1"
|
|
bitfld.long 0x00 28.--31. "SEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BC,Port bit reset register"
|
|
bitfld.long 0x00 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 5. "CR5,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 4. "CR4,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 0. "CR0,Port cleat bit" "0,1"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "TG,Port bit toggle register"
|
|
bitfld.long 0x00 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 5. "TG5,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 4. "TG4,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 0. "TG0,Port toggle bit" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x48000800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,GPIO port control register"
|
|
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CTL14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "CTL13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CTL12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "CTL11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CTL10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "CTL9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CTL8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "CTL7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CTL6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "CTL5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CTL4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CTL3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CTL2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "CTL1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CTL0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OMODE,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OM15,Port x configuration bit 15" "0,1"
|
|
bitfld.long 0x00 14. "OM14,Port x configuration bit 14" "0,1"
|
|
bitfld.long 0x00 13. "OM13,Port x configuration bit 13" "0,1"
|
|
bitfld.long 0x00 12. "OM12,Port x configuration bit 12" "0,1"
|
|
bitfld.long 0x00 11. "OM11,Port x configuration bit 11" "0,1"
|
|
bitfld.long 0x00 10. "OM10,Port x configuration bit 10" "0,1"
|
|
bitfld.long 0x00 9. "OM9,Port x configuration bit 9" "0,1"
|
|
bitfld.long 0x00 8. "OM8,Port x configuration bit 8" "0,1"
|
|
bitfld.long 0x00 7. "OM7,Port x configuration bit 7" "0,1"
|
|
bitfld.long 0x00 6. "OM6,Port x configuration bit 6" "0,1"
|
|
bitfld.long 0x00 5. "OM5,Port x configuration bit 5" "0,1"
|
|
bitfld.long 0x00 4. "OM4,Port x configuration bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OM3,Port x configuration bit 3" "0,1"
|
|
bitfld.long 0x00 2. "OM2,Port x configuration bit 2" "0,1"
|
|
bitfld.long 0x00 1. "OM1,Port x configuration bit 1" "0,1"
|
|
bitfld.long 0x00 0. "OM0,Port x configuration bit 0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPD,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "OSPD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OSPD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUD,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "PUD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PUD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ISTAT,GPIO port input data register"
|
|
bitfld.long 0x00 15. "ISTAT15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ISTAT14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ISTAT13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ISTAT12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ISTAT11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ISTAT10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ISTAT9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ISTAT8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ISTAT7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ISTAT6,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "ISTAT5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ISTAT4,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ISTAT3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ISTAT2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ISTAT1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ISTAT0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OCTL,GPIO port output data register"
|
|
bitfld.long 0x00 15. "OCTL15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OCTL14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OCTL13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OCTL12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OCTL11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OCTL10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OCTL9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OCTL8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OCTL7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OCTL6,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "OCTL5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OCTL4,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OCTL3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OCTL2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OCTL1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OCTL0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BOP,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "CR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "CR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "CR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "CR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "CR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "CR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "CR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "CR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "CR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "CR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 21. "CR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "CR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "CR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "CR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "CR0,Port x reset bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BOP15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BOP14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BOP13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BOP12,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "BOP11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BOP10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BOP9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BOP8,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BOP7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BOP6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BOP5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BOP4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BOP3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BOP2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "BOP1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BOP0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFSEL0,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "SEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFSEL1,GPIO alternate function register 1"
|
|
bitfld.long 0x00 28.--31. "SEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BC,Port bit reset register"
|
|
bitfld.long 0x00 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 5. "CR5,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 4. "CR4,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x00 0. "CR0,Port cleat bit" "0,1"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "TG,Port bit toggle register"
|
|
bitfld.long 0x00 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 5. "TG5,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 4. "TG4,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 0. "TG0,Port toggle bit" "0,1"
|
|
tree.end
|
|
tree "GPIOF"
|
|
base ad:0x48001400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,GPIOF port control register"
|
|
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CTL14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "CTL13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CTL12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "CTL11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CTL10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "CTL9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CTL8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "CTL7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CTL6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "CTL5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CTL4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CTL3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CTL2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "CTL1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CTL0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OMODE,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OM15,Port x configuration bit 15" "0,1"
|
|
bitfld.long 0x00 14. "OM14,Port x configuration bit 14" "0,1"
|
|
bitfld.long 0x00 13. "OM13,Port x configuration bit 13" "0,1"
|
|
bitfld.long 0x00 12. "OM12,Port x configuration bit 12" "0,1"
|
|
bitfld.long 0x00 11. "OM11,Port x configuration bit 11" "0,1"
|
|
bitfld.long 0x00 10. "OM10,Port x configuration bit 10" "0,1"
|
|
bitfld.long 0x00 9. "OM9,Port x configuration bit 9" "0,1"
|
|
bitfld.long 0x00 8. "OM8,Port x configuration bit 8" "0,1"
|
|
bitfld.long 0x00 7. "OM7,Port x configuration bit 7" "0,1"
|
|
bitfld.long 0x00 6. "OM6,Port x configuration bit 6" "0,1"
|
|
bitfld.long 0x00 5. "OM5,Port x configuration bit 5" "0,1"
|
|
bitfld.long 0x00 4. "OM4,Port x configuration bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OM3,Port x configuration bit 3" "0,1"
|
|
bitfld.long 0x00 2. "OM2,Port x configuration bit 2" "0,1"
|
|
bitfld.long 0x00 1. "OM1,Port x configuration bit 1" "0,1"
|
|
bitfld.long 0x00 0. "OM0,Port x configuration bit 0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPD,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "OSPD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OSPD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUD,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUD15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUD14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUD13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUD12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUD11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUD10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUD9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUD8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "PUD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PUD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ISTAT,GPIO port input data register"
|
|
bitfld.long 0x00 15. "ISTAT15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ISTAT14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ISTAT13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ISTAT12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ISTAT11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ISTAT10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ISTAT9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ISTAT8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ISTAT7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ISTAT6,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "ISTAT5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ISTAT4,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ISTAT3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ISTAT2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ISTAT1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ISTAT0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OCTL,GPIO port output data register"
|
|
bitfld.long 0x00 15. "OCTL15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OCTL14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OCTL13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OCTL12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OCTL11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OCTL10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OCTL9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OCTL8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OCTL7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OCTL6,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "OCTL5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OCTL4,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OCTL3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OCTL2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OCTL1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OCTL0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BOP,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "CR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "CR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "CR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "CR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "CR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "CR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "CR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "CR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "CR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "CR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 21. "CR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "CR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "CR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "CR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "CR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BOP15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BOP14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BOP13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BOP12,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "BOP11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BOP10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BOP9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BOP8,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BOP7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BOP6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BOP5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BOP4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BOP3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BOP2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "BOP1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BOP0,Port x set bit y (y= 0..15)" "0,1"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BC,Port bit reset register"
|
|
bitfld.long 0x00 15. "CR15,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 14. "CR14,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 13. "CR13,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 12. "CR12,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 11. "CR11,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 10. "CR10,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 9. "CR9,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 8. "CR8,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 7. "CR7,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 6. "CR6,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 5. "CR5,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 4. "CR4,Port x Reset bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CR3,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 2. "CR2,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 1. "CR1,Port x Reset bit y" "0,1"
|
|
bitfld.long 0x00 0. "CR0,Port x Reset bit y" "0,1"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "TG,Port bit toggle register"
|
|
bitfld.long 0x00 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 5. "TG5,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 4. "TG4,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x00 0. "TG0,Port toggle bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40005400 ad:0x40005800)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,Control register 0"
|
|
bitfld.long 0x00 15. "SRESET,Software reset" "0,1"
|
|
bitfld.long 0x00 13. "SALT,SMBus alert" "0,1"
|
|
bitfld.long 0x00 12. "PECTRANS,Packet error checking" "0,1"
|
|
bitfld.long 0x00 11. "POAP,Acknowledge/PEC Position (for data reception)" "0,1"
|
|
bitfld.long 0x00 10. "ACKEN,Acknowledge enable" "0,1"
|
|
bitfld.long 0x00 9. "STOP,Stop condition" "0,1"
|
|
bitfld.long 0x00 8. "START,Start generation" "0,1"
|
|
bitfld.long 0x00 7. "SS,SCL Stretching(Slave mode)" "0,1"
|
|
bitfld.long 0x00 6. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x00 5. "PECEN,PEC enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ARPEN,ARP enable" "0,1"
|
|
bitfld.long 0x00 3. "SMBSEL,SMBus type" "0,1"
|
|
bitfld.long 0x00 1. "SMBEN,SMBus mode" "0,1"
|
|
bitfld.long 0x00 0. "I2CEN,Peripheral enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,Control register 1"
|
|
bitfld.long 0x00 12. "DMALST,Flag indicating DMA last transfer" "0,1"
|
|
bitfld.long 0x00 11. "DMAON,DMA mode switch" "0,1"
|
|
bitfld.long 0x00 10. "BUFIE,Buffer interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "EVIE,Event interrupt enable" "0,1"
|
|
bitfld.long 0x00 8. "ERRIE,Error interrupt enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "I2CCLK,Peripheral clock frequency"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SADDR0,Own address register 0"
|
|
bitfld.long 0x00 15. "ADDFORMAT,Addressing mode (slave mode)" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRESS,Interface address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SADDR1,Own address register 1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDRESS2,Interface address"
|
|
bitfld.long 0x00 0. "DUADEN,Dual addressing mode enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DATA,Data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRB,Transmission or reception data buffer"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT0,Transfer status register 0"
|
|
bitfld.long 0x00 15. "SMBALT,SMBus alert" "0,1"
|
|
bitfld.long 0x00 14. "SMBTO,Timeout signal in SMBus mode" "0,1"
|
|
bitfld.long 0x00 12. "PECERR,PEC error when receiving data" "0,1"
|
|
bitfld.long 0x00 11. "OUERR,Overrun/Underrun occurs in slave mode" "0,1"
|
|
bitfld.long 0x00 10. "AERR,Acknowledge error" "0,1"
|
|
bitfld.long 0x00 9. "LOSTARB,Arbitration lost (master mode)" "0,1"
|
|
bitfld.long 0x00 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x00 7. "TBE,I2C_DATA is Empty during transmitting" "0,1"
|
|
rbitfld.long 0x00 6. "RBNE,I2C_DATA is not Empty during receiving" "0,1"
|
|
rbitfld.long 0x00 4. "STPDET,Stop detection (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "ADD10SEND,Header of 10-bit address is sent in master mode" "0,1"
|
|
rbitfld.long 0x00 2. "BTC,Byte transmission completed" "0,1"
|
|
rbitfld.long 0x00 1. "ADDSEND,Address sent (master mode)/matched (slave mode)" "0,1"
|
|
rbitfld.long 0x00 0. "SBSEND,Start bit (Master mode)" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "STAT1,Transfer status register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PECV,Packet error checking register"
|
|
bitfld.long 0x00 7. "DUMODF,Dual flag (Slave mode)" "0,1"
|
|
bitfld.long 0x00 6. "HSTSMB,SMBus host header (Slave mode)" "0,1"
|
|
bitfld.long 0x00 5. "DEFSMB,SMBus device default address (Slave mode)" "0,1"
|
|
bitfld.long 0x00 4. "RXGC,General call address (Slave mode)" "0,1"
|
|
bitfld.long 0x00 2. "TR,Transmitter/receiver" "0,1"
|
|
bitfld.long 0x00 1. "I2CBSY,Bus busy" "0,1"
|
|
bitfld.long 0x00 0. "MASTER,Master/slave" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CKCFG,Clock configure register"
|
|
bitfld.long 0x00 15. "FAST,I2C master mode selection" "0,1"
|
|
bitfld.long 0x00 14. "DTCY,Fast mode duty cycle" "0,1"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLKC,Clock control register in Fast/Standard mode (Master mode)"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RT,Rise time register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RISETIME,Maximum rise time in master mode"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SAMCS,SAM control and status register"
|
|
bitfld.long 0x00 15. "RFR,Rxframe rise flag" "0,1"
|
|
bitfld.long 0x00 14. "RFF,Rxframe fall flag" "0,1"
|
|
bitfld.long 0x00 13. "TFR,Txframe rise flag" "0,1"
|
|
bitfld.long 0x00 12. "TFF,Txframe fall flag" "0,1"
|
|
bitfld.long 0x00 9. "RXF,level of rx frame signal" "0,1"
|
|
bitfld.long 0x00 8. "TXF,level of tx frame signal" "0,1"
|
|
bitfld.long 0x00 7. "RFRIE,Rx frame rise interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "RFFIE,Rx frame fall interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "TFRIE,Tx frame rise interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "TFFIE,Tx frame fall interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "STOEN,SAM_V interface timeout detect enable" "0,1"
|
|
bitfld.long 0x00 0. "SAMEN,SAM_V interface enable" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "FMPCFG,Fast-mode-plus configure register"
|
|
bitfld.long 0x00 0. "FMPEN,Fast-mode-plus enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "ISER$1,Interrupt Set Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,SETENA"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "ICER$1,Interrupt Clear Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,CLRENA"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "ISPR$1,Interrupt Set-Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,SETPEND"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "ICPR$1,Interrupt Clear-Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,CLRPEND"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "IABR$1,Interrupt Active bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "IABR,IABR"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "ITNS$1,Interrupt Active bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ITNS,ITNS"
|
|
repeat.end
|
|
group.byte 0x300++0x00
|
|
line.byte 0x00 "IPR0,Interrupt Priority Register 0"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_00,PRI_00"
|
|
group.byte 0x301++0x00
|
|
line.byte 0x00 "IPR1,Interrupt Priority Register 1"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_01,PRI_01"
|
|
group.byte 0x302++0x00
|
|
line.byte 0x00 "IPR2,Interrupt Priority Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_02,PRI_02"
|
|
group.byte 0x303++0x00
|
|
line.byte 0x00 "IPR3,Interrupt Priority Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_03,PRI_03"
|
|
group.byte 0x304++0x00
|
|
line.byte 0x00 "IPR4,Interrupt Priority Register 4"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_04,PRI_04"
|
|
group.byte 0x305++0x00
|
|
line.byte 0x00 "IPR5,Interrupt Priority Register 5"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_05,PRI_05"
|
|
group.byte 0x306++0x00
|
|
line.byte 0x00 "IPR6,Interrupt Priority Register 6"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_06,PRI_06"
|
|
group.byte 0x307++0x00
|
|
line.byte 0x00 "IPR7,Interrupt Priority Register 7"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_07,PRI_07"
|
|
group.byte 0x308++0x00
|
|
line.byte 0x00 "IPR8,Interrupt Priority Register 8"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_08,PRI_08"
|
|
group.byte 0x309++0x00
|
|
line.byte 0x00 "IPR9,Interrupt Priority Register 9"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_09,PRI_09"
|
|
group.byte 0x30A++0x00
|
|
line.byte 0x00 "IPR10,Interrupt Priority Register 10"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_10,PRI_10"
|
|
group.byte 0x30B++0x00
|
|
line.byte 0x00 "IPR11,Interrupt Priority Register 11"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_11,PRI_11"
|
|
group.byte 0x30C++0x00
|
|
line.byte 0x00 "IPR12,Interrupt Priority Register 12"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_12,PRI_12"
|
|
group.byte 0x30D++0x00
|
|
line.byte 0x00 "IPR13,Interrupt Priority Register 13"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_13,PRI_13"
|
|
group.byte 0x30E++0x00
|
|
line.byte 0x00 "IPR14,Interrupt Priority Register 14"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_14,PRI_14"
|
|
group.byte 0x30F++0x00
|
|
line.byte 0x00 "IPR15,Interrupt Priority Register 15"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_15,PRI_15"
|
|
group.byte 0x310++0x00
|
|
line.byte 0x00 "IPR16,Interrupt Priority Register 16"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_16,PRI_16"
|
|
group.byte 0x311++0x00
|
|
line.byte 0x00 "IPR17,Interrupt Priority Register 17"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_17,PRI_17"
|
|
group.byte 0x312++0x00
|
|
line.byte 0x00 "IPR18,Interrupt Priority Register 18"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_18,PRI_18"
|
|
group.byte 0x313++0x00
|
|
line.byte 0x00 "IPR19,Interrupt Priority Register 19"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_19,PRI_19"
|
|
group.byte 0x314++0x00
|
|
line.byte 0x00 "IPR20,Interrupt Priority Register 20"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_20,PRI_20"
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "IPR21,Interrupt Priority Register 21"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_21,PRI_21"
|
|
group.byte 0x316++0x00
|
|
line.byte 0x00 "IPR22,Interrupt Priority Register 22"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_22,PRI_22"
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "IPR23,Interrupt Priority Register 23"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_23,PRI_23"
|
|
group.byte 0x318++0x00
|
|
line.byte 0x00 "IPR24,Interrupt Priority Register 24"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_24,PRI_24"
|
|
group.byte 0x319++0x00
|
|
line.byte 0x00 "IPR25,Interrupt Priority Register 25"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_25,PRI_25"
|
|
group.byte 0x31A++0x00
|
|
line.byte 0x00 "IPR26,Interrupt Priority Register 26"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_26,PRI_26"
|
|
group.byte 0x31B++0x00
|
|
line.byte 0x00 "IPR27,Interrupt Priority Register 27"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_27,PRI_27"
|
|
group.byte 0x31C++0x00
|
|
line.byte 0x00 "IPR28,Interrupt Priority Register 28"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_28,PRI_28"
|
|
group.byte 0x31D++0x00
|
|
line.byte 0x00 "IPR29,Interrupt Priority Register 29"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_29,PRI_29"
|
|
group.byte 0x31E++0x00
|
|
line.byte 0x00 "IPR30,Interrupt Priority Register 30"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_30,PRI_30"
|
|
group.byte 0x31F++0x00
|
|
line.byte 0x00 "IPR31,Interrupt Priority Register 31"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI_31,PRI_31"
|
|
tree.end
|
|
tree "PMU (Program Memory Unit)"
|
|
base ad:0x40007000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,power control register"
|
|
bitfld.long 0x00 14.--15. "LDOVS,LDO output voltage select" "0,1,2,3"
|
|
bitfld.long 0x00 8. "BKPWEN,Backup Domain Write Enable" "0,1"
|
|
bitfld.long 0x00 5.--7. "LVDT,Low Voltage Detector Threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "LVDEN,Low Voltage Detector Enable" "0,1"
|
|
bitfld.long 0x00 3. "STBRST,Standby Flag Reset" "0,1"
|
|
bitfld.long 0x00 2. "WURST,Wakeup Flag Reset" "0,1"
|
|
bitfld.long 0x00 1. "STBMOD,Standby Mode" "0,1"
|
|
bitfld.long 0x00 0. "LDOLP,LDO Low Power Mode" "0,1"
|
|
sif cpuis("GD32E231*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CS,power control/status register"
|
|
bitfld.long 0x00 14. "WUPEN6,WKUP pin6 Enable" "0,1"
|
|
bitfld.long 0x00 13. "WUPEN5,WKUP pin5 Enable" "0,1"
|
|
bitfld.long 0x00 8. "WUPEN0,WKUP pin0 Enable" "0,1"
|
|
rbitfld.long 0x00 2. "LVDF,Low Voltage Detector Status Flag" "0,1"
|
|
rbitfld.long 0x00 1. "STBF,Standby flag" "0,1"
|
|
rbitfld.long 0x00 0. "WUF,Wakeup flag" "0,1"
|
|
endif
|
|
sif cpuis("GD32E230*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CS,power control/status register"
|
|
bitfld.long 0x00 14. "WUPEN6,WKUP pin6 Enable" "0,1"
|
|
bitfld.long 0x00 13. "WUPEN5,WKUP pin5 Enable" "0,1"
|
|
bitfld.long 0x00 9. "WUPEN1,WKUP pin1 Enable" "0,1"
|
|
bitfld.long 0x00 8. "WUPEN0,WKUP pin0 Enable" "0,1"
|
|
rbitfld.long 0x00 2. "LVDF,Low Voltage Detector Status Flag" "0,1"
|
|
rbitfld.long 0x00 1. "STBF,Standby flag" "0,1"
|
|
rbitfld.long 0x00 0. "WUF,Wakeup flag" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "RCU (Reset and clock unit)"
|
|
base ad:0x40021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,Control register 0"
|
|
rbitfld.long 0x00 25. "PLLSTB,PLL Clock Stabilization Flag" "0,1"
|
|
bitfld.long 0x00 24. "PLLEN,PLL enable" "0,1"
|
|
bitfld.long 0x00 19. "CKMEN,HXTAL Clock Monitor Enable" "0,1"
|
|
bitfld.long 0x00 18. "HXTALBPS,External crystal oscillator (HXTAL) clock bypass mode enable" "0,1"
|
|
rbitfld.long 0x00 17. "HXTALSTB,External crystal oscillator (HXTAL) clock stabilization flag" "0,1"
|
|
bitfld.long 0x00 16. "HXTALEN,External High Speed oscillator Enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "IRC8MCALIB,High Speed Internal Oscillator calibration value register"
|
|
bitfld.long 0x00 3.--7. "IRC8MADJ,High Speed Internal Oscillator clock trim adjust value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. "IRC8MSTB,IRC8M High Speed Internal Oscillator stabilization Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IRC8MEN,Internal High Speed oscillator Enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG0,Clock configuration register 0 (RCU_CFG0)"
|
|
bitfld.long 0x00 31. "PLLDV,The CK_PLL divide by 1 or 2 for CK_OUT" "0,1"
|
|
bitfld.long 0x00 28.--30. "CKOUTDIV,The CK_OUT divider which the CK_OUT frequency can be reduced" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 27. "PLLMF_MSB,Bit 4 of PLLMF register" "0,1"
|
|
bitfld.long 0x00 24.--26. "CKOUTSEL,CK_OUT Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--21. "PLLMF,PLL multiply factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17. "PLLPREDV,HXTAL divider for PLL source clock selection" "0,1"
|
|
bitfld.long 0x00 16. "PLLSEL,PLL Clock Source Selection" "0,1"
|
|
bitfld.long 0x00 14.--15. "ADCPSC,ADC clock prescaler selection" "0,1,2,3"
|
|
bitfld.long 0x00 11.--13. "APB2PSC,APB2 prescaler selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "APB1PSC,APB1 prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--7. "AHBPSC,AHB prescaler selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "SCSS,System clock switch status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SCS,System clock switch" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT,Clock interrupt register (RCU_INT)"
|
|
bitfld.long 0x00 23. "CKMIC,HXTAL Clock Stuck Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 21. "IRC28MSTBIC,IRC28M stabilization Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 20. "PLLSTBIC,PLL stabilization Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 19. "HXTALSTBIC,HXTAL Stabilization Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 18. "IRC8MSTBIC,IRC8M Stabilization Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 17. "LXTALSTBIC,LXTAL Stabilization Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 16. "IRC40KSTBIC,IRC40K Stabilization Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 13. "IRC28MSTBIE,IRC28M Stabilization Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 12. "PLLSTBIE,PLL Stabilization Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "HXTALSTBIE,HXTAL Stabilization Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. "IRC8MSTBIE,IRC8M Stabilization Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. "LXTALSTBIE,LXTAL Stabilization Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 8. "IRC40KSTBIE,IRC40K Stabilization interrupt enable" "0,1"
|
|
rbitfld.long 0x00 7. "CKMIF,HXTAL Clock Stuck Interrupt Flag" "0,1"
|
|
rbitfld.long 0x00 5. "IRC28MSTBIF,IRC28M stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0x00 4. "PLLSTBIF,PLL stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0x00 3. "HXTALSTBIF,HXTAL stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0x00 2. "IRC8MSTBIF,IRC8M stabilization interrupt flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "LXTALSTBIF,LXTAL stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0x00 0. "IRC40KSTBIF,IRC40K stabilization interrupt flag" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "APB2RST,APB2 reset register (RCU_APB2RST)"
|
|
bitfld.long 0x00 18. "TIMER16RST,TIMER16 reset" "0,1"
|
|
bitfld.long 0x00 17. "TIMER15RST,TIMER15 reset" "0,1"
|
|
bitfld.long 0x00 16. "TIMER14RST,TIMER14 reset" "0,1"
|
|
bitfld.long 0x00 14. "USART0RST,USART0 Reset" "0,1"
|
|
bitfld.long 0x00 12. "SPI0RST,SPI0 Reset" "0,1"
|
|
bitfld.long 0x00 11. "TIMER0RST,TIMER0 reset" "0,1"
|
|
bitfld.long 0x00 9. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0x00 0. "CFGCMPRST,System configuration and comparator reset" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "APB1RST,APB1 reset register (RCU_APB1RST)"
|
|
bitfld.long 0x00 28. "PMURST,Power control reset" "0,1"
|
|
bitfld.long 0x00 22. "I2C1RST,I2C1 reset" "0,1"
|
|
bitfld.long 0x00 21. "I2C0RST,I2C0 reset" "0,1"
|
|
bitfld.long 0x00 17. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0x00 14. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0x00 11. "WWDGTRST,Window watchdog timer reset" "0,1"
|
|
bitfld.long 0x00 8. "TIMER13RST,TIMER13 timer reset" "0,1"
|
|
bitfld.long 0x00 4. "TIMER5RST,TIMER5 timer reset" "0,1"
|
|
bitfld.long 0x00 1. "TIMER2RST,TIMER2 timer reset" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "AHBEN,AHB enable register (RCU_AHBEN)"
|
|
bitfld.long 0x00 22. "PFEN,GPIO port F clock enable" "0,1"
|
|
bitfld.long 0x00 19. "PCEN,GPIO port C clock enable" "0,1"
|
|
bitfld.long 0x00 18. "PBEN,GPIO port B clock enable" "0,1"
|
|
bitfld.long 0x00 17. "PAEN,GPIO port A clock enable" "0,1"
|
|
bitfld.long 0x00 6. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x00 4. "FMCSPEN,FMC clock during sleep mode enable" "0,1"
|
|
bitfld.long 0x00 2. "SRAMSPEN,SRAM interface clock during sleep mode enable" "0,1"
|
|
bitfld.long 0x00 0. "DMAEN,DMA clock enable" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "APB2EN,APB2 enable register (RCU_APB2EN)"
|
|
bitfld.long 0x00 22. "DBGMCUEN,DBGMCU clock enable" "0,1"
|
|
bitfld.long 0x00 18. "TIMER16EN,TIMER16 timer clock enable" "0,1"
|
|
bitfld.long 0x00 17. "TIMER15EN,TIMER15 timer clock enable" "0,1"
|
|
bitfld.long 0x00 16. "TIMER14EN,TIMER14 timer clock enable" "0,1"
|
|
bitfld.long 0x00 14. "USART0EN,USART0 clock enable" "0,1"
|
|
bitfld.long 0x00 12. "SPI0EN,SPI0 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "TIMER0EN,TIMER0 timer clock enable" "0,1"
|
|
bitfld.long 0x00 9. "ADCEN,ADC interface clock enable" "0,1"
|
|
bitfld.long 0x00 0. "CFGCMPEN,System configuration and comparator clock enable" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "APB1EN,APB1 enable register (RCU_APB1EN)"
|
|
bitfld.long 0x00 28. "PMUEN,Power interface clock enable" "0,1"
|
|
bitfld.long 0x00 22. "I2C1EN,I2C1 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "I2C0EN,I2C0 clock enable" "0,1"
|
|
bitfld.long 0x00 17. "USART1EN,USART1 clock enable" "0,1"
|
|
bitfld.long 0x00 14. "SPI1EN,SPI1 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "WWDGTEN,Window watchdog timer clock enable" "0,1"
|
|
bitfld.long 0x00 8. "TIMER13EN,TIMER13 timer clock enable" "0,1"
|
|
bitfld.long 0x00 4. "TIMER5EN,TIMER5 timer clock enable" "0,1"
|
|
bitfld.long 0x00 1. "TIMER2EN,TIMER2 timer clock enable" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BDCTL,Backup domain control register (RCU_BDCTL)"
|
|
bitfld.long 0x00 16. "BKPRST,Backup domain reset" "0,1"
|
|
bitfld.long 0x00 15. "RTCEN,RTC clock enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "RTCSRC,RTC clock entry selection" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "LXTALDRI,LXTAL drive capability" "0,1,2,3"
|
|
bitfld.long 0x00 2. "LXTALBPS,LXTAL bypass mode enable" "0,1"
|
|
rbitfld.long 0x00 1. "LXTALSTB,External low-speed oscillator stabilization" "0,1"
|
|
bitfld.long 0x00 0. "LXTALEN,LXTAL enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RSTSCK,Reset source /clock register (RCU_RSTSCK)"
|
|
bitfld.long 0x00 31. "LPRSTF,Low-power reset flag" "0,1"
|
|
bitfld.long 0x00 30. "WWDGTRSTF,Window watchdog timer reset flag" "0,1"
|
|
bitfld.long 0x00 29. "FWDGTRSTF,Free Watchdog timer reset flag" "0,1"
|
|
bitfld.long 0x00 28. "SWRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x00 27. "PORRSTF,Power reset flag" "0,1"
|
|
bitfld.long 0x00 26. "EPRSTF,External PIN reset flag" "0,1"
|
|
bitfld.long 0x00 25. "OBLRSTF,Option byte loader reset flag" "0,1"
|
|
bitfld.long 0x00 24. "RSTFC,Reset flag clear" "0,1"
|
|
bitfld.long 0x00 23. "V12RSTF,V12 domain Power reset flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "IRC40KSTB,IRC40K stabilization" "0,1"
|
|
bitfld.long 0x00 0. "IRC40KEN,IRC40K enable" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AHBRST,AHB reset register"
|
|
bitfld.long 0x00 22. "PFRST,GPIO port F reset" "0,1"
|
|
bitfld.long 0x00 19. "PCRST,GPIO port C reset" "0,1"
|
|
bitfld.long 0x00 18. "PBRST,GPIO port B reset" "0,1"
|
|
bitfld.long 0x00 17. "PARST,GPIO port A reset" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CFG1,Configuration register 1"
|
|
bitfld.long 0x00 0.--3. "PREDV,CK_HXTAL or CK_IRC48M divider previous PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG2,Configuration register 2"
|
|
bitfld.long 0x00 31. "ADCPSC,Bit 2 of ADCPSC" "0,1"
|
|
bitfld.long 0x00 16. "IRC28MDIV,CK_IRC28M divider 2 or not" "0,1"
|
|
bitfld.long 0x00 8. "ADCSEL,CK_ADC clock source selection" "0,1"
|
|
bitfld.long 0x00 0.--1. "USART0SEL,CK_USART0 clock source selection" "0,1,2,3"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "IRC28MCALIB,Internal 28M RC Oscillator calibration value register"
|
|
bitfld.long 0x00 3.--7. "IRC28MADJ,Internal 28M RC Oscillator clock trim adjust value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. "IRC28MSTB,IRC28M Internal 28M RC Oscillator stabilization Flag" "0,1"
|
|
bitfld.long 0x00 0. "IRC28MEN,IRC28M Internal 28M RC oscillator Enable" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VKEY,Voltage key register"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,The key of RCU_DSV register"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DSV,Deep-sleep mode voltage register"
|
|
bitfld.long 0x00 0.--1. "DSLPVS,Deep-sleep mode voltage select" "0,1,2,3"
|
|
tree.end
|
|
tree "RTC (Real-time Counter)"
|
|
base ad:0x40002800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIME,time register"
|
|
bitfld.long 0x00 22. "PM,AM/PM mark" "0,1"
|
|
bitfld.long 0x00 20.--21. "HRT,Hour tens in BCD code" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HRU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. "SCT,Second tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SCU,Second units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DATE,date register"
|
|
bitfld.long 0x00 20.--23. "YRT,Year tens in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YRU,Year units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "DOW,Days of the week" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "MONT,Month tens in BCD code" "0,1"
|
|
bitfld.long 0x00 8.--11. "MONU,Month units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "DAYT,Date tens in BCD code" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DAYU,Date units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("GD32E231*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL,control register"
|
|
bitfld.long 0x00 18. "DSM,Backup" "0,1"
|
|
bitfld.long 0x00 17. "S1H,Subtract 1 hour (winter time change)" "0,1"
|
|
bitfld.long 0x00 16. "A1H,Add 1 hour (summer time change)" "0,1"
|
|
bitfld.long 0x00 12. "ALRM0IE,Alarm A interrupt enable" "0,1"
|
|
bitfld.long 0x00 8. "ALRM0EN,Alarm A enable" "0,1"
|
|
bitfld.long 0x00 6. "CS,Hour format" "0,1"
|
|
bitfld.long 0x00 5. "BPSHAD,Bypass the shadow registers" "0,1"
|
|
bitfld.long 0x00 4. "REFEN,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0,1"
|
|
endif
|
|
sif cpuis("GD32E230*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL,control register"
|
|
bitfld.long 0x00 23. "COEN,Calibration output enable" "0,1"
|
|
bitfld.long 0x00 21.--22. "OS,Output selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. "OPOL,Output polarity" "0,1"
|
|
bitfld.long 0x00 19. "COS,Calibration output selection" "0,1"
|
|
bitfld.long 0x00 18. "DSM,Backup" "0,1"
|
|
bitfld.long 0x00 17. "S1H,Subtract 1 hour (winter time change)" "0,1"
|
|
bitfld.long 0x00 16. "A1H,Add 1 hour (summer time change)" "0,1"
|
|
bitfld.long 0x00 15. "TSIE,Time-stamp interrupt enable" "0,1"
|
|
bitfld.long 0x00 12. "ALRM0IE,Alarm A interrupt enable" "0,1"
|
|
bitfld.long 0x00 11. "TSEN,timestamp enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ALRM0EN,Alarm A enable" "0,1"
|
|
bitfld.long 0x00 6. "CS,Hour format" "0,1"
|
|
bitfld.long 0x00 5. "BPSHAD,Bypass the shadow registers" "0,1"
|
|
bitfld.long 0x00 4. "REFEN,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0,1"
|
|
bitfld.long 0x00 3. "TSEG,Time-stamp event active edge" "0,1"
|
|
endif
|
|
sif cpuis("GD32E231*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STAT,initialization and status register"
|
|
rbitfld.long 0x00 16. "SCPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x00 14. "TP1F,RTC_TAMP1 detection flag" "0,1"
|
|
bitfld.long 0x00 8. "ALRM0F,Alarm A flag" "0,1"
|
|
bitfld.long 0x00 7. "INITM,Initialization mode" "0,1"
|
|
rbitfld.long 0x00 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x00 5. "RSYNF,Registers synchronization flag" "0,1"
|
|
rbitfld.long 0x00 4. "YCM,Initialization status flag" "0,1"
|
|
rbitfld.long 0x00 3. "SOPF,Shift operation pending" "0,1"
|
|
rbitfld.long 0x00 0. "ALRM0WF,Alarm A write flag" "0,1"
|
|
endif
|
|
sif cpuis("GD32E230*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STAT,initialization and status register"
|
|
rbitfld.long 0x00 16. "SCPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x00 14. "TP1F,RTC_TAMP1 detection flag" "0,1"
|
|
bitfld.long 0x00 13. "TP0F,RTC_TAMP0 detection flag" "0,1"
|
|
bitfld.long 0x00 12. "TSOVRF,Time-stamp overflow flag" "0,1"
|
|
bitfld.long 0x00 11. "TSF,Time-stamp flag" "0,1"
|
|
bitfld.long 0x00 8. "ALRM0F,Alarm A flag" "0,1"
|
|
bitfld.long 0x00 7. "INITM,Initialization mode" "0,1"
|
|
rbitfld.long 0x00 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x00 5. "RSYNF,Registers synchronization flag" "0,1"
|
|
rbitfld.long 0x00 4. "YCM,Initialization status flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "SOPF,Shift operation pending" "0,1"
|
|
rbitfld.long 0x00 0. "ALRM0WF,Alarm A write flag" "0,1"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PSC,prescaler register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "FACTOR_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x00 0.--14. 1. "FACTOR_S,Synchronous prescaler factor"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRM0TD,alarm A register"
|
|
bitfld.long 0x00 31. "MSKD,Alarm date mask" "0,1"
|
|
bitfld.long 0x00 30. "DOWS,Week day selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "DAYT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DAYU,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "MSKH,Alarm hours mask" "0,1"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HRT,Hour tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HRU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MSKM,Alarm minutes mask" "0,1"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSKS,Alarm seconds mask" "0,1"
|
|
bitfld.long 0x00 4.--6. "SCT,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SCU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "WPK,write protection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WPK,Write protection key"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SS,sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SSC,Sub second value"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "SHIFTCTL,shift control register"
|
|
bitfld.long 0x00 31. "A1S,One second add" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. "SFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TTS,timestamp time register"
|
|
bitfld.long 0x00 22. "PM,AM/PM mark" "0,1"
|
|
bitfld.long 0x00 20.--21. "HRT,Hour tens in BCD code" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HRU,Hour units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. "SCT,Second tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SCU,Second units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DTS,Date of time stamp register"
|
|
bitfld.long 0x00 13.--15. "DOW,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "MONT,Month tens in BCD code" "0,1"
|
|
bitfld.long 0x00 8.--11. "MONU,Month units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--6. "DAYT,Date tens in BCD code" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "DAYU,Date units in BCD code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SSTS,time-stamp sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SSC,Sub second value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "HRFC,High resolution frequency compensation register"
|
|
bitfld.long 0x00 15. "FREQI,Increase RTC frequency by 488.5PPM" "0,1"
|
|
bitfld.long 0x00 14. "CWND8,Frequency compensation window 8 second selected" "0,1"
|
|
bitfld.long 0x00 13. "CWND16,Frequency compensation window 16 second selected" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "CMSK,Calibration mask number"
|
|
sif cpuis("GD32E230*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TAMP,tamper and alternate function configuration register"
|
|
bitfld.long 0x00 23. "PC15MDE,PC15 mode" "0,1"
|
|
bitfld.long 0x00 22. "PC15VAL,PC15 value" "0,1"
|
|
bitfld.long 0x00 21. "PC14MDE,PC14 mode" "0,1"
|
|
bitfld.long 0x00 20. "PC14VAL,PC14 value" "0,1"
|
|
bitfld.long 0x00 19. "PC13MDE,PC13 mode" "0,1"
|
|
bitfld.long 0x00 18. "PC13VAL,RTC_ALARM output type/PC13 value" "0,1"
|
|
bitfld.long 0x00 15. "DISPU,RTC_TAMPx pull-up disable" "0,1"
|
|
bitfld.long 0x00 13.--14. "PRCH,RTC_TAMPx precharge duration" "0,1,2,3"
|
|
bitfld.long 0x00 11.--12. "FLT,RTC_TAMPx filter count" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "FREQ,Tamper sampling frequency" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "TPTS,Activate timestamp on tamper detection event" "0,1"
|
|
bitfld.long 0x00 4. "TP1EG,Tamper 1 event trigger edge" "0,1"
|
|
bitfld.long 0x00 3. "TP1EN,Tamper 1 detection enable" "0,1"
|
|
bitfld.long 0x00 2. "TPIE,Tamper detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TP0EG,Active level for RTC_TAMP1 input" "0,1"
|
|
bitfld.long 0x00 0. "TP0EN,Tamper 0 event trigger edge" "0,1"
|
|
endif
|
|
sif cpuis("GD32E231*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TAMP,tamper and alternate function configuration register"
|
|
bitfld.long 0x00 23. "PC15MDE,PC15 mode" "0,1"
|
|
bitfld.long 0x00 22. "PC15VAL,PC15 value" "0,1"
|
|
bitfld.long 0x00 21. "PC14MDE,PC14 mode" "0,1"
|
|
bitfld.long 0x00 20. "PC14VAL,PC14 value" "0,1"
|
|
bitfld.long 0x00 15. "DISPU,RTC_TAMPx pull-up disable" "0,1"
|
|
bitfld.long 0x00 13.--14. "PRCH,RTC_TAMPx precharge duration" "0,1,2,3"
|
|
bitfld.long 0x00 11.--12. "FLT,RTC_TAMPx filter count" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "FREQ,Tamper sampling frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "TP1EG,Tamper 1 event trigger edge" "0,1"
|
|
bitfld.long 0x00 3. "TP1EN,Tamper 1 detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TPIE,Tamper detection interrupt enable" "0,1"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ALRM0SS,alarm 0 sub second register"
|
|
bitfld.long 0x00 24.--27. "MSKSSC,Mask control bit of SSC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--14. 1. "SSC,Alarm sub second value"
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "BKP$1,backup register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,BKP data"
|
|
repeat.end
|
|
tree.end
|
|
tree "SPI (Serial peripheral interface)"
|
|
tree "SPI0"
|
|
base ad:0x40013000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 15. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0x00 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
|
|
bitfld.long 0x00 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x00 12. "CRCNT,CRC transfer next" "0,1"
|
|
bitfld.long 0x00 11. "FF16,Data frame format" "0,1"
|
|
bitfld.long 0x00 10. "RO,Receive only" "0,1"
|
|
bitfld.long 0x00 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
|
|
bitfld.long 0x00 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
|
|
bitfld.long 0x00 7. "LF,LSB First Mode" "0,1"
|
|
bitfld.long 0x00 6. "SPIEN,SPI enable" "0,1"
|
|
bitfld.long 0x00 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. "MSTMOD,Master Mode Enable" "0,1"
|
|
bitfld.long 0x00 1. "CKPL,Clock Polarity Selection" "0,1"
|
|
bitfld.long 0x00 0. "CKPH,Clock Phase Selection" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 7. "TBEIE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 6. "RBNEIE,Receive Buffer Not Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "TMOD,SPI TI Mode Enable" "0,1"
|
|
bitfld.long 0x00 3. "NSSP,SPI NSS Pulse Mode Enable" "0,1"
|
|
bitfld.long 0x00 2. "NSSDRV,NSS output enable" "0,1"
|
|
bitfld.long 0x00 1. "DMATEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x00 0. "DMAREN,Rx buffer DMA enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STAT,status register"
|
|
bitfld.long 0x00 8. "FERR,Format Error" "0,1"
|
|
rbitfld.long 0x00 7. "TRANS,Transmitting On-going Bit" "0,1"
|
|
rbitfld.long 0x00 6. "RXORERR,Reception Overrun Error Bit" "0,1"
|
|
rbitfld.long 0x00 5. "CONFERR,SPI Configuration error" "0,1"
|
|
bitfld.long 0x00 4. "CRCERR,SPI CRC Error Bit" "0,1"
|
|
rbitfld.long 0x00 3. "TXURERR,Transmission underrun error bit" "0,1"
|
|
rbitfld.long 0x00 2. "I2SCH,I2S channel side" "0,1"
|
|
rbitfld.long 0x00 1. "TBE,Transmit Buffer Empty" "0,1"
|
|
rbitfld.long 0x00 0. "RBNE,Receive Buffer Not Empty" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DATA,data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,Data register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CPCPOLY,CRC polynomial register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RCRC,RX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCRC,RX RCR register"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TCRC,TX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TCRC,Tx CRC register"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2SCTL,I2S configuration register"
|
|
bitfld.long 0x00 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x00 10. "I2SEN,I2S Enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "I2SOPMOD,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x00 7. "PCMSMOD,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x00 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x00 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x00 1.--2. "DTLEN,Data length to be transferred" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CHLEN,Channel length (number of bits per audio channel)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2SPSC,I2S prescaler register"
|
|
bitfld.long 0x00 9. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x00 8. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Dividing factor for the prescaler"
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40003800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 15. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0x00 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
|
|
bitfld.long 0x00 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x00 12. "CRCNT,CRC transfer next" "0,1"
|
|
bitfld.long 0x00 11. "CRCL,CRC length" "0,1"
|
|
bitfld.long 0x00 10. "RO,Receive only" "0,1"
|
|
bitfld.long 0x00 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
|
|
bitfld.long 0x00 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
|
|
bitfld.long 0x00 7. "LF,LSB First Mode" "0,1"
|
|
bitfld.long 0x00 6. "SPIEN,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "MSTMOD,Master Mode Enable" "0,1"
|
|
bitfld.long 0x00 1. "CKPL,Clock Polarity Selection" "0,1"
|
|
bitfld.long 0x00 0. "CKPH,Clock Phase Selection" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 14. "TXDMA_ODD,Odd bytes in TX DMA channel" "0,1"
|
|
bitfld.long 0x00 13. "RXDMA_ODD,Odd bytes in RX DMA channel" "0,1"
|
|
bitfld.long 0x00 12. "BYTEN,Byte access enable" "0,1"
|
|
bitfld.long 0x00 8.--11. "DZ,Date size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "TBEIE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 6. "RBNEIE,Receive Buffer Not Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "TMOD,SPI TI Mode Enable" "0,1"
|
|
bitfld.long 0x00 3. "NSSP,SPI NSS Pulse Mode Enable" "0,1"
|
|
bitfld.long 0x00 2. "NSSDRV,NSS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DMATEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x00 0. "DMAREN,Rx buffer DMA enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STAT,status register"
|
|
rbitfld.long 0x00 11.--12. "TXLVL,Tx FIFO level" "0,1,2,3"
|
|
rbitfld.long 0x00 9.--10. "RXLVL,Rx FIFO level" "0,1,2,3"
|
|
bitfld.long 0x00 8. "FERR,Format Error" "0,1"
|
|
rbitfld.long 0x00 7. "TRANS,Transmitting On-going Bit" "0,1"
|
|
rbitfld.long 0x00 6. "RXORERR,Reception Overrun Error Bit" "0,1"
|
|
rbitfld.long 0x00 5. "CONFERR,SPI Configuration error" "0,1"
|
|
bitfld.long 0x00 4. "CRCERR,SPI CRC Error Bit" "0,1"
|
|
rbitfld.long 0x00 1. "TBE,Transmit Buffer Empty" "0,1"
|
|
rbitfld.long 0x00 0. "RBNE,Receive Buffer Not Empty" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DATA,data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,Data register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CPCPOLY,CRC polynomial register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RCRC,RX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCRC,RX RCR register"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TCRC,TX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TCRC,Tx CRC register"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2SCTL,I2S configuration register"
|
|
bitfld.long 0x00 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x00 10. "I2SEN,I2S Enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "I2SOPMOD,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x00 7. "PCMSMOD,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x00 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x00 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x00 1.--2. "DTLEN,Data length to be transferred" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CHLEN,Channel length (number of bits per audio channel)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2SPSC,I2S prescaler register"
|
|
bitfld.long 0x00 9. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x00 8. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Dividing factor for the prescaler"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QCTL,SPI quad wird control register"
|
|
bitfld.long 0x00 2. "IO23_DRV,Drive IO2 and IO3 enable" "0,1"
|
|
bitfld.long 0x00 1. "QRD,Quad wire read select" "0,1"
|
|
bitfld.long 0x00 0. "QMOD,Quad wire mode enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
sif cpuis("GD32E231*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG0,System configuration register 0"
|
|
bitfld.long 0x00 12. "TIMER16_DMA_RMP,Timer 16 DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 11. "TIMER15_DMA_RMP,Timer 15 DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 10. "USART0_RX_DMA_RMP,USART0_RX DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 9. "USART0_TX_DMA_RMP,USART0_TX DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 8. "ADC_DMA_RMP,ADC DMA request remapping enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PA11_PA12_RMP,PA11 and PA12 remapping bit for small packages" "0,1"
|
|
rbitfld.long 0x00 0.--1. "BOOT_MODE,Boot mode" "0,1,2,3"
|
|
endif
|
|
sif cpuis("GD32E230*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG0,System configuration register 0"
|
|
bitfld.long 0x00 19. "PB9_HCCE,PB9 pin high current capability enable" "0,1"
|
|
bitfld.long 0x00 12. "TIMER16_DMA_RMP,Timer 16 DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 11. "TIMER15_DMA_RMP,Timer 15 DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 10. "USART0_RX_DMA_RMP,USART0_RX DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 9. "USART0_TX_DMA_RMP,USART0_TX DMA request remapping enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ADC_DMA_RMP,ADC DMA request remapping enable" "0,1"
|
|
bitfld.long 0x00 4. "PA11_PA12_RMP,PA11 and PA12 remapping bit for small packages" "0,1"
|
|
rbitfld.long 0x00 0.--1. "BOOT_MODE,Boot mode" "0,1,2,3"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EXTISS0,EXTI sources selection register 0"
|
|
bitfld.long 0x00 12.--15. "EXTI3_SS,EXTI 3 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "EXTI2_SS,EXTI 2 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "EXTI1_SS,EXTI 1 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "EXTI0_SS,EXTI 0 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EXTISS1,EXTI sources selection register 1"
|
|
bitfld.long 0x00 12.--15. "EXTI7_SS,EXTI 7 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "EXTI6_SS,EXTI 6 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "EXTI5_SS,EXTI 5 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "EXTI4_SS,EXTI 4 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EXTISS2,EXTI sources selection register 2"
|
|
bitfld.long 0x00 12.--15. "EXTI11_SS,EXTI 11 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "EXTI10_SS,EXTI 10 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "EXTI9_SS,EXTI 9 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "EXTI8_SS,EXTI 8 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EXTISS3,EXTI sources selection register 3"
|
|
bitfld.long 0x00 12.--15. "EXTI15_SS,EXTI 15 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "EXTI14_SS,EXTI 14 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "EXTI13_SS,EXTI 13 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "EXTI12_SS,EXTI 12 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CFG2,System configuration register 2"
|
|
bitfld.long 0x00 8. "SRAM_PCEF,SRAM parity check error flag" "0,1"
|
|
bitfld.long 0x00 2. "LVD_LOCK,LVD lock" "0,1"
|
|
bitfld.long 0x00 1. "SRAM_PARITY_ERROR_LOCK,SRAM parity check error lock" "0,1"
|
|
bitfld.long 0x00 0. "LOCKUP_LOCK,Cortex-M4 LOCKUP output lock" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CPU_IRQ_LAT,IRQ Latency register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IRQ_LATENCY,specifies the minimum number of cycles between an interrupt"
|
|
tree.end
|
|
tree "TIMER (Timer/Counter)"
|
|
tree "TIMER0"
|
|
base ad:0x40012C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CAM,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 14. "ISO3,Idle state of channel 3 output" "0,1"
|
|
bitfld.long 0x00 13. "ISO2N,Idle state of channel 2 complementary output" "0,1"
|
|
bitfld.long 0x00 12. "ISO2,Idle state of channel 2 output" "0,1"
|
|
bitfld.long 0x00 11. "ISO1N,Idle state of channel 1 complementary output" "0,1"
|
|
bitfld.long 0x00 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x00 9. "ISO0N,Idle state of channel 0 complementary output" "0,1"
|
|
bitfld.long 0x00 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x00 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "DMAS,DMA request source selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CCUC,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x00 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCFG,slave mode configuration register"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "SCM1,Part of SMC for enable External clock mode1" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETFC,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OCRC,Trigger selection" "0,1"
|
|
bitfld.long 0x00 0.--2. "SMC,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "CMTDEN,Reserved" "0,1"
|
|
bitfld.long 0x00 12. "CH3DEN,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CH2DEN,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CH1DEN,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CH0DEN,Capture/Compare 0 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "CMTIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CH3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CH2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CH1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CH0IE,Capture/Compare 0 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTF,status register"
|
|
bitfld.long 0x00 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x00 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x00 7. "BRKIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "CMTIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CH3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CH2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CH1IF,Capture/Compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH0IF,Capture/compare 0 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SWEVG,Software event generation register"
|
|
bitfld.long 0x00 7. "BRKG,Break event generation" "0,1"
|
|
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x00 5. "CMTG,Channel commutation event generation" "0,1"
|
|
bitfld.long 0x00 4. "CH3G,Channel 3's capture or compare event generation" "0,1"
|
|
bitfld.long 0x00 3. "CH2G,Channel 2's capture or compare event generation" "0,1"
|
|
bitfld.long 0x00 2. "CH1G,Channel 1's capture or compare event generation" "0,1"
|
|
bitfld.long 0x00 1. "CH0G,Channel 0's capture or compare event generation" "0,1"
|
|
bitfld.long 0x00 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Input,capture/compare mode register 0 (input mode)"
|
|
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHCTL1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x00 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x00 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHCTL1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "CH3CAPFLT,Channel 3 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "CH2CAPFLT,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH2CAPPSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH2MS,Capture/compare 2 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHCTL2,capture/compare enable register"
|
|
bitfld.long 0x00 13. "CH3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CH3EN,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CH2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 10. "CH2NEN,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x00 9. "CH2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CH2EN,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CH1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 6. "CH1NEN,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 5. "CH1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CH1EN,Capture/Compare 1 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH0NP,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CH0NEN,Capture/Compare 0 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CH0P,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CH0EN,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CREP,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CREP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0CV,capture/compare register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture/Compare 0 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH1CV,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture/Compare 1 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CH2CV,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH2VAL,Capture/Compare 2 value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH3CV,capture/compare register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH3VAL,Capture/Compare 3 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x00 15. "POEN,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "OAEN,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BRKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BRKEN,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "ROS,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "IOS,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "PROT,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTCFG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACFG,DMA configuration register"
|
|
bitfld.long 0x00 8.--12. "DMATC,DMA transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DMATA,DMA transfer access start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMATB,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA register for burst accesses"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG,Configuration register"
|
|
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x00 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER2"
|
|
base ad:0x40000400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CAM,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 7. "TI0S,TI0 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMC,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "DMAS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCFG,slave mode control register"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "SMC1,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETFC,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OCRC,OCREF clear source selection" "0,1"
|
|
bitfld.long 0x00 0.--2. "SMC,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CH3DEN,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CH2DEN,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CH1DEN,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CH0DEN,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CH3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CH2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CH1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH0IE,Capture/Compare 0 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTF,interrupt flag register"
|
|
bitfld.long 0x00 12. "CH3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CH2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CH1OF,Capture/compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CH0OF,Capture/Compare 0 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CH3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CH2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CH1IF,Capture/Compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CH0IF,Capture/compare 0 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SWEVG,event generation register"
|
|
bitfld.long 0x00 6. "TRGG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CH3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 3. "CH2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 2. "CH1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 1. "CH0G,Capture/compare 0 generation" "0,1"
|
|
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Output,capture/compare mode register 0 (output mode)"
|
|
bitfld.long 0x00 15. "CH1COMCEN,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "CH1COMCTL,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "CH1COMSEN,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "CH1COMFEN,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CH1MS,Capture/Compare 1 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "CH0COMCEN,Output compare 0 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "CH0COMCTL,Output compare 0 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH0COMSEN,Output compare 0 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "CH0COMFEN,Output compare 0 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Input,capture/compare mode register 0 (input mode)"
|
|
bitfld.long 0x00 12.--15. "CH1CAPFLT,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "CH1CAPPSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CH1MS,Capture/compare 1 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "CH0CAPFLT,Input capture 0 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH0CAPPSC,Input capture 0 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHCTL1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 15. "CH3COMCEN,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "CH3COMCTL,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "CH3COMSEN,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "CH3COMFEN,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CH3MS,Capture/Compare 3 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "CH2COMCEN,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "CH2COMCTL,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH2COMSEN,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "CH2COMFEN,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH2MS,Capture/Compare 2 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHCTL1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "CH3CAPFLT,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "CH3CAPPSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CH3MS,Capture/Compare 3 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "CH2CAPFLT,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH2CAPPSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH2MS,Capture/Compare 2 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHCTL2,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CH3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CH3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CH3EN,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CH2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CH2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CH2EN,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CH1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CH1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CH1EN,Capture/Compare 1 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CH0NP,Capture/Compare 0 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH0P,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CH0EN,Capture/Compare 0 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CARL,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0CV,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH1CV,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CH2CV,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH2VAL,High Capture/Compare value (TIM2 only)"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH3CV,capture/compare register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH3VAL,High Capture/Compare value (TIM2 only)"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACFG,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DMATC,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DMATA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMATB,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA register for burst accesses"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG,Configuration"
|
|
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER5"
|
|
base ad:0x40001000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 4.--6. "MMC,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTF,status register"
|
|
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SWEVG,event generation register"
|
|
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Low counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CARL,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIMER13"
|
|
base ad:0x40002000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 1"
|
|
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 1. "CH0IE,Capture/Compare 0 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTF,interrupt flag register"
|
|
bitfld.long 0x00 9. "CH0OF,Capture/Compare 0 overcapture flag" "0,1"
|
|
bitfld.long 0x00 1. "CH0IF,Capture/compare 0 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SWEVG,event generation register"
|
|
bitfld.long 0x00 1. "CH0G,Capture/compare 0 generation" "0,1"
|
|
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 4.--6. "CH0COMCTL,Output Compare 0 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH0COMSEN,Output Compare 0 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "CH0COMFEN,Output compare 0 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Input,capture/compare mode register (input mode)"
|
|
bitfld.long 0x00 4.--7. "CH0CAPFLT,Input capture 0 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH0CAPPSC,Input capture 0 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHCTL2,capture/compare enable register"
|
|
bitfld.long 0x00 3. "CH0NP,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CH0P,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CH0EN,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CARL,Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0CV,capture/compare register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture/Compare 1 value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IRMP,channel input remap register"
|
|
bitfld.long 0x00 0.--1. "CI0_RMP,Timer input 0 remap" "0,1,2,3"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG,configuration register"
|
|
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER14"
|
|
base ad:0x40014000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 10. "ISO1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 9. "ISO0N,Output Idle state 0" "0,1"
|
|
bitfld.long 0x00 8. "ISO0,Output Idle state 0" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMC,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "DMAS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUC,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCSE,Capture/compare preloaded control" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCFG,slave mode configuration register"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMC,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CH1DEN,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CH0DEN,Capture/Compare 0 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "CMTIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CH1IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CH0IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTF,interrupt flag register"
|
|
bitfld.long 0x00 10. "CH1OF,Capture/compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CH0OF,Capture/Compare 0 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BRKIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "CMTIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CH1IF,Capture/Compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CH0IF,Capture/compare 0 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SWEVG,event generation register"
|
|
bitfld.long 0x00 7. "BRKG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TRGG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "CMTG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 2. "CH1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 1. "CH0G,Capture/compare 0 generation" "0,1"
|
|
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 12.--14. "CH1COMCTL,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "CH1COMSEN,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "CH1COMFEN,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CH1MS,Capture/Compare 1 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "CH0COMCTL,Output Compare 0 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH0COMSEN,Output Compare 0 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "CH0COMFEN,Output Compare 0 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Input,capture/compare mode register 0 (input mode)"
|
|
bitfld.long 0x00 12.--15. "CH1CAPFLT,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "CH1CAPPSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CH1MS,Capture/Compare 1 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "CH0CAPFLT,Input capture 0 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH0CAPPSC,Input capture 0 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHCTL2,capture/compare enable register"
|
|
bitfld.long 0x00 7. "CH1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CH1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CH1EN,Capture/Compare 1 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CH0NP,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CH0NEN,Capture/Compare 0 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CH0P,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CH0EN,Capture/Compare 0 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CARL,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CREP,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CREP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0CV,capture/compare register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture/Compare 0 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH1CV,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CCHP,break and dead-time register"
|
|
bitfld.long 0x00 15. "POEN,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "OAEN,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BRKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BRKEN,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "ROS,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "IOS,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "PROT,complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTCFG,Dead-time generator configure"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACFG,DMA configuration register"
|
|
bitfld.long 0x00 8.--12. "DMATC,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DMATA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMATB,DMA transfer buffer register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA register for burst accesses"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG,configuration register"
|
|
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x00 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
repeat 2. (list 15. 16.) (list ad:0x40014400 ad:0x40014800)
|
|
tree "TIMER$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,control register 0"
|
|
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,control register 1"
|
|
bitfld.long 0x00 9. "ISO0N,Output Idle state 0" "0,1"
|
|
bitfld.long 0x00 8. "ISO0,Output Idle state 0" "0,1"
|
|
bitfld.long 0x00 3. "DMAS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUC,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCSE,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 9. "CH0DEN,Capture/Compare 0 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "CMTIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CH0IE,Capture/Compare 0 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTF,interrupt flag register"
|
|
bitfld.long 0x00 9. "CH0OF,Capture/Compare 0 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BRKIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "CMTIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CH0IF,Capture/compare 0 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SWEVG,event generation register"
|
|
bitfld.long 0x00 7. "BRKG,Break generation" "0,1"
|
|
bitfld.long 0x00 5. "CMTG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 1. "CH0G,Capture/compare 0 generation" "0,1"
|
|
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 4.--6. "CH0COMCTL,Output Compare 0 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CH0COMSEN,Output Compare 0 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "CH0COMFEN,Output Compare 0 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHCTL0_Input,capture/compare mode register 0 (input mode)"
|
|
bitfld.long 0x00 4.--7. "CH0CAPFLT,Input capture 0 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "CH0CAPPSC,Input capture 0 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CH0MS,Capture/Compare 0 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHCTL2,capture/compare enable register"
|
|
bitfld.long 0x00 3. "CH0NP,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CH0NEN,Capture/Compare 0 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CH0P,Capture/Compare 0 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CH0EN,Capture/Compare 0 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CARL,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CREP,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CREP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0CV,capture/compare register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture/Compare 0 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CCHP,break and dead-time register"
|
|
bitfld.long 0x00 15. "POEN,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "OAEN,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BRKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BRKEN,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "ROS,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "IOS,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "PROT,complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTCFG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACFG,DMA configuration register"
|
|
bitfld.long 0x00 8.--12. "DMATC,DMA transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DMATA,DMA transfer access start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMATB,DMA transfer buffer register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA register for burst accesses"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG,configuration register"
|
|
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x00 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "USART (Universal synchronous asynchronous receiver transmitter)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40013800 ad:0x40004400)
|
|
tree "USART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,Control register 0"
|
|
bitfld.long 0x00 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x00 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x00 21.--25. "DEA,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "DED,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "OVSMOD,Oversampling mode" "0,1"
|
|
bitfld.long 0x00 14. "AMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x00 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x00 12. "WL,Word length" "0,1"
|
|
bitfld.long 0x00 11. "WM,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x00 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x00 9. "PM,Parity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PERRIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "TBEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "RBNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x00 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x00 0. "UEN,USART enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ADDR,Address of the USART node"
|
|
bitfld.long 0x00 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x00 21.--22. "ABDM,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x00 20. "ABDEN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x00 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x00 18. "DINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x00 17. "TINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 16. "RINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x00 14. "LMEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "STB,STOP bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 11. "CKEN,Clock enable" "0,1"
|
|
bitfld.long 0x00 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x00 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x00 8. "CLEN,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "LBLEN,LIN break detection length" "0,1"
|
|
bitfld.long 0x00 4. "ADDM,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL2,Control register 2"
|
|
bitfld.long 0x00 22. "WUIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x00 20.--21. "WUM,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x00 17.--19. "SCRTNUM,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x00 12. "OVRD,Overrun Disable" "0,1"
|
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bitfld.long 0x00 11. "OSB,One sample bit method enable" "0,1"
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bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
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bitfld.long 0x00 9. "CTSEN,CTS enable" "0,1"
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bitfld.long 0x00 8. "RTSEN,RTS enable" "0,1"
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newline
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bitfld.long 0x00 7. "DENT,DMA enable transmitter" "0,1"
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bitfld.long 0x00 6. "DENR,DMA enable receiver" "0,1"
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bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
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bitfld.long 0x00 4. "NKEN,Smartcard NACK enable" "0,1"
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bitfld.long 0x00 3. "HDEN,Half-duplex selection" "0,1"
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bitfld.long 0x00 2. "IRLP,IrDA low-power" "0,1"
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bitfld.long 0x00 1. "IREN,IrDA mode enable" "0,1"
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bitfld.long 0x00 0. "ERRIE,Error interrupt enable" "0,1"
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group.long 0x0C++0x03
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line.long 0x00 "BAUD,Baud rate register"
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hexmask.long.word 0x00 4.--15. 1. "BRR_INT,integer of baud-rate divider"
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bitfld.long 0x00 0.--3. "BRR_FRA,integer of baud-rate divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "GP,Guard time and prescaler register"
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hexmask.long.byte 0x00 8.--15. 1. "GUAT,Guard time value"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
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group.long 0x14++0x03
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line.long 0x00 "RT,Receiver timeout register"
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hexmask.long.byte 0x00 24.--31. 1. "BL,Block Length"
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hexmask.long.tbyte 0x00 0.--23. 1. "RT,Receiver timeout value"
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wgroup.long 0x18++0x03
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line.long 0x00 "CMD,Request register"
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bitfld.long 0x00 4. "TXFCMD,Transmit data flush request" "0,1"
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bitfld.long 0x00 3. "RXFCMD,Receive data flush request" "0,1"
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bitfld.long 0x00 2. "MMCMD,Mute mode request" "0,1"
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bitfld.long 0x00 1. "SBKCMD,Send break request" "0,1"
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bitfld.long 0x00 0. "ABDCMD,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x03
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line.long 0x00 "STAT,Interrupt & status register"
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bitfld.long 0x00 22. "REA,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x00 21. "TEA,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x00 20. "WUF,Wakeup from Stop mode flag" "0,1"
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bitfld.long 0x00 19. "RWU,Receiver wakeup from Mute mode" "0,1"
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bitfld.long 0x00 18. "SBF,Send break flag" "0,1"
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bitfld.long 0x00 17. "AMF,character match flag" "0,1"
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bitfld.long 0x00 16. "BSY,Busy flag" "0,1"
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bitfld.long 0x00 15. "ABDF,Auto baud rate flag" "0,1"
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bitfld.long 0x00 14. "ABDE,Auto baud rate error" "0,1"
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bitfld.long 0x00 12. "EBF,End of block flag" "0,1"
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bitfld.long 0x00 11. "RTF,Receiver timeout" "0,1"
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newline
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bitfld.long 0x00 10. "CTS,CTS flag" "0,1"
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bitfld.long 0x00 9. "CTSF,CTS interrupt flag" "0,1"
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bitfld.long 0x00 8. "LBDF,LIN break detection flag" "0,1"
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bitfld.long 0x00 7. "TBE,Transmit data register empty" "0,1"
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bitfld.long 0x00 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x00 5. "RBNE,Read data register not empty" "0,1"
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bitfld.long 0x00 4. "IDLEF,Idle line detected" "0,1"
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bitfld.long 0x00 3. "ORERR,Overrun error" "0,1"
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bitfld.long 0x00 2. "NERR,Noise detected flag" "0,1"
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bitfld.long 0x00 1. "FERR,Framing error" "0,1"
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bitfld.long 0x00 0. "PERR,Parity error" "0,1"
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wgroup.long 0x20++0x03
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line.long 0x00 "INTC,Interrupt flag clear register"
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bitfld.long 0x00 20. "WUC,Wakeup from Stop mode clear flag" "0,1"
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bitfld.long 0x00 17. "AMC,Character match clear flag" "0,1"
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bitfld.long 0x00 12. "EBC,End of timeout clear flag" "0,1"
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bitfld.long 0x00 11. "RTC,Receiver timeout clear flag" "0,1"
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bitfld.long 0x00 9. "CTSC,CTS clear flag" "0,1"
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bitfld.long 0x00 8. "LBDC,LIN break detection clear flag" "0,1"
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bitfld.long 0x00 6. "TCC,Transmission complete clear flag" "0,1"
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bitfld.long 0x00 4. "IDLEC,Idle line detected clear flag" "0,1"
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bitfld.long 0x00 3. "OREC,Overrun error clear flag" "0,1"
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bitfld.long 0x00 2. "NEC,Noise detected clear flag" "0,1"
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bitfld.long 0x00 1. "FEC,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x00 0. "PEC,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x03
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line.long 0x00 "RDATA,Receive data register"
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hexmask.long.word 0x00 0.--8. 1. "RDATA,Receive data value"
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group.long 0x28++0x03
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line.long 0x00 "TDATA,Transmit data register"
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hexmask.long.word 0x00 0.--8. 1. "TDATA,Transmit data value"
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group.long 0xC0++0x03
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line.long 0x00 "CHC,coherence control register"
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bitfld.long 0x00 8. "EPERR,Early parity error flag" "0,1"
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bitfld.long 0x00 0. "HCM,Hardware flow control coherence mode" "0,1"
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group.long 0xD0++0x03
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line.long 0x00 "RFCS,USART receive FIFO control and status register"
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bitfld.long 0x00 15. "RFFINT,Receive FIFO full interrupt flag" "0,1"
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rbitfld.long 0x00 12.--14. "RFCNT,Receive FIFO count number" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 11. "RFF,Receive FIFO full flag" "0,1"
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rbitfld.long 0x00 10. "RFE,Receive FIFO empty flag" "0,1"
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bitfld.long 0x00 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
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bitfld.long 0x00 8. "RFEN,Receive FIFO enable" "0,1"
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bitfld.long 0x00 0. "ELNACK,Early NKEN when smartcard mode is selected" "0,1"
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tree.end
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repeat.end
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tree.end
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tree "WWDGT (Window watchdog timer)"
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base ad:0x40002C00
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group.long 0x00++0x03
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line.long 0x00 "CTL,Control register"
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bitfld.long 0x00 7. "WDGTEN,Activation bit" "0,1"
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hexmask.long.byte 0x00 0.--6. 1. "CNT,7-bit counter"
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group.long 0x04++0x03
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line.long 0x00 "CFG,Configuration register"
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bitfld.long 0x00 9. "EWIE,Early wakeup interrupt" "0,1"
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bitfld.long 0x00 7.--8. "PSC,Prescaler" "0,1,2,3"
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hexmask.long.byte 0x00 0.--6. 1. "WIN,7-bit window value"
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group.long 0x08++0x03
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line.long 0x00 "STAT,Status register"
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bitfld.long 0x00 0. "EWIF,Early wakeup interrupt flag" "0,1"
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tree.end
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autoindent.off
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newline
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