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d411edd9b47003e0a9ef98de9aef8259ddea419d
Gen4_R-Car_Trace32/2_Trunk/perep9301.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: Cirrus Logic EP9301 On-Chip Peripherals
; @Props: Released
; @Author: PIO ETA
; @Date: 2005-02-24
; @Manufacturer: Cirrus Logic
; @Core: ARM920T
; @Copyright: (c) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perep9301.per 17494 2024-02-15 12:42:17Z kwisniewski $
config 16. 8.
width 16. 8.
base ad:0x00000000
tree "System Controller"
base 0x80930000
;begin include file EP9301/system.ph
;parameters:
rgroup 0x0000++0x03
line.long 0x00 "PwrSts,Power/State Control State Register"
hexmask.long.byte 0x00 24.--31. 1. " CHIPMAN ,Chip Manufacturer"
hexmask.long.byte 0x00 16.--23. 1. " CHIPID ,Chip ID Bits"
textline " "
bitfld.long 0x00 15. " WDTFLG ,Watchdog Timer Flag" "Cleared,Reset"
bitfld.long 0x00 13. " CLDFLG ,Clod Start Flag" "Cleared,Power-on-Reset"
textline " "
bitfld.long 0x00 12. " TEST_RESET ,Test Reset Flag" "Not activated,Activated"
bitfld.long 0x00 11. " RSTFLG ,Reset Flag" "Cleared,Reset pressed"
textline " "
bitfld.long 0x00 10. " SW_RESET ,Software Reset Flag" "Not activated,Activated"
bitfld.long 0x00 9. " PLL2_LOCK_REG ,Registered PLL1 Clock" "Cleared,Set"
textline " "
bitfld.long 0x00 8. " PLL2_LOCK ,PLL2 Lock" "Not locked,Locked"
bitfld.long 0x00 7. " PLL1_LOCK_REG ,Registered PLL1 Clock" "Cleared,Set"
textline " "
bitfld.long 0x00 6. " PLL1_LOCK ,PLL1 Lock" "Not locked,Locked"
hexmask.long.byte 0x00 0.--5. 1. " RTCDIV ,RTC Divider"
group 0x0004++0x03
line.long 0x00 "PwrCnt,Clock/Debug Control Status Register"
bitfld.long 0x00 31. " FIR_EN ,Gate FIRCLK to IrDA" "Off,On"
bitfld.long 0x00 29. " UARTBAUD ,UART Baud Rate" "Divided by 2,Full speed"
textline " "
bitfld.long 0x00 28. " USH_EN ,Gate HCLK to the USB Host Block" "Off,On"
bitfld.long 0x00 27. " DMAM2MCH1 ,DMA Controller Channel M1 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " DMAM2MCH0 ,DMA Controller Channel M0 Enable" "Disabled,Enabled"
bitfld.long 0x00 25. " DMAM2PCH8 ,DMA Controller Channel P8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24. " DMAM2PCH9 ,DMA Controller Channel P9 Enable" "Disabled,Enabled"
bitfld.long 0x00 23. " DMAM2PCH6 ,DMA Controller Channel P6 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " DMAM2PCH7 ,DMA Controller Channel P7 Enable" "Disabled,Enabled"
bitfld.long 0x00 21. " DMAM2PCH4 ,DMA Controller Channel P4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 20. " DMAM2PCH5 ,DMA Controller Channel P5 Enable" "Disabled,Enabled"
bitfld.long 0x00 19. " DMAM2PCH2 ,DMA Controller Channel P2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " DMAM2PCH3 ,DMA Controller Channel P3 Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " DMAM2PCH0 ,DMA Controller Channel P0 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " DMAM2PCH1 ,DMA Controller Channel P1 Enable" "Disabled,Enabled"
rgroup 0x0008++0x03
line.long 0x00 "Halt,Halt Mode when Reading"
rgroup 0x000C++0x03
line.long 0x00 "Standby,Standby Mode when Readnig"
wgroup 0x0018++0x03
line.long 0x00 "TEOI,When Write Clearing Tick Interrupt"
wgroup 0x001C++0x03
line.long 0x00 "STFClr,Clear CLDFLG RSTFLG WDTFLG when Write"
group 0x0020++7
line.long 0x00 "ClkSet1,Clock Speed Control 1 Register"
bitfld.long 0x00 25.--27. " FCLKDIV ,Divider Ratio Between VOC and Processor Clock" "1,2,4,8,16,Reserved..."
bitfld.long 0x00 24. " SMCROM ,Gate off HCLK to Static Memory Controller" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " nBYP ,Processor Clock Dividers" "External clock,PLL Clock"
bitfld.long 0x00 20.--22. " HCLKDIV ,Divider Ratio Between VCO and HCLK" "1,2,4,5,6,8,16,32,?..."
textline " "
bitfld.long 0x00 18.--19. " PLCKDIV ,Ratio Divider Between HCLK AHB and APB Clock" "1,2,4,8"
bitfld.long 0x00 16.--17. " PLL1_PS ,VCO Clock in PLL1 Divider" "1,2,4,8"
textline " "
hexmask.long.byte 0x00 11.--15. 1. " PLL1X2FBD1 ,Second Feedback Divider for PLL1"
hexmask.long.byte 0x00 5.--10. 1. " PLL1X2FBD2 ,First Feedback Divider for PLL1"
textline " "
hexmask.long.byte 0x00 0.--4. 1. " PLL1X2IPD ,Input Divider for PLL1"
line.long 0x04 "ClkSet2,Clock Speed Control 2 Register"
hexmask.long.byte 0x04 28.--31. 1. " USBDIV ,Divide ratio for USB Clock"
bitfld.long 0x04 19. " nBYP2 ,Clock Source for Processor Clock Dividers" "External clock,PLL2"
textline " "
bitfld.long 0x04 18. " PLL2_EN ,PLL2 Enable" "Disabled,Enabled"
bitfld.long 0x04 16.--17. " PLL2_PS ,Final Divide of VCO Clock" "1,2,4,8"
textline " "
hexmask.long.byte 0x04 11.--15. 1. " PLL2X2FBD1 ,Second Feedback Divider for PLL2"
hexmask.long.byte 0x04 5.--10. 1. " PLL2X2FBD2 ,First Feedback Divider for PLL2"
textline " "
hexmask.long.byte 0x04 0.--4. 1. " PLL2X2IPD ,Input Divider for PLL2"
group 0x0040++7
line.long 0x00 "ScratchReg0,Scratch Register 0"
hexfld.long 0x00 " Value ,Scratch Register 0 Value"
line.long 0x04 "ScratchReg1,Scratch Register 1"
hexfld.long 0x04 " Value ,Scratch Register 1 Value"
group 0x0050++7
line.long 0x00 "APBWait,APB Wait Register"
bitfld.long 0x00 0. " NO_WRITE_WAIT ,Wait State Adding for AHB/APB" "No,Yes"
line.long 0x04 "BusMstrArb,Bus Master Arbitration Register"
bitfld.long 0x04 9. " MACENFIQ ,MAC form AHB Requests Ignore if FIQ Active" "Allowed,Ignored"
bitfld.long 0x04 8. " MACENIRQ ,MAC form AHB Requests Ignore" "Allowed,Ignored"
textline " "
bitfld.long 0x04 7. " USHENFIQ ,USB form AHB Requests Ignore if FIQ Active" "Allowed,Ignored"
bitfld.long 0x04 6. " USHENIRQ ,USB form AHB Requests Ignore" "Allowed,Ignored"
textline " "
bitfld.long 0x04 5. " DMAENFIQ ,DMA form AHB Requests Ignore if FIQ Active" "Allowed,Ignored"
bitfld.long 0x04 4. " DMAENIRQ ,DMA form AHB Requests Ignore" "Allowed,Ignored"
textline " "
bitfld.long 0x04 3. " PRICORE ,Core Priority Select" "Normal,Highest"
bitfld.long 0x04 0.--1. " PRI_ORD ,Priority of AHB Arbiter" "PRIOR00,PRIOR01,PRIOR10,PRIOR11"
wgroup 0x0058++0x03
line.long 0x00 "BootModeClr,Boot Mode Clear Register"
group 0x0080++0x03
line.long 0x00 "DeviceCfg,Device Configuration Register"
bitfld.long 0x00 31. " SWRST ,Software Reset" "Low,High"
bitfld.long 0x00 30. " D1onG ,External DMA1 Hardware Handshake Signals Mapped to EGPIO Pins" "Not supported,Mapped"
textline " "
bitfld.long 0x00 29. " D0onG ,External DMA0 Hardware Handshake Signals Mapped to EGPIO Pins" "Not supported,Mapped"
bitfld.long 0x00 28. " IonU2 ,IrDA on UART2" "UART,IrDA"
textline " "
bitfld.long 0x00 25. " MonG ,Modem on GPIO" "Not used,Used"
bitfld.long 0x00 20. " U2EN ,UART2 Enable" "Clock active,Clock off"
textline " "
bitfld.long 0x00 18. " U1EN ,UART1 Enable" "Clock active,Clock off"
bitfld.long 0x00 17. " TIN ,Touchscreen Controller Inactive" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " HC1IN ,HDLC1 Clock In" "Input,Output"
bitfld.long 0x00 12. " HC1EN ,HDLC1 Clock Enable" "Not used,Enabled"
textline " "
bitfld.long 0x00 7. " I2SonSSP ,I2S on SSP Pins" "Disabled,Enabled"
bitfld.long 0x00 6. " I2SonAC97 ,I2S on AC97 Pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " ADCPD ,ADC Power Down" "Power down,Active"
bitfld.long 0x00 0. " SHena ,Standby/Halt Enable" "Disabled,Enabled"
group 0x0088++7
line.long 0x00 "MIRClkDiv,MIR Clock Divider Register"
bitfld.long 0x00 15. " MENA ,Enable MIR_CLK Divider" "Disabled,Enabled"
bitfld.long 0x00 14. " ESEL ,External Clock Source Select" "External XTAL1,Internal PLLs"
textline " "
bitfld.long 0x00 13. " PSEL ,PLL Source Select" "PLL1,PLL2"
bitfld.long 0x00 8.--9. " PDIV ,Pre-Divider Value" "Disabled,2,2.5,3"
textline " "
hexmask.long.byte 0x00 0.--6. 1. " MDIV ,MIR_CLK Divider Value"
line.long 0x04 "I2SClkDiv,I2S Audio Clock Divider Register"
bitfld.long 0x04 31. " SENA ,Enable Audio Clock Generation" "Disabled,Enabled"
bitfld.long 0x04 30. " SLAVE ,I2S Slave" "Off,On"
textline " "
bitfld.long 0x04 29. " ORIDE ,Override I2S Master Configuration" "Use,Override"
bitfld.long 0x04 20. " DROP ,Drop SCLK Clocks" "No drop,Drop"
textline " "
bitfld.long 0x04 19. " SPOL ,SCLK Polarity" "Rising edge,Falling edge"
bitfld.long 0x04 17.--18. " LRDIV ,LRCLK Divide Select" "SCLK/32,SCLK/64,SCLK/128,Reserved"
textline " "
bitfld.long 0x04 16. " SDIV ,SCLK Dicide Select" "MCLK/2,MCLK/4"
bitfld.long 0x04 15. " MENA ,Enable Master Clock Generation" "Disabled,Enabled"
textline " "
bitfld.long 0x04 14. " ESEL ,External Clock Source Select" "External XTAL1,Internal PLLs"
bitfld.long 0x04 13. " PSEL ,PLL Source Select" "PLL1,PLL2"
textline " "
bitfld.long 0x04 8.--9. " PDIV ,Pre-Divider Value" "Disabled,2,2.5,3"
hexmask.long.byte 0x04 0.--6. 1. " MDIV ,MCLK Divider Value"
group 0x0090++0x03
line.long 0x00 "ADCClkDiv,ADC Clock Divider"
bitfld.long 0x00 31. " ADCEN ,ADC Clock Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " ADIV ,ADC Clock Divider Value" "Divide by 16,Divide by 4"
group 0x0094++0x03
line.long 0x00 "ChipID,Chip ID Register"
hexmask.long.byte 0x00 28.--31. 1. " REV ,Revision"
hexmask.long.word 0x00 0.--15. 1. " ID ,Chip ID"
group 0x0098++0x03
line.long 0x00 "SysCfg,System Configuration Register"
hexmask.long.byte 0x00 28.--31. 1. " REV ,Revision"
bitfld.long 0x00 8. " SBOOT ,Serial Boot Flag" "Normal,Serial"
textline " "
bitfld.long 0x00 7. " LCSn7 ,Bus Width for Boot Code" "Low,High"
bitfld.long 0x00 6. " LCSn6 ,Bus Width for Boot Code" "Low,High"
textline " "
bitfld.long 0x00 5. " LASD0 ,Boot Device Type" "Synchronous,Asynchronous"
bitfld.long 0x00 4. " LEEDA ,Latched Version of EEDAT Pin" "Low,High"
textline " "
bitfld.long 0x00 3. " LEECLK ,External/Internal Boot" "External,Internal"
bitfld.long 0x00 1. " LCSn2 ,Watchdog Startup Action" "Watchdog disabled,Watchdog active"
textline " "
bitfld.long 0x00 0. " LCSn1 ,Watchdog Startup Action" "Reset duration disabled,Reset duration active"
group 0x00C0++0x03
line.long 0x00 "SysSWLock,Software Lock Register"
hexmask.long.byte 0x00 0.--7. 1. " LOCK ,Lock Code Value"
;end include file EP9301/system.ph
tree.end
tree "Vector Interrupt Controller"
base 0x80000000
;begin include file EP9301/Interrupt.ph
;parameters:
width 18. 8.
tree "Vector Interrupt Controller 1(VIC1)"
base 0x800B0000
;begin include file EP9301/Interrupt/Global-VIC1.ph
;parameters: 1
rgroup 0x0000++0x0B
line.long 0x00 "VIC1IRQStatus,IRQ Status Register"
bitfld.long 0x00 26. " IRQStatus26 ,IRQ Interrupt Status Bit 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. " IRQStatus25 ,IRQ Interrupt Status Bit 25" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 24. " IRQStatus24 ,IRQ Interrupt Status Bit 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. " IRQStatus23 ,IRQ Interrupt Status Bit 23" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 22. " IRQStatus22 ,IRQ Interrupt Status Bit 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. " IRQStatus21 ,IRQ Interrupt Status Bit 21" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 20. " IRQStatus20 ,IRQ Interrupt Status Bit 20" "No interrupt,Interrupt"
bitfld.long 0x00 18. " IRQStatus18 ,IRQ Interrupt Status Bit 18" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 17. " IRQStatus17 ,IRQ Interrupt Status Bit 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. " IRQStatus16 ,IRQ Interrupt Status Bit 16" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " IRQStatus15 ,IRQ Interrupt Status Bit 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. " IRQStatus14 ,IRQ Interrupt Status Bit 14" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 13. " IRQStatus13 ,IRQ Interrupt Status Bit 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. " IRQStatus12 ,IRQ Interrupt Status Bit 12" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " IRQStatus11 ,IRQ Interrupt Status Bit 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. " IRQStatus10 ,IRQ Interrupt Status Bit 10" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " IRQStatus9 ,IRQ Interrupt Status Bit 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. " IRQStatus8 ,IRQ Interrupt Status Bit 8" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " IRQStatus7 ,IRQ Interrupt Status Bit 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. " IRQStatus6 ,IRQ Interrupt Status Bit 6" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " IRQStatus5 ,IRQ Interrupt Status Bit 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. " IRQStatus4 ,IRQ Interrupt Status Bit 4" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " IRQStatus3 ,IRQ Interrupt Status Bit 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. " IRQStatus2 ,IRQ Interrupt Status Bit 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " IRQStatus1 ,IRQ Interrupt Status Bit 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. " IRQStatus0 ,IRQ Interrupt Status Bit 0" "No interrupt,Interrupt"
line.long 0x04 "VIC1FIQStatus,FIQ Status Register"
bitfld.long 0x04 26. " FIQStatus26 ,FIQ Interrupt Status Bit 26" "No interrupt,Interrupt"
bitfld.long 0x04 25. " FIQStatus25 ,FIQ Interrupt Status Bit 25" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 24. " FIQStatus24 ,FIQ Interrupt Status Bit 24" "No interrupt,Interrupt"
bitfld.long 0x04 23. " FIQStatus23 ,FIQ Interrupt Status Bit 23" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 22. " FIQStatus22 ,FIQ Interrupt Status Bit 22" "No interrupt,Interrupt"
bitfld.long 0x04 21. " FIQStatus21 ,FIQ Interrupt Status Bit 21" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 20. " FIQStatus20 ,FIQ Interrupt Status Bit 20" "No interrupt,Interrupt"
bitfld.long 0x04 18. " FIQStatus18 ,FIQ Interrupt Status Bit 18" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 17. " FIQStatus17 ,FIQ Interrupt Status Bit 17" "No interrupt,Interrupt"
bitfld.long 0x04 16. " FIQStatus16 ,FIQ Interrupt Status Bit 16" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 15. " FIQStatus15 ,FIQ Interrupt Status Bit 15" "No interrupt,Interrupt"
bitfld.long 0x04 14. " FIQStatus14 ,FIQ Interrupt Status Bit 14" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 13. " FIQStatus13 ,FIQ Interrupt Status Bit 13" "No interrupt,Interrupt"
bitfld.long 0x04 12. " FIQStatus12 ,FIQ Interrupt Status Bit 12" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 11. " FIQStatus11 ,FIQ Interrupt Status Bit 11" "No interrupt,Interrupt"
bitfld.long 0x04 10. " FIQStatus10 ,FIQ Interrupt Status Bit 10" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 9. " FIQStatus9 ,FIQ Interrupt Status Bit 9" "No interrupt,Interrupt"
bitfld.long 0x04 8. " FIQStatus8 ,FIQ Interrupt Status Bit 8" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " FIQStatus7 ,FIQ Interrupt Status Bit 7" "No interrupt,Interrupt"
bitfld.long 0x04 6. " FIQStatus6 ,FIQ Interrupt Status Bit 6" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 5. " FIQStatus5 ,FIQ Interrupt Status Bit 5" "No interrupt,Interrupt"
bitfld.long 0x04 4. " FIQStatus4 ,FIQ Interrupt Status Bit 4" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " FIQStatus3 ,FIQ Interrupt Status Bit 3" "No interrupt,Interrupt"
bitfld.long 0x04 2. " FIQStatus2 ,FIQ Interrupt Status Bit 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 1. " FIQStatus1 ,FIQ Interrupt Status Bit 1" "No interrupt,Interrupt"
bitfld.long 0x04 0. " FIQStatus0 ,FIQ Interrupt Status Bit 0" "No interrupt,Interrupt"
line.long 0x08 "VIC1RawIntr,Raw Interrupt Status Register"
bitfld.long 0x08 26. " RawIntr26 ,Interrupt Status Bit 26 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 25. " RawIntr25 ,Interrupt Status Bit 25 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 24. " RawIntr24 ,Interrupt Status Bit 24 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 23. " RawIntr23 ,Interrupt Status Bit 23 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 22. " RawIntr22 ,Interrupt Status Bit 22 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 21. " RawIntr21 ,Interrupt Status Bit 21 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 20. " RawIntr20 ,Interrupt Status Bit 20 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 18. " RawIntr18 ,Interrupt Status Bit 18 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 17. " RawIntr17 ,Interrupt Status Bit 17 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 16. " RawIntr16 ,Interrupt Status Bit 16 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 15. " RawIntr15 ,Interrupt Status Bit 15 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 14. " RawIntr14 ,Interrupt Status Bit 14 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 13. " RawIntr13 ,Interrupt Status Bit 13 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 12. " RawIntr12 ,Interrupt Status Bit 12 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 11. " RawIntr11 ,Interrupt Status Bit 11 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 10. " RawIntr10 ,Interrupt Status Bit 10 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 9. " RawIntr9 ,Interrupt Status Bit 9 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 8. " RawIntr8 ,Interrupt Status Bit 8 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 7. " RawIntr7 ,Interrupt Status Bit 7 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 6. " RawIntr6 ,Interrupt Status Bit 6 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 5. " RawIntr5 ,Interrupt Status Bit 5 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 4. " RawIntr4 ,Interrupt Status Bit 4 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 3. " RawIntr3 ,Interrupt Status Bit 3 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 2. " RawIntr2 ,Interrupt Status Bit 2 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 1. " RawIntr1 ,Interrupt Status Bit 1 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 0. " RawIntr0 ,Interrupt Status Bit 0 without Masking" "No interrupt,Interrupt"
group 0x000C++7
line.long 0x00 "VIC1IntSelect,Interrupt Select Register"
bitfld.long 0x00 26. " IntSelect26 ,Interrupt Type Select Bit 26" "FIQ,IRQ"
bitfld.long 0x00 25. " IntSelect25 ,Interrupt Type Select Bit 25" "FIQ,IRQ"
bitfld.long 0x00 24. " IntSelect24 ,Interrupt Type Select Bit 24" "FIQ,IRQ"
textline " "
bitfld.long 0x00 23. " IntSelect23 ,Interrupt Type Select Bit 23" "FIQ,IRQ"
bitfld.long 0x00 22. " IntSelect22 ,Interrupt Type Select Bit 22" "FIQ,IRQ"
bitfld.long 0x00 21. " IntSelect21 ,Interrupt Type Select Bit 21" "FIQ,IRQ"
textline " "
bitfld.long 0x00 20. " IntSelect20 ,Interrupt Type Select Bit 20" "FIQ,IRQ"
bitfld.long 0x00 18. " IntSelect18 ,Interrupt Type Select Bit 18" "FIQ,IRQ"
bitfld.long 0x00 17. " IntSelect17 ,Interrupt Type Select Bit 17" "FIQ,IRQ"
textline " "
bitfld.long 0x00 16. " IntSelect16 ,Interrupt Type Select Bit 16" "FIQ,IRQ"
bitfld.long 0x00 15. " IntSelect15 ,Interrupt Type Select Bit 15" "FIQ,IRQ"
bitfld.long 0x00 14. " IntSelect14 ,Interrupt Type Select Bit 14" "FIQ,IRQ"
textline " "
bitfld.long 0x00 13. " IntSelect13 ,Interrupt Type Select Bit 13" "FIQ,IRQ"
bitfld.long 0x00 12. " IntSelect12 ,Interrupt Type Select Bit 12" "FIQ,IRQ"
bitfld.long 0x00 11. " IntSelect11 ,Interrupt Type Select Bit 11" "FIQ,IRQ"
textline " "
bitfld.long 0x00 10. " IntSelect10 ,Interrupt Type Select Bit 10" "FIQ,IRQ"
bitfld.long 0x00 9. " IntSelect9 ,Interrupt Type Select Bit 9" "FIQ,IRQ"
bitfld.long 0x00 8. " IntSelect8 ,Interrupt Type Select Bit 8" "FIQ,IRQ"
textline " "
bitfld.long 0x00 7. " IntSelect7 ,Interrupt Type Select Bit 7" "FIQ,IRQ"
bitfld.long 0x00 6. " IntSelect6 ,Interrupt Type Select Bit 6" "FIQ,IRQ"
bitfld.long 0x00 5. " IntSelect5 ,Interrupt Type Select Bit 5" "FIQ,IRQ"
textline " "
bitfld.long 0x00 4. " IntSelect4 ,Interrupt Type Select Bit 4" "FIQ,IRQ"
bitfld.long 0x00 3. " IntSelect3 ,Interrupt Type Select Bit 3" "FIQ,IRQ"
bitfld.long 0x00 2. " IntSelect2 ,Interrupt Type Select Bit 2" "FIQ,IRQ"
textline " "
bitfld.long 0x00 1. " IntSelect1 ,Interrupt Type Select Bit 1" "FIQ,IRQ"
bitfld.long 0x00 0. " IntSelect0 ,Interrupt Type Select Bit 0" "FIQ,IRQ"
line.long 0x04 "VIC1IntEnable,Interrupt Enable Register"
bitfld.long 0x04 26. " IntEnable26 ,Interrupt Enable Bit 26" "Disabled,Enabled"
bitfld.long 0x04 25. " IntEnable25 ,Interrupt Enable Bit 25" "Disabled,Enabled"
bitfld.long 0x04 24. " IntEnable24 ,Interrupt Enable Bit 24" "Disabled,Enabled"
textline " "
bitfld.long 0x04 23. " IntEnable23 ,Interrupt Enable Bit 23" "Disabled,Enabled"
bitfld.long 0x04 22. " IntEnable22 ,Interrupt Enable Bit 22" "Disabled,Enabled"
bitfld.long 0x04 21. " IntEnable21 ,Interrupt Enable Bit 21" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " IntEnable20 ,Interrupt Enable Bit 20" "Disabled,Enabled"
bitfld.long 0x04 18. " IntEnable18 ,Interrupt Enable Bit 18" "Disabled,Enabled"
bitfld.long 0x04 17. " IntEnable17 ,Interrupt Enable Bit 17" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " IntEnable16 ,Interrupt Enable Bit 16" "Disabled,Enabled"
bitfld.long 0x04 15. " IntEnable15 ,Interrupt Enable Bit 15" "Disabled,Enabled"
bitfld.long 0x04 14. " IntEnable14 ,Interrupt Enable Bit 14" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " IntEnable13 ,Interrupt Enable Bit 13" "Disabled,Enabled"
bitfld.long 0x04 12. " IntEnable12 ,Interrupt Enable Bit 12" "Disabled,Enabled"
bitfld.long 0x04 11. " IntEnable11 ,Interrupt Enable Bit 11" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " IntEnable10 ,Interrupt Enable Bit 10" "Disabled,Enabled"
bitfld.long 0x04 9. " IntEnable9 ,Interrupt Enable Bit 9" "Disabled,Enabled"
bitfld.long 0x04 8. " IntEnable8 ,Interrupt Enable Bit 8" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " IntEnable7 ,Interrupt Enable Bit 7" "Disabled,Enabled"
bitfld.long 0x04 6. " IntEnable6 ,Interrupt Enable Bit 6" "Disabled,Enabled"
bitfld.long 0x04 5. " IntEnable5 ,Interrupt Enable Bit 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " IntEnable4 ,Interrupt Enable Bit 4" "Disabled,Enabled"
bitfld.long 0x04 3. " IntEnable3 ,Interrupt Enable Bit 3" "Disabled,Enabled"
bitfld.long 0x04 2. " IntEnable2 ,Interrupt Enable Bit 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " IntEnable1 ,Interrupt Enable Bit 1" "Disabled,Enabled"
bitfld.long 0x04 0. " IntEnable0 ,Interrupt Enable Bit 0" "Disabled,Enabled"
wgroup 0x0014++0x03
line.long 0x00 "VIC1IntEnClear,Interrupt Enable Clear Register"
bitfld.long 0x00 26. " IntEnableClr26 ,Interrupt Enable Clear Bit 26" "No effect,Clear"
bitfld.long 0x00 25. " IntEnableClr25 ,Interrupt Enable Clear Bit 25" "No effect,Clear"
textline " "
bitfld.long 0x00 24. " IntEnableClr24 ,Interrupt Enable Clear Bit 24" "No effect,Clear"
bitfld.long 0x00 23. " IntEnableClr23 ,Interrupt Enable Clear Bit 23" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " IntEnableClr22 ,Interrupt Enable Clear Bit 22" "No effect,Clear"
bitfld.long 0x00 21. " IntEnableClr21 ,Interrupt Enable Clear Bit 21" "No effect,Clear"
textline " "
bitfld.long 0x00 20. " IntEnableClr20 ,Interrupt Enable Clear Bit 20" "No effect,Clear"
bitfld.long 0x00 18. " IntEnableClr18 ,Interrupt Enable Clear Bit 18" "No effect,Clear"
textline " "
bitfld.long 0x00 17. " IntEnableClr17 ,Interrupt Enable Clear Bit 17" "No effect,Clear"
bitfld.long 0x00 16. " IntEnableClr16 ,Interrupt Enable Clear Bit 16" "No effect,Clear"
textline " "
bitfld.long 0x00 15. " IntEnableClr15 ,Interrupt Enable Clear Bit 15" "No effect,Clear"
bitfld.long 0x00 14. " IntEnableClr14 ,Interrupt Enable Clear Bit 14" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " IntEnableClr13 ,Interrupt Enable Clear Bit 13" "No effect,Clear"
bitfld.long 0x00 12. " IntEnableClr12 ,Interrupt Enable Clear Bit 12" "No effect,Clear"
textline " "
bitfld.long 0x00 11. " IntEnableClr11 ,Interrupt Enable Clear Bit 11" "No effect,Clear"
bitfld.long 0x00 10. " IntEnableClr10 ,Interrupt Enable Clear Bit 10" "No effect,Clear"
textline " "
bitfld.long 0x00 9. " IntEnableClr9 ,Interrupt Enable Clear Bit 9" "No effect,Clear"
bitfld.long 0x00 8. " IntEnableClr8 ,Interrupt Enable Clear Bit 8" "No effect,Clear"
textline " "
bitfld.long 0x00 7. " IntEnableClr7 ,Interrupt Enable Clear Bit 7" "No effect,Clear"
bitfld.long 0x00 6. " IntEnableClr6 ,Interrupt Enable Clear Bit 6" "No effect,Clear"
textline " "
bitfld.long 0x00 5. " IntEnableClr5 ,Interrupt Enable Clear Bit 5" "No effect,Clear"
bitfld.long 0x00 4. " IntEnableClr4 ,Interrupt Enable Clear Bit 4" "No effect,Clear"
textline " "
bitfld.long 0x00 3. " IntEnableClr3 ,Interrupt Enable Clear Bit 3" "No effect,Clear"
bitfld.long 0x00 2. " IntEnableClr2 ,Interrupt Enable Clear Bit 2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " IntEnableClr1 ,Interrupt Enable Clear Bit 1" "No effect,Clear"
bitfld.long 0x00 0. " IntEnableClr0 ,Interrupt Enable Clear Bit 0" "No effect,Clear"
group 0x0018++0x03
line.long 0x00 "VIC1SoftInt,Software Interrupt Register"
bitfld.long 0x00 31. " SoftInt31 ,Software Interrupt Bit 31" "No effect,Generated"
bitfld.long 0x00 30. " SoftInt30 ,Software Interrupt Bit 30" "No effect,Generated"
textline " "
bitfld.long 0x00 29. " SoftInt29 ,Software Interrupt Bit 29" "No effect,Generated"
bitfld.long 0x00 28. " SoftInt28 ,Software Interrupt Bit 28" "No effect,Generated"
textline " "
bitfld.long 0x00 27. " SoftInt27 ,Software Interrupt Bit 27" "No effect,Generated"
bitfld.long 0x00 26. " SoftInt26 ,Software Interrupt Bit 26" "No effect,Generated"
textline " "
bitfld.long 0x00 25. " SoftInt25 ,Software Interrupt Bit 25" "No effect,Generated"
bitfld.long 0x00 24. " SoftInt24 ,Software Interrupt Bit 24" "No effect,Generated"
textline " "
bitfld.long 0x00 23. " SoftInt23 ,Software Interrupt Bit 23" "No effect,Generated"
bitfld.long 0x00 22. " SoftInt22 ,Software Interrupt Bit 22" "No effect,Generated"
textline " "
bitfld.long 0x00 21. " SoftInt21 ,Software Interrupt Bit 21" "No effect,Generated"
bitfld.long 0x00 20. " SoftInt20 ,Software Interrupt Bit 20" "No effect,Generated"
textline " "
bitfld.long 0x00 19. " SoftInt19 ,Software Interrupt Bit 19" "No effect,Generated"
bitfld.long 0x00 18. " SoftInt18 ,Software Interrupt Bit 18" "No effect,Generated"
textline " "
bitfld.long 0x00 17. " SoftInt17 ,Software Interrupt Bit 17" "No effect,Generated"
bitfld.long 0x00 16. " SoftInt16 ,Software Interrupt Bit 16" "No effect,Generated"
textline " "
bitfld.long 0x00 15. " SoftInt15 ,Software Interrupt Bit 15" "No effect,Generated"
bitfld.long 0x00 14. " SoftInt14 ,Software Interrupt Bit 14" "No effect,Generated"
textline " "
bitfld.long 0x00 13. " SoftInt13 ,Software Interrupt Bit 13" "No effect,Generated"
bitfld.long 0x00 12. " SoftInt12 ,Software Interrupt Bit 12" "No effect,Generated"
textline " "
bitfld.long 0x00 11. " SoftInt11 ,Software Interrupt Bit 11" "No effect,Generated"
bitfld.long 0x00 10. " SoftInt10 ,Software Interrupt Bit 10" "No effect,Generated"
textline " "
bitfld.long 0x00 9. " SoftInt9 ,Software Interrupt Bit 9" "No effect,Generated"
bitfld.long 0x00 8. " SoftInt8 ,Software Interrupt Bit 8" "No effect,Generated"
textline " "
bitfld.long 0x00 7. " SoftInt7 ,Software Interrupt Bit 7" "No effect,Generated"
bitfld.long 0x00 6. " SoftInt6 ,Software Interrupt Bit 6" "No effect,Generated"
textline " "
bitfld.long 0x00 5. " SoftInt5 ,Software Interrupt Bit 5" "No effect,Generated"
bitfld.long 0x00 4. " SoftInt4 ,Software Interrupt Bit 4" "No effect,Generated"
textline " "
bitfld.long 0x00 3. " SoftInt3 ,Software Interrupt Bit 3" "No effect,Generated"
bitfld.long 0x00 2. " SoftInt2 ,Software Interrupt Bit 2" "No effect,Generated"
textline " "
bitfld.long 0x00 1. " SoftInt1 ,Software Interrupt Bit 1" "No effect,Generated"
bitfld.long 0x00 0. " SoftInt0 ,Software Interrupt Bit 0" "No effect,Generated"
wgroup 0x001C++0x03
line.long 0x00 "VIC1SoftIntClear,Software Interrupt Clear Register"
bitfld.long 0x00 31. " SoftIntClr31 ,Software Interrupt Clear Bit 31" "No effect,Clear"
bitfld.long 0x00 30. " SoftIntClr30 ,Software Interrupt Clear Bit 30" "No effect,Clear"
textline " "
bitfld.long 0x00 29. " SoftIntClr29 ,Software Interrupt Clear Bit 29" "No effect,Clear"
bitfld.long 0x00 28. " SoftIntClr28 ,Software Interrupt Clear Bit 28" "No effect,Clear"
textline " "
bitfld.long 0x00 27. " SoftIntClr27 ,Software Interrupt Clear Bit 27" "No effect,Clear"
bitfld.long 0x00 26. " SoftIntClr26 ,Software Interrupt Clear Bit 26" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " SoftIntClr25 ,Software Interrupt Clear Bit 25" "No effect,Clear"
bitfld.long 0x00 24. " SoftIntClr24 ,Software Interrupt Clear Bit 24" "No effect,Clear"
textline " "
bitfld.long 0x00 23. " SoftIntClr23 ,Software Interrupt Clear Bit 23" "No effect,Clear"
bitfld.long 0x00 22. " SoftIntClr22 ,Software Interrupt Clear Bit 22" "No effect,Clear"
textline " "
bitfld.long 0x00 21. " SoftIntClr21 ,Software Interrupt Clear Bit 21" "No effect,Clear"
bitfld.long 0x00 20. " SoftIntClr20 ,Software Interrupt Clear Bit 20" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " SoftIntClr19 ,Software Interrupt Clear Bit 19" "No effect,Clear"
bitfld.long 0x00 18. " SoftIntClr18 ,Software Interrupt Clear Bit 18" "No effect,Clear"
textline " "
bitfld.long 0x00 17. " SoftIntClr17 ,Software Interrupt Clear Bit 17" "No effect,Clear"
bitfld.long 0x00 16. " SoftIntClr16 ,Software Interrupt Clear Bit 16" "No effect,Clear"
textline " "
bitfld.long 0x00 15. " SoftIntClr15 ,Software Interrupt Clear Bit 15" "No effect,Clear"
bitfld.long 0x00 14. " SoftIntClr14 ,Software Interrupt Clear Bit 14" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " SoftIntClr13 ,Software Interrupt Clear Bit 13" "No effect,Clear"
bitfld.long 0x00 12. " SoftIntClr12 ,Software Interrupt Clear Bit 12" "No effect,Clear"
textline " "
bitfld.long 0x00 11. " SoftIntClr11 ,Software Interrupt Clear Bit 11" "No effect,Clear"
bitfld.long 0x00 10. " SoftIntClr10 ,Software Interrupt Clear Bit 10" "No effect,Clear"
textline " "
bitfld.long 0x00 9. " SoftIntClr9 ,Software Interrupt Clear Bit 9" "No effect,Clear"
bitfld.long 0x00 8. " SoftIntClr8 ,Software Interrupt Clear Bit 8" "No effect,Clear"
textline " "
bitfld.long 0x00 7. " SoftIntClr7 ,Software Interrupt Clear Bit 7" "No effect,Clear"
bitfld.long 0x00 6. " SoftIntClr6 ,Software Interrupt Clear Bit 6" "No effect,Clear"
textline " "
bitfld.long 0x00 5. " SoftIntClr5 ,Software Interrupt Clear Bit 5" "No effect,Clear"
bitfld.long 0x00 4. " SoftIntClr4 ,Software Interrupt Clear Bit 4" "No effect,Clear"
textline " "
bitfld.long 0x00 3. " SoftIntClr3 ,Software Interrupt Clear Bit 3" "No effect,Clear"
bitfld.long 0x00 2. " SoftIntClr2 ,Software Interrupt Clear Bit 2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " SoftIntClr1 ,Software Interrupt Clear Bit 1" "No effect,Clear"
bitfld.long 0x00 0. " SoftIntClr0 ,Software Interrupt Clear Bit 0" "No effect,Clear"
group 0x0020++0x03
line.long 0x00 "VIC1Protection,Protection Enable Register"
bitfld.long 0x00 0. " Protection ,Protection Enable" "Disabled,Enabled"
group 0x0030++7
line.long 0x00 "VIC1VectAddr,Vector Address Register"
hexfld.long 0x00 " VectorAddr ,Vector Address Value"
line.long 0x04 "VIC1DefVectAddr,Default Vector Address Register"
hexfld.long 0x04 " DefVectorAddr ,Default Vector Address Value"
;end include file EP9301/Interrupt/Global-VIC1.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0100 0
group 0x0100++0x03
line.long 0x00 "VIC1VectAddr0,Vector Address 0 Register"
hexfld.long 0x00 " VectorAddr ,Vector 0 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0104 1
group 0x0104++0x03
line.long 0x00 "VIC1VectAddr1,Vector Address 1 Register"
hexfld.long 0x00 " VectorAddr ,Vector 1 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0108 2
group 0x0108++0x03
line.long 0x00 "VIC1VectAddr2,Vector Address 2 Register"
hexfld.long 0x00 " VectorAddr ,Vector 2 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x010C 3
group 0x010C++0x03
line.long 0x00 "VIC1VectAddr3,Vector Address 3 Register"
hexfld.long 0x00 " VectorAddr ,Vector 3 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0110 4
group 0x0110++0x03
line.long 0x00 "VIC1VectAddr4,Vector Address 4 Register"
hexfld.long 0x00 " VectorAddr ,Vector 4 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0114 5
group 0x0114++0x03
line.long 0x00 "VIC1VectAddr5,Vector Address 5 Register"
hexfld.long 0x00 " VectorAddr ,Vector 5 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0118 6
group 0x0118++0x03
line.long 0x00 "VIC1VectAddr6,Vector Address 6 Register"
hexfld.long 0x00 " VectorAddr ,Vector 6 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x011C 7
group 0x011C++0x03
line.long 0x00 "VIC1VectAddr7,Vector Address 7 Register"
hexfld.long 0x00 " VectorAddr ,Vector 7 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0120 8
group 0x0120++0x03
line.long 0x00 "VIC1VectAddr8,Vector Address 8 Register"
hexfld.long 0x00 " VectorAddr ,Vector 8 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0124 9
group 0x0124++0x03
line.long 0x00 "VIC1VectAddr9,Vector Address 9 Register"
hexfld.long 0x00 " VectorAddr ,Vector 9 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0128 10
group 0x0128++0x03
line.long 0x00 "VIC1VectAddr10,Vector Address 10 Register"
hexfld.long 0x00 " VectorAddr ,Vector 10 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x012C 11
group 0x012C++0x03
line.long 0x00 "VIC1VectAddr11,Vector Address 11 Register"
hexfld.long 0x00 " VectorAddr ,Vector 11 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0130 12
group 0x0130++0x03
line.long 0x00 "VIC1VectAddr12,Vector Address 12 Register"
hexfld.long 0x00 " VectorAddr ,Vector 12 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0134 13
group 0x0134++0x03
line.long 0x00 "VIC1VectAddr13,Vector Address 13 Register"
hexfld.long 0x00 " VectorAddr ,Vector 13 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x0138 14
group 0x0138++0x03
line.long 0x00 "VIC1VectAddr14,Vector Address 14 Register"
hexfld.long 0x00 " VectorAddr ,Vector 14 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 1 0x013C 15
group 0x013C++0x03
line.long 0x00 "VIC1VectAddr15,Vector Address 15 Register"
hexfld.long 0x00 " VectorAddr ,Vector 15 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0200 0
group 0x0200++0x03
line.long 0x00 "VIC1VectCntrl0,Vector Control 0 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0204 1
group 0x0204++0x03
line.long 0x00 "VIC1VectCntrl1,Vector Control 1 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0208 2
group 0x0208++0x03
line.long 0x00 "VIC1VectCntrl2,Vector Control 2 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x020C 3
group 0x020C++0x03
line.long 0x00 "VIC1VectCntrl3,Vector Control 3 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0210 4
group 0x0210++0x03
line.long 0x00 "VIC1VectCntrl4,Vector Control 4 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0214 5
group 0x0214++0x03
line.long 0x00 "VIC1VectCntrl5,Vector Control 5 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0218 6
group 0x0218++0x03
line.long 0x00 "VIC1VectCntrl6,Vector Control 6 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x021C 7
group 0x021C++0x03
line.long 0x00 "VIC1VectCntrl7,Vector Control 7 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0220 8
group 0x0220++0x03
line.long 0x00 "VIC1VectCntrl8,Vector Control 8 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0224 9
group 0x0224++0x03
line.long 0x00 "VIC1VectCntrl9,Vector Control 9 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0228 10
group 0x0228++0x03
line.long 0x00 "VIC1VectCntrl10,Vector Control 10 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x022C 11
group 0x022C++0x03
line.long 0x00 "VIC1VectCntrl11,Vector Control 11 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0230 12
group 0x0230++0x03
line.long 0x00 "VIC1VectCntrl12,Vector Control 12 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0234 13
group 0x0234++0x03
line.long 0x00 "VIC1VectCntrl13,Vector Control 13 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x0238 14
group 0x0238++0x03
line.long 0x00 "VIC1VectCntrl14,Vector Control 14 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 1 0x023C 15
group 0x023C++0x03
line.long 0x00 "VIC1VectCntrl15,Vector Control 15 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/IDReg.ph
;parameters: 1
rgroup 0xFE0++0x03
line.long 0x00 "VIC1PeriphID0,Peripherial Identification Register Bits [7:0] Register"
rgroup 0xFE4++0x03
line.long 0x00 "VIC1PeriphID1,Peripherial Identification Register Bits [15:8] Register"
rgroup 0xFE8++0x03
line.long 0x00 "VIC1PeriphID2,Peripherial Identification Register Bits [23:16] Register"
rgroup 0xFEC++0x03
line.long 0x00 "VIC1PeriphID3,Peripherial Identification Register Bits [31:24] Register"
;end include file EP9301/Interrupt/IDReg.ph
tree.end
tree "Vector Interrupt Controller 2(VIC2)"
base 0x800C0000
;begin include file EP9301/Interrupt/Global-VIC2.ph
;parameters: 2
rgroup 0x0000++0x0B
line.long 0x00 "VIC2IRQStatus,IRQ Status Register"
bitfld.long 0x00 31. " IRQStatus31 ,IRQ Interrupt Status Bit 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. " IRQStatus30 ,IRQ Interrupt Status Bit 30" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 29. " IRQStatus29 ,IRQ Interrupt Status Bit 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. " IRQStatus28 ,IRQ Interrupt Status Bit 28" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " IRQStatus27 ,IRQ Interrupt Status Bit 27" "No interrupt,Interrupt"
bitfld.long 0x00 24. " IRQStatus24 ,IRQ Interrupt Status Bit 24" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 22. " IRQStatus22 ,IRQ Interrupt Status Bit 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. " IRQStatus21 ,IRQ Interrupt Status Bit 21" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 20. " IRQStatus20 ,IRQ Interrupt Status Bit 20" "No interrupt,Interrupt"
bitfld.long 0x00 19. " IRQStatus19 ,IRQ Interrupt Status Bit 19" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 14. " IRQStatus14 ,IRQ Interrupt Status Bit 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. " IRQStatus13 ,IRQ Interrupt Status Bit 13" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 10. " IRQStatus10 ,IRQ Interrupt Status Bit 10" "No interrupt,Interrupt"
bitfld.long 0x00 8. " IRQStatus8 ,IRQ Interrupt Status Bit 8" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " IRQStatus7 ,IRQ Interrupt Status Bit 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. " IRQStatus6 ,IRQ Interrupt Status Bit 6" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " IRQStatus5 ,IRQ Interrupt Status Bit 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. " IRQStatus4 ,IRQ Interrupt Status Bit 4" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " IRQStatus3 ,IRQ Interrupt Status Bit 3" "No interrupt,Interrupt"
bitfld.long 0x00 1. " IRQStatus1 ,IRQ Interrupt Status Bit 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " IRQStatus0 ,IRQ Interrupt Status Bit 0" "No interrupt,Interrupt"
line.long 0x04 "VIC2FIQStatus,FIQ Status Register"
bitfld.long 0x04 31. " FIQStatus31 ,FIQ Interrupt Status Bit 31" "No interrupt,Interrupt"
bitfld.long 0x04 30. " FIQStatus30 ,FIQ Interrupt Status Bit 30" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 29. " FIQStatus29 ,FIQ Interrupt Status Bit 29" "No interrupt,Interrupt"
bitfld.long 0x04 28. " FIQStatus28 ,FIQ Interrupt Status Bit 28" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 27. " FIQStatus27 ,FIQ Interrupt Status Bit 27" "No interrupt,Interrupt"
bitfld.long 0x04 24. " FIQStatus24 ,FIQ Interrupt Status Bit 24" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 22. " FIQStatus22 ,FIQ Interrupt Status Bit 22" "No interrupt,Interrupt"
bitfld.long 0x04 21. " FIQStatus21 ,FIQ Interrupt Status Bit 21" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 20. " FIQStatus20 ,FIQ Interrupt Status Bit 20" "No interrupt,Interrupt"
bitfld.long 0x04 19. " FIQStatus19 ,FIQ Interrupt Status Bit 19" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 14. " FIQStatus14 ,FIQ Interrupt Status Bit 14" "No interrupt,Interrupt"
bitfld.long 0x04 13. " FIQStatus13 ,FIQ Interrupt Status Bit 13" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 10. " FIQStatus10 ,FIQ Interrupt Status Bit 10" "No interrupt,Interrupt"
bitfld.long 0x04 8. " FIQStatus8 ,FIQ Interrupt Status Bit 8" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " FIQStatus7 ,FIQ Interrupt Status Bit 7" "No interrupt,Interrupt"
bitfld.long 0x04 6. " FIQStatus6 ,FIQ Interrupt Status Bit 6" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 5. " FIQStatus5 ,FIQ Interrupt Status Bit 5" "No interrupt,Interrupt"
bitfld.long 0x04 4. " FIQStatus4 ,FIQ Interrupt Status Bit 4" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " FIQStatus3 ,FIQ Interrupt Status Bit 3" "No interrupt,Interrupt"
bitfld.long 0x04 1. " FIQStatus1 ,FIQ Interrupt Status Bit 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " FIQStatus0 ,FIQ Interrupt Status Bit 0" "No interrupt,Interrupt"
line.long 0x08 "VIC2RawIntr,Raw Interrupt Status Register"
bitfld.long 0x08 31. " RawIntr31 ,Interrupt Status Bit 31 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 30. " RawIntr30 ,Interrupt Status Bit 30 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 29. " RawIntr29 ,Interrupt Status Bit 29 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 28. " RawIntr28 ,Interrupt Status Bit 28 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 27. " RawIntr27 ,Interrupt Status Bit 27 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 24. " RawIntr24 ,Interrupt Status Bit 24 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 22. " RawIntr22 ,Interrupt Status Bit 22 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 21. " RawIntr21 ,Interrupt Status Bit 21 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 20. " RawIntr20 ,Interrupt Status Bit 20 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 19. " RawIntr19 ,Interrupt Status Bit 19 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 14. " RawIntr14 ,Interrupt Status Bit 14 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 13. " RawIntr13 ,Interrupt Status Bit 13 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 10. " RawIntr10 ,Interrupt Status Bit 10 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 8. " RawIntr8 ,Interrupt Status Bit 8 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 7. " RawIntr7 ,Interrupt Status Bit 7 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 6. " RawIntr6 ,Interrupt Status Bit 6 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 5. " RawIntr5 ,Interrupt Status Bit 5 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 4. " RawIntr4 ,Interrupt Status Bit 4 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 3. " RawIntr3 ,Interrupt Status Bit 3 without Masking" "No interrupt,Interrupt"
bitfld.long 0x08 1. " RawIntr1 ,Interrupt Status Bit 1 without Masking" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 0. " RawIntr0 ,Interrupt Status Bit 0 without Masking" "No interrupt,Interrupt"
group 0x000C++7
line.long 0x00 "VIC2IntSelect,Interrupt Select Register"
bitfld.long 0x00 31. " IntSelect31 ,Interrupt Type Select Bit 31" "FIQ,IRQ"
bitfld.long 0x00 30. " IntSelect30 ,Interrupt Type Select Bit 30" "FIQ,IRQ"
bitfld.long 0x00 29. " IntSelect29 ,Interrupt Type Select Bit 29" "FIQ,IRQ"
textline " "
bitfld.long 0x00 28. " IntSelect28 ,Interrupt Type Select Bit 28" "FIQ,IRQ"
bitfld.long 0x00 27. " IntSelect27 ,Interrupt Type Select Bit 27" "FIQ,IRQ"
bitfld.long 0x00 24. " IntSelect24 ,Interrupt Type Select Bit 24" "FIQ,IRQ"
textline " "
bitfld.long 0x00 22. " IntSelect22 ,Interrupt Type Select Bit 22" "FIQ,IRQ"
bitfld.long 0x00 21. " IntSelect21 ,Interrupt Type Select Bit 21" "FIQ,IRQ"
bitfld.long 0x00 20. " IntSelect20 ,Interrupt Type Select Bit 20" "FIQ,IRQ"
textline " "
bitfld.long 0x00 19. " IntSelect19 ,Interrupt Type Select Bit 19" "FIQ,IRQ"
bitfld.long 0x00 14. " IntSelect14 ,Interrupt Type Select Bit 14" "FIQ,IRQ"
bitfld.long 0x00 13. " IntSelect13 ,Interrupt Type Select Bit 13" "FIQ,IRQ"
textline " "
bitfld.long 0x00 10. " IntSelect10 ,Interrupt Type Select Bit 10" "FIQ,IRQ"
bitfld.long 0x00 8. " IntSelect8 ,Interrupt Type Select Bit 8" "FIQ,IRQ"
bitfld.long 0x00 7. " IntSelect7 ,Interrupt Type Select Bit 7" "FIQ,IRQ"
textline " "
bitfld.long 0x00 6. " IntSelect6 ,Interrupt Type Select Bit 6" "FIQ,IRQ"
bitfld.long 0x00 5. " IntSelect5 ,Interrupt Type Select Bit 5" "FIQ,IRQ"
bitfld.long 0x00 4. " IntSelect4 ,Interrupt Type Select Bit 4" "FIQ,IRQ"
textline " "
bitfld.long 0x00 3. " IntSelect3 ,Interrupt Type Select Bit 3" "FIQ,IRQ"
bitfld.long 0x00 1. " IntSelect1 ,Interrupt Type Select Bit 1" "FIQ,IRQ"
bitfld.long 0x00 0. " IntSelect0 ,Interrupt Type Select Bit 0" "FIQ,IRQ"
line.long 0x04 "VIC2IntEnable,Interrupt Enable Register"
bitfld.long 0x04 31. " IntEnable31 ,Interrupt Enable Bit 31" "Disabled,Enabled"
bitfld.long 0x04 30. " IntEnable30 ,Interrupt Enable Bit 30" "Disabled,Enabled"
bitfld.long 0x04 29. " IntEnable29 ,Interrupt Enable Bit 29" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " IntEnable28 ,Interrupt Enable Bit 28" "Disabled,Enabled"
bitfld.long 0x04 27. " IntEnable27 ,Interrupt Enable Bit 27" "Disabled,Enabled"
bitfld.long 0x04 24. " IntEnable24 ,Interrupt Enable Bit 24" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " IntEnable22 ,Interrupt Enable Bit 22" "Disabled,Enabled"
bitfld.long 0x04 21. " IntEnable21 ,Interrupt Enable Bit 21" "Disabled,Enabled"
bitfld.long 0x04 20. " IntEnable20 ,Interrupt Enable Bit 20" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " IntEnable19 ,Interrupt Enable Bit 19" "Disabled,Enabled"
bitfld.long 0x04 14. " IntEnable14 ,Interrupt Enable Bit 14" "Disabled,Enabled"
bitfld.long 0x04 13. " IntEnable13 ,Interrupt Enable Bit 13" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " IntEnable10 ,Interrupt Enable Bit 10" "Disabled,Enabled"
bitfld.long 0x04 8. " IntEnable8 ,Interrupt Enable Bit 8" "Disabled,Enabled"
bitfld.long 0x04 7. " IntEnable7 ,Interrupt Enable Bit 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " IntEnable6 ,Interrupt Enable Bit 6" "Disabled,Enabled"
bitfld.long 0x04 5. " IntEnable5 ,Interrupt Enable Bit 5" "Disabled,Enabled"
bitfld.long 0x04 4. " IntEnable4 ,Interrupt Enable Bit 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " IntEnable3 ,Interrupt Enable Bit 3" "Disabled,Enabled"
bitfld.long 0x04 1. " IntEnable1 ,Interrupt Enable Bit 1" "Disabled,Enabled"
bitfld.long 0x04 0. " IntEnable0 ,Interrupt Enable Bit 0" "Disabled,Enabled"
wgroup 0x0014++0x03
line.long 0x00 "VIC2IntEnClear,Interrupt Enable Clear Register"
bitfld.long 0x00 31. " IntEnableClr31 ,Interrupt Enable Clear Bit 31" "No effect,Clear"
bitfld.long 0x00 30. " IntEnableClr30 ,Interrupt Enable Clear Bit 30" "No effect,Clear"
textline " "
bitfld.long 0x00 29. " IntEnableClr29 ,Interrupt Enable Clear Bit 29" "No effect,Clear"
bitfld.long 0x00 28. " IntEnableClr28 ,Interrupt Enable Clear Bit 28" "No effect,Clear"
textline " "
bitfld.long 0x00 27. " IntEnableClr27 ,Interrupt Enable Clear Bit 27" "No effect,Clear"
bitfld.long 0x00 24. " IntEnableClr24 ,Interrupt Enable Clear Bit 24" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " IntEnableClr22 ,Interrupt Enable Clear Bit 22" "No effect,Clear"
bitfld.long 0x00 21. " IntEnableClr21 ,Interrupt Enable Clear Bit 21" "No effect,Clear"
textline " "
bitfld.long 0x00 20. " IntEnableClr20 ,Interrupt Enable Clear Bit 20" "No effect,Clear"
bitfld.long 0x00 19. " IntEnableClr19 ,Interrupt Enable Clear Bit 19" "No effect,Clear"
textline " "
bitfld.long 0x00 14. " IntEnableClr14 ,Interrupt Enable Clear Bit 14" "No effect,Clear"
bitfld.long 0x00 13. " IntEnableClr13 ,Interrupt Enable Clear Bit 13" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " IntEnableClr10 ,Interrupt Enable Clear Bit 10" "No effect,Clear"
bitfld.long 0x00 8. " IntEnableClr8 ,Interrupt Enable Clear Bit 8" "No effect,Clear"
textline " "
bitfld.long 0x00 7. " IntEnableClr7 ,Interrupt Enable Clear Bit 7" "No effect,Clear"
bitfld.long 0x00 6. " IntEnableClr6 ,Interrupt Enable Clear Bit 6" "No effect,Clear"
textline " "
bitfld.long 0x00 5. " IntEnableClr5 ,Interrupt Enable Clear Bit 5" "No effect,Clear"
bitfld.long 0x00 4. " IntEnableClr4 ,Interrupt Enable Clear Bit 4" "No effect,Clear"
textline " "
bitfld.long 0x00 3. " IntEnableClr3 ,Interrupt Enable Clear Bit 3" "No effect,Clear"
bitfld.long 0x00 1. " IntEnableClr1 ,Interrupt Enable Clear Bit 1" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " IntEnableClr0 ,Interrupt Enable Clear Bit 0" "No effect,Clear"
group 0x0018++0x03
line.long 0x00 "VIC2SoftInt,Software Interrupt Register"
bitfld.long 0x00 31. " SoftInt31 ,Software Interrupt Bit 31" "No effect,Generated"
bitfld.long 0x00 30. " SoftInt30 ,Software Interrupt Bit 30" "No effect,Generated"
textline " "
bitfld.long 0x00 29. " SoftInt29 ,Software Interrupt Bit 29" "No effect,Generated"
bitfld.long 0x00 28. " SoftInt28 ,Software Interrupt Bit 28" "No effect,Generated"
textline " "
bitfld.long 0x00 27. " SoftInt27 ,Software Interrupt Bit 27" "No effect,Generated"
bitfld.long 0x00 26. " SoftInt26 ,Software Interrupt Bit 26" "No effect,Generated"
textline " "
bitfld.long 0x00 25. " SoftInt25 ,Software Interrupt Bit 25" "No effect,Generated"
bitfld.long 0x00 24. " SoftInt24 ,Software Interrupt Bit 24" "No effect,Generated"
textline " "
bitfld.long 0x00 23. " SoftInt23 ,Software Interrupt Bit 23" "No effect,Generated"
bitfld.long 0x00 22. " SoftInt22 ,Software Interrupt Bit 22" "No effect,Generated"
textline " "
bitfld.long 0x00 21. " SoftInt21 ,Software Interrupt Bit 21" "No effect,Generated"
bitfld.long 0x00 20. " SoftInt20 ,Software Interrupt Bit 20" "No effect,Generated"
textline " "
bitfld.long 0x00 19. " SoftInt19 ,Software Interrupt Bit 19" "No effect,Generated"
bitfld.long 0x00 18. " SoftInt18 ,Software Interrupt Bit 18" "No effect,Generated"
textline " "
bitfld.long 0x00 17. " SoftInt17 ,Software Interrupt Bit 17" "No effect,Generated"
bitfld.long 0x00 16. " SoftInt16 ,Software Interrupt Bit 16" "No effect,Generated"
textline " "
bitfld.long 0x00 15. " SoftInt15 ,Software Interrupt Bit 15" "No effect,Generated"
bitfld.long 0x00 14. " SoftInt14 ,Software Interrupt Bit 14" "No effect,Generated"
textline " "
bitfld.long 0x00 13. " SoftInt13 ,Software Interrupt Bit 13" "No effect,Generated"
bitfld.long 0x00 12. " SoftInt12 ,Software Interrupt Bit 12" "No effect,Generated"
textline " "
bitfld.long 0x00 11. " SoftInt11 ,Software Interrupt Bit 11" "No effect,Generated"
bitfld.long 0x00 10. " SoftInt10 ,Software Interrupt Bit 10" "No effect,Generated"
textline " "
bitfld.long 0x00 9. " SoftInt9 ,Software Interrupt Bit 9" "No effect,Generated"
bitfld.long 0x00 8. " SoftInt8 ,Software Interrupt Bit 8" "No effect,Generated"
textline " "
bitfld.long 0x00 7. " SoftInt7 ,Software Interrupt Bit 7" "No effect,Generated"
bitfld.long 0x00 6. " SoftInt6 ,Software Interrupt Bit 6" "No effect,Generated"
textline " "
bitfld.long 0x00 5. " SoftInt5 ,Software Interrupt Bit 5" "No effect,Generated"
bitfld.long 0x00 4. " SoftInt4 ,Software Interrupt Bit 4" "No effect,Generated"
textline " "
bitfld.long 0x00 3. " SoftInt3 ,Software Interrupt Bit 3" "No effect,Generated"
bitfld.long 0x00 2. " SoftInt2 ,Software Interrupt Bit 2" "No effect,Generated"
textline " "
bitfld.long 0x00 1. " SoftInt1 ,Software Interrupt Bit 1" "No effect,Generated"
bitfld.long 0x00 0. " SoftInt0 ,Software Interrupt Bit 0" "No effect,Generated"
wgroup 0x001C++0x03
line.long 0x00 "VIC2SoftIntClear,Software Interrupt Clear Register"
bitfld.long 0x00 31. " SoftIntClr31 ,Software Interrupt Clear Bit 31" "No effect,Clear"
bitfld.long 0x00 30. " SoftIntClr30 ,Software Interrupt Clear Bit 30" "No effect,Clear"
textline " "
bitfld.long 0x00 29. " SoftIntClr29 ,Software Interrupt Clear Bit 29" "No effect,Clear"
bitfld.long 0x00 28. " SoftIntClr28 ,Software Interrupt Clear Bit 28" "No effect,Clear"
textline " "
bitfld.long 0x00 27. " SoftIntClr27 ,Software Interrupt Clear Bit 27" "No effect,Clear"
bitfld.long 0x00 26. " SoftIntClr26 ,Software Interrupt Clear Bit 26" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " SoftIntClr25 ,Software Interrupt Clear Bit 25" "No effect,Clear"
bitfld.long 0x00 24. " SoftIntClr24 ,Software Interrupt Clear Bit 24" "No effect,Clear"
textline " "
bitfld.long 0x00 23. " SoftIntClr23 ,Software Interrupt Clear Bit 23" "No effect,Clear"
bitfld.long 0x00 22. " SoftIntClr22 ,Software Interrupt Clear Bit 22" "No effect,Clear"
textline " "
bitfld.long 0x00 21. " SoftIntClr21 ,Software Interrupt Clear Bit 21" "No effect,Clear"
bitfld.long 0x00 20. " SoftIntClr20 ,Software Interrupt Clear Bit 20" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " SoftIntClr19 ,Software Interrupt Clear Bit 19" "No effect,Clear"
bitfld.long 0x00 18. " SoftIntClr18 ,Software Interrupt Clear Bit 18" "No effect,Clear"
textline " "
bitfld.long 0x00 17. " SoftIntClr17 ,Software Interrupt Clear Bit 17" "No effect,Clear"
bitfld.long 0x00 16. " SoftIntClr16 ,Software Interrupt Clear Bit 16" "No effect,Clear"
textline " "
bitfld.long 0x00 15. " SoftIntClr15 ,Software Interrupt Clear Bit 15" "No effect,Clear"
bitfld.long 0x00 14. " SoftIntClr14 ,Software Interrupt Clear Bit 14" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " SoftIntClr13 ,Software Interrupt Clear Bit 13" "No effect,Clear"
bitfld.long 0x00 12. " SoftIntClr12 ,Software Interrupt Clear Bit 12" "No effect,Clear"
textline " "
bitfld.long 0x00 11. " SoftIntClr11 ,Software Interrupt Clear Bit 11" "No effect,Clear"
bitfld.long 0x00 10. " SoftIntClr10 ,Software Interrupt Clear Bit 10" "No effect,Clear"
textline " "
bitfld.long 0x00 9. " SoftIntClr9 ,Software Interrupt Clear Bit 9" "No effect,Clear"
bitfld.long 0x00 8. " SoftIntClr8 ,Software Interrupt Clear Bit 8" "No effect,Clear"
textline " "
bitfld.long 0x00 7. " SoftIntClr7 ,Software Interrupt Clear Bit 7" "No effect,Clear"
bitfld.long 0x00 6. " SoftIntClr6 ,Software Interrupt Clear Bit 6" "No effect,Clear"
textline " "
bitfld.long 0x00 5. " SoftIntClr5 ,Software Interrupt Clear Bit 5" "No effect,Clear"
bitfld.long 0x00 4. " SoftIntClr4 ,Software Interrupt Clear Bit 4" "No effect,Clear"
textline " "
bitfld.long 0x00 3. " SoftIntClr3 ,Software Interrupt Clear Bit 3" "No effect,Clear"
bitfld.long 0x00 2. " SoftIntClr2 ,Software Interrupt Clear Bit 2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " SoftIntClr1 ,Software Interrupt Clear Bit 1" "No effect,Clear"
bitfld.long 0x00 0. " SoftIntClr0 ,Software Interrupt Clear Bit 0" "No effect,Clear"
group 0x0020++0x03
line.long 0x00 "VIC2Protection,Protection Enable Register"
bitfld.long 0x00 0. " Protection ,Protection Enable" "Disabled,Enabled"
group 0x0030++7
line.long 0x00 "VIC2VectAddr,Vector Address Register"
hexfld.long 0x00 " VectorAddr ,Vector Address Value"
line.long 0x04 "VIC2DefVectAddr,Default Vector Address Register"
hexfld.long 0x04 " DefVectorAddr ,Default Vector Address Value"
;end include file EP9301/Interrupt/Global-VIC2.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0100 0
group 0x0100++0x03
line.long 0x00 "VIC2VectAddr0,Vector Address 0 Register"
hexfld.long 0x00 " VectorAddr ,Vector 0 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0104 1
group 0x0104++0x03
line.long 0x00 "VIC2VectAddr1,Vector Address 1 Register"
hexfld.long 0x00 " VectorAddr ,Vector 1 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0108 2
group 0x0108++0x03
line.long 0x00 "VIC2VectAddr2,Vector Address 2 Register"
hexfld.long 0x00 " VectorAddr ,Vector 2 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x010C 3
group 0x010C++0x03
line.long 0x00 "VIC2VectAddr3,Vector Address 3 Register"
hexfld.long 0x00 " VectorAddr ,Vector 3 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0110 4
group 0x0110++0x03
line.long 0x00 "VIC2VectAddr4,Vector Address 4 Register"
hexfld.long 0x00 " VectorAddr ,Vector 4 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0114 5
group 0x0114++0x03
line.long 0x00 "VIC2VectAddr5,Vector Address 5 Register"
hexfld.long 0x00 " VectorAddr ,Vector 5 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0118 6
group 0x0118++0x03
line.long 0x00 "VIC2VectAddr6,Vector Address 6 Register"
hexfld.long 0x00 " VectorAddr ,Vector 6 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x011C 7
group 0x011C++0x03
line.long 0x00 "VIC2VectAddr7,Vector Address 7 Register"
hexfld.long 0x00 " VectorAddr ,Vector 7 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0120 8
group 0x0120++0x03
line.long 0x00 "VIC2VectAddr8,Vector Address 8 Register"
hexfld.long 0x00 " VectorAddr ,Vector 8 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0124 9
group 0x0124++0x03
line.long 0x00 "VIC2VectAddr9,Vector Address 9 Register"
hexfld.long 0x00 " VectorAddr ,Vector 9 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0128 10
group 0x0128++0x03
line.long 0x00 "VIC2VectAddr10,Vector Address 10 Register"
hexfld.long 0x00 " VectorAddr ,Vector 10 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x012C 11
group 0x012C++0x03
line.long 0x00 "VIC2VectAddr11,Vector Address 11 Register"
hexfld.long 0x00 " VectorAddr ,Vector 11 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0130 12
group 0x0130++0x03
line.long 0x00 "VIC2VectAddr12,Vector Address 12 Register"
hexfld.long 0x00 " VectorAddr ,Vector 12 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0134 13
group 0x0134++0x03
line.long 0x00 "VIC2VectAddr13,Vector Address 13 Register"
hexfld.long 0x00 " VectorAddr ,Vector 13 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x0138 14
group 0x0138++0x03
line.long 0x00 "VIC2VectAddr14,Vector Address 14 Register"
hexfld.long 0x00 " VectorAddr ,Vector 14 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/Vector.ph
;parameters: 2 0x013C 15
group 0x013C++0x03
line.long 0x00 "VIC2VectAddr15,Vector Address 15 Register"
hexfld.long 0x00 " VectorAddr ,Vector 15 Address Register"
;end include file EP9301/Interrupt/Vector.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0200 0
group 0x0200++0x03
line.long 0x00 "VIC2VectCntrl0,Vector Control 0 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0204 1
group 0x0204++0x03
line.long 0x00 "VIC2VectCntrl1,Vector Control 1 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0208 2
group 0x0208++0x03
line.long 0x00 "VIC2VectCntrl2,Vector Control 2 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x020C 3
group 0x020C++0x03
line.long 0x00 "VIC2VectCntrl3,Vector Control 3 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0210 4
group 0x0210++0x03
line.long 0x00 "VIC2VectCntrl4,Vector Control 4 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0214 5
group 0x0214++0x03
line.long 0x00 "VIC2VectCntrl5,Vector Control 5 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0218 6
group 0x0218++0x03
line.long 0x00 "VIC2VectCntrl6,Vector Control 6 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x021C 7
group 0x021C++0x03
line.long 0x00 "VIC2VectCntrl7,Vector Control 7 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0220 8
group 0x0220++0x03
line.long 0x00 "VIC2VectCntrl8,Vector Control 8 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0224 9
group 0x0224++0x03
line.long 0x00 "VIC2VectCntrl9,Vector Control 9 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0228 10
group 0x0228++0x03
line.long 0x00 "VIC2VectCntrl10,Vector Control 10 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x022C 11
group 0x022C++0x03
line.long 0x00 "VIC2VectCntrl11,Vector Control 11 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0230 12
group 0x0230++0x03
line.long 0x00 "VIC2VectCntrl12,Vector Control 12 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0234 13
group 0x0234++0x03
line.long 0x00 "VIC2VectCntrl13,Vector Control 13 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x0238 14
group 0x0238++0x03
line.long 0x00 "VIC2VectCntrl14,Vector Control 14 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/VectCtrl.ph
;parameters: 2 0x023C 15
group 0x023C++0x03
line.long 0x00 "VIC2VectCntrl15,Vector Control 15 Register"
bitfld.long 0x00 5. " E ,Interrupt Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--4. 1. " IntSource ,Interrupt Source"
;end include file EP9301/Interrupt/VectCtrl.ph
;begin include file EP9301/Interrupt/IDReg.ph
;parameters: 2
rgroup 0xFE0++0x03
line.long 0x00 "VIC2PeriphID0,Peripherial Identification Register Bits [7:0] Register"
rgroup 0xFE4++0x03
line.long 0x00 "VIC2PeriphID1,Peripherial Identification Register Bits [15:8] Register"
rgroup 0xFE8++0x03
line.long 0x00 "VIC2PeriphID2,Peripherial Identification Register Bits [23:16] Register"
rgroup 0xFEC++0x03
line.long 0x00 "VIC2PeriphID3,Peripherial Identification Register Bits [31:24] Register"
;end include file EP9301/Interrupt/IDReg.ph
tree.end
width 16. 8.
;end include file EP9301/Interrupt.ph
tree.end
tree "1/10/100 Mbps Ethernet LAN Controller"
base 0x80010000
;begin include file EP9301/LAN.ph
;parameters:
tree "Control Registers"
group 0x0000++0x0B
line.long 0x00 "RXCtl,MAC Receiver Control Register"
bitfld.long 0x00 20. " PauseA ,Pause Accept" "Clear,Set"
bitfld.long 0x00 19. " RxFCE1 ,Rx Flow Control Enable Bit 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " RxFCE0 ,Rx Flow Control Enable Bit 0" "Disabled,Enabled"
bitfld.long 0x00 17. " BCRC ,Buffer CRC" "Not receive,Receive"
textline " "
bitfld.long 0x00 16. " SRxON ,Serial Receive On" "Disabled,Enabled"
bitfld.long 0x00 13. " RCRCA ,Runt CRCA" "Clear,Set"
textline " "
bitfld.long 0x00 12. " RA ,Runt A" "Clear,Set"
bitfld.long 0x00 11. " PA ,Promiscuous" "Clear,Set"
textline " "
bitfld.long 0x00 10. " BA ,Broadcast A" "Clear,Set"
bitfld.long 0x00 9. " MA ,Mulitcast A" "Clear,Set"
textline " "
bitfld.long 0x00 8. " IAHA ,Individual Address Hash A" "Clear,Set"
bitfld.long 0x00 3. " IA3 ,Individual Accept 3" "Clear,Set"
textline " "
bitfld.long 0x00 2. " IA2 ,Individual Accept 2" "Clear,Set"
bitfld.long 0x00 1. " IA1 ,Individual Accept 1" "Clear,Set"
textline " "
bitfld.long 0x00 0. " IA0 ,Individual Accept 0" "Clear,Set"
line.long 0x04 "TXCtl,MAC Transmitter Control Register"
bitfld.long 0x04 7. " DefDis ,2-part Defeferral Disable" "Enabled,Disabled"
bitfld.long 0x04 6. " MBE ,Mopdified Backoff Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " ICRC ,Inhibit CRC" "Clear,Set"
bitfld.long 0x04 4. " TxPD ,Tx Pad Disable" "Enabled,Disabled"
textline " "
bitfld.long 0x04 3. " OColl ,One Collision" "Clear,Set"
bitfld.long 0x04 2. " SP ,Send Pause" "No transmit,Transmit"
textline " "
bitfld.long 0x04 1. " PB ,Pause Busy" "No pause is transmitting,Pause is transmitting"
bitfld.long 0x04 0. " STxON ,Serial Transmitt On" "Disabled,Enabled"
line.long 0x08 "TestCtl,MAC Test Control Register"
bitfld.long 0x08 7. " MACF ,MAC Fast" "Normal timing,Speed-up"
bitfld.long 0x08 6. " MFDX ,MAC Full Duplex" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " DB ,Disable Backoff" "Enabled,Disabled"
group 0x0020++0x0B
line.long 0x00 "SelfCtl,MAC Self Control Register"
hexmask.long.byte 0x00 9.--14. 1. " MDCDIV ,MDC Clock Divisior"
bitfld.long 0x00 8. " PSPRS ,Preamble Supress" "32 ones before SFD,SFD no MDIO"
textline " "
bitfld.long 0x00 7. " RWP ,Remote Wake Pin" "No,Yes"
bitfld.long 0x00 5. " GPO8 ,General Purpose Output 0" "Low,High"
textline " "
bitfld.long 0x00 4. " PUWE ,Power Up Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " PDWE ,Power Down Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " MIIL ,MII Loopback" "No loopback,Loopback"
bitfld.long 0x00 0. " RESET ,Soft Reset" "No effect,Reset"
line.long 0x04 "IntEn,MAC Intrerrupt Enable Register"
bitfld.long 0x04 29. " RxMIE ,Receive Miss Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " RxBIE ,Receive Buffer Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 27. " RxSQIE ,Receive Status Queue Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " TxLEIE ,Transmit Length Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 25. " ECIE ,End of Chain Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " TxUHIE ,Transmit Underrun Halt Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 18. " MOIE ,Receive Miss Overflow Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 17. " TxCOIE ,Transmit Collision Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 16. " RxROIE ,Receive Runt Overflow Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " MIIE ,MII Management Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 11. " PHYSIE ,PHY Status Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " TIE ,Timer Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 8. " SWIE ,Software Interrupt" "Not generated,Generated"
textline " "
bitfld.long 0x04 3. " TSQIE ,Transmit Status Queue Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " REOFIE ,Receive End of Frame Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " REOBIE ,Receive End of Buffer Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RHDRIE ,Receive Header Interrupt Enable" "Disabled,Enabled"
line.long 0x08 "IntStsP,MAC Interrupt Status Preserve Register"
bitfld.long 0x08 30. " RWI ,Remote Wakeup Interrupt" "No interrupt,Interrupt"
bitfld.long 0x08 29. " RxMI ,Receive Frame Discarded" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 28. " RxBI ,Last Available Descriptor Read to MAC" "No interrupt,Interrupt"
bitfld.long 0x08 27. " RxSQI ,Receive Status Queue" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 26. " TxLEI ,Transmit Length Error" "No interrupt,Interrupt"
bitfld.long 0x08 25. " ECI ,Exhausted Transmit Descriptor Chain" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 24. " TxUHI ,Out of Data during Transmission" "No interrupt,Interrupt"
bitfld.long 0x08 18. " MOI ,Received Frames Lost in Buffer" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 17. " TxCOI ,Transmit Collision" "No interrupt,Interrupt"
bitfld.long 0x08 16. " RxROI ,Receive Collision" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 12. " MIII ,Management Operation on MII Completed" "No interrupt,Interrupt"
bitfld.long 0x08 11. " PHYI ,SHY Status Change" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 10. " TI ,GT Timer Reaches Zero" "No interrupt,Interrupt"
bitfld.long 0x08 9. " AHBE ,AHB Cycle Terminated Incorrectly" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 8. " SWI ," "0,1"
bitfld.long 0x08 4. " OTHER ,Status of others that bits 2,3,10 Present" "Clear,Set"
textline " "
bitfld.long 0x08 3. " TxSQ ,Status Affecting Transmit Status Queue" "No,Yes"
bitfld.long 0x08 2. " RxSQ ,Status Affecting Receive Status Queue" "No,Yes"
rgroup 0x002C++0x03
line.long 0x00 "IntStsC,MAC Interrupt Status Clear Register"
bitfld.long 0x00 30. " RWI ,Remote Wakeup Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 29. " RxMI ,Receive Frame Discarded" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 28. " RxBI ,Last Available Descriptor Read to MAC" "No interrupt,Interrupt"
bitfld.long 0x00 27. " RxSQI ,Receive Status Queue" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 26. " TxLEI ,Transmit Length Error" "No interrupt,Interrupt"
bitfld.long 0x00 25. " ECI ,Exhausted Transmit Descriptor Chain" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 24. " TxUHI ,Out of Data during Transmission" "No interrupt,Interrupt"
bitfld.long 0x00 18. " MOI ,Received Frames Lost in Buffer" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 17. " TxCOI ,Transmit Collision" "No interrupt,Interrupt"
bitfld.long 0x00 16. " RxROI ,Receive Collision" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " MIII ,Management Operation on MII Completed" "No interrupt,Interrupt"
bitfld.long 0x00 11. " PHYI ,SHY Status Change" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 10. " TI ,GT Timer Reaches Zero" "No interrupt,Interrupt"
bitfld.long 0x00 9. " AHBE ,AHB Cycle Terminated Incorrectly" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 8. " SWI ," "0,1"
bitfld.long 0x00 4. " OTHER ,Status of others that bits 2,3,10 Present" "Clear,Set"
textline " "
bitfld.long 0x00 3. " TxSQ ,Status Affecting Transmit Status Queue" "No,Yes"
bitfld.long 0x00 2. " RxSQ ,Status Affecting Receive Status Queue" "No,Yes"
group 0x0038++0x17
line.long 0x00 "DiagAd,MAC Diagnostic Address Register"
hexmask.long.byte 0x00 0.--7. 1. " ADDR ,Diagnostic Address"
line.long 0x04 "DiagDa,MAC Diagnostic Data"
hexfld.long 0x04 " DATA ,Diagnostic Data Register"
line.long 0x08 "GT,MAC General Timer Register"
hexmask.long.word 0x08 16.--31. 1. " GTC ,General Timer Count"
hexmask.long.word 0x08 0.--15. 1. " GTP ,General Timer Period"
line.long 0x0C "FCT,MAC Flow Control Timer Register"
hexmask.long.tbyte 0x0C 0.--31. 1. " FCT ,Flow Control Timer Value"
line.long 0x10 "FCF,MAC Flow Control Format Register"
hexmask.long.word 0x10 16.--31. 1. " MACCT ,MAC Control Type"
hexmask.long.word 0x10 0.--15. 1. " TPT ,Transmit Pause Time"
line.long 0x14 "AFP,MAC Address Filter Pointer Register"
bitfld.long 0x14 0.--2. " AFP ,Address Filter Pointer" "Primary individual,Secondary address,Secondary address,Secondary address,Reserved,Reserved,Destination address,Hash table used"
group 0x0050++7
line.quad 0x00 "IndAd,MAC Individual Address Register"
hexmask.quad 0x00 0.--47. 1. " IAD ,Individual Address"
group 0x0050++7
line.quad 0x00 "HashTbl,MAC Hash Table Register"
hexfld.quad 0x00 " HTb ,Hash Table"
group 0x0060++7
line.long 0x00 "GIIntSts,MAC Global Interrupt Status Register"
bitfld.long 0x00 15. " INT ,Global Interrupt Bit" "Interrupt not occured,Interrupt occured"
line.long 0x04 "GlIntMsk,MAC Global Interrupt Mask Register"
bitfld.long 0x04 15. " INT ,Global Interrupt Mask Bit" "Not masked,Masked"
rgroup 0x0068++0x03
line.long 0x00 "GIIntROSts,MAC Global Interrupt Read-Only Status Register"
bitfld.long 0x00 15. " INT ,Global Interrupt Read-Only Status Bit" "Interrupt not occured,Interrupt occured"
wgroup 0x006C++0x03
line.long 0x00 "GIIntFrc,MAC Global Interrupt Force Register"
bitfld.long 0x00 15. " INT ,Global Interrupt Force Bit" "No effect,Enabled"
rgroup 0x0070++0x0B
line.long 0x00 "TXCollCnt,MAC Transmission Collision Count Register"
hexmask.long.word 0x00 0.--15. 1. " TXC ,Transmission Collision Count Value"
line.long 0x04 "RXMissCnt,MAC Receive Miss Count Register"
hexmask.long.word 0x04 0.--15. 1. " RMC ,Receive Miss Count Value"
line.long 0x08 "RXRuntCnt,MAC Receive Runt Count Register"
hexmask.long.word 0x08 0.--15. 1. " RRC ,Receive Runt Count"
tree.end
tree "MII/PHY Registers"
group 0x0010++7
line.long 0x00 "MIICmd,MAC MII Command Registers"
bitfld.long 0x00 14.--15. " OP ,OP Code" "Reserved,Write,Read,Reserved"
hexmask.long.byte 0x00 10.--13. 1. " PHYAD ,PHY Address"
hexmask.long.byte 0x00 0.--4. 1. " REGAD ,Register Address"
line.long 0x04 "MIData,MAC MII Data Register"
hexmask.long.word 0x04 0.--15. 1. " MIIData ,MII Data"
rgroup 0x0018++0x03
line.long 0x00 "MIISts,MAC MII Status Register"
bitfld.long 0x00 0. " BUSY ,MII Busy" "Not busy,Busy"
tree.end
tree "Descriptor Processor Registers"
group 0x0080++0x03
line.long 0x00 "BMCtl,MAC Bus Master Control Register"
bitfld.long 0x00 13. " MT ,Manual Transfer" "No,Yes"
bitfld.long 0x00 12. " TT ,Timed Transfer" "No,Yes"
bitfld.long 0x00 11. " UnH ,Underrun Halt" "Not halted,Halted"
textline " "
bitfld.long 0x00 10. " TxChR ,Transmit Channel Reset" "No effect,Reset"
bitfld.long 0x00 9. " TxDis ,Transmit Disable" "Enabled,Disabled"
bitfld.long 0x00 8. " TxEn ,Transmit Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " EH2 ,Enable Header 2" "Disabled,Enabled"
bitfld.long 0x00 5. " EH1 ,Enable Header 1" "Disabled,Enabled"
bitfld.long 0x00 4. " EEOB ,Enable EOB" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " RxChR ,Receive Channel Reset" "No effect,Reset"
bitfld.long 0x00 1. " RxDis ,Receive Disable" "Enabled,Disabled"
bitfld.long 0x00 0. " RxEn ,Receive Enable" "Disabled,Enabled"
rgroup 0x0084++0x03
line.long 0x00 "BMSts,MAC Bus Master Status Register"
bitfld.long 0x00 7. " TxAct ,Transmit Active" "Not active,Active"
bitfld.long 0x00 4. " TP ,Transfer Pending" "Not pending,Pending"
bitfld.long 0x00 3. " RxAct ,Receive Active" "Not active,Active"
textline " "
bitfld.long 0x00 0.--2. " QID ,Queue ID" "Receive data,Transmit data,Receive status,Transmit status,Receive descriptor,Transmit descriptor,,"
tree.end
tree "Descriptor Processor Receive"
group 0x0088++0x03
line.long 0x00 "RXBCA,MAC Receive Buffer Current Address Register"
hexfld.long 0x00 " RBCA ,Receive Buffer Current Address"
group 0x0090++0x03
line.long 0x00 "RXDQBAdd,MAC Receive Descriptor Queue Base Address Register"
hexfld.long 0x00 " RDBA ,Receive Descriptor Base Address"
group 0x0094++0x03
line.word 0x00 "RXDQBLen,MAC Receive Descriptor Queue Base Length Register"
hexfld.word 0x00 " RDBL ,Receive Descriptor Length Address"
line.word 0x02 "RXDQCurLen,MAC Receive Descriptor Queue Curent Length Register"
hexfld.word 0x02 " RDCL ,Receive Descriptor Base Length"
group 0x0098++0x07
line.long 0x00 "RXDQCurAdd,MAC Receive Descriptor Queue Curent Address Register"
hexfld.long 0x00 " RDCA ,Receive Descriptor Curent Address"
line.long 0x04 "RXDEnq,MAC Receive Descriptor Enqueue Register"
hexmask.long.word 0x04 16.--31. 1. " RDV ,Receive Descriptor Value"
hexmask.long.byte 0x04 0.--7. 1. " RDI ,Receive Descriptor Incerment"
group 0x00A0++0x03
line.long 0x00 "RxStsQBAdd,MAC Receive Status Queue Base Address Register"
hexfld.long 0x00 " RSQBA ,Receive Status Queue Base Address"
group 0x00A4++0x03
line.word 0x00 "RxStsQBLen,MAC Receive Status Queue Base Length Register"
hexfld.word 0x00 " RSQBL ,Receive Status Queue Base Length"
line.word 0x02 "RxStsQBCurLen,MAC Receive Status Queue Current Length Register"
hexfld.word 0x02 " RSQCL ,Receive Status Queue Current Length"
group 0x00A8++0x07
line.long 0x00 "RxStsQBCurAdd,MAC Receive Status Queue Address Register"
hexfld.long 0x00 " RSQCA ,Receive Status Queue Address"
line.long 0x04 "RxStsEnq,MAC Receive Status Enqueue Register"
hexmask.long.word 0x04 16.--31. 1. " RSV ,Receive Status Value"
hexmask.long.byte 0x04 0.--7. 1. " RSI ,Receive Stauts Incerment"
tree.end
tree "Descriptor Processor Transmit"
group 0x00B0++0x03
line.long 0x00 "TXDQBAdd,MAC Transmit Descriptor Queue Base Address Register"
hexfld.long 0x00 " TDBA ,Transmit Descriptor Base Address"
group 0x00B4++0x03
line.word 0x00 "TXDQBLen,MAC Transmit Descriptor Queue Base Length Register"
hexfld.word 0x00 " TDBL ,Transmit Descriptor Length Address"
line.word 0x02 "TXDQCurLen,MAC Transmit Descriptor Queue Current Length Register"
hexfld.word 0x02 " TDCL ,Transmit Descriptor Base Length"
group 0x00B8++0x07
line.long 0x00 "TXDQCurAdd,MAC Transmit Descriptor Queue Current Address Register"
hexfld.long 0x00 " TDCA ,Transmit Descriptor Curent Address"
line.long 0x04 "TXDEnq,MAC Transmit Descriptor Enqueue Register"
hexmask.long.word 0x04 16.--31. 1. " TDV ,Transmit Descriptor Value"
hexmask.long.byte 0x04 0.--7. 1. " TDI ,Transmit Descriptor Incerment"
group 0x00C0++0x03
line.long 0x00 "TXStsQBAdd,MAC Transmit Status Queue Base Address Register"
hexfld.long 0x00 " TSQBA ,Transmit Status Queue Base Address"
group 0x00C4++0x03
line.word 0x00 "TXStsQBLen,MAC Transmit Status Queue Base Length Register"
hexfld.word 0x00 " TSQBL ,Transmit Status Queue Base Length"
line.word 0x02 "TXStsQBCurLen,MAC Transmit Status Queue Current Address Register"
hexfld.word 0x02 " TSQCL ,Transmit Status Queue Current Length"
group 0x00C8++0x03
line.long 0x00 "TXStsQBCurAdd,MAC Transmit Status Queue Current Address Register"
hexfld.long 0x00 " TSQCA ,Transmit Status Queue Address"
group 0x00D0++0x0F
line.long 0x00 "RXBufTrshld,MAC Receive Buffer Threshold Register"
hexmask.long.byte 0x00 18.--25. 1. " RDHT ,Receive Data Hard Threshold"
hexmask.long.byte 0x00 2.--9. 1. " RDST ,Receive Data Soft Threshold"
line.long 0x04 "TXBufTrshld,MAC Transmit Buffer Threshold Register"
hexmask.long.byte 0x04 18.--25. 1. " TDHT ,Transmit Data Hard Threshold"
hexmask.long.byte 0x04 2.--9. 1. " TDST ,Transmit Data Soft Threshold"
line.long 0x08 "RXStsTrshld,MAC Receive Status Threshold Register"
hexmask.long.byte 0x08 18.--21. 1. " RSHT ,Receive Status Hard Threshold"
hexmask.long.byte 0x08 2.--5. 1. " RSST ,Receive Status Soft Threshold"
line.long 0x0C "TXStsTrshld,MAC Transmit Status Threshold Register"
hexmask.long.byte 0x0C 18.--21. 1. " TSHT ,Transmit Status Hard Threshold"
hexmask.long.byte 0x0C 2.--5. 1. " TSST ,Transmit Status Soft Threshold"
group 0x00E0++0x0F
line.long 0x00 "RXDTrshld,MAC Receive Descriptor Threshold Register"
hexmask.long.byte 0x00 18.--21. 1. " RDHT ,Receive Descriptor Hard Threshold"
hexmask.long.byte 0x00 2.--5. 1. " RDST ,Receive Descriptor Soft Threshold"
line.long 0x04 "TXDTrshld,MAC Transmit Descriptor Threshold Register"
hexmask.long.byte 0x04 18.--21. 1. " TDHT ,Transmit Descriptor Hard Threshold"
hexmask.long.byte 0x04 2.--5. 1. " TDST ,Transmit Descriptor Soft Threshold"
line.long 0x08 "MaxFrmLen,MAC Maximum Frame Length Register"
hexmask.long.byte 0x08 16.--21. 1. " MFL ,Maximum Frame Length"
hexmask.long.byte 0x08 0.--5. 1. " TST ,Transmit Start Threshold"
line.long 0x0C "RXHdrLen,MAC Receive Header Length Register"
hexmask.long.word 0x0C 16.--26. 1. " RHL2 ,Receive Header Length 2"
hexmask.long.word 0x0C 0.--9. 1. " RHL1 ,Receive Header Length 1"
tree.end
tree "MAC FIFO Memory"
group 0x4000++0x03
hide.long 0x00 "MACFIFO,MAC FIFO RAM"
button "MACFIFO" "d sd:0x80014000++0x10FF /long"
tree.end
;end include file EP9301/LAN.ph
tree.end
tree "DMA Controller"
base 0x80000000
;begin include file EP9301/DMA.ph
;parameters:
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0000 0
tree "M2P Channel 0"
group 0x0000++7
line.long 0x00 "CONTROL,Channel 0 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (0==0||0==2||0==4||0==6||0==8)
group (0x0000+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (0==1||0==3||0==5||0==7||0==9)
group (0x0000+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0000+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0000+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0000+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0000+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0000+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0000+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0040 1
tree "M2P Channel 1"
group 0x0040++7
line.long 0x00 "CONTROL,Channel 1 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (1==0||1==2||1==4||1==6||1==8)
group (0x0040+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (1==1||1==3||1==5||1==7||1==9)
group (0x0040+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0040+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0040+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0040+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0040+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0040+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0040+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0080 2
tree "M2P Channel 2"
group 0x0080++7
line.long 0x00 "CONTROL,Channel 2 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (2==0||2==2||2==4||2==6||2==8)
group (0x0080+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (2==1||2==3||2==5||2==7||2==9)
group (0x0080+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0080+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0080+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0080+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0080+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0080+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0080+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x00C0 3
tree "M2P Channel 3"
group 0x00C0++7
line.long 0x00 "CONTROL,Channel 3 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (3==0||3==2||3==4||3==6||3==8)
group (0x00C0+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (3==1||3==3||3==5||3==7||3==9)
group (0x00C0+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x00C0+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x00C0+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x00C0+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x00C0+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x00C0+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x00C0+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2M.ph
;parameters: 0x0100 0
tree "M2M Channel 0"
group 0x0100++7
line.long 0x00 "CONTROL,Channel 0 Control Register"
hexmask.long.byte 0x00 25.--31. 1. " PSWC ,Peripheral Wait States Count"
bitfld.long 0x00 24. " NO-HDSK ,Handshake Protocol Requirement" "Required,Not required"
textline " "
bitfld.long 0x00 22.--23. " RSS ,Request Source Selection" "External Dreq,Internal SSPRx,Internal SSPTx,Internal IDE"
bitfld.long 0x00 21. " NFBIntEn ,Interrupt Generation in DMA_BUF_ON State" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19.--20. " DREQP ,DMA Request Pin Polarity" "Active low level sensitive,Active high level sensitive,Active low edge sensitive,Active high edge sensitive"
bitfld.long 0x00 17. " DACKP ,DMA Acknowledge Pin Polarity" "Active low,Active high"
textline " "
bitfld.long 0x00 16. " ERDP ,End of Transfer/Terminal Count Pin Direction & Polarity" "Active low,Active high"
bitfld.long 0x00 15. " ETDP ,End of Transfer/Terminal Count Pin Direction & Polarity" "Active low,Active high"
textline " "
bitfld.long 0x00 13.--14. " TM ,Transfer Mode" "Software initiated M2M,Hardware Initiated M2P,Hardware Initiated P2M,Not used"
bitfld.long 0x00 12. " SAH ,Source Address Hold" "Increment,Hold"
textline " "
bitfld.long 0x00 11. " DAH ,Destination Address Hold" "Increment,Hold"
bitfld.long 0x00 9.--10. " PW ,Peripheral Width" "Byte,Halfword,Word,Not used"
textline " "
bitfld.long 0x00 5.--8. " BWC ,Bandwidth Control" "Full,16,16,16,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
bitfld.long 0x00 4. " START ,Start Transfer" "Stopped,Started"
textline " "
bitfld.long 0x00 3. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " DONEIntEn ,DONE Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " SCT ,Source Copy Transfer" "Low,High"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 2. " NFBInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " DONEInt ,Transaction Done Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
rgroup (0x0100+0x000C)++0x03
line.long 0x00 "STATUS,Channel 0 Status Register"
bitfld.long 0x00 13. " DREQS ,DREQ Status" "0,1"
textline " "
bitfld.long 0x00 12. " NB ,Next Buffer Status Bit" "0,1"
textline " "
bitfld.long 0x00 11. " NFB ,Next Buffer during Transfer Programmed" "Yes,No"
textline " "
bitfld.long 0x00 9.--10. " EOTS ,End-of-Transfer Status" "Not requested for any descriptor,Requested for descriptor 0,Requested for descriptor 1,Requested for all descriptors"
textline " "
bitfld.long 0x00 7.--8. " TCS ,Terminal Count Status" "Not reached for buffer descriptor 0 & 1,Not reached for buffer descriptor only for 0,Not reached for buffer descriptor only for 1,Reached for all"
textline " "
bitfld.long 0x00 6. " DONE ,Transfer Completed Succefully" "Not succesfully,Succefully"
textline " "
bitfld.long 0x00 4.--5. " CurrentState[4:3] ,M2M Buffer FSM" "NO_BUF,BUF_ON,BUF_NEXT,?..."
textline " "
bitfld.long 0x00 1.--3. " CurrentState[2:0] ,M2M Channel Control FSM" "IDLE,STALL,MEM_RD,MEM_WR,BWC_WAIT,?..."
textline " "
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
group (0x0100+0x0010)++0x0F
line.long 0x00 "BCR0,Channel Byte Count Register 0"
hexmask.long.word 0x00 0.--15. 1. " BCR0 ,Channel Bytes Count"
line.long 0x04 "BCR1,Channel Byte Count Register 1"
hexmask.long.word 0x04 0.--15. 1. " BCR0 ,Channel Bytes Count"
line.long 0x08 "SAR_BASE0,Source Base Memory Address Register"
hexfld.long 0x08 " SAR_BASE0 ,Base Memory Address"
line.long 0x0C "SAR_BASE1,Source Base Memory Address Register"
hexfld.long 0x0C " SAR_BASE1 ,Base Memory Address"
rgroup (0x0100+0x0024)++7.
line.long 0x00 "SAR_CURRENT0,Source Base Memory Address Register 0"
hexfld.long 0x00 " SAR_CURRENT0 ,Base Memory Address"
line.long 0x04 "SAR_CURRENT1,Source Base Memory Address Register 1"
hexfld.long 0x04 " SAR_CURRENT1 ,Base Memory Address"
group (0x0100+0x002C)++7.
line.long 0x00 "DAR_BASE0,Destination Base Memory Address Register"
hexfld.long 0x00 " DAR_BASE0 ,Base Memory Address"
line.long 0x04 "DAR_BASE1,Destination Base Memory Address Register"
hexfld.long 0x04 " DAR_BASE1 ,Base Memory Address"
rgroup (0x0100+0x0034)++0x03
line.long 0x00 "DAR_CURRENT0,Destination Base Memory Address Register 0"
hexfld.long 0x00 " DAR_CURRENT0 ,Base Memory Address"
rgroup (0x0100+0x003C)++0x03
line.long 0x00 "DAR_CURRENT1,Destination Base Memory Address Register 0"
hexfld.long 0x00 " DAR_CURRENT1 ,Base Memory Address"
tree.end
;end include file EP9301/DMA/M2M.ph
;begin include file EP9301/DMA/M2M.ph
;parameters: 0x0140 1
tree "M2M Channel 1"
group 0x0140++7
line.long 0x00 "CONTROL,Channel 1 Control Register"
hexmask.long.byte 0x00 25.--31. 1. " PSWC ,Peripheral Wait States Count"
bitfld.long 0x00 24. " NO-HDSK ,Handshake Protocol Requirement" "Required,Not required"
textline " "
bitfld.long 0x00 22.--23. " RSS ,Request Source Selection" "External Dreq,Internal SSPRx,Internal SSPTx,Internal IDE"
bitfld.long 0x00 21. " NFBIntEn ,Interrupt Generation in DMA_BUF_ON State" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19.--20. " DREQP ,DMA Request Pin Polarity" "Active low level sensitive,Active high level sensitive,Active low edge sensitive,Active high edge sensitive"
bitfld.long 0x00 17. " DACKP ,DMA Acknowledge Pin Polarity" "Active low,Active high"
textline " "
bitfld.long 0x00 16. " ERDP ,End of Transfer/Terminal Count Pin Direction & Polarity" "Active low,Active high"
bitfld.long 0x00 15. " ETDP ,End of Transfer/Terminal Count Pin Direction & Polarity" "Active low,Active high"
textline " "
bitfld.long 0x00 13.--14. " TM ,Transfer Mode" "Software initiated M2M,Hardware Initiated M2P,Hardware Initiated P2M,Not used"
bitfld.long 0x00 12. " SAH ,Source Address Hold" "Increment,Hold"
textline " "
bitfld.long 0x00 11. " DAH ,Destination Address Hold" "Increment,Hold"
bitfld.long 0x00 9.--10. " PW ,Peripheral Width" "Byte,Halfword,Word,Not used"
textline " "
bitfld.long 0x00 5.--8. " BWC ,Bandwidth Control" "Full,16,16,16,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
bitfld.long 0x00 4. " START ,Start Transfer" "Stopped,Started"
textline " "
bitfld.long 0x00 3. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " DONEIntEn ,DONE Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " SCT ,Source Copy Transfer" "Low,High"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 2. " NFBInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " DONEInt ,Transaction Done Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
rgroup (0x0140+0x000C)++0x03
line.long 0x00 "STATUS,Channel 1 Status Register"
bitfld.long 0x00 13. " DREQS ,DREQ Status" "0,1"
textline " "
bitfld.long 0x00 12. " NB ,Next Buffer Status Bit" "0,1"
textline " "
bitfld.long 0x00 11. " NFB ,Next Buffer during Transfer Programmed" "Yes,No"
textline " "
bitfld.long 0x00 9.--10. " EOTS ,End-of-Transfer Status" "Not requested for any descriptor,Requested for descriptor 0,Requested for descriptor 1,Requested for all descriptors"
textline " "
bitfld.long 0x00 7.--8. " TCS ,Terminal Count Status" "Not reached for buffer descriptor 0 & 1,Not reached for buffer descriptor only for 0,Not reached for buffer descriptor only for 1,Reached for all"
textline " "
bitfld.long 0x00 6. " DONE ,Transfer Completed Succefully" "Not succesfully,Succefully"
textline " "
bitfld.long 0x00 4.--5. " CurrentState[4:3] ,M2M Buffer FSM" "NO_BUF,BUF_ON,BUF_NEXT,?..."
textline " "
bitfld.long 0x00 1.--3. " CurrentState[2:0] ,M2M Channel Control FSM" "IDLE,STALL,MEM_RD,MEM_WR,BWC_WAIT,?..."
textline " "
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
group (0x0140+0x0010)++0x0F
line.long 0x00 "BCR0,Channel Byte Count Register 0"
hexmask.long.word 0x00 0.--15. 1. " BCR0 ,Channel Bytes Count"
line.long 0x04 "BCR1,Channel Byte Count Register 1"
hexmask.long.word 0x04 0.--15. 1. " BCR0 ,Channel Bytes Count"
line.long 0x08 "SAR_BASE0,Source Base Memory Address Register"
hexfld.long 0x08 " SAR_BASE0 ,Base Memory Address"
line.long 0x0C "SAR_BASE1,Source Base Memory Address Register"
hexfld.long 0x0C " SAR_BASE1 ,Base Memory Address"
rgroup (0x0140+0x0024)++7.
line.long 0x00 "SAR_CURRENT0,Source Base Memory Address Register 0"
hexfld.long 0x00 " SAR_CURRENT0 ,Base Memory Address"
line.long 0x04 "SAR_CURRENT1,Source Base Memory Address Register 1"
hexfld.long 0x04 " SAR_CURRENT1 ,Base Memory Address"
group (0x0140+0x002C)++7.
line.long 0x00 "DAR_BASE0,Destination Base Memory Address Register"
hexfld.long 0x00 " DAR_BASE0 ,Base Memory Address"
line.long 0x04 "DAR_BASE1,Destination Base Memory Address Register"
hexfld.long 0x04 " DAR_BASE1 ,Base Memory Address"
rgroup (0x0140+0x0034)++0x03
line.long 0x00 "DAR_CURRENT0,Destination Base Memory Address Register 0"
hexfld.long 0x00 " DAR_CURRENT0 ,Base Memory Address"
rgroup (0x0140+0x003C)++0x03
line.long 0x00 "DAR_CURRENT1,Destination Base Memory Address Register 0"
hexfld.long 0x00 " DAR_CURRENT1 ,Base Memory Address"
tree.end
;end include file EP9301/DMA/M2M.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0200 5
tree "M2P Channel 5"
group 0x0200++7
line.long 0x00 "CONTROL,Channel 5 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (5==0||5==2||5==4||5==6||5==8)
group (0x0200+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (5==1||5==3||5==5||5==7||5==9)
group (0x0200+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0200+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0200+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0200+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0200+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0200+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0200+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0240 4
tree "M2P Channel 4"
group 0x0240++7
line.long 0x00 "CONTROL,Channel 4 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (4==0||4==2||4==4||4==6||4==8)
group (0x0240+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (4==1||4==3||4==5||4==7||4==9)
group (0x0240+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0240+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0240+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0240+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0240+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0240+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0240+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0280 7
tree "M2P Channel 7"
group 0x0280++7
line.long 0x00 "CONTROL,Channel 7 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (7==0||7==2||7==4||7==6||7==8)
group (0x0280+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (7==1||7==3||7==5||7==7||7==9)
group (0x0280+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0280+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0280+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0280+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0280+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0280+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0280+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x02C0 6
tree "M2P Channel 6"
group 0x02C0++7
line.long 0x00 "CONTROL,Channel 6 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (6==0||6==2||6==4||6==6||6==8)
group (0x02C0+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (6==1||6==3||6==5||6==7||6==9)
group (0x02C0+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x02C0+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x02C0+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x02C0+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x02C0+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x02C0+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x02C0+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0300 9
tree "M2P Channel 9"
group 0x0300++7
line.long 0x00 "CONTROL,Channel 9 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (9==0||9==2||9==4||9==6||9==8)
group (0x0300+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (9==1||9==3||9==5||9==7||9==9)
group (0x0300+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0300+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0300+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0300+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0300+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0300+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0300+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
;begin include file EP9301/DMA/M2P.ph
;parameters: 0x0340 8
tree "M2P Channel 8"
group 0x0340++7
line.long 0x00 "CONTROL,Channel 8 Control Register"
bitfld.long 0x00 6. " ICE ,Ignore Channel Error Bit" "Not ingored,Ignored"
bitfld.long 0x00 5. " ABORT ,Behaviour when NEXT and Periperal Error" "NEXT->ON,NEXT->STALL"
textline " "
bitfld.long 0x00 4. " ENABLE ,Channel Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CHErrorIntEn ,Channel Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NFBIntEn ,NFB Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " STALLIntEn ,STALL Interrupt Enable" "Disabled,Enabled"
line.long 0x04 "INTERRUPT,Interrupt Status Register"
bitfld.long 0x04 3. " ChErrorInt ,Data Stream Error Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 1. " NFBInt ,New Buffer Required Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " STALLInt ,Channel Stalled Interrupt" "No interrupt,Interrupt"
if (8==0||8==2||8==4||8==6||8==8)
group (0x0340+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT0,PORT2,PORT4,PORT6,PORT8,PORT10,PORT12,PORT14,PORT16,PORT18,Not used,Not used,Not used,Not used,Not used,Not used"
elif (8==1||8==3||8==5||8==7||8==9)
group (0x0340+0x0008)++0x03
line.long 0x00 "PPALLOC,Peripheral Port Allocation"
bitfld.long 0x00 0.--3. " PPALLOC ,Port Allocation" "PORT1,PORT3,PORT5,PORT7,PORT9,PORT11,PORT13,PORT15,PORT17,PORT19,Not used,Not used,Not used,Not used,Not used,Not used"
endif
rgroup (0x0340+0x000C)++0x03
line.long 0x00 "STATUS,Channel Status Register"
hexmask.long.byte 0x00 7.--11. 1. " BYTES ,Nuber of Valid DMA Data"
bitfld.long 0x00 6. " NextBuffer ,Next Free Buffer for Update" "MAXCNT0/BASE0,MAXCNT1/BASE1"
textline " "
bitfld.long 0x00 4.--5. " CurrentState ,Current Channel State" "IDLE,STALL,ON,NEXT"
bitfld.long 0x00 3. " ChError ,Buffer Transfer Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " NFB ,Channel FSM Moved from NEXT to ON" "Not in ON,In ON"
bitfld.long 0x00 0. " STALL ,Channel Stalled" "Not stalled,Stalled"
rgroup (0x0340+0x0014)++0x03
line.long 0x00 "REMAIN,Channel Bytes Remaining Register"
hexmask.long.word 0x00 0.--15. 1. " REMAIN ,Bytes Remaining"
group (0x0340+0x0020)++7
line.long 0x00 "MAXCNT0,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT0 ,Byte Count"
line.long 0x04 "BASE0,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE0 ,Base Address"
rgroup (0x0340+0x0028)++0x03
line.long 0x00 "CURRENT0,Channel Current Address Register"
hexfld.long 0x00 " CURRENT0 ,Current Address"
group (0x0340+0x0030)++7
line.long 0x00 "MAXCNT1,Maximum Byte Count Register"
hexmask.long.word 0x00 0.--15. 1. " MAXCNT1 ,Byte Count"
line.long 0x04 "BASE1,Base Address for Current and Next DMA Transfer"
hexfld.long 0x00 " BASE1 ,Base Address"
rgroup (0x0340+0x0038)++0x03
line.long 0x00 "CURRENT1,Channel Current Address Register"
hexfld.long 0x00 " CURRENT1 ,Current Address"
tree.end
;end include file EP9301/DMA/M2P.ph
textline ""
;begin include file EP9301/DMA/Global.ph
;parameters:
group 0x0380++0x03
line.long 0x00 "DMAChArb,DMA Channel Arbitration Register"
bitfld.long 0x00 11. " D11 ,M2M Channel 1 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 10. " D10 ,M2M Channel 0 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 9. " D9 ,M2P Channel 8 Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 8. " D8 ,M2P Channel 9 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 7. " D7 ,M2P Channel 6 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. " D6 ,M2P Channel 7 Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " D5 ,M2P Channel 4 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 4. " D4 ,M2P Channel 5 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 3. " D3 ,M2P Channel 2 Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 2. " D2 ,M2P Channel 3 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. " D1 ,M2P Channel 0 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 0. " D0 ,M2P Channel 1 Interrupt" "No interrupt,Interrupt"
group 0x03C0++0x03
line.long 0x00 "DMAGIInt,DMA Global Interrupt Register"
bitfld.long 0x00 0. " CHARB ,DMA Channel Arbitration" "Normal,Reversed"
;end include file EP9301/DMA/Global.ph
;end include file EP9301/DMA.ph
tree.end
tree "Universal Serial Bus Controller (USB)"
base 0x80020000
;begin include file EP9301/USB.ph
;parameters:
width 20. 8.
rgroup 0x0000++0x03
line.long 0x00 "HcRevision,Revision of OHCI Specification Register"
hexmask.long.byte 0x00 0.--7. 1. " REV ,HCI Specification Revision"
group 0x0004++0x13
line.long 0x00 "HcControl,Host Controller Operating Modes Register"
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Not connected,Connected"
bitfld.long 0x00 8. " IR ,Interrupt Routing" "Not routed,Routed"
textline " "
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State" "USBRESET,USBRESUME,USBOPERATIONAL,USBSUSPEND"
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio" "1:1,2:1,3:1,4:1"
line.long 0x04 "HcCommandStatus,Host Controller Status Register"
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "00,01,10,11"
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
textline " "
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
line.long 0x08 "HcInterruptStatus,Host Controller Interrupt Status Information Register"
bitfld.long 0x08 30. " OC ,Ownership Change" "Not changed,Changed"
bitfld.long 0x08 6. " RSHC ,Root Hub Status Change" "Not changed,Changed"
bitfld.long 0x08 5. " FNO ,Frame Number Overflow" "Not overflowed,Overflowed"
textline " "
bitfld.long 0x08 4. " UE ,Unrecoverable Error" "No error,Error"
bitfld.long 0x08 3. " RD ,Resume Detected" "Not detected,Detected"
bitfld.long 0x08 2. " SF ,Start of Frame" "Not started,Started"
textline " "
bitfld.long 0x08 1. " WDH ,Writeback Done Head" "Clear,HC written"
bitfld.long 0x08 0. " SO ,Scheduling Overrun" "Not overruned,Overruned"
line.long 0x0C "HcInterruptEnable,Host Controller Interrupt Enable Register"
bitfld.long 0x0C 31. " MIE ,Master Interrupt Enable" "No effect,Enabled"
bitfld.long 0x0C 30. " OC ,Ownership Change Interrupt Enable" "No effect,Enabled"
bitfld.long 0x0C 6. " RSHC ,Root Hub Status Change Interrupt Enable" "No effect,Enabled"
textline " "
bitfld.long 0x0C 5. " FNO ,Frame Number Overflow Interrupt Enable" "No effect,Enabled"
bitfld.long 0x0C 4. " UE ,Unrecoverable Error Interrupt Enable" "No effect,Enabled"
bitfld.long 0x0C 3. " RD ,Resume Detected Interrupt Enable" "No effect,Enabled"
textline " "
bitfld.long 0x0C 2. " SF ,Start of Frame Interrupt Enable" "No effect,Enabled"
bitfld.long 0x0C 1. " WDH ,Writeback Done Head Interrupt Enable" "No effect,Enabled"
bitfld.long 0x0C 0. " SO ,Scheduling Overrun Interrupt Enable" "No effect,Enabled"
line.long 0x10 "HcInterruptDisable,Host Controller Interrupt Disable Register"
bitfld.long 0x10 31. " MIE ,Master Interrupt Disable" "No effect,Disabled"
bitfld.long 0x10 30. " OC ,Ownership Change Interrupt Disable" "No effect,Disabled"
bitfld.long 0x10 6. " RSHC ,Root Hub Status Change Interrupt Disable" "No effect,Disabled"
textline " "
bitfld.long 0x10 5. " FNO ,Frame Number Overflow Interrupt Disable" "No effect,Disabled"
bitfld.long 0x10 4. " UE ,Unrecoverable Error Interrupt Disable" "No effect,Disabled"
bitfld.long 0x10 3. " RD ,Resume Detected Interrupt Disable" "No effect,Disabled"
textline " "
bitfld.long 0x10 2. " SF ,Start of Frame Interrupt Disable" "No effect,Disabled"
bitfld.long 0x10 1. " WDH ,Writeback Done Head Interrupt Disable" "No effect,Disabled"
bitfld.long 0x10 0. " SO ,Scheduling Overrun Interrupt Disable" "No effect,Disabled"
group 0x0018++0x1B
line.long 0x00 "HcHCCA,Host Controller Communication Area Register"
hexmask.long.tbyte 0x00 8.--31. 1. " AD ,Base Physical Address of Host Communication Area"
line.long 0x04 "HcPeriodCurrentED,Current Endpoint Descriptor Register"
hexmask.long.long 0x04 4.--31. 1. " AD ,Period Current ED Value"
line.long 0x08 "HcControlHeadED,First Endpoint Descriptor of the Control List Register"
hexmask.long.long 0x08 4.--31. 1. " AD ,Control Head ED Value"
line.long 0x0C "HcControlCurrentED,Current Endpoint Descriptor of the Control List Register"
hexmask.long.long 0x0C 4.--31. 1. " AD ,Control Current ED Value"
line.long 0x10 "HcBulkHeadED,First Endpoint Descriptor of the Bulk List Register"
hexmask.long.long 0x10 4.--31. 1. " AD ,Bulk Head ED Value"
line.long 0x14 "HcBulkCurrentED,Current Endpoint Descriptor of the Bulk List Register"
hexmask.long.long 0x14 4.--31. 1. " AD ,Bulk Current ED Value"
line.long 0x18 "HcDoneHead,Last Completed Transfer Descriptor Register"
hexmask.long.long 0x18 4.--31. 1. " AD ,Bulk Current ED Value"
group 0x0034++0x0B
line.long 0x00 "HcFmInterval,Time Interval in Frame Register"
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Larges Data Packet"
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
line.long 0x04 "HcFmRemaining,Time Remaining Register"
bitfld.long 0x04 31. " FRT ,Frame Remaining Toggle" "Low,High"
hexmask.long.word 0x04 0.--13. 1. " FR ,Frame Remaining"
line.long 0x08 "HcFmNumber,Timing Reference 16-bit Counter Register"
hexmask.long.word 0x08 0.--15. 1. " FN ,Frame Number"
group 0x0040++7
line.long 0x00 "HcPeriodicStart,Start Proccessing Time Register"
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start Value"
line.long 0x04 "HcHcLSTreshold,Time of LS Packet Transmission Register"
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Treshold"
group 0x0048++0x03
line.long 0x00 "HcRhDescriptorA,Root Hub Register A"
hexmask.long.byte 0x00 24.--31. 1. " P ,Power On to Power Good Time"
bitfld.long 0x00 12. " NOCP ,No Overcurrent Protection" "No protection,Protected"
textline " "
bitfld.long 0x00 11. " OCPM ,OverCurrent Protection Mode" "All ports,Per-port"
bitfld.long 0x00 10. " DT ,Device Type" "Not compound device,Reserved"
textline " "
bitfld.long 0x00 9. " NPS ,No Power Switching" "Power switched,Always on"
bitfld.long 0x00 8. " PSM ,Power Switching Mode" "At same time,Individually"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number of Downstream Ports"
group 0x004C++0x03
line.long 0x00 "HcRhDescriptorB,Root Hub Register B"
bitfld.long 0x00 19. " PPCM3 ,Port Power Control Mask Bit 3" "Global switch,Per-port control"
bitfld.long 0x00 18. " PPCM2 ,Port Power Control Mask Bit 2" "Global switch,Per-port control"
textline " "
bitfld.long 0x00 17. " PPCM1 ,Port Power Control Mask Bit 1" "Global switch,Per-port control"
bitfld.long 0x00 16. " PPCM0 ,Port Power Control Mask Bit 0" "Reserved..."
textline " "
bitfld.long 0x00 3. " DR3 ,Device Removable Bit 3" "Removable,Not removable"
bitfld.long 0x00 2. " DR2 ,Device Removable Bit 2" "Removable,Not removable"
textline " "
bitfld.long 0x00 1. " DR1 ,Device Removable Bit 1" "Removable,Not removable"
bitfld.long 0x00 0. " DR0 ,Device Removable Bit 0" "Reserved..."
rgroup 0x0050++0x03
line.long 0x00 "HcRhStatus(Read),Root Hub Status Register (Read)"
bitfld.long 0x00 17. " CCIC ,Overcurrent Indicator Change" "Not changed,Changed"
bitfld.long 0x00 16. " LPSC ,Read Local Power Status Change" "Low,High"
textline " "
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " OCI ,Overcurrent Indicator" "No overcurrend,Overcurrend"
textline " "
bitfld.long 0x00 0. " LPS ,Local Power Status" "Low,High"
wgroup 0x0050++0x03
line.long 0x00 "HcRhStatus(Write),Root Hub Status Register (Write)"
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
bitfld.long 0x00 17. " CCIC ,Overcurrent Indicator Change" "No effect,Changed"
textline " "
bitfld.long 0x00 16. " LPSC ,Set Global Power " "No effect,Power on"
bitfld.long 0x00 15. " DRWE ,Set Remote Wakeup Enable" "No effect,Enabled"
textline " "
bitfld.long 0x00 1. " OCI ,Overcurrent Indicator" "No overcurrend,Overcurrend"
bitfld.long 0x00 0. " LPS ,Clear Globlal Power" "No effect,Clear"
rgroup 0x0054++0x03
line.long 0x00 "HcRhPortStatus[1],Port 1 Control/Status Register (Read)"
bitfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not changed,Changed"
bitfld.long 0x00 19. " OCIC ,Port Overcurrent Indicator Status Change" "Not changed,Changed"
textline " "
bitfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not changed,Changed"
bitfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
textline " "
bitfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached" "Full speed,Low speed"
textline " "
bitfld.long 0x00 8. " PPS ,Power Port Status" "Power off,Power on"
bitfld.long 0x00 4. " PRS ,Port Reset Status" "No reset,Reset"
textline " "
bitfld.long 0x00 3. " POCI ,Port Overcurrent Indicator" "No overcurrend,Overcurrend"
bitfld.long 0x00 2. " PSS ,Port Suspend Status" "Not suspended,Suspended"
textline " "
bitfld.long 0x00 1. " PES ,Port Enable Status" "Disabled,Enabled"
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device connected"
wgroup 0x0054++0x03
line.long 0x00 "HcRhPortStatus[1],Port 1 Control/Status Register (Write)"
bitfld.long 0x00 9. " LSDA ,Clear Status Change" "No effect,Clear"
bitfld.long 0x00 8. " PPS ,Set Power Port" "No effect,Set"
textline " "
bitfld.long 0x00 4. " PRS ,Set Port Reset" "No effect,Reset"
bitfld.long 0x00 3. " POCI ,Clear Suspend Status" "No effect,Clear"
textline " "
bitfld.long 0x00 2. " PSS ,Set Port Suspend" "No effect,Set"
bitfld.long 0x00 1. " PES ,Set Port Enable" "No effect,Set"
textline " "
bitfld.long 0x00 0. " CCS ,Clear Port Enable" "No effect,Clear"
rgroup 0x005C++0x03
line.long 0x00 "HcRhPortStatus[2],Port 2 Control/Status Register (Read)"
bitfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not changed,Changed"
bitfld.long 0x00 19. " OCIC ,Port Overcurrent Indicator Status Change" "Not changed,Changed"
textline " "
bitfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not changed,Changed"
bitfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
textline " "
bitfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached" "Full speed,Low speed"
textline " "
bitfld.long 0x00 8. " PPS ,Power Port Status" "Power off,Power on"
bitfld.long 0x00 4. " PRS ,Port Reset Status" "No reset,Reset"
textline " "
bitfld.long 0x00 3. " POCI ,Port Overcurrent Indicator" "No overcurrend,Overcurrend"
bitfld.long 0x00 2. " PSS ,Port Suspend Status" "Not suspended,Suspended"
textline " "
bitfld.long 0x00 1. " PES ,Port Enable Status" "Disabled,Enabled"
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device connected"
wgroup 0x005C++0x03
line.long 0x00 "HcRhPortStatus[2],Port 2 Control/Status Register (Write)"
bitfld.long 0x00 9. " LSDA ,Clear Status Change" "No effect,Clear"
bitfld.long 0x00 8. " PPS ,Set Power Port" "No effect,Set"
textline " "
bitfld.long 0x00 4. " PRS ,Set Port Reset" "No effect,Reset"
bitfld.long 0x00 3. " POCI ,Clear Suspend Status" "No effect,Clear"
textline " "
bitfld.long 0x00 2. " PSS ,Set Port Suspend" "No effect,Set"
bitfld.long 0x00 1. " PES ,Set Port Enable" "No effect,Set"
textline " "
bitfld.long 0x00 0. " CCS ,Clear Port Enable" "No effect,Clear"
group 0x0080++0x03
line.long 0x00 "USBCfgCtrl,Through Software Configuration Register"
bitfld.long 0x00 4. " TRCS ,Counter Select Value" "Low,High"
bitfld.long 0x00 3. " TPOC3 ,Port 3 Disconnect Control" "Connected,Disconnected"
textline " "
bitfld.long 0x00 2. " TPOC2 ,Port 2 Disconnect Control" "Connected,Disconnected"
bitfld.long 0x00 1. " TPOC1 ,Port 1 Disconnect Control" "Connected,Disconnected"
group 0x0084++0x03
line.long 0x00 "USBHCISts,Host Controller Interface"
bitfld.long 0x00 2. " RWU ,Host Controller Remote Wakeup" "No wakeup,Wakeup"
bitfld.long 0x00 1. " MSN ,Host Controller New Frame" "No new frame,New frame"
textline " "
bitfld.long 0x00 0. " MBA ,Host Controller Buffer Access Indication" "Not accessing,Accessing"
width 16. 8.
;end include file EP9301/USB.ph
tree.end
tree "Static Memory Controller"
base 0x80080000
;begin include file EP9301/Memory.ph
;parameters: 0x0000 0
group 0x0000++0x03
line.long 0x00 "SMCBCR0,Bank Config Register 0"
bitfld.long 0x00 30. " EBIBRKDIS ,EBI Break Disable" "Enabled,Disabled"
bitfld.long 0x00 28.--29. " MW ,Memory Width" "8-bit,16-bit,32-bit,32-bit"
bitfld.long 0x00 27. " PME ,Page Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " WP ,Write Protect" "SDRAM,ROM and RAM"
bitfld.long 0x00 25. " WPERR ,Write Protection Error Status" "No error,Error"
hexmask.long.byte 0x00 11.--15. 1. " WST2 ,Wait State 2"
textline " "
bitfld.long 0x00 10. " RBLE ,Read Byte Lane Enable" "Driven high,Driven low"
hexmask.long.byte 0x00 5.--9. 1. " WST1 ,Wait State 1"
hexmask.long.byte 0x00 0.--3. 1. " IDCY ,Idle Cycle"
;end include file EP9301/Memory.ph
;begin include file EP9301/Memory.ph
;parameters: 0x0004 1
group 0x0004++0x03
line.long 0x00 "SMCBCR1,Bank Config Register 1"
bitfld.long 0x00 30. " EBIBRKDIS ,EBI Break Disable" "Enabled,Disabled"
bitfld.long 0x00 28.--29. " MW ,Memory Width" "8-bit,16-bit,32-bit,32-bit"
bitfld.long 0x00 27. " PME ,Page Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " WP ,Write Protect" "SDRAM,ROM and RAM"
bitfld.long 0x00 25. " WPERR ,Write Protection Error Status" "No error,Error"
hexmask.long.byte 0x00 11.--15. 1. " WST2 ,Wait State 2"
textline " "
bitfld.long 0x00 10. " RBLE ,Read Byte Lane Enable" "Driven high,Driven low"
hexmask.long.byte 0x00 5.--9. 1. " WST1 ,Wait State 1"
hexmask.long.byte 0x00 0.--3. 1. " IDCY ,Idle Cycle"
;end include file EP9301/Memory.ph
;begin include file EP9301/Memory.ph
;parameters: 0x0008 2
group 0x0008++0x03
line.long 0x00 "SMCBCR2,Bank Config Register 2"
bitfld.long 0x00 30. " EBIBRKDIS ,EBI Break Disable" "Enabled,Disabled"
bitfld.long 0x00 28.--29. " MW ,Memory Width" "8-bit,16-bit,32-bit,32-bit"
bitfld.long 0x00 27. " PME ,Page Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " WP ,Write Protect" "SDRAM,ROM and RAM"
bitfld.long 0x00 25. " WPERR ,Write Protection Error Status" "No error,Error"
hexmask.long.byte 0x00 11.--15. 1. " WST2 ,Wait State 2"
textline " "
bitfld.long 0x00 10. " RBLE ,Read Byte Lane Enable" "Driven high,Driven low"
hexmask.long.byte 0x00 5.--9. 1. " WST1 ,Wait State 1"
hexmask.long.byte 0x00 0.--3. 1. " IDCY ,Idle Cycle"
;end include file EP9301/Memory.ph
;begin include file EP9301/Memory.ph
;parameters: 0x000C 3
group 0x000C++0x03
line.long 0x00 "SMCBCR3,Bank Config Register 3"
bitfld.long 0x00 30. " EBIBRKDIS ,EBI Break Disable" "Enabled,Disabled"
bitfld.long 0x00 28.--29. " MW ,Memory Width" "8-bit,16-bit,32-bit,32-bit"
bitfld.long 0x00 27. " PME ,Page Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " WP ,Write Protect" "SDRAM,ROM and RAM"
bitfld.long 0x00 25. " WPERR ,Write Protection Error Status" "No error,Error"
hexmask.long.byte 0x00 11.--15. 1. " WST2 ,Wait State 2"
textline " "
bitfld.long 0x00 10. " RBLE ,Read Byte Lane Enable" "Driven high,Driven low"
hexmask.long.byte 0x00 5.--9. 1. " WST1 ,Wait State 1"
hexmask.long.byte 0x00 0.--3. 1. " IDCY ,Idle Cycle"
;end include file EP9301/Memory.ph
;begin include file EP9301/Memory.ph
;parameters: 0x0018 6
group 0x0018++0x03
line.long 0x00 "SMCBCR6,Bank Config Register 6"
bitfld.long 0x00 30. " EBIBRKDIS ,EBI Break Disable" "Enabled,Disabled"
bitfld.long 0x00 28.--29. " MW ,Memory Width" "8-bit,16-bit,32-bit,32-bit"
bitfld.long 0x00 27. " PME ,Page Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " WP ,Write Protect" "SDRAM,ROM and RAM"
bitfld.long 0x00 25. " WPERR ,Write Protection Error Status" "No error,Error"
hexmask.long.byte 0x00 11.--15. 1. " WST2 ,Wait State 2"
textline " "
bitfld.long 0x00 10. " RBLE ,Read Byte Lane Enable" "Driven high,Driven low"
hexmask.long.byte 0x00 5.--9. 1. " WST1 ,Wait State 1"
hexmask.long.byte 0x00 0.--3. 1. " IDCY ,Idle Cycle"
;end include file EP9301/Memory.ph
;begin include file EP9301/Memory.ph
;parameters: 0x001C 7
group 0x001C++0x03
line.long 0x00 "SMCBCR7,Bank Config Register 7"
bitfld.long 0x00 30. " EBIBRKDIS ,EBI Break Disable" "Enabled,Disabled"
bitfld.long 0x00 28.--29. " MW ,Memory Width" "8-bit,16-bit,32-bit,32-bit"
bitfld.long 0x00 27. " PME ,Page Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " WP ,Write Protect" "SDRAM,ROM and RAM"
bitfld.long 0x00 25. " WPERR ,Write Protection Error Status" "No error,Error"
hexmask.long.byte 0x00 11.--15. 1. " WST2 ,Wait State 2"
textline " "
bitfld.long 0x00 10. " RBLE ,Read Byte Lane Enable" "Driven high,Driven low"
hexmask.long.byte 0x00 5.--9. 1. " WST1 ,Wait State 1"
hexmask.long.byte 0x00 0.--3. 1. " IDCY ,Idle Cycle"
;end include file EP9301/Memory.ph
tree.end
tree "SDRAM,SyncROM and SyncFLASH Controller"
base 0x80060000
;begin include file EP9301/SDRAM.ph
;parameters:
group 0x0004++7
line.long 0x00 "GIConfig,Global Configuration Register"
bitfld.long 0x00 31. " CKE ,Synchronous Memory Clock Enable Control" "Disabled,Enabled"
bitfld.long 0x00 30. " ClkShutdown ,Synchronous Memory Clock Shutdown Control" "Free running,Gated"
textline " "
bitfld.long 0x00 7. " ReArbEn ,Rearbitration Controller Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " LCR ,Load Command Register" "Clear,Set"
textline " "
bitfld.long 0x00 5. " SMEMBust ,Synchronous Memory Mode Register" "Idle,Busy"
bitfld.long 0x00 1. " MRS ,Synchronous Memory Mode Register" "Clear,Set"
textline " "
bitfld.long 0x00 0. " Initialize ,Initialize Bit" "Clear,Set"
line.long 0x04 "RefreshTimr,Refresh Timer Register"
hexmask.long.word 0x04 0.--15. 1. " RefCnt ,Refresh Count"
rgroup 0x000C++0x03
line.long 0x00 "BootSts,Boot Status"
bitfld.long 0x00 2. " LatchedASDO ,Boot Media" "Asynchronous ROM,Synchronous ROM"
bitfld.long 0x00 0.--1. " Width ,Boot Memory Width" "8-bit,16-bit,32-bit,32-bit"
group 0x0010++0x0F
line.long 0x00 "SDRAMDevCfg0,Device Configuration 0"
bitfld.long 0x00 24. " AutoPrecharge ,Auto Precharge" "No auto,Auto"
bitfld.long 0x00 20.--21. " RasToCas ,Synchronous Memory RAS to CAS Latency" "Reserved,Reserved,2,3"
textline " "
bitfld.long 0x00 19. " WBL ,Write Burst Length" "Low,High"
bitfld.long 0x00 16.--18. " CasLat ,Synchronous Memory CAS Latency" "Reserved,2,3,4,5,6,7,8"
textline " "
bitfld.long 0x00 7. " SFConfigAddr ,Configuration Address Register Read" "Normal,SyncFLASH"
bitfld.long 0x00 6. " 2KPAGE ,Synchronous Memory 2 KByte Page Mode" "Not 2K,2 KByte"
textline " "
bitfld.long 0x00 5. " SROMLL ,SROM Lookalike Mode" "Clear,Set"
bitfld.long 0x00 4. " SROM512 ,SROM Maximum Burst Size=512" "Not 512 depth,Depth 512"
textline " "
bitfld.long 0x00 3. " BankCount ,Bank Count" "Two-bank,Four-bank"
line.long 0x04 "SDRAMDevCfg1,Device Configuration 1"
bitfld.long 0x04 24. " AutoPrecharge ,Auto Precharge" "No auto,Auto"
bitfld.long 0x04 20.--21. " RasToCas ,Synchronous Memory RAS to CAS Latency" "Reserved,Reserved,2,3"
textline " "
bitfld.long 0x04 19. " WBL ,Write Burst Length" "Low,High"
bitfld.long 0x04 16.--18. " CasLat ,Synchronous Memory CAS Latency" "Reserved,2,3,4,5,6,7,8"
textline " "
bitfld.long 0x04 7. " SFConfigAddr ,Configuration Address Register Read" "Normal,SyncFLASH"
bitfld.long 0x04 6. " 2KPAGE ,Synchronous Memory 2 KByte Page Mode" "Not 2K,2 KByte"
textline " "
bitfld.long 0x04 5. " SROMLL ,SROM Lookalike Mode" "Clear,Set"
bitfld.long 0x04 4. " SROM512 ,SROM Maximum Burst Size=512" "Not 512 depth,Depth 512"
textline " "
bitfld.long 0x04 3. " BankCount ,Bank Count" "Two-bank,Four-bank"
line.long 0x08 "SDRAMDevCfg2,Device Configuration 2"
bitfld.long 0x08 24. " AutoPrecharge ,Auto Precharge" "No auto,Auto"
bitfld.long 0x08 20.--21. " RasToCas ,Synchronous Memory RAS to CAS Latency" "Reserved,Reserved,2,3"
textline " "
bitfld.long 0x08 19. " WBL ,Write Burst Length" "Low,High"
bitfld.long 0x08 16.--18. " CasLat ,Synchronous Memory CAS Latency" "Reserved,2,3,4,5,6,7,8"
textline " "
bitfld.long 0x08 7. " SFConfigAddr ,Configuration Address Register Read" "Normal,SyncFLASH"
bitfld.long 0x08 6. " 2KPAGE ,Synchronous Memory 2 KByte Page Mode" "Not 2K,2 KByte"
textline " "
bitfld.long 0x08 5. " SROMLL ,SROM Lookalike Mode" "Clear,Set"
bitfld.long 0x08 4. " SROM512 ,SROM Maximum Burst Size=512" "Not 512 depth,Depth 512"
textline " "
bitfld.long 0x08 3. " BankCount ,Bank Count" "Two-bank,Four-bank"
bitfld.long 0x08 2. " ExtBusWidth ,External Bus Width" "32-bits,16-bits"
line.long 0x0C "SDRAMDevCfg3,Device Configuration 3"
bitfld.long 0x0C 24. " AutoPrecharge ,Auto Precharge" "No auto,Auto"
bitfld.long 0x0C 20.--21. " RasToCas ,Synchronous Memory RAS to CAS Latency" "Reserved,Reserved,2,3"
textline " "
bitfld.long 0x0C 19. " WBL ,Write Burst Length" "Low,High"
bitfld.long 0x0C 16.--18. " CasLat ,Synchronous Memory CAS Latency" "Reserved,2,3,4,5,6,7,8"
textline " "
bitfld.long 0x0C 7. " SFConfigAddr ,Configuration Address Register Read" "Normal,SyncFLASH"
bitfld.long 0x0C 6. " 2KPAGE ,Synchronous Memory 2 KByte Page Mode" "Not 2K,2 KByte"
textline " "
bitfld.long 0x0C 5. " SROMLL ,SROM Lookalike Mode" "Clear,Set"
bitfld.long 0x0C 4. " SROM512 ,SROM Maximum Burst Size=512" "Not 512 depth,Depth 512"
textline " "
bitfld.long 0x0C 3. " BankCount ,Bank Count" "Two-bank,Four-bank"
;end include file EP9301/SDRAM.ph
tree.end
tree "UART1 With HDLC and Modem Control Signals"
base 0x808C0000
;begin include file EP9301/UART1.ph
;parameters:
width 20. 8.
tree "UART Registers"
group 0x0000++0x17
line.long 0x00 "UART1Data,UART1 Data Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,UART Data"
line.long 0x04 "UART1RXSts,UART1 Receive Status Register/Error Clear Register"
bitfld.long 0x04 3. " OE ,Overrun Error" "No error,Error"
bitfld.long 0x04 2. " BE ,Break Error" "No error,Error"
textline " "
bitfld.long 0x04 1. " PE ,Parity Error" "No error,Error"
bitfld.long 0x04 0. " FE ,Framing Error" "No error,Error"
line.long 0x08 "UART1LinCtrlHigh,UART1 Line Control Register High"
bitfld.long 0x08 5.--6. " WLEN ,Number of Bits per Frame" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x08 4. " FEN ,FIFO Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "One bit,Two bits"
bitfld.long 0x08 2. " EPS ,Even Parity Select" "Odd,Even"
textline " "
bitfld.long 0x08 1. " PEN ,Parity Enable" "Disabled,Enabled"
bitfld.long 0x08 0. " BRK ,Send Break" "Normal,Output low"
line.long 0x0C "UART1LinCtrlMid,UART1 Line Control Register Middle"
hexmask.long.byte 0x0C 0.--7. 1. " BR ,Baud Rate Divisior Bits 15-8"
line.long 0x10 "UART1LinCtrlLow,UART1 Line Control Register Low"
hexmask.long.byte 0x10 0.--7. 1. " BR ,Baud Rate Divisior 7-0"
line.long 0x14 "UART1Ctrl,UART1 Control Register"
bitfld.long 0x14 7. " LBE ,Loopback Enable" "Disabled,Enabled"
bitfld.long 0x14 6. " RTIE ,Receive Timeout" "Disabled,Enabled"
textline " "
bitfld.long 0x14 5. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x14 4. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " MSIE ,Modem Status Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x14 0. " UARTE ,UART Enable" "Disabled,Enabled"
rgroup 0x0018++0x03
line.long 0x00 "UART1Flag,UART1 Flag Register"
bitfld.long 0x00 7. " TXFE ,Transmit FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full"
textline " "
bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full"
bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " BUSY ,UART Busy" "Not busy,Busy"
bitfld.long 0x00 2. " DCD ,Data Carrier Detect Status" "Clear,Set"
textline " "
bitfld.long 0x00 1. " DSR ,Data Set Ready Status" "Not ready,Ready"
bitfld.long 0x00 0. " CTS ,Clear To Send Status" "Not clear,Clear"
group 0x001C++0x03
line.long 0x00 "UART1IntIDIntClr,UART1 Interrupt Identification and Interrupt Clear Register"
bitfld.long 0x00 3. " RTIS ,Receive Timeout Interrupt Status" "Clear,Set"
bitfld.long 0x00 2. " TIS ,Transmit Interrupt Status" "FIFO full,FIFO not full"
textline " "
bitfld.long 0x00 1. " RIS ,Receive Interrupt Status" "FIFO empty,FIFO not empty"
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
group 0x0028++0x03
line.long 0x00 "UART1DMACtrl,UART1 DMA Control Register"
bitfld.long 0x00 2. " DMAERR ,RX DMA Error Handling Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TXDMAE ,TX DMA Interface Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " RXDMAE ,RX DMA Interface Enable" "Disabled,Enabled"
tree.end
tree "Modem Registers"
group 0x0100++0x03
line.long 0x00 "UART1ModemCtrl,UART1 Modem Control Register"
bitfld.long 0x00 4. " LOOP ,Loopback Function Control" "No loopback,Loopback"
bitfld.long 0x00 3. " OUT2 ,OUT2 Function" "Clear,Set"
textline " "
bitfld.long 0x00 2. " OUT1 ,OUT1 Function" "Clear,Set"
bitfld.long 0x00 1. " RTS ,RTS Output Signal" "RTSn low,RTSn high"
textline " "
bitfld.long 0x00 0. " DTR ,DTR Output Signal" "DTRn low,DTRn high"
rgroup 0x0104++0x03
line.long 0x00 "UART1ModemSts,UART1 Modem Status Register"
bitfld.long 0x00 7. " DCD ,Inverse of DCDn Input Pin" "Not inversed,Inversed"
bitfld.long 0x00 6. " RI ,Inverse of RI Input Pin" "Not inversed,Inversed"
textline " "
bitfld.long 0x00 5. " DSR ,Inverse of DSR Input Pin" "Not inversed,Inversed"
bitfld.long 0x00 4. " CTS ,Inverse of CTS Input Pin" "Not inversed,Inversed"
textline " "
bitfld.long 0x00 3. " DDCD ,Delta DCD-DCDn Pin Change" "Not changed,Changed"
bitfld.long 0x00 2. " TERI ,Trailing Edge Ring Indicator" "RI not changed,RI not changed"
textline " "
bitfld.long 0x00 1. " DDSR ,Delta DSR-DSRn Pin Change" "Not changed,Changed"
bitfld.long 0x00 0. " DCTS ,Delta CTS-CTSn Pin Change" "Not changed,Changed"
tree.end
tree "HDLC Registers"
group 0x020C++0x03
line.long 0x00 "UART1HDLCtrl,HDLC Control Register"
bitfld.long 0x00 27. " CMAS ,Clock Master" "Internal,External"
bitfld.long 0x00 26. " TXCM ,Transmit Clock Mode" "Do not generate,Generate"
textline " "
bitfld.long 0x00 25. " RXCM ,Receive Clock Mode" "Do not generate,Generate"
bitfld.long 0x00 24. " TXENC ,Transmit Encoding Method" "NRZ,Manchester"
textline " "
bitfld.long 0x00 23. " RXENC ,Receive Encoding Method" "NRZ,Manchester"
bitfld.long 0x00 22. " SYNC ,Synchronous/Asynchronous HDLC Mode" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 21. " TFCEN ,Transmit Frame Complete Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TABEN ,Transmit Frame Abort Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " RFCEN ,Receive Frame Complete Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " RILEN ,Receive Information Lost Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 17. " RFLEN ,Receive Frame Lost Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " RTOEN ,Receiver Time Out Interrupt Enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--15. 1. " FLAG ,Minimum Number of Opening and CLosing Flags for HDLC TX"
bitfld.long 0x00 11. " CRCN ,CRC Polarity Control" "CRC not inverted,CRC inverted"
textline " "
bitfld.long 0x00 10. " CRCApd ,CRC Pass Through" "Not passed,Passed"
bitfld.long 0x00 9. " IDLE ,Idle Mode" "Mark mode,Flag mode"
textline " "
bitfld.long 0x00 7.--8. " AME ,Address Match Enable" "No address,4x1 byte,2x2 byte,Undefined"
bitfld.long 0x00 6. " IDLSpec ,Idle in Space" "In mark,In space"
textline " "
bitfld.long 0x00 5. " CRCZ ,CRC Zero Seed" "All ones,All zeros"
bitfld.long 0x00 4. " RXE ,HDLC Receive Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " TXE ,HDLC Transmit Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " TUS ,Transmit FIFO Underrun Select" "Transmit stop,Transmit abort"
textline " "
bitfld.long 0x00 1. " CRCR ,CRC Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " CRCS ,CRC Size" "CRC-CCITT,CRC-32"
group 0x0210++7
line.long 0x00 "UART1HDLCAddMtchVal,HDLC Address Match Register"
hexfld.long 0x00 " AMV ,Address Match Value"
line.long 0x04 "UART1HDLCAddMask,HDLC Address Mask Register"
hexfld.long 0x04 " AMSK ,Address Mask Value"
rgroup 0x0218++0x03
line.long 0x00 "UART1HDLCRXInfoBuf,HDLC Receive Information Buffer Register"
bitfld.long 0x00 17. " BPLLE ,Buffer Digital PLL Error" "Not aborted,Aborted"
hexmask.long.word 0x00 4.--14. 1. " BC ,Received Frame Byte Count"
textline " "
bitfld.long 0x00 3. " BFRE ,Buffered Framing Error" "No error,Error"
bitfld.long 0x00 2. " BROR ,Buffered Receiver Over Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " BRCE ,Buffered CRC Error" "No error,Error"
bitfld.long 0x00 0. " BRAB ,Buffered Receiver Error" "No error,Error"
group 0x021C++0x03
line.long 0x00 "UART1HDLCSts,HDLC Status Register"
bitfld.long 0x00 17. " PLLE ,Digital PLL Error" "No error,Error"
bitfld.long 0x00 16. " PLLCC ,Digital PLL Carrier Sense" "Not sensed,Sensed"
textline " "
bitfld.long 0x00 15. " LNKIDL ,Link Idle" "RX not changed,RX changed"
bitfld.long 0x00 14. " CRE ,CRC Error" "No CRC,CRC"
textline " "
bitfld.long 0x00 13. " ROR ,Receive FIFO Overrun" "Not overruned,Overruned"
bitfld.long 0x00 12. " TBY ,Transmitter Busy" "Not busy,Busy"
textline " "
bitfld.long 0x00 11. " RIF ,Receiver In Frame" "Idle,Receiving frame"
bitfld.long 0x00 9. " RAB ,Receiver Abort" "Not aborted,Aborted"
textline " "
bitfld.long 0x00 8. " RTO ,Receiver Time Out" "Set,Clear"
bitfld.long 0x00 7. " EOF ,End of Frame" "No end of frame,End of frame"
textline " "
bitfld.long 0x00 6. " RFL ,Receive Frame Lost" "Not lost,Lost"
bitfld.long 0x00 5. " RIL ,Receive Information Buffer Lost" "Not lost,Lost"
textline " "
bitfld.long 0x00 4. " RFC ,Receive Frame Complete" "Not completed,Completed"
bitfld.long 0x00 3. " RFS ,Receive FIFO Service Request" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " TAB ,Transmitted Frame Aborted" "Not aborted,Aborted"
bitfld.long 0x00 1. " TFC ,Transmit Frame Complete" "Not completed,Completed"
textline " "
bitfld.long 0x00 0. " TFS ,Transmit FIFO Service Request" "FIFO full TX disabled,FIFO not full TX enabled"
tree.end
width 16. 8.
;end include file EP9301/UART1.ph
tree.end
tree "UART2"
base 0x808D0000
;begin include file EP9301/UART2.ph
;parameters:
width 18. 8.
group 0x0000++0x17
line.long 0x00 "UART2Data,UART Data Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,UART Data"
line.long 0x04 "UART2RXSts,UART Receive Status Register aand Error Clear Register"
bitfld.long 0x04 3. " OE ,Overrun Error" "No error,Error"
bitfld.long 0x04 2. " BE ,Break Error" "No error,Error"
textline " "
bitfld.long 0x04 1. " PE ,Parity Error" "No error,Error"
bitfld.long 0x04 0. " FE ,Framing Error" "No error,Error"
line.long 0x08 "UART2LinCtrlHigh,UART Line Control High Register"
bitfld.long 0x08 5.--6. " WLEN ,Number of Bits per Frame" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x08 4. " FEN ,FIFO Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "One bit,Two bits"
bitfld.long 0x08 2. " EPS ,Even Parity Select" "Odd,Even"
textline " "
bitfld.long 0x08 1. " PEN ,Parity Enable" "Disabled,Enabled"
bitfld.long 0x08 0. " BRK ,Send Break" "Normal,Output low"
line.long 0x0C "UART2LinCtrlMid,UART Line Control Midle Register"
hexmask.long.byte 0x0C 0.--7. 1. " BR ,Baud Rate Divisior 15-8"
line.long 0x10 "UART2LinCtrlLow,UART Line Control Low Register"
hexmask.long.byte 0x10 0.--7. 1. " BR ,Baud Rate Divisior 7-0"
line.long 0x14 "UART2Ctrl,UART Control Register"
bitfld.long 0x14 7. " LBE ,Loopback Enable" "Disabled,Enabled"
bitfld.long 0x14 6. " RTIE ,Receive Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 5. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x14 4. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " MSIE ,Modem Status Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x14 2. " SIRLP ,SIR Low Power Mode" "Normal,Low power"
textline " "
bitfld.long 0x14 1. " SIEN ,SIE Enable" "Disabled,Enabled"
bitfld.long 0x14 0. " UARTE ,UART Enable" "Disabled,Enabled"
rgroup 0x0018++0x03
line.long 0x00 "UART2Flag,UART Flag Register"
bitfld.long 0x00 7. " TXFE ,Transmit FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full"
textline " "
bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full"
bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " BUSY ,UART Busy" "Not busy,Busy"
bitfld.long 0x00 2. " DCD ,Data Carrier Detect Status" "Clear,Set"
textline " "
bitfld.long 0x00 1. " DSR ,Data Set Ready Status" "Not ready,Ready"
bitfld.long 0x00 0. " CTS ,Clear To Send Status" "Not clear,Clear"
group 0x001C++0x03
line.long 0x00 "UART1IntIDIntClr,UART1 Interrupt Identification and Interrupt Clear Register"
bitfld.long 0x00 3. " RTIS ,Receive Timeout Interrupt Status" "Clear,Set"
bitfld.long 0x00 2. " TIS ,Transmit Interrupt Status" "FIFO full,FIFO not full"
textline " "
bitfld.long 0x00 1. " RIS ,Receive Interrupt Status" "FIFO empty,FIFO not empty"
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
group 0x0020++0x0B
line.long 0x00 "UART2IrLowPwrCntr,UART IrDA Low Power Divisior Register"
hexmask.long.byte 0x00 0.--7. 1. " ILPDV ,IrDA Low Power Divisior Bits"
line.long 0x04 "UART2DMACtrl,UART DMA Control Register"
bitfld.long 0x04 2. " DMAERR ,RX DMA Error Handling Enable" "Disabled,Enabled"
bitfld.long 0x04 1. " TXDMAE ,TX DMA Interface Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " RXDMAE ,RX DMA Interface Enable" "Disabled,Enabled"
line.long 0x08 "UART2TMR,UART SIR Loopback Register"
bitfld.long 0x08 1. " SIRTEST ,SIR Test Enable" "Disabled,Enabled"
;end include file EP9301/UART2.ph
tree.end
tree "IrDA"
base 0x808B0000
;begin include file EP9301/IrDA.ph
;parameters:
width 16. 8.
group 0x0000++0x0B
line.long 0x00 "IrEnable,IrDA Enable Register"
bitfld.long 0x00 4. " FD ,Fast Done Status" "Not done,Done"
bitfld.long 0x00 3. " MD ,Medium Done Status" "Not done,Done"
textline " "
bitfld.long 0x00 2. " LBM ,Loopback Mode" "Normal,Loopback"
bitfld.long 0x00 0.--1. " EN ,Enable Value" "No encoder,SIR,MIR,FIR"
line.long 0x04 "IrCtrl,IrDA Control Register"
bitfld.long 0x04 7. " AME ,Address Match Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " RXP ,Receve Polarity Control" "Not inverted,Inverted"
textline " "
bitfld.long 0x04 5. " TXP ,Transmit Polarity Control" "Not inverted,Inverted"
bitfld.long 0x04 4. " RXE ,Receiver Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " TXE ,Transmit Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " TUS ,Transmit Buffer Underrun Select" "Causes stop flag,Causes abort"
textline " "
bitfld.long 0x04 1. " BRD ,MIR Bit Rate Select" "0.576Mbit/s,1.152Mbit/s"
line.long 0x08 "IrAdrMatchVal,IrDA Address Match Value Register"
hexmask.long.word 0x08 0.--7. 1. " AMV , Address Match Value"
rgroup 0x000C++0x03
line.long 0x00 "IrFlag,IrDA Flag Register"
bitfld.long 0x00 9. " TBY ,Transmitter Busy Flag" "Not busy,Busy"
bitfld.long 0x00 8. " RIF ,Receive In Frame" "In preamble/start,In frame"
textline " "
bitfld.long 0x00 7. " RSY ,Receiver Synchronized Flag" "Hunt mode,Sychronized"
bitfld.long 0x00 6. " EOF ,End of Frame" "Frame not completed,Frame completed"
textline " "
bitfld.long 0x00 4.--5. " WST ,Width Status" "All valid,Least byte,Least two,Least three"
bitfld.long 0x00 3. " FRE ,FIR Framing Error" "No error,Error"
textline " "
bitfld.long 0x00 2. " ROR ,Receive Buffer Overrun" "Not overruned,Overruned"
bitfld.long 0x00 1. " CRE ,CRC Error" "No error,Error"
textline " "
bitfld.long 0x00 0. " RAB ,Receiver Abort" "Not aborted,Aborted"
group 0x0010++0x03
line.long 0x00 "IrData,IrDA Data Register"
hexfld.long 0x00 " DATA ,IrDA Data Word"
wgroup 0x0014++0x0B
line.long 0x00 "IrDataTail,IrDA Data Tail Register"
hexfld.long 0x00 " DATA ,IrDA Transmit Payload Data"
line.long 0x04 "IrDataTail,IrDA Data Tail Register"
hexfld.long 0x04 " DATA ,IrDA Transmit Payload Data"
line.long 0x08 "IrDataTail,IrDA Data Tail Register"
hexfld.long 0x08 " DATA ,IrDA Transmit Payload Data"
rgroup 0x0020++7
line.long 0x00 "IrRIB,IrDA Receive Information Register"
hexmask.long.word 0x00 4.--14. 1. " BC ,Received Frame Byte Count"
bitfld.long 0x00 3. " BFRE ,Buffered Framing Error" "No error,Error"
textline " "
bitfld.long 0x00 2. " BROR ,Buffered Receiver Over Error" "No error,Error"
bitfld.long 0x00 1. " BRCE ,Buffered CRC Error" "No error,Error"
textline " "
bitfld.long 0x00 0. " BRAB ,Buffered Receiver Error" "No error,Error"
line.long 0x04 "IrTR0,IrDA Test Register 0"
hexmask.long.word 0x04 0.--10. 1. " BC ,Byte Count"
group 0x0028++0x03
line.long 0x00 "IrDMACR,IrDA DMA Control Register"
bitfld.long 0x00 2. " DMAERR ,RX DMA Error Handling Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TXDAE ,TX DMA Interface Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " RXDMAE ,RX DMA Interface Enable" "Disabled,Enabled"
group 0x0030++0x03
line.long 0x00 "SIRTR0,IrDA Slow InfraRed Test Register 0"
bitfld.long 0x00 7. " SIREN ,State of SIERN After Synchronization" "Low,High"
bitfld.long 0x00 6. " SIROUT ,State of SIROUT" "Low,High"
textline " "
bitfld.long 0x00 5. " TXD ,State of TXD Input" "Low,High"
bitfld.long 0x00 4. " RXD ,State of RXD Input" "Low,High"
textline " "
bitfld.long 0x00 3. " SIRT ," "0,1"
bitfld.long 0x00 2. " SIRIN ," "0,1"
textline " "
bitfld.long 0x00 1. " S16CLK ," "0,1"
bitfld.long 0x00 0. " TSIRC ," "0,1"
group 0x0080++7
line.long 0x00 "MISR,MIR Status Register"
bitfld.long 0x00 6. " RFL ,Receive Frame Lost" "Not lost,Lost"
bitfld.long 0x00 5. " RIL ,Receive Information Buffer Lost" "Not lost,Lost"
textline " "
bitfld.long 0x00 4. " RFC ,Receive Frame Complete" "Not completed,Completed"
bitfld.long 0x00 3. " RFS ,Reveive Buffer Service Request" "Not requested,Requested"
textline " "
bitfld.long 0x00 2. " TAB ,Transmit Frame Aborted" "Not aborted,Aborted"
bitfld.long 0x00 1. " TFC ,Transmit Frame Complete" "Not completed,Completed"
textline " "
bitfld.long 0x00 0. " TFS ,Transmit Buffer Service Request" "Not requested,Requested"
line.long 0x04 "MIMR,MIR Interrupt Mask Register"
bitfld.long 0x04 6. " RFL ,RFL Mask Bit" "Not masked,Masked"
bitfld.long 0x04 5. " RIL ,RIL Mask Bit" "Not masked,Masked"
textline " "
bitfld.long 0x04 4. " RFC ,RFC Mask Bit" "Not masked,Masked"
bitfld.long 0x04 3. " RFS ,RFS Mask Bit" "Not masked,Masked"
textline " "
bitfld.long 0x04 2. " TAB ,TAB Mask Bit" "Not masked,Masked"
bitfld.long 0x04 1. " TFC ,TFC Mask Bit" "Not masked,Masked"
textline " "
bitfld.long 0x04 0. " TFS ,TFS Mask Bit" "Not masked,Masked"
rgroup 0x0088++0x03
line.long 0x00 "MIIR,MIR Interrupt Register"
bitfld.long 0x00 6. " RFL ,RFL Masked Bit" "Low,High"
bitfld.long 0x00 5. " RIL ,RIL Masked Bit" "Low,High"
textline " "
bitfld.long 0x00 4. " RFC ,RFC Masked Bit" "Low,High"
bitfld.long 0x00 3. " RFS ,RFS Masked Bit" "Low,High"
textline " "
bitfld.long 0x00 2. " TAB ,TAB Masked Bit" "Low,High"
bitfld.long 0x00 1. " TFC ,TFC Masked Bit" "Low,High"
textline " "
bitfld.long 0x00 0. " TFS ,TFS Masked Bit" "Low,High"
group 0x0180++7
line.long 0x00 "FISR,FIR Status Register"
bitfld.long 0x00 6. " RFL ,Receive Frame Lost" "Not lost,Lost"
bitfld.long 0x00 5. " RIL ,Receive Information Buffer Lost" "Not lost,Lost"
textline " "
bitfld.long 0x00 4. " RFC ,Receive Frame Complete" "Not completed,Completed"
bitfld.long 0x00 3. " RFS ,Reveive Buffer Service Request" "Not requested,Requested"
textline " "
bitfld.long 0x00 2. " TAB ,Transmit Frame Aborted" "Not aborted,Aborted"
bitfld.long 0x00 1. " TFC ,Transmit Frame Complete" "Not completed,Completed"
textline " "
bitfld.long 0x00 0. " TFS ,Transmit Buffer Service Request" "Not requested,Requested"
line.long 0x04 "FIMR,FIR Interrupt Mask Register"
bitfld.long 0x04 6. " RFL ,RFL Mask Bit" "Not masked,Masked"
bitfld.long 0x04 5. " RIL ,RIL Mask Bit" "Not masked,Masked"
textline " "
bitfld.long 0x04 4. " RFC ,RFC Mask Bit" "Not masked,Masked"
bitfld.long 0x04 3. " RFS ,RFS Mask Bit" "Not masked,Masked"
textline " "
bitfld.long 0x04 2. " TAB ,TAB Mask Bit" "Not masked,Masked"
bitfld.long 0x04 1. " TFC ,TFC Mask Bit" "Not masked,Masked"
textline " "
bitfld.long 0x04 0. " TFS ,TFS Mask Bit" "Not masked,Masked"
rgroup 0x0188++0x03
line.long 0x00 "FIIR,FIR Interrupt Register"
bitfld.long 0x00 6. " RFL ,RFL Masked Bit" "Low,High"
bitfld.long 0x00 5. " RIL ,RIL Masked Bit" "Low,High"
textline " "
bitfld.long 0x00 4. " RFC ,RFC Masked Bit" "Low,High"
bitfld.long 0x00 3. " RFS ,RFS Masked Bit" "Low,High"
textline " "
bitfld.long 0x00 2. " TAB ,TAB Masked Bit" "Low,High"
bitfld.long 0x00 1. " TFC ,TFC Masked Bit" "Low,High"
textline " "
bitfld.long 0x00 0. " TFS ,TFS Masked Bit" "Low,High"
;end include file EP9301/IrDA.ph
tree.end
tree "Timers"
base 0x80810000
;begin include file EP9301/Timer.ph
;parameters:
tree "Timer 1"
group 0x0000++0x03
line.long 0x00 "Timer1Load,Timer 1 Load Register"
hexmask.long.word 0x00 0.--15. 1. " Load ,Load Value"
rgroup 0x0004++0x03
line.long 0x00 "Timer1Value,Timer 1 Value Register"
hexmask.long.word 0x00 0.--15. 1. " Value ,Current Timer Value"
group 0x0008++0x03
line.long 0x00 "Timer1Control,Timer 1 Control Register"
bitfld.long 0x00 7. " ENABLE ,Timer Enable Bit" "Disabled,Enabled"
bitfld.long 0x00 6. " MODE ,Operation Mode" "Free running,Periodic"
bitfld.long 0x00 3. " CLKSEL ,Clock Select" "2kHz,508Hz"
wgroup 0x000C++0x03
line.long 0x00 "Timer1Clear,Timer 1 Clear Register"
tree.end
tree "Timer 2"
group 0x0020++0x03
line.long 0x00 "Timer2Load,Timer 2 Load Register"
hexmask.long.word 0x00 0.--15. 1. " Load ,Load Value"
rgroup 0x0024++0x03
line.long 0x00 "Timer2Value,Timer 2 Value Register"
hexmask.long.word 0x00 0.--15. 1. " Value ,Current Timer Value"
group 0x0028++0x03
line.long 0x00 "Timer2Control,Timer 2 Control Register"
bitfld.long 0x00 7. " ENABLE ,Timer Enable Bit" "Disabled,Enabled"
bitfld.long 0x00 6. " MODE ,Operation Mode" "Free running,Periodic"
bitfld.long 0x00 3. " CLKSEL ,Clock Select" "2kHz,508Hz"
wgroup 0x002C++0x03
line.long 0x00 "Timer2Clear,Timer 2 Clear Register"
tree.end
tree "Timer 3"
group 0x0080++0x03
line.long 0x00 "Timer3Load,Timer 3 Load Register"
hexmask.long 0x00 0.--31. 1. " Load ,Load Value"
rgroup 0x0084++0x03
line.long 0x00 "Timer3Value,Timer 3 Value Register"
hexmask.long 0x00 0.--31. 1. " Value ,Current Timer Value"
group 0x0088++0x03
line.long 0x00 "TImer3Control,Timer 3 Control Register"
bitfld.long 0x00 7. " ENABLE ,Timer Enable Bit" "Disabled,Enabled"
bitfld.long 0x00 6. " MODE ,Operation Mode" "Free running,Periodic"
bitfld.long 0x00 3. " CLKSEL ,Clock Select" "2kHz,508Hz"
wgroup 0x008C++0x03
line.long 0x00 "Timer3Clear,Timer 3 Clear Register"
tree.end
tree "Timer 4"
rgroup 0x0060++0x03
line.long 0x00 "Timer4ValueLow,Timer 4 Value Low Register"
hexmask.long 0x00 0.--31. 1. " Value ,Timer 4 Low Value"
group 0x0064++0x03
line.long 0x00 "Timer4Enable,Timer 4 Enable/Value High Register"
bitfld.long 0x00 8. " Enable ,Timer 4 Enable" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--7. 1. " Value ,Timer 4 High Value"
tree.end
;end include file EP9301/Timer.ph
tree.end
tree "Watchdog Timer"
base 0x80940000
;begin include file EP9301/Watchdog.ph
;parameters:
width 16. 8.
rgroup 0x0000++0x03
line.long 0x00 "Watchdog,Watchdog Control Register (Read only)"
bitfld.long 0x00 6. " PLSDSN ,Pulse Disable Not" "Disabled,Enabled"
bitfld.long 0x00 5. " VRID ,Software Override of Hardware Watchdog Disable" "Not overrided,Overrided"
bitfld.long 0x00 4. " SWDIS ,Software Wachdog Disable" "Enabled,Disabled"
textline " "
bitfld.long 0x00 3. " HWDIS ,Hardware Watchdog Disable" "Enabled,Disabled"
bitfld.long 0x00 2. " URST ,User Reset Status Flip Flop" "No reset,User reset"
bitfld.long 0x00 1. " 3LRST ,Three Key Reset Status Flip Flop" "No reset,Three-key reset"
textline " "
bitfld.long 0x00 0. " WD ,Watchdog Reset Status Flip Flop" "No reset,Reset"
wgroup 0x0000++0x03
line.long 0x00 "Watchdog,Watchdog Control Register (Write only)"
hexmask.long 0x00 0.--15. 1. " CTL ,Watchdog Control Bits"
group 0x0004++0x03
line.long 0x00 "WDSTatus,Watchdog Storage Register"
hexmask.long.byte 0x00 0.--6. 1. " STAT ,Watchdog Status Bits"
;end include file EP9301/Watchdog.ph
tree.end
tree "Real Time Clock with Software Trim"
base 0x80920000
;begin include file EP9301/RTC.ph
;parameters:
rgroup 0x0000++0x03
line.long 0x00 "RTCData,RTC Data Register"
hexfld.long 0x00 " RTCDR ,Counter Value"
group 0x0004++0x03
line.long 0x00 "RTCMatch,RTC Match Register"
hexfld.long 0x00 " RTCMR ,Match Value"
group 0x0008++0x03
line.long 0x00 "RTCSts,RTC Status/EOI Register"
bitfld.long 0x00 0. " INTR ,Interrupt Status" "No Interrupt,Interrupt"
group 0x000C++0x03
line.long 0x00 "RTCLoad,RTC Load Register"
hexfld.long 0x00 " RTCLR ,Load Value"
group 0x0010++0x03
line.long 0x00 "RTCCtrl,RTC Control Register"
bitfld.long 0x00 0. " MIE ,Match Interrupt Enable" "Disabled,Enabled"
group 0x0108++0x03
line.long 0x00 "RTCSWComp,RTC Software Compensation"
hexmask.long.byte 0x00 16.--20. 1. " DEL ,Number of Clocks to Delete"
hexmask.long.word 0x00 0.--15. 1. " INT ,Counter Pre-Load Integer Value"
;end include file EP9301/RTC.ph
tree.end
tree "I2S Controller"
base 0x80820000
;begin include file EP9301/I2S.ph
;parameters:
tree "I2S TX Registers"
group 0x0010++7
line.long 0x00 "I2STXLft,Left Transmit Data Register"
hexfld.long 0x00 " I2s_tx_left ,Transmit Left Data Word"
line.long 0x04 "I2SRXRt,Right Transmit Data Register for Channel 0"
hexfld.long 0x04 " I2s_tx_right ,Transmit Right Data Word"
group 0x0028++7
line.long 0x00 "I2STXLinCtrlData,Line Control Data Register"
bitfld.long 0x00 2. " Left_Right_Justify ,Data Justify" "Left,Right"
textline " "
bitfld.long 0x00 1. " TXUF_REPEAT_SAMPLE ,Data Trasmit After TX Underflow" "Repeat sample,Transmit ones"
textline " "
bitfld.long 0x00 0. " TXDIR ,Transmit Data Shift Direction" "MSB first,LSB First"
line.long 0x04 "I2STXCtrl,Control Register"
bitfld.long 0x04 1. " TXUFIE ,Transmit Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " TXEMPTY_int_level ,Transmit Empty Interrupt Level Select" "When half empty,When empty"
group 0x0030++0x03
line.long 0x00 "I2STXWrdLen,Word Length Register"
bitfld.long 0x00 0.--1. " WL ,Word Length" "16-bit,24-bit,32-bit,"
group 0x0034++0x03
line.long 0x00 "I2STXEn,TX Channel Enable Register"
bitfld.long 0x00 0. " I2s_tx_EN ,TX Channel Enable" "Disabled,Enabled"
tree.end
tree "I2S RX Registers"
rgroup 0x0040++7
line.long 0x00 "I2SRXLft,Left Receive Data Register"
hexfld.long 0x00 " I2s_rx_left ,Receive Left Data Word"
line.long 0x04 "I2SRXRt,Right Receive Data Register"
hexfld.long 0x04 " I2s_rx_right ,Receive Right Data Word"
group 0x0058++0x0B
line.long 0x00 "I2SRXLinCtrlData,Line Control Data Register"
bitfld.long 0x00 2. " Left_Right_Justify ,Data Justify" "Left,Right"
textline " "
bitfld.long 0x00 0. " RXDIR ,Receive Data Shift Direction" "MSB first,LSB First"
line.long 0x04 "I2SRXCtrl,Control Register"
bitfld.long 0x04 1. " ROUFIE ,Receive Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " RXFull_int_level ,Receive Full Interrupt Level Select" "When half full,When full"
line.long 0x08 "I2SRXWrdLen,Word Length Register"
bitfld.long 0x08 0.--1. " WL ,Word Length" "16-bit,24-bit,32-bit,"
group 0x0064++0x03
line.long 0x00 "I2SRXEn,RX Channel Enable Register"
bitfld.long 0x00 0. " I2s_rx_EN ,RX Channel Enable" "Disabled,Enabled"
tree.end
tree "I2S Configuration and Status Registers"
if ((data.long(d:0x80820000)&0x00000060)==0x00000000)
group 0x0000++0x03
line.long 0x00 "I2STXClkCfg,Transmitter Clock Configuration Register"
bitfld.long 0x00 5.--6. " I2s_tx_bcr ,TX Bit Clock Rate" "I2STXClkCfg[4],Fixed at 32x,Fixed at 64x,Fixed at 128x"
bitfld.long 0x00 4. " I2s_fx_nbcg ,TX Not Bit Clock Gating Mode" "Low,High"
textline " "
bitfld.long 0x00 3. " I2s_mstr ,TX Audio Clock Master/Slave" "Slave,Master"
bitfld.long 0x00 2. " I2s_trel ,Timing of Irckt Respect to Sdix Data Outputs" "Together,One cycle before"
textline " "
bitfld.long 0x00 1. " I2s_tckp ,TX Bitclk Polarity" "Negative,Positive"
bitfld.long 0x00 0. " I2s_tlrs ,Irckt Polarity" "Low->left/High->right,Low->high/High->left"
else
group 0x0000++0x03
line.long 0x00 "I2STXClkCfg,Transmitter Clock Configuration Register"
bitfld.long 0x00 5.--6. " I2s_tx_bcr ,TX Bit Clock Rate" "I2STXClkCfg[4],Fixed at 32x,Fixed at 64x,Fixed at 128x"
textline " "
bitfld.long 0x00 3. " I2s_mstr ,TX Audio Clock Master/Slave" "Slave,Master"
bitfld.long 0x00 2. " I2s_trel ,Timing of Irckt Respect to Sdix Data Outputs" "Together,One cycle before"
textline " "
bitfld.long 0x00 1. " I2s_tckp ,TX Bitclk Polarity" "Negative,Positive"
bitfld.long 0x00 0. " I2s_tlrs ,Irckt Polarity" "Low->left/High->right,Low->high/High->left"
endif
if ((data.long(d:0x80820004)&0x00000060)==0x00000000)
group 0x0004++0x03
line.long 0x00 "I2SRXClkCfg,Receiver Clock Configuration Register"
bitfld.long 0x00 5.--6. " I2s_rx_bcr ,RX Bit Clock Rate" "I2STXClkCfg[4],Fixed at 32x,Fixed at 64x,Fixed at 128x"
bitfld.long 0x00 4. " I2s_fx_nbcg ,RX Not Bit Clock Gating Mode" "Low,High"
textline " "
bitfld.long 0x00 3. " I2s_mstr ,RX Audio Clock Master/Slave" "Slave,Master"
bitfld.long 0x00 2. " I2s_trel ,Timing of Irckr Respect to Sdix Data Outputs" "Together,One cycle before"
textline " "
bitfld.long 0x00 1. " I2s_tckp ,RX Bitclk Polarity" "Negative,Positive"
bitfld.long 0x00 0. " I2s_tlrs ,Irckr Polarity" "Low->left/High->right,Low->high/High->left"
else
group 0x0004++0x03
line.long 0x00 "I2SRXClkCfg,Receiver Clock Configuration Register"
bitfld.long 0x00 5.--6. " I2s_rx_bcr ,RX Bit Clock Rate" "I2STXClkCfg[4],Fixed at 32x,Fixed at 64x,Fixed at 128x"
textline " "
bitfld.long 0x00 3. " I2s_mstr ,RX Audio Clock Master/Slave" "Slave,Master"
bitfld.long 0x00 2. " I2s_trel ,Timing of Irckr Respect to Sdix Data Outputs" "Together,One cycle before"
textline " "
bitfld.long 0x00 1. " I2s_tckp ,RX Bitclk Polarity" "Negative,Positive"
bitfld.long 0x00 0. " I2s_tlrs ,Irckr Polarity" "Low->left/High->right,Low->high/High->left"
endif
group 0x0008++0x03
line.long 0x00 "I2SGISts,I2S Global Status Register"
bitfld.long 0x00 17. " rx_fifo_half_full ,RX FIFO Half Full" "Not half full,Half full"
bitfld.long 0x00 16. " rx_fifo_empty ,RX FIFO Empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 15. " rx_fifo_full ,RX FIFO Full" "Not full,Full"
bitfld.long 0x00 14. " tx_fifo_half_full ,TX FIFO Half Full" "Not half full,Half full"
textline " "
bitfld.long 0x00 13. " tx_fifo_empty ,TX FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 12. " tx_fifo_full ,TX FIFO Full" "Not full,Full"
textline " "
bitfld.long 0x00 9. " rx_underflow ,RX Underflow" "Not underflowed,Underflowed"
bitfld.long 0x00 6. " tx_overflow ,TX Overflow" "Not overflowed,Overflowed"
textline " "
bitfld.long 0x00 3. " rx_overflow ,RX Overflow" "Not overflowed,Overflowed"
bitfld.long 0x00 0. " tx_underflow ,TX Underflow" "Not underflowed,Underflowed"
group 0x000C++0x03
line.long 0x00 "I2SGICtrl,I2S Global Control Register"
bitfld.long 0x00 1. " I2s_loopback ,Loopback Operation" "No loopback mode,Loopback mode"
bitfld.long 0x00 0. " I2s_ife ,PCLK Enable" "Off,On"
tree.end
;end include file EP9301/I2S.ph
tree.end
tree "AC'97 Controller"
base 0x80880000
;begin include file EP9301/AC97.ph
;parameters:
tree "Channel Registers"
group 0x0000++0x03
line.long 0x00 "AC97DR,Data Read/Write from/to FIFO"
hexfld.long 0x00 " DATA ,Data Receive/Transmit"
group 0x0004++7
line.long 0x00 "AC97RXCR,Receive Control Register"
hexmask.long.word 0x00 17.--28. 1. " TOC ,Time-Out Count Value"
bitfld.long 0x00 16. " FDIS ,FIFO Disable" "Enabled,Disabled"
bitfld.long 0x00 15. " CM ,Compact Mode Enable" "Jutified,Compact"
textline " "
bitfld.long 0x00 13.--14. " RSIZE ,Size of Data Word" "16 bits,18 bits,20 bits,12 bits"
bitfld.long 0x00 12. " RX12 ,FIFO Stores SLOT12 Data" "Not stored,Stored"
bitfld.long 0x00 11. " RX11 ,FIFO Stores SLOT11 Data" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " RX10 ,FIFO Stores SLOT10 Data" "Not stored,Stored"
bitfld.long 0x00 9. " RX9 ,FIFO Stores SLOT9 Data" "Not stored,Stored"
bitfld.long 0x00 8. " RX8 ,FIFO Stores SLOT8 Data" "Not stored,Stored"
textline " "
bitfld.long 0x00 7. " RX7 ,FIFO Stores SLOT7 Data" "Not stored,Stored"
bitfld.long 0x00 6. " RX6 ,FIFO Stores SLOT6 Data" "Not stored,Stored"
bitfld.long 0x00 5. " RX5 ,FIFO Stores SLOT5 Data" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " RX4 ,FIFO Stores SLOT4 Data" "Not stored,Stored"
bitfld.long 0x00 3. " RX3 ,FIFO Stores SLOT3 Data" "Not stored,Stored"
bitfld.long 0x00 2. " RX2 ,FIFO Stores SLOT2 Data" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " RX1 ,FIFO Stores SLOT1 Data" "Not stored,Stored"
bitfld.long 0x00 0. " REN ,PCLK and Receive Enable for Channel " "Disabled,Enabled"
line.long 0x04 "AC97TXCR,Transmit Control Register"
bitfld.long 0x04 16. " FDIS ,FIFO Disable" "Enabled,Disabled"
bitfld.long 0x04 15. " CM ,Compact Mode Enable" "Jutified,Compact"
bitfld.long 0x04 13.--14. " TSIZE ,Size of Data Word" "16 bits,18 bits,20 bits,12 bits"
textline " "
bitfld.long 0x04 12. " TX12 ,FIFO Stores SLOT12 Data" "Not Stored,Stored"
bitfld.long 0x04 11. " TX11 ,FIFO Stores SLOT11 Data" "Not Stored,Stored"
bitfld.long 0x04 10. " TX10 ,FIFO Stores SLOT10 Data" "Not Stored,Stored"
textline " "
bitfld.long 0x04 9. " TX9 ,FIFO Stores SLOT9 Data" "Not Stored,Stored"
bitfld.long 0x04 8. " TX8 ,FIFO Stores SLOT8 Data" "Not Stored,Stored"
bitfld.long 0x04 7. " TX7 ,FIFO Stores SLOT7 Data" "Not Stored,Stored"
textline " "
bitfld.long 0x04 6. " TX6 ,FIFO Stores SLOT6 Data" "Not Stored,Stored"
bitfld.long 0x04 5. " TX5 ,FIFO Stores SLOT5 Data" "Not Stored,Stored"
bitfld.long 0x04 4. " TX4 ,FIFO Stores SLOT4 Data" "Not Stored,Stored"
textline " "
bitfld.long 0x04 3. " TX3 ,FIFO Stores SLOT3 Data" "Not Stored,Stored"
bitfld.long 0x04 2. " TX2 ,FIFO Contains SLOT2 Data" "Not contains,Contains"
bitfld.long 0x04 1. " TX1 ,FIFO Contains SLOT1 Data" "Not contains,Contains"
textline " "
bitfld.long 0x04 0. " TEN ,PCLK and Transmit Enable for Channel " "Disabled,Enabled"
rgroup 0x000C++0x0B
line.long 0x00 "AC97SR,Status Register"
bitfld.long 0x00 6. " TXUE ,TX Underrun Error" "No error,Error"
bitfld.long 0x00 5. " RXOE ,RX Overrun Error" "No error,Error"
bitfld.long 0x00 4. " TXBUSY ,TX Busy" "Not busy,Busy"
textline " "
bitfld.long 0x00 3. " TXFF ,Transmit FIFO Full Flag" "Not full,Full"
bitfld.long 0x00 2. " RXFF ,Receive FIFO Full Flag" "Not full,Full"
bitfld.long 0x00 1. " TXFE ,Transmit FIFO Empty Flag" "Not empty,Empty"
textline " "
bitfld.long 0x00 0. " RXFE ,Receive FIFO Empty Flag" "Not empty,Empty"
line.long 0x04 "AC97RISR,Raw Interrupt Status Register"
bitfld.long 0x04 3. " RIS ,RX Half Full Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x04 2. " TIS ,TX Half Empty Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x04 1. " RTIS ,RX Timeout Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " TCIS ,TX Complete Interrupt Status" "No interrupt,Interrupt"
line.long 0x08 "AC97ISR,Interrupt Status Register"
bitfld.long 0x08 3. " RIS ,RX Interrupt Assertion" "Not asserted,Asserted"
bitfld.long 0x08 2. " TIS ,TX Interrupt Assertion" "Not asserted,Asserted"
bitfld.long 0x08 1. " RTIS ,RX Timeout Interrupt Assertion" "Not asserted,Asserted"
textline " "
bitfld.long 0x08 0. " TCIS ,TX Complete Interrupt Assertion" "Not asserted,Asserted"
group 0x0018++0x03
line.long 0x00 "AC97IE,Interrupt Enable Register"
bitfld.long 0x00 3. " RIE ,RX Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " TIE ,TX Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RTIE ,RX Timeout Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " TCIE ,TX Complete Interrupt Enable" "Disabled,Enabled"
tree.end
tree "Main Registers"
group 0x0080++0x0B
line.long 0x00 "AC97S1Data,Slot 1 Data Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Read/Write Data Value"
line.long 0x04 "AC97S2Data,Slot 2 Data Register"
hexmask.long.word 0x04 0.--15. 1. " DATA ,Read/Write Data Value"
line.long 0x08 "AC97S12Data,Slot 12 Data Register"
hexmask.long.tbyte 0x08 0.--19. 1. " DATA ,Read/Write Data Value"
group 0x008C++0x03
line.long 0x00 "AC97RGIS,Raw Global Interrupt Status Register"
bitfld.long 0x00 6. " SLOT2TXCOMPLETE ,AC97 Slot 2 Data Tramsmission Complete" "Not completed,Completed"
bitfld.long 0x00 5. " CODECREADY ,Codec Ready" "Not ready,Ready"
textline " "
bitfld.long 0x00 4. " WINT ,RAW Wakeup Interrupt Status" "Not asserted,Asserted"
bitfld.long 0x00 3. " GPIOINT ,GPIOINT Status Bit" "Low,High"
textline " "
bitfld.long 0x00 2. " GPIOTXCOMPLETE ,GPIO Transmission Complete" "Not completed,Completed"
bitfld.long 0x00 1. " SLOT2RXVALID ,New Data in AC97S2Data Register" "No new data,New data"
textline " "
bitfld.long 0x00 0. " SLOT1TXCOMPLETE ,Transmission Complete" "Not completed,Completed"
rgroup 0x0090++0x03
line.long 0x00 "AC97GIS,Global Interrupt Status Register"
bitfld.long 0x00 6. " SLOT2TXCOMPLETE ,AC97 Slot 2 Data Tramsmission Complete Interrupt Assertion" "Not asserted,Asserted"
bitfld.long 0x00 5. " CODECREADY ,Codec Ready Interrupt Assertion" "Not asserted,Asserted"
textline " "
bitfld.long 0x00 4. " WINT ,RAW Wakeup Interrupt Assertion" "Not asserted,Asserted"
bitfld.long 0x00 3. " GPIOINT ,GPIOINT Bit Interrupt Assertion" "Not asserted,Asserted"
textline " "
bitfld.long 0x00 2. " GPIOTXCOMPLETE ,GPIO Transmission Complete Interrupt Assertion" "Not asserted,Asserted"
bitfld.long 0x00 1. " SLOT2RXVALID ,New Data in AC97S2Data Register Interrupt Assertion" "Not asserted,Asserted"
textline " "
bitfld.long 0x00 0. " SLOT1TXCOMPLETE ,Transmission Complete Interrupt Assertion" "Not asserted,Asserted"
group 0x0094++0x03
line.long 0x00 "AC97IM,Interrupt Enable Register"
bitfld.long 0x00 6. " SLOT2TXCOMPLETE ,AC97 Slot 2 Data Tramsmission Complete Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " CODECREADY ,Codec Ready Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " WINT ,RAW Wakeup Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " GPIOINT ,GPIOINT Bit Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " GPIOTXCOMPLETE ,GPIO Transmission Complete Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " SLOT2RXVALID ,New Data in AC97S2Data Register Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " SLOT1TXCOMPLETE ,Transmission Complete Interrupt Enable" "Disabled,Enabled"
wgroup 0x0098++0x03
line.long 0x00 "AC97EOI,End of Interrupt Register"
bitfld.long 0x00 1. " CODECREADY ,Codec Ready Interrupt Clear" "No effect,Clear"
bitfld.long 0x00 0. " WINT ,Wakeup Interrupt Status Clear" "No effect,Clear"
group 0x009C++0x0B
line.long 0x00 "AC97GCR,Global Control Register"
bitfld.long 0x00 2. " CODECReady ,CODEC Ready" "Not ready,Ready"
bitfld.long 0x00 1. " LOOP ,Loopback Mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " AC97IFE ,AC97IF Enable" "Disabled,Enabled"
line.long 0x04 "AC97Reset,Controller Reset Register"
bitfld.long 0x04 2. " EFORCER ,Forced RESET Enable" "Disabled,Enabled"
bitfld.long 0x04 1. " FORCEDRESET ,Force Reset" "No reset,Reset"
textline " "
bitfld.long 0x04 0. " TIMEDRESET ,Timed Reset" "No reset,Reset"
line.long 0x08 "AC97SYNC,SYNC Control Register"
bitfld.long 0x08 2. " EFORCES ,Forced SYNC Enable" "Disabled,Enabled"
bitfld.long 0x08 1. " FORCEDSYNC ,Forced SYNC" "Not forced,Forced"
textline " "
bitfld.long 0x08 0. " TIMEDSYNC ,Forced Timed SYNC" "Not forced,Forced"
rgroup 0x00A8++0x03
line.long 0x00 "AC97GCIS,Global Channel FIFO Interrupt Status Register"
hexmask.long.byte 0x00 16.--22. 1. " AC97GIS ,Copy of GIS Interrupt Register"
hexmask.long.byte 0x00 12.--15. 1. " AC97ISR4 ,Copy of GISR4 Interrupt Register"
textline " "
hexmask.long.byte 0x00 8.--11. 1. " AC97ISR3 ,Copy of GISR3 Interrupt Register"
hexmask.long.byte 0x00 4.--7. 1. " AC97ISR3 ,Copy of GISR2 Interrupt Register"
textline " "
hexmask.long.byte 0x00 0.--3. 1. " AC97ISR1 ,Copy of GISR1 Interrupt Register"
tree.end
;end include file EP9301/AC97.ph
tree.end
tree "Synchronous Serial Port (SSP)"
base 0x808A0000
;begin include file EP9301/SSP.ph
;parameters:
group 0x0000++7
line.long 0x00 "SSPCR0,Control Register 0"
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial Clock Rate"
bitfld.long 0x00 7. " SPH ,SCLKOUT Phase" "Low,High"
bitfld.long 0x00 6. " SPO ,SCLKOUT Polarity" "Low,High"
textline " "
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI serial,Microwire,Reserved"
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,?..."
line.long 0x04 "SSPCR1,Control Register 1"
bitfld.long 0x04 6. " SOD ,Slave-Mode Output Disable" "Drive SSPTXD,Not drive SSPTXD"
bitfld.long 0x04 5. " MS ,Master/Slave Mode Select" "Master,Slave"
bitfld.long 0x04 4. " SSE ,Synchronous Serial Port Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " LBM ,Loop Back Mode" "Normal,Loop Back"
bitfld.long 0x04 2. " RORIE ,Receive FIFO Overrun Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x04 1. " TIE ,Transmit FIFO Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " RIE ,Receive FIFO Interrupt Enable" "Disabled,Enabled"
group 0x0008++0x03
line.long 0x00 "SSPDR,Transmit/Receive FIFO"
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data"
rgroup 0x000C++0x03
line.long 0x00 "SSPSR,Status Register"
bitfld.long 0x00 4. " BSY ,SSP Busy Flag" "Idle,Busy"
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
bitfld.long 0x00 2. " RNE ,Receive FIFO not Empty" "Empty,Not empty"
textline " "
bitfld.long 0x00 1. " TNF ,Transmit FIFO not Full" "Full,Not full"
bitfld.long 0x00 0. " TFE ,Tramsnit FIFO Empty" "Not empty,Empty"
group 0x0010++0x03
line.long 0x00 "SSPCPSR,Clock Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Clock Pre-scale Divisior"
rgroup 0x0014++0x03
line.long 0x00 "SSPIIR,Interrupt Identification Register"
bitfld.long 0x00 2. " RORIS ,SSP Receive FIFO Overrun Interrupt Status" "Not asserted,Asserted"
bitfld.long 0x00 1. " TIS ,SSP Transmit FIFO Service Request Interrupt Status" "Not asserted,Asserted"
bitfld.long 0x00 0. " RIS ,SSP Receive FIFO Service Request Interrupt Status" "Not asserted,Asserted"
wgroup 0x0014++0x03
line.long 0x00 "SSPICR,Interrupt Clear Register"
;end include file EP9301/SSP.ph
tree.end
tree "Analog-to-Digital Interface (ADC)"
base 0x80900000
;begin include file EP9301/ADC.ph
;parameters:
rgroup 0x0008++0x03
line.long 0x00 "ADCResult,ADC Result Register"
bitfld.long 0x00 31. " SDR ,Synchronous Data Ready" "Not ready,Ready"
hexmask.long.word 0x00 0.--11. 1. " AD ,ADC Conversion Data"
group 0x0018++0x03
line.long 0x00 "ADCSwitch,ADC Switch Matrix Register"
hexfld.long 0x00 " SCTL ,Analog Switch Control Value"
rgroup 0x0020++0x03
line.long 0x00 "ADCSWLock,ADC Software Lock Register"
bitfld.long 0x00 0. " SWLCK[0] ,Softwate Lock" "Locked,Unlocked"
wgroup 0x0020++0x03
line.long 0x00 "ADCSWLock,ADC Software Lock Register"
hexmask.long.byte 0x00 0.--7. 1. " SWLOCK ,Software Lock Bits"
group 0x0024++0x03
line.long 0x00 "ADCIntEn,ADC Interrupt Enable Register"
bitfld.long 0x00 11. " RINTEN ,Synchronous Data Ready Interrupt Enable" "Disabled,Enabled"
;end include file EP9301/ADC.ph
tree.end
tree "GPIO Interface"
base 0x80840000
;begin include file EP9301/GPIO.ph
;parameters:
tree "PORT A"
base 0x80840000
;begin include file EP9301/GPIO/PORTAB.ph
;parameters: 0x0000 A
group 0x0000++0x03
line.long 0x00 "PADR,Port A Data Register"
bitfld.long 0x00 7. " PAData7 ,Port A Data Pin 7" "Low,High"
bitfld.long 0x00 6. " PAData6 ,Port A Data Pin 6" "Low,High"
bitfld.long 0x00 5. " PAData5 ,Port A Data Pin 5" "Low,High"
textline " "
bitfld.long 0x00 4. " PAData4 ,Port A Data Pin 4" "Low,High"
bitfld.long 0x00 3. " PAData3 ,Port A Data Pin 3" "Low,High"
bitfld.long 0x00 2. " PAData2 ,Port A Data Pin 2" "Low,High"
textline " "
bitfld.long 0x00 1. " PAData1 ,Port A Data Pin 1" "Low,High"
bitfld.long 0x00 0. " PAData0 ,Port A Data Pin 0" "Low,High"
group (0x0000+0x0010)++0x03
line.long 0x00 "PADDR,Port A Data Direction Register"
bitfld.long 0x00 7. " PADIR7 ,Port A Direction Pin 7" "Input,Output"
bitfld.long 0x00 6. " PADIR6 ,Port A Direction Pin 6" "Input,Output"
bitfld.long 0x00 5. " PADIR5 ,Port A Direction Pin 5" "Input,Output"
textline " "
bitfld.long 0x00 4. " PADIR4 ,Port A Direction Pin 4" "Input,Output"
bitfld.long 0x00 3. " PADIR3 ,Port A Direction Pin 3" "Input,Output"
bitfld.long 0x00 2. " PADIR2 ,Port A Direction Pin 2" "Input,Output"
textline " "
bitfld.long 0x00 1. " PADIR1 ,Port A Direction Pin 1" "Input,Output"
bitfld.long 0x00 0. " PADIR0 ,Port A Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTAB.ph
;begin include file EP9301/GPIO/INTAB.ph
;parameters: 0x0090 A
group (0x0090+0x000C)++0x03
line.long 0x00 "GPIOAIntEn,GPIO A Interrupt Enable"
bitfld.long 0x00 7. " PAINT7 ,Port A Interrupt Enable Pin 7" "Disabled,Enabled"
bitfld.long 0x00 6. " PAINT6 ,Port A Interrupt Enable Pin 6" "Disabled,Enabled"
bitfld.long 0x00 5. " PAINT5 ,Port A Interrupt Enable Pin 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " PAINT4 ,Port A Interrupt Enable Pin 4" "Disabled,Enabled"
bitfld.long 0x00 3. " PAINT3 ,Port A Interrupt Enable Pin 3" "Disabled,Enabled"
bitfld.long 0x00 2. " PAINT2 ,Port A Interrupt Enable Pin 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " PAINT1 ,Port A Interrupt Enable Pin 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PAINT0 ,Port A Interrupt Enable Pin 0" "Disabled,Enabled"
group 0x0090++7
line.long 0x00 "GPIOAIntType1,GPIO A Interrupt Type Regiter 1"
bitfld.long 0x00 7. " PAINTE7 ,Pin 7 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 6. " PAINTE6 ,Pin 6 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 5. " PAINTE5 ,Pin5 Level/Edge Sensitive" "Level,Edge"
textline " "
bitfld.long 0x00 4. " PAINTE4 ,Pin 4 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 3. " PAINTE3 ,Pin 3 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 2. " PAINTE2 ,Pin 2 Level/Edge Sensitive" "Level,Edge"
textline " "
bitfld.long 0x00 1. " PAINTE1 ,Pin 1 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 0. " PAINTE0 ,Pin 0 Level/Edge Sensitive" "Level,Edge"
line.long 0x04 "GPIOAIntType2,GPIO A Interrupt Type Regiter 2"
bitfld.long 0x04 7. " PAINTE7 ,Pin 7 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 6. " PAINTE6 ,Pin 6 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 5. " PAINTE5 ,Pin 5 Falling/Rising Sensitive" "Falling edge,Rising edge"
textline " "
bitfld.long 0x04 4. " PAINTE4 ,Pin 4 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 3. " PAINTE3 ,Pin 3 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 2. " PAINTE2 ,Pin 2 Falling/Rising Sensitive" "Falling edge,Rising edge"
textline " "
bitfld.long 0x04 1. " PAINTE1 ,Pin 1 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 0. " PAINTE0 ,Pin 0 Falling/Rising Sensitive" "Falling edge,Rising edge"
wgroup (0x0090+0x0008)++0x03
line.long 0x00 "GPIOAEOI,GPIO A End of Interrupt Register"
bitfld.long 0x00 7. " PAINTC7 ,Interrupt Clear on Pin 7" "No effect,Clear"
bitfld.long 0x00 6. " PAINTC6 ,Interrupt Clear on Pin 6" "No effect,Clear"
bitfld.long 0x00 5. " PAINTC5 ,Interrupt Clear on Pin 5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " PAINTC4 ,Interrupt Clear on Pin 4" "No effect,Clear"
bitfld.long 0x00 3. " PAINTC3 ,Interrupt Clear on Pin 3" "No effect,Clear"
bitfld.long 0x00 2. " PAINTC2 ,Interrupt Clear on Pin 2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " PAINTC1 ,Interrupt Clear on Pin 1" "No effect,Clear"
bitfld.long 0x00 0. " PAINTC0 ,Interrupt Clear on Pin 0" "No effect,Clear"
group (0x0090+0x0018)++0x03
line.long 0x00 "GPIOADB,GPIO A Debounce Enable"
bitfld.long 0x00 7. " PAINTDB7 ,Pin 7 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " PAINTDB6 ,Pin 6 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PAINTDB5 ,Pin 5 Debounce Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " PAINTDB4 ,Pin 4 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " PAINTDB3 ,Pin 3 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " PAINTDB2 ,Pin 2 Debounce Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " PAINTDB1 ,Pin 1 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " PAINTDB0 ,Pin 0 Debounce Enable" "Disabled,Enabled"
rgroup (0x0090+0x0014)++0x03
line.long 0x00 "RawIntStsA,GPIO A Raw Interrupt Status"
bitfld.long 0x00 7. " PAINTRS7 ,Pin 7 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 6. " PAINTRS6 ,Pin 6 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 5. " PAINTRS5 ,Pin 5 Raw Interrupt Status" "Not Signalled,Signalled"
textline " "
bitfld.long 0x00 4. " PAINTRS4 ,Pin 4 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 3. " PAINTRS3 ,Pin 3 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 2. " PAINTRS2 ,Pin 2 Raw Interrupt Status" "Not Signalled,Signalled"
textline " "
bitfld.long 0x00 1. " PAINTRS1 ,Pin 1 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 0. " PAINTRS0 ,Pin 0 Raw Interrupt Status" "Not Signalled,Signalled"
rgroup (0x0090+0x0010)++0x03
line.long 0x00 "IntStsA,GPIO A Interrupt Status"
bitfld.long 0x00 7. " PAINTS7 ,Pin 7 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " PAINTS6 ,Pin 6 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 5. " PAINTS5 ,Pin 5 Masked Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 4. " PAINTS4 ,Pin 4 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 3. " PAINTS3 ,Pin 3 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " PAINTS2 ,Pin 2 Masked Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " PAINTS1 ,Pin 1 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " PAINTS0 ,Pin 0 Masked Interrupt Status" "No interrupt,Interrupt"
;end include file EP9301/GPIO/INTAB.ph
tree.end
tree "PORT B"
base 0x80840000
;begin include file EP9301/GPIO/PORTAB.ph
;parameters: 0x0004 B
group 0x0004++0x03
line.long 0x00 "PBDR,Port B Data Register"
bitfld.long 0x00 7. " PBData7 ,Port B Data Pin 7" "Low,High"
bitfld.long 0x00 6. " PBData6 ,Port B Data Pin 6" "Low,High"
bitfld.long 0x00 5. " PBData5 ,Port B Data Pin 5" "Low,High"
textline " "
bitfld.long 0x00 4. " PBData4 ,Port B Data Pin 4" "Low,High"
bitfld.long 0x00 3. " PBData3 ,Port B Data Pin 3" "Low,High"
bitfld.long 0x00 2. " PBData2 ,Port B Data Pin 2" "Low,High"
textline " "
bitfld.long 0x00 1. " PBData1 ,Port B Data Pin 1" "Low,High"
bitfld.long 0x00 0. " PBData0 ,Port B Data Pin 0" "Low,High"
group (0x0004+0x0010)++0x03
line.long 0x00 "PBDDR,Port B Data Direction Register"
bitfld.long 0x00 7. " PBDIR7 ,Port B Direction Pin 7" "Input,Output"
bitfld.long 0x00 6. " PBDIR6 ,Port B Direction Pin 6" "Input,Output"
bitfld.long 0x00 5. " PBDIR5 ,Port B Direction Pin 5" "Input,Output"
textline " "
bitfld.long 0x00 4. " PBDIR4 ,Port B Direction Pin 4" "Input,Output"
bitfld.long 0x00 3. " PBDIR3 ,Port B Direction Pin 3" "Input,Output"
bitfld.long 0x00 2. " PBDIR2 ,Port B Direction Pin 2" "Input,Output"
textline " "
bitfld.long 0x00 1. " PBDIR1 ,Port B Direction Pin 1" "Input,Output"
bitfld.long 0x00 0. " PBDIR0 ,Port B Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTAB.ph
;begin include file EP9301/GPIO/INTAB.ph
;parameters: 0x00AC B
group (0x00AC+0x000C)++0x03
line.long 0x00 "GPIOBIntEn,GPIO B Interrupt Enable"
bitfld.long 0x00 7. " PBINT7 ,Port B Interrupt Enable Pin 7" "Disabled,Enabled"
bitfld.long 0x00 6. " PBINT6 ,Port B Interrupt Enable Pin 6" "Disabled,Enabled"
bitfld.long 0x00 5. " PBINT5 ,Port B Interrupt Enable Pin 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " PBINT4 ,Port B Interrupt Enable Pin 4" "Disabled,Enabled"
bitfld.long 0x00 3. " PBINT3 ,Port B Interrupt Enable Pin 3" "Disabled,Enabled"
bitfld.long 0x00 2. " PBINT2 ,Port B Interrupt Enable Pin 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " PBINT1 ,Port B Interrupt Enable Pin 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PBINT0 ,Port B Interrupt Enable Pin 0" "Disabled,Enabled"
group 0x00AC++7
line.long 0x00 "GPIOBIntType1,GPIO B Interrupt Type Regiter 1"
bitfld.long 0x00 7. " PBINTE7 ,Pin 7 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 6. " PBINTE6 ,Pin 6 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 5. " PBINTE5 ,Pin5 Level/Edge Sensitive" "Level,Edge"
textline " "
bitfld.long 0x00 4. " PBINTE4 ,Pin 4 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 3. " PBINTE3 ,Pin 3 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 2. " PBINTE2 ,Pin 2 Level/Edge Sensitive" "Level,Edge"
textline " "
bitfld.long 0x00 1. " PBINTE1 ,Pin 1 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 0. " PBINTE0 ,Pin 0 Level/Edge Sensitive" "Level,Edge"
line.long 0x04 "GPIOBIntType2,GPIO B Interrupt Type Regiter 2"
bitfld.long 0x04 7. " PBINTE7 ,Pin 7 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 6. " PBINTE6 ,Pin 6 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 5. " PBINTE5 ,Pin 5 Falling/Rising Sensitive" "Falling edge,Rising edge"
textline " "
bitfld.long 0x04 4. " PBINTE4 ,Pin 4 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 3. " PBINTE3 ,Pin 3 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 2. " PBINTE2 ,Pin 2 Falling/Rising Sensitive" "Falling edge,Rising edge"
textline " "
bitfld.long 0x04 1. " PBINTE1 ,Pin 1 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 0. " PBINTE0 ,Pin 0 Falling/Rising Sensitive" "Falling edge,Rising edge"
wgroup (0x00AC+0x0008)++0x03
line.long 0x00 "GPIOBEOI,GPIO B End of Interrupt Register"
bitfld.long 0x00 7. " PBINTC7 ,Interrupt Clear on Pin 7" "No effect,Clear"
bitfld.long 0x00 6. " PBINTC6 ,Interrupt Clear on Pin 6" "No effect,Clear"
bitfld.long 0x00 5. " PBINTC5 ,Interrupt Clear on Pin 5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " PBINTC4 ,Interrupt Clear on Pin 4" "No effect,Clear"
bitfld.long 0x00 3. " PBINTC3 ,Interrupt Clear on Pin 3" "No effect,Clear"
bitfld.long 0x00 2. " PBINTC2 ,Interrupt Clear on Pin 2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " PBINTC1 ,Interrupt Clear on Pin 1" "No effect,Clear"
bitfld.long 0x00 0. " PBINTC0 ,Interrupt Clear on Pin 0" "No effect,Clear"
group (0x00AC+0x0018)++0x03
line.long 0x00 "GPIOBDB,GPIO B Debounce Enable"
bitfld.long 0x00 7. " PBINTDB7 ,Pin 7 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " PBINTDB6 ,Pin 6 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PBINTDB5 ,Pin 5 Debounce Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " PBINTDB4 ,Pin 4 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " PBINTDB3 ,Pin 3 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " PBINTDB2 ,Pin 2 Debounce Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " PBINTDB1 ,Pin 1 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " PBINTDB0 ,Pin 0 Debounce Enable" "Disabled,Enabled"
rgroup (0x00AC+0x0014)++0x03
line.long 0x00 "RawIntStsB,GPIO B Raw Interrupt Status"
bitfld.long 0x00 7. " PBINTRS7 ,Pin 7 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 6. " PBINTRS6 ,Pin 6 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 5. " PBINTRS5 ,Pin 5 Raw Interrupt Status" "Not Signalled,Signalled"
textline " "
bitfld.long 0x00 4. " PBINTRS4 ,Pin 4 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 3. " PBINTRS3 ,Pin 3 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 2. " PBINTRS2 ,Pin 2 Raw Interrupt Status" "Not Signalled,Signalled"
textline " "
bitfld.long 0x00 1. " PBINTRS1 ,Pin 1 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 0. " PBINTRS0 ,Pin 0 Raw Interrupt Status" "Not Signalled,Signalled"
rgroup (0x00AC+0x0010)++0x03
line.long 0x00 "IntStsB,GPIO B Interrupt Status"
bitfld.long 0x00 7. " PBINTS7 ,Pin 7 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " PBINTS6 ,Pin 6 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 5. " PBINTS5 ,Pin 5 Masked Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 4. " PBINTS4 ,Pin 4 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 3. " PBINTS3 ,Pin 3 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " PBINTS2 ,Pin 2 Masked Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " PBINTS1 ,Pin 1 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " PBINTS0 ,Pin 0 Masked Interrupt Status" "No interrupt,Interrupt"
;end include file EP9301/GPIO/INTAB.ph
tree.end
tree "PORT C"
base 0x80840000
;begin include file EP9301/GPIO/PORTC.ph
;parameters: 0x0008 C
group 0x0008++0x03
line.long 0x00 "PCDR,Port C Data Register"
bitfld.long 0x00 0. " PCData0 ,Port C Data Pin 0" "Low,High"
group (0x0008+0x0010)++0x03
line.long 0x00 "PCDDR,Port C Data Direction Register"
bitfld.long 0x00 0. " PCDIR0 ,Port C Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTC.ph
tree.end
tree "PORT E"
base 0x80840000
;begin include file EP9301/GPIO/PORTEG.ph
;parameters: 0x0020 E
group 0x0020++7
line.long 0x00 "PEDR,Port E Data Register"
bitfld.long 0x00 1. " PEData1 ,Port E Data Pin 1" "Low,High"
bitfld.long 0x00 0. " PEData0 ,Port E Data Pin 0" "Low,High"
line.long 0x04 "PEDDR,Port E Data Direction Register"
bitfld.long 0x04 1. " PEDIR1 ,Port E Direction Pin 1" "Input,Output"
bitfld.long 0x04 0. " PEDIR0 ,Port E Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTEG.ph
tree.end
tree "PORT F"
base 0x80840000
;begin include file EP9301/GPIO/PORTF.ph
;parameters: 0x0030 F
group 0x0030++7
line.long 0x00 "PFDR,Port F Data Register"
bitfld.long 0x00 2. " PFData2 ,Port F Data Pin 2" "Low,High"
bitfld.long 0x00 1. " PFData1 ,Port F Data Pin 1" "Low,High"
bitfld.long 0x00 0. " PFData0 ,Port F Data Pin 0" "Low,High"
line.long 0x04 "PFDDR,Port F Data Direction Register"
bitfld.long 0x04 2. " PFDIR2 ,Port F Direction Pin 2" "Input,Output"
bitfld.long 0x04 1. " PFDIR1 ,Port F Direction Pin 1" "Input,Output"
bitfld.long 0x04 0. " PFDIR0 ,Port F Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTF.ph
;begin include file EP9301/GPIO/INTF.ph
;parameters: 0x004C F
group (0x004C+0x000C)++0x03
line.long 0x00 "GPIOFIntEn,GPIO F Interrupt Enable"
bitfld.long 0x00 2. " PFINT2 ,Port F Interrupt Enable Pin 2" "Disabled,Enabled"
bitfld.long 0x00 1. " PFINT1 ,Port F Interrupt Enable Pin 1" "Disabled,Enabled"
bitfld.long 0x00 0. " PFINT0 ,Port F Interrupt Enable Pin 0" "Disabled,Enabled"
group 0x004C++7
line.long 0x00 "GPIOFIntType1,GPIO F Interrupt Type Regiter 1"
bitfld.long 0x00 2. " PFINTE2 ,Pin 2 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 1. " PFINTE1 ,Pin 1 Level/Edge Sensitive" "Level,Edge"
bitfld.long 0x00 0. " PFINTE0 ,Pin 0 Level/Edge Sensitive" "Level,Edge"
line.long 0x04 "GPIOFIntType2,GPIO F Interrupt Type Regiter 2"
bitfld.long 0x04 2. " PFINTE2 ,Pin 2 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 1. " PFINTE1 ,Pin 1 Falling/Rising Sensitive" "Falling edge,Rising edge"
bitfld.long 0x04 0. " PFINTE0 ,Pin 0 Falling/Rising Sensitive" "Falling edge,Rising edge"
wgroup (0x004C+0x0008)++0x03
line.long 0x00 "GPIOFEOI,GPIO F End of Interrupt Register"
bitfld.long 0x00 2. " PFINTC2 ,Interrupt Clear on Pin 2" "No effect,Clear"
bitfld.long 0x00 1. " PFINTC1 ,Interrupt Clear on Pin 1" "No effect,Clear"
bitfld.long 0x00 0. " PFINTC0 ,Interrupt Clear on Pin 0" "No effect,Clear"
group (0x004C+0x0018)++0x03
line.long 0x00 "GPIOFDB,GPIO F Debounce Enable"
bitfld.long 0x00 2. " PFINTDB2 ,Pin 2 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " PFINTDB1 ,Pin 1 Debounce Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " PFINTDB0 ,Pin 0 Debounce Enable" "Disabled,Enabled"
rgroup (0x004C+0x0014)++0x03
line.long 0x00 "RawIntStsF,GPIO F Raw Interrupt Status"
bitfld.long 0x00 2. " PFINTRS2 ,Pin 2 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 1. " PFINTRS1 ,Pin 1 Raw Interrupt Status" "Not Signalled,Signalled"
bitfld.long 0x00 0. " PFINTRS0 ,Pin 0 Raw Interrupt Status" "Not Signalled,Signalled"
rgroup (0x004C+0x0010)++0x03
line.long 0x00 "IntStsF,GPIO F Interrupt Status"
bitfld.long 0x00 2. " PFINTS2 ,Pin 2 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 1. " PFINTS1 ,Pin 1 Masked Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " PFINTS0 ,Pin 0 Masked Interrupt Status" "No interrupt,Interrupt"
;end include file EP9301/GPIO/INTF.ph
tree.end
tree "PORT G"
base 0x80840000
;begin include file EP9301/GPIO/PORTEG.ph
;parameters: 0x0038 G
group 0x0038++7
line.long 0x00 "PGDR,Port G Data Register"
bitfld.long 0x00 1. " PGData1 ,Port G Data Pin 1" "Low,High"
bitfld.long 0x00 0. " PGData0 ,Port G Data Pin 0" "Low,High"
line.long 0x04 "PGDDR,Port G Data Direction Register"
bitfld.long 0x04 1. " PGDIR1 ,Port G Direction Pin 1" "Input,Output"
bitfld.long 0x04 0. " PGDIR0 ,Port G Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTEG.ph
tree.end
tree "PORT H"
base 0x80840000
;begin include file EP9301/GPIO/PORTH.ph
;parameters: 0x0040 H
group 0x0040++7
line.long 0x00 "PHDR,Port H Data Register"
bitfld.long 0x00 3. " PHData3 ,Port H Data Pin 3" "Low,High"
bitfld.long 0x00 2. " PHData2 ,Port H Data Pin 2" "Low,High"
textline " "
bitfld.long 0x00 1. " PHData1 ,Port H Data Pin 1" "Low,High"
bitfld.long 0x00 0. " PHData0 ,Port H Data Pin 0" "Low,High"
line.long 0x04 "PHDDR,Port H Data Direction Register"
bitfld.long 0x04 3. " PHDIR3 ,Port H Direction Pin 3" "Input,Output"
bitfld.long 0x04 2. " PHDIR2 ,Port H Direction Pin 2" "Input,Output"
textline " "
bitfld.long 0x04 1. " PHDIR1 ,Port H Direction Pin 1" "Input,Output"
bitfld.long 0x04 0. " PHDIR0 ,Port H Direction Pin 0" "Input,Output"
;end include file EP9301/GPIO/PORTH.ph
tree.end
textline ""
;begin include file EP9301/GPIO/EE.ph
;parameters:
group 0x00C8++0x03
line.long 0x00 "EEDrive,EEPROM Interface Pin Drive Type Control"
bitfld.long 0x00 1. " DATOD ,EEDAT Pin Output Driver" "Low,High"
bitfld.long 0x00 0. " CLKOD ,EECLK Pin Output Driver" "Low,High"
;end include file EP9301/GPIO/EE.ph
;end include file EP9301/GPIO.ph
tree.end
tree "Security"
base 0x80830000
;begin include file EP9301/Security.ph
;parameters:
rgroup 0x2714++0x03
line.long 0x00 "ExtensionID,Part ID for EP93xx Devices"
hexmask.long.byte 0x00 1.--8. 1. " PartID ,Identification Number"
;end include file EP9301/Security.ph
tree.end
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