18588 lines
1.2 MiB
18588 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: AT91SAM9261/60/63 On-Chip Peripherals
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; @Props: Released
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; @Author: ADI, GAC, JAZ, KAM
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; @Changelog:
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; 2006-04-10
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; 2006-08-04
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; 2007-03-06
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; 2008-08-22
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: 6062.pdf (2006-02-03); 6062s.pdf (2006-02-03); doc6221.pdf (2006-09-22)
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; doc6249.pdf (2006-12-14)
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; Open_Host_Controller_Interface_Specification_for_USB__1_0A1.DOC
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; @Core: ARM926EJ-S
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perat91sam926x.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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width 0x0b
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base ad:0x00000000
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
|
|
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
|
|
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0xfffffd00
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "RSTC_CR,Reset Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "RSTC_SR,Reset Controller Status Register"
|
|
bitfld.long 0x00 17. " SRCMP ,Software Reset Command in Progress" "Not performed/ready,Performed/busy"
|
|
bitfld.long 0x00 16. " NRSTL ,NRST Pin Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RSTTYP ,Reset Type" "General Reset,Wake Up Reset,Watchdog Reset,Software Reset,User Reset,?..."
|
|
bitfld.long 0x00 0. " URSTS ,User Reset Status" "No high-to-low edge,High-to-low transition"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "RSTC_SR,Reset Controller Status Register"
|
|
in
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RSTC_MR,Reset Controller Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 16. " BODIEN , Brownout Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2-cycles,4-cycles,8-cycles,16-cycles,32-cycles,64-cycles,128-cycles,256-cycles,512-cycles,1024-cycles,2048-cycles,4096-cycles,8192-cycles,16384-cycles,32768-cycles,65536-cycles"
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "RTT (Real-Time Timer)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "RTT0"
|
|
base ad:0xfffffd50
|
|
width 11.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTT_MR,Real-Time Timer Mode Register"
|
|
bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "No effect,Restarted"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value"
|
|
line.long 0x4 "RTT_AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "RTT_VR,Real-Time Timer Value Register"
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "RTT_SR,Real-time Timer Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "RTT1"
|
|
base ad:0xfffffd20
|
|
width 11.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTT_MR,Real-Time Timer Mode Register"
|
|
bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "No effect,Restarted"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value"
|
|
line.long 0x4 "RTT_AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "RTT_VR,Real-Time Timer Value Register"
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "RTT_SR,Real-time Timer Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
base ad:0xfffffd20
|
|
endif
|
|
width 11.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTT_MR,Real-Time Timer Mode Register"
|
|
bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "No effect,Restarted"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value"
|
|
line.long 0x4 "RTT_AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "RTT_VR,Real-Time Timer Value Register"
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "RTT_SR,Real-time Timer Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PIT (Periodic Interval Timer)"
|
|
base ad:0xfffffd30
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PIT_MR,Periodic Interval Timer Mode Register"
|
|
bitfld.long 0x00 25. " PITIEN ,Periodic Interval Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PITEN ,Period Interval Timer Enabled" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. 1. " PIV ,Periodic Interval Value"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "PIT_SR,Periodic Interval Timer Status Register"
|
|
in
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x0 "PIT_PIVR,Periodic Interval Timer Value Register"
|
|
in
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x0 "PIT_PIIR,Periodic Interval Timer Image Register"
|
|
in
|
|
else
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "PIT_SR,Periodic Interval Timer Status Register"
|
|
bitfld.long 0x00 0. " PITS ,Periodic Interval Timer Status" "Not reached,Reached"
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x0 "PIT_PIVR,Periodic Interval Timer Value Register"
|
|
in
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "PIT_PIIR,Periodic Interval Timer Image Register"
|
|
hexmask.long.word 0x0 20.--31. 1. " PICNT ,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. " CPIV ,Current Periodic Interval Value"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0xfffffd40
|
|
width 8.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "WDT_CR,Watchdog Timer Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restart"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "WDT_MR,Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Running,Stopped"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog Processor Reset" "All,Processor"
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "WDT_SR,Watchdog Timer Status Register"
|
|
bitfld.long 0x00 1. " WDERR ,Watchdog Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " WDUNF ,Watchdog Underflow" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "WDT_SR,Status Register"
|
|
in
|
|
endif
|
|
;wgroup 0x0++0x0
|
|
width 0xb
|
|
tree.end
|
|
tree "SHDWC (Shutdown Controller)"
|
|
base ad:0xfffffd10
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "SHDW_CR,Shutdown Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " SHDW ,Shut Down Command" "No effect,Shut down"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SHDW_MR,Shutdown Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 17. " RTCWKEN , Real-time Clock Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 16. " RTTWKEN ,Real-time Timer Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CPTWK0 ,Counter on Wake-Up 0" "1 cycle,17 cycles,33 cycles,49 cycles,65 cycles,81 cycles,97 cycles,113 cycles,129 cycles,145 cycles,161 cycles,177 cycles,193 cycles,209 cycles,225 cycles,241 cycles"
|
|
bitfld.long 0x00 0.--1. " WKMODE0 ,Wake-Up Mode 0" "No wake-up,Low/high,High/low,Both"
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "SHDW_SR,Shutdown Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "Bus Matrix"
|
|
sif (cpu()=="AT91SAM9261")
|
|
base ad:0xffffee00
|
|
width 14.
|
|
sif (cpu()=="AT91SAM9G10")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "MATRIX_MCFG,Bus Matrix Master Configuration Register"
|
|
bitfld.long 0x00 1. " RCB1 ,AHB Master 1 Remap Command Bit" "No effect,Remapped"
|
|
bitfld.long 0x00 0. " RCB0 ,AHB Master 0 Remap Command Bit" "No effect,Remapped"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x0 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x4 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x4 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x8 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0xC 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x10 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "MATRIX_MCFG,Bus Matrix Master Configuration Register"
|
|
bitfld.long 0x00 4. " RCB4 ,AHB Master 4 Remap Command Bit" "No effect,Remapped"
|
|
bitfld.long 0x00 3. " RCB3 ,AHB Master 3 Remap Command Bit" "No effect,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RCB2 ,AHB Master 2 Remap Command Bit" "No effect,Remapped"
|
|
bitfld.long 0x00 1. " RCB1 ,AHB Master 1 Remap Command Bit" "No effect,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCB0 ,AHB Master 0 Remap Command Bit" "No effect,Remapped"
|
|
line.long 0x4 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x4 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x8 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0xC 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x10 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x14 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x14 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "EBI_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x00 8. " EBI_DBPUC ,EBI Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
bitfld.long 0x00 3. " EBI_CS3A ,EBI Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EBI_CS1A ,EBI Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
line.long 0x4 "USB_PUCR,USB Pad Pull-Up Control Register"
|
|
bitfld.long 0x4 30. " UDP_PUP_ON ,UDP Pad Pull-Up Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
sif (cpu()=="AT91SAM9260")
|
|
base ad:0xffffee00
|
|
width 14.
|
|
group.long 0x00++0x17
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0xC "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x10 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x14 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x0 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x0 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x0 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x4 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x4 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x4 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x8 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x8 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0xC 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x10 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x10 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x14 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x14 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x14 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x14 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x0 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x0 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x0 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x4 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x4 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x4 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x8 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x8 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0xC 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x10 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x10 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A for Slave 5 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
else
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
endif
|
|
width 14.
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MATRIX_MRCR,Master Remap Control Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 5. " RCB5 ,Remap Command Bit for AHB Master 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCB4 ,Remap Command Bit for AHB Master 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCB3 ,Remap Command Bit for AHB Master 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCB2 ,Remap Command Bit for AHB Master 2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for AHB Master 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for AHB Master 0" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "MATRIX_TCR,Bus Matrix TCM Configuration Register"
|
|
bitfld.long 0x00 4.--7. " DTCM_SIZE ,DTCM Enabled Memory Block Size" "0-KB,Reserved,Reserved,Reserved,Reserved,16-KB,32-KB,?..."
|
|
bitfld.long 0x00 0.--3. " ITCM_SIZE ,ITCM Enabled Memory Block Size" "0-KB,Reserved,Reserved,Reserved,Reserved,16-KB,32-KB,?..."
|
|
endif
|
|
group.long 0x120++3
|
|
line.long 0x0 "EBI1_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x0 16. " VDDIOMSEL ,Memory voltage selection" "1.8V,3.3V"
|
|
bitfld.long 0x0 8. " EBI_DBPUC ,EBI1 Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
bitfld.long 0x0 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " EBI_CS3A ,EBI1 Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
bitfld.long 0x0 1. " EBI_CS1A ,EBI1 Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
width 0xb
|
|
endif
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xffffec00
|
|
width 0xd
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "MATRIX_TCMR,Bus Matrix TCM Configuration Register"
|
|
bitfld.long 0x00 4.--7. " DTCM_SIZE ,Size of DTCM enabled memory block" "0 KB,Reserved,Reserved,Reserved,Reserved,16 KB,32 KB,?..."
|
|
bitfld.long 0x00 0.--3. " ITCM_SIZE ,Size of ITCM enabled memory block" "0 KB,Reserved,Reserved,Reserved,Reserved,16 KB,32 KB,?..."
|
|
width 0xa
|
|
group.long 0x120++0x7
|
|
line.long 0x00 "EBI0_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x00 16. " VDDIOMSEL ,Memory voltage selection" "1.8V,3.3V"
|
|
bitfld.long 0x00 8. " EBI0_DBPUC ,EBI0 Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EBI0_CS5A ,EBI0 Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
bitfld.long 0x00 4. " EBI0_CS4A ,EBI0 Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EBI0_CS3A ,EBI0 Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
bitfld.long 0x00 1. " EBI0_CS1A ,EBI0 Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
line.long 0x04 "EBI1_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x04 16. " VDDIOMSEL ,Memory voltage selection" "1.8V,3.3V"
|
|
bitfld.long 0x04 8. " EBI1_DBPUC ,EBI1 Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EBI1_CS3A ,EBI1 Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
bitfld.long 0x04 1. " EBI1_CS1A ,EBI1 Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree.open "SMC (Static Memory Controller)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "SMC0"
|
|
base ad:0xffffe400
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x60+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x60+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x60+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x70+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x70+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x70+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "SMC1"
|
|
base ad:0xffffea00
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x60+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x60+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x60+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe400+0x70+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe400+0x70+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe400+0x70+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe400+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
base ad:0xffffec00
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x60+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x60+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x60+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x70+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x70+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x70+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "SDRAMC (SDRAM Controller)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "SDRAMC0"
|
|
base ad:0xffffe200
|
|
width 12.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SDRAMC_MR,SDRAMC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,SDRAMC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "SDRAMC_TR,SDRAMC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,SDRAMC Refresh Timer Count"
|
|
line.long 0x8 "SDRAMC_CR,SDRAMC Configuration Register"
|
|
bitfld.long 0x8 28.--31. " TXSR ,Exit Self Refresh to Active Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 24.--27. " TRAS ,Active to Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 20.--23. " TRCD ,Row to Column Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 16.--19. " TRP ,Row Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " TRC ,Row Cycle Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 8.--11. " TWR ,Write Recovery Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 7. " DBW ,Data Bus Width" "32,16"
|
|
bitfld.long 0x8 5.--6. " CAS ,CAS Latency" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 4. " NB ,Number of Banks" "2 banks,4 banks"
|
|
bitfld.long 0x8 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRAMC_LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCSR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
group.long 0x1c++0x3
|
|
line.long 0x0 "SDRAMC_IMR,SDRAMC Interrupt Mask Register"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RES_set/clr ,Refresh Error Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SDRAMC_ISR,SDRAMC Interrupt Status Register"
|
|
bitfld.long 0x00 0. " Res ,Refresh Error Status" "No error,Error"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SDRAMC_MDR,SDRAMC Memory Device Register"
|
|
bitfld.long 0x0 0.--1. " MD ,Memory Device Type" "SDRAM,Low-power,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "SDRAMC1"
|
|
base ad:0xffffe800
|
|
width 12.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SDRAMC_MR,SDRAMC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,SDRAMC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "SDRAMC_TR,SDRAMC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,SDRAMC Refresh Timer Count"
|
|
line.long 0x8 "SDRAMC_CR,SDRAMC Configuration Register"
|
|
bitfld.long 0x8 28.--31. " TXSR ,Exit Self Refresh to Active Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 24.--27. " TRAS ,Active to Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 20.--23. " TRCD ,Row to Column Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 16.--19. " TRP ,Row Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " TRC ,Row Cycle Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 8.--11. " TWR ,Write Recovery Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 7. " DBW ,Data Bus Width" "32,16"
|
|
bitfld.long 0x8 5.--6. " CAS ,CAS Latency" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 4. " NB ,Number of Banks" "2 banks,4 banks"
|
|
bitfld.long 0x8 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRAMC_LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCSR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
group.long 0x1c++0x3
|
|
line.long 0x0 "SDRAMC_IMR,SDRAMC Interrupt Mask Register"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RES_set/clr ,Refresh Error Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SDRAMC_ISR,SDRAMC Interrupt Status Register"
|
|
bitfld.long 0x00 0. " Res ,Refresh Error Status" "No error,Error"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SDRAMC_MDR,SDRAMC Memory Device Register"
|
|
bitfld.long 0x0 0.--1. " MD ,Memory Device Type" "SDRAM,Low-power,?..."
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
base ad:0xffffea00
|
|
width 12.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SDRAMC_MR,SDRAMC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,SDRAMC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "SDRAMC_TR,SDRAMC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,SDRAMC Refresh Timer Count"
|
|
line.long 0x8 "SDRAMC_CR,SDRAMC Configuration Register"
|
|
bitfld.long 0x8 28.--31. " TXSR ,Exit Self Refresh to Active Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 24.--27. " TRAS ,Active to Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 20.--23. " TRCD ,Row to Column Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 16.--19. " TRP ,Row Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " TRC ,Row Cycle Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 8.--11. " TWR ,Write Recovery Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 7. " DBW ,Data Bus Width" "32,16"
|
|
bitfld.long 0x8 5.--6. " CAS ,CAS Latency" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 4. " NB ,Number of Banks" "2 banks,4 banks"
|
|
bitfld.long 0x8 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRAMC_LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCSR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
group.long 0x1c++0x3
|
|
line.long 0x0 "SDRAMC_IMR,SDRAMC Interrupt Mask Register"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RES_set/clr ,Refresh Error Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SDRAMC_ISR,SDRAMC Interrupt Status Register"
|
|
bitfld.long 0x00 0. " Res ,Refresh Error Status" "No error,Error"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SDRAMC_MDR,SDRAMC Memory Device Register"
|
|
bitfld.long 0x0 0.--1. " MD ,Memory Device Type" "SDRAM,Low-power,?..."
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9260")
|
|
tree "ECC (Error Corrected Code)"
|
|
base ad:0xffffe800
|
|
width 0x9
|
|
wgroup.long 0x00++3
|
|
line.long 0x00 "ECC_CR,ECC Control Register"
|
|
bitfld.long 0x00 0. " RST ,RESET Parity" "No effect,Reset"
|
|
group.long 0x04++3
|
|
line.long 0x00 "ECC_MR,ECC Mode Register"
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page Size" "528 words,1056 words,2112 words,4224 words"
|
|
rgroup.long 0x08++0xb
|
|
line.long 0x00 "ECC_SR,ECC Status Register"
|
|
bitfld.long 0x00 2. " MULERR ,Multiple Error" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR ,ECC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RECERR ,Recoverable Error" "No error,Error"
|
|
line.long 0x04 "ECC_PR,ECC Parity Register"
|
|
hexmask.long.byte 0x04 0.--3. 1. " BITADDR ,Corrupted bit offset where an error occurred"
|
|
hexmask.long.word 0x04 4.--15. 1. " WORDADDR ,Word address where an error occurred"
|
|
line.long 0x08 "ECC_NPR,ECC NParity Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " NPARITY ,NPARITY Value"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree.open "ECC (Error Corrected Code)"
|
|
tree "ECC0"
|
|
base ad:0xffffe000
|
|
width 0x9
|
|
wgroup.long 0x00++3
|
|
line.long 0x00 "ECC_CR,ECC Control Register"
|
|
bitfld.long 0x00 0. " RST ,RESET Parity" "No effect,Reset"
|
|
group.long 0x04++3
|
|
line.long 0x00 "ECC_MR,ECC Mode Register"
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page Size" "528 words,1056 words,2112 words,4224 words"
|
|
rgroup.long 0x08++0xb
|
|
line.long 0x00 "ECC_SR,ECC Status Register"
|
|
bitfld.long 0x00 2. " MULERR ,Multiple Error" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR ,ECC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RECERR ,Recoverable Error" "No error,Error"
|
|
line.long 0x04 "ECC_PR,ECC Parity Register"
|
|
hexmask.long.byte 0x04 0.--3. 1. " BITADDR ,Corrupted bit offset where an error occurred"
|
|
hexmask.long.word 0x04 4.--15. 1. " WORDADDR ,Word address where an error occurred"
|
|
line.long 0x08 "ECC_NPR,ECC NParity Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " NPARITY ,NPARITY Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "ECC1"
|
|
base ad:0xffffe600
|
|
width 0x9
|
|
wgroup.long 0x00++3
|
|
line.long 0x00 "ECC_CR,ECC Control Register"
|
|
bitfld.long 0x00 0. " RST ,RESET Parity" "No effect,Reset"
|
|
group.long 0x04++3
|
|
line.long 0x00 "ECC_MR,ECC Mode Register"
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page Size" "528 words,1056 words,2112 words,4224 words"
|
|
rgroup.long 0x08++0xb
|
|
line.long 0x00 "ECC_SR,ECC Status Register"
|
|
bitfld.long 0x00 2. " MULERR ,Multiple Error" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR ,ECC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RECERR ,Recoverable Error" "No error,Error"
|
|
line.long 0x04 "ECC_PR,ECC Parity Register"
|
|
hexmask.long.byte 0x04 0.--3. 1. " BITADDR ,Corrupted bit offset where an error occurred"
|
|
hexmask.long.word 0x04 4.--15. 1. " WORDADDR ,Word address where an error occurred"
|
|
line.long 0x08 "ECC_NPR,ECC NParity Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " NPARITY ,NPARITY Value"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "DMAC (DMA Controller)"
|
|
base ad:0x00800000
|
|
width 0xc
|
|
group.long (0x00+0x0)++0x3
|
|
line.long 0x00 "DMAC_SAR0,Channel 0 Source Address Register"
|
|
group.long (0x8+0x0)++3
|
|
line.long 0x00 "DMAC_DAR0,Channel 0 Destination Address Register"
|
|
group.long (0x10+0x0)++3
|
|
line.long 0x00 "DMAC_LLP0,Channel 0 Linked List Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " LOC ,Address of the next LLI"
|
|
group.long (0x18+0x0)++3
|
|
line.long 0x00 "DMAC_CTL0L,Channel 0 Control Register Low"
|
|
bitfld.long 0x00 28. " LLP_S_EN ,LLP Source Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LLP_D_EN ,LLP Destination Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " SMS ,Source Master Select" "AHB master 1,?..."
|
|
bitfld.long 0x00 23.--24. " DMS ,Destination Master Select" "AHB master 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " TT_FC ,Transfer Type and Flow Control" "Mem2Mem/DMAC,Mem2Per/DMAC,Per2Mem/DMAC,Per2Per/DMAC,Per2Mem/Per,Per2Per/Src Per,Mem2Per/Per,Per2Per/Dst Per"
|
|
bitfld.long 0x00 18. " D_SCAT_EN ,Destination Scatter Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_GATH_EN ,Source Gather Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--16. " SRC_MSIZE ,Source Burst Transaction Length" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " DEST_MSIZE ,Destination Burst Transaction Length" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--10. " SINC ,Source Address Increment" "Incremented,Decremented,Not changed,Not changed"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " DINC ,Character to be Transmitted" "Incremented,Decremented,Not changed,Not changed"
|
|
bitfld.long 0x00 4.--6. " SRC_TR_WIDTH ,Source Transfer Width" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " DST_TR_WIDTH ,Destination Transfer Width" "8,16,32,?..."
|
|
bitfld.long 0x00 0. " INT_EN ,Interrupt Enable Bit" "Disabled,Enabled"
|
|
group.long (0x1c+0x0)++3
|
|
line.long 0x00 "DMAC_CTL0H,Channel 0 Control Register High"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BLOCK_TS ,Block Transfer Size"
|
|
bitfld.long 0x00 12. " DONE ,Done Bit" "Not complete,Complete"
|
|
group.long (0x40+0x0)++3
|
|
line.long 0x00 "DMAC_CFG0L,Channel 0 Configuration Register Low"
|
|
bitfld.long 0x00 31. " RELOAD_DS ,Automatic Destination Reload" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 30. " RELOAD_SR ,Automatic Source Reload" "Not reloaded,Reloaded"
|
|
textline " "
|
|
hexmask.long.word 0x00 20.--29. 1. " MAX_ABRST ,Maximum AMBA Burst Length"
|
|
bitfld.long 0x00 19. " SR_HS_POL ,Source Handshaking Interface Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DS_HS_POL ,Destination Handshaking Interface Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 17. " LOCK_B ,Bus Lock Bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOCK_CH ,Channel Lock Bit" "Not locked ,Locked"
|
|
bitfld.long 0x00 14.--15. " LOCK_B_L ,Bus Lock Level" "Transfer,Block transfer,Transaction,Transaction"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " LOCK_CH_L ,Channel Lock Level" "Transfer,Block transfer,Transaction,Transaction"
|
|
bitfld.long 0x00 11. " HS_SEL_SRC ,Source Software or Hardware Handshaking Select" "Hardware,Software"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HS_SEL_DST ,Destination Software or Hardware Handshaking Select" "Hardware,Software"
|
|
bitfld.long 0x00 9. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CH_SUSP ,Channel Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 5.--7. " CH_PRIOR ,Channel priority" "0,1,2,3,4,5,6,7"
|
|
group.long (0x44+0x0)++3
|
|
line.long 0x00 "DMAC_CFG0H,Channel 0 Configuration Register High"
|
|
hexmask.long.byte 0x00 11.--14. 1. " DEST_PER ,Destination Hardware Handshaking Interface"
|
|
hexmask.long.byte 0x00 7.--10. 1. " SRC_PER ,Source Hardware Handshaking Interface"
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--4. 1. " PROTCTL ,Protection Control"
|
|
bitfld.long 0x00 1. " FIFO_MODE ,R/W 0x0 FIFO Mode Select" "Single AMBA transfer,Half or more of depth"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCMODE ,Flow Control Mode" "Serviced,Not serviced"
|
|
group.long (0x48+0x0)++3
|
|
line.long 0x00 "DMAC_SGR0,Channel 0 Source Gather Register"
|
|
hexmask.long.byte 0x00 20.--23. 1. " SGC ,Source gather count"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " SGI ,Source Gather Interval"
|
|
group.long (0x50+0x0)++3
|
|
line.long 0x00 "DMAC_DSR0,Channel 0 Destination Scatter Register"
|
|
hexmask.long.byte 0x00 20.--23. 1. " DSC ,Destination Scatter count"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " DSI ,Destination Scatter Interval"
|
|
group.long (0x00+0x58)++0x3
|
|
line.long 0x00 "DMAC_SAR1,Channel 1 Source Address Register"
|
|
group.long (0x8+0x58)++3
|
|
line.long 0x00 "DMAC_DAR1,Channel 1 Destination Address Register"
|
|
group.long (0x10+0x58)++3
|
|
line.long 0x00 "DMAC_LLP1,Channel 1 Linked List Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " LOC ,Address of the next LLI"
|
|
group.long (0x18+0x58)++3
|
|
line.long 0x00 "DMAC_CTL1L,Channel 1 Control Register Low"
|
|
bitfld.long 0x00 28. " LLP_S_EN ,LLP Source Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LLP_D_EN ,LLP Destination Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " SMS ,Source Master Select" "AHB master 1,?..."
|
|
bitfld.long 0x00 23.--24. " DMS ,Destination Master Select" "AHB master 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " TT_FC ,Transfer Type and Flow Control" "Mem2Mem/DMAC,Mem2Per/DMAC,Per2Mem/DMAC,Per2Per/DMAC,Per2Mem/Per,Per2Per/Src Per,Mem2Per/Per,Per2Per/Dst Per"
|
|
bitfld.long 0x00 18. " D_SCAT_EN ,Destination Scatter Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_GATH_EN ,Source Gather Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--16. " SRC_MSIZE ,Source Burst Transaction Length" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " DEST_MSIZE ,Destination Burst Transaction Length" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--10. " SINC ,Source Address Increment" "Incremented,Decremented,Not changed,Not changed"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " DINC ,Character to be Transmitted" "Incremented,Decremented,Not changed,Not changed"
|
|
bitfld.long 0x00 4.--6. " SRC_TR_WIDTH ,Source Transfer Width" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " DST_TR_WIDTH ,Destination Transfer Width" "8,16,32,?..."
|
|
bitfld.long 0x00 0. " INT_EN ,Interrupt Enable Bit" "Disabled,Enabled"
|
|
group.long (0x1c+0x58)++3
|
|
line.long 0x00 "DMAC_CTL1H,Channel 1 Control Register High"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BLOCK_TS ,Block Transfer Size"
|
|
bitfld.long 0x00 12. " DONE ,Done Bit" "Not complete,Complete"
|
|
group.long (0x40+0x58)++3
|
|
line.long 0x00 "DMAC_CFG1L,Channel 1 Configuration Register Low"
|
|
bitfld.long 0x00 31. " RELOAD_DS ,Automatic Destination Reload" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 30. " RELOAD_SR ,Automatic Source Reload" "Not reloaded,Reloaded"
|
|
textline " "
|
|
hexmask.long.word 0x00 20.--29. 1. " MAX_ABRST ,Maximum AMBA Burst Length"
|
|
bitfld.long 0x00 19. " SR_HS_POL ,Source Handshaking Interface Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DS_HS_POL ,Destination Handshaking Interface Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 17. " LOCK_B ,Bus Lock Bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOCK_CH ,Channel Lock Bit" "Not locked ,Locked"
|
|
bitfld.long 0x00 14.--15. " LOCK_B_L ,Bus Lock Level" "Transfer,Block transfer,Transaction,Transaction"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " LOCK_CH_L ,Channel Lock Level" "Transfer,Block transfer,Transaction,Transaction"
|
|
bitfld.long 0x00 11. " HS_SEL_SRC ,Source Software or Hardware Handshaking Select" "Hardware,Software"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HS_SEL_DST ,Destination Software or Hardware Handshaking Select" "Hardware,Software"
|
|
bitfld.long 0x00 9. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CH_SUSP ,Channel Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 5.--7. " CH_PRIOR ,Channel priority" "0,1,2,3,4,5,6,7"
|
|
group.long (0x44+0x58)++3
|
|
line.long 0x00 "DMAC_CFG1H,Channel 1 Configuration Register High"
|
|
hexmask.long.byte 0x00 11.--14. 1. " DEST_PER ,Destination Hardware Handshaking Interface"
|
|
hexmask.long.byte 0x00 7.--10. 1. " SRC_PER ,Source Hardware Handshaking Interface"
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--4. 1. " PROTCTL ,Protection Control"
|
|
bitfld.long 0x00 1. " FIFO_MODE ,R/W 0x0 FIFO Mode Select" "Single AMBA transfer,Half or more of depth"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCMODE ,Flow Control Mode" "Serviced,Not serviced"
|
|
group.long (0x48+0x58)++3
|
|
line.long 0x00 "DMAC_SGR1,Channel 1 Source Gather Register"
|
|
hexmask.long.byte 0x00 20.--23. 1. " SGC ,Source gather count"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " SGI ,Source Gather Interval"
|
|
group.long (0x50+0x58)++3
|
|
line.long 0x00 "DMAC_DSR1,Channel 1 Destination Scatter Register"
|
|
hexmask.long.byte 0x00 20.--23. 1. " DSC ,Destination Scatter count"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " DSI ,Destination Scatter Interval"
|
|
width 0x14
|
|
rgroup.long 0x2c0++3
|
|
line.long 0x00 "DMAC_RawTfr,Raw Status for IntTfr Interrupt"
|
|
bitfld.long 0x00 1. " RAW1 ,Raw interrupt channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAW0 ,Raw interrupt channel 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x2c8++3
|
|
line.long 0x00 "DMAC_RawBlock,Raw Status for IntBlock Interrupt"
|
|
bitfld.long 0x00 1. " RAW1 ,Raw interrupt channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAW0 ,Raw interrupt channel 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x2d0++3
|
|
line.long 0x00 "DMAC_RawSrcTran,Raw Status for IntSrcTran Interrupt"
|
|
bitfld.long 0x00 1. " RAW1 ,Raw interrupt channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAW0 ,Raw interrupt channel 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x2d8++3
|
|
line.long 0x00 "DMAC_RawDstTran,Raw Status for IntDstTran Interrupt"
|
|
bitfld.long 0x00 1. " RAW1 ,Raw interrupt channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAW0 ,Raw interrupt channel 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x2e0++3
|
|
line.long 0x00 "DMAC_RawErr,Raw Status for IntErr Interrupt"
|
|
bitfld.long 0x00 1. " RAW1 ,Raw interrupt channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAW0 ,Raw interrupt channel 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x2e8++3
|
|
line.long 0x00 "DMAC_StatusTfr,Status for IntTfr Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,Interrupt Status 1" "Not complete,Complete"
|
|
bitfld.long 0x00 0. " STATUS0 ,Interrupt Status 0" "Not complete,Complete"
|
|
rgroup.long 0x2f0++3
|
|
line.long 0x00 "DMAC_StatusBlock,Status for IntBlock Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,Interrupt Status 1" "Not complete,Complete"
|
|
bitfld.long 0x00 0. " STATUS0 ,Interrupt Status 0" "Not complete,Complete"
|
|
rgroup.long 0x2f8++3
|
|
line.long 0x00 "DMAC_StatusSrcTran,Status for IntSrcTran Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,Interrupt Status 1" "Not complete,Complete"
|
|
bitfld.long 0x00 0. " STATUS0 ,Interrupt Status 0" "Not complete,Complete"
|
|
rgroup.long 0x300++3
|
|
line.long 0x00 "DMAC_StatusDstTran,Status for IntDstTran Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,Interrupt Status 1" "Not complete,Complete"
|
|
bitfld.long 0x00 0. " STATUS0 ,Interrupt Status 0" "Not complete,Complete"
|
|
rgroup.long 0x308++3
|
|
line.long 0x00 "DMAC_StatusErr,Status for IntErr Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,Interrupt Status 1" "Not complete,Complete"
|
|
bitfld.long 0x00 0. " STATUS0 ,Interrupt Status 0" "Not complete,Complete"
|
|
group.long 0x310++3
|
|
line.long 0x00 "DMAC_MaskTfr,Mask for IntTfr Interrupt"
|
|
bitfld.long 0x00 9. " INT_M_WE1 ,Interrupt Mask Write Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INT_M_WE0 ,Interrupt Mask Write Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NT_MASK1 ,Interrupt Mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " NT_MASK0 ,Interrupt Mask 0" "Masked,Unmasked"
|
|
group.long 0x318++3
|
|
line.long 0x00 "DMAC_MaskBlock,Mask for IntBlock Interrupt"
|
|
bitfld.long 0x00 9. " INT_M_WE1 ,Interrupt Mask Write Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INT_M_WE0 ,Interrupt Mask Write Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NT_MASK1 ,Interrupt Mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " NT_MASK0 ,Interrupt Mask 0" "Masked,Unmasked"
|
|
group.long 0x320++3
|
|
line.long 0x00 "DMAC_MaskSrcTran,Mask for IntSrcTran Interrupt"
|
|
bitfld.long 0x00 9. " INT_M_WE1 ,Interrupt Mask Write Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INT_M_WE0 ,Interrupt Mask Write Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NT_MASK1 ,Interrupt Mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " NT_MASK0 ,Interrupt Mask 0" "Masked,Unmasked"
|
|
group.long 0x328++3
|
|
line.long 0x00 "DMAC_MaskDstTran,Mask for IntDstTran Interrupt"
|
|
bitfld.long 0x00 9. " INT_M_WE1 ,Interrupt Mask Write Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INT_M_WE0 ,Interrupt Mask Write Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NT_MASK1 ,Interrupt Mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " NT_MASK0 ,Interrupt Mask 0" "Masked,Unmasked"
|
|
group.long 0x330++3
|
|
line.long 0x00 "DMAC_MaskErr,Mask for IntErr Interrupt"
|
|
bitfld.long 0x00 9. " INT_M_WE1 ,Interrupt Mask Write Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INT_M_WE0 ,Interrupt Mask Write Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NT_MASK1 ,Interrupt Mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " NT_MASK0 ,Interrupt Mask 0" "Masked,Unmasked"
|
|
wgroup.long 0x338++3
|
|
line.long 0x00 "DMAC_ClearTfr,Clear for IntTfr Interrupt"
|
|
bitfld.long 0x00 1. " CLEAR1 ,Interrupt Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " CLEAR0 ,Interrupt Clear 0" "No effect,Cleared"
|
|
wgroup.long 0x340++3
|
|
line.long 0x00 "DMAC_ClearBlock,Clear for IntBlock Interrupt"
|
|
bitfld.long 0x00 1. " CLEAR1 ,Interrupt Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " CLEAR0 ,Interrupt Clear 0" "No effect,Cleared"
|
|
wgroup.long 0x348++3
|
|
line.long 0x00 "DMAC_ClearSrcTran,Clear for IntSrcTran Interrupt"
|
|
bitfld.long 0x00 1. " CLEAR1 ,Interrupt Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " CLEAR0 ,Interrupt Clear 0" "No effect,Cleared"
|
|
wgroup.long 0x350++3
|
|
line.long 0x00 "DMAC_ClearDstTran,Clear for IntDstTran Interrupt"
|
|
bitfld.long 0x00 1. " CLEAR1 ,Interrupt Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " CLEAR0 ,Interrupt Clear 0" "No effect,Cleared"
|
|
wgroup.long 0x358++3
|
|
line.long 0x00 "DMAC_ClearErr,Clear for IntErr Interrupt"
|
|
bitfld.long 0x00 1. " CLEAR1 ,Interrupt Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " CLEAR0 ,Interrupt Clear 0" "No effect,Cleared"
|
|
rgroup.long 0x360++3
|
|
line.long 0x00 "DMAC_StatusInt,Status for each interrupt type"
|
|
bitfld.long 0x00 4. " ERR ,OR of the contents of DMAC_StatusErr Register" "0,1"
|
|
bitfld.long 0x00 3. " DSTT ,OR of the contents of DMAC_StatusDstTran Register" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRCT ,OR of the contents of DMAC_StatusSrcTran Register" "0,1"
|
|
bitfld.long 0x00 1. " BLOCK ,OR of the contents of DMAC_StatusBlock Register" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFR ,OR of the contents of DMAC_StatusTfr Register" "0,1"
|
|
group.long 0x368++3
|
|
line.long 0x00 "DMAC_ReqSrcReg,Source Software Transaction Request Register"
|
|
bitfld.long 0x00 9. " REQ_WE1 ,Request write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " REQ_WE0 ,Request write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRC_REQ1 ,Source request 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " SRC_REQ0 ,Source request 0" "Not requested,Requested"
|
|
group.long 0x370++3
|
|
line.long 0x00 "DMAC_ReqDstReg,Destination Software Transaction Request Register"
|
|
bitfld.long 0x00 9. " REQ_WE1 ,Request write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " REQ_WE0 ,Request write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DST_REQ1 ,Destination request 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " DST_REQ0 ,Destination request 0" "Not requested,Requested"
|
|
group.long 0x378++3
|
|
line.long 0x00 "DMAC_SglReqSrcReg,Single Source Transaction Request Register"
|
|
bitfld.long 0x00 9. " REQ_WE1 ,Request write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " REQ_WE0 ,Request write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S_SG_REQ1 ,Source single request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " S_SG_REQ0 ,Source single request" "Not requested,Requested"
|
|
group.long 0x380++3
|
|
line.long 0x00 "DMAC_SglReqDstReg,Single Destination Transaction Request Register"
|
|
bitfld.long 0x00 9. " REQ_WE1 ,Request write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " REQ_WE0 ,Request write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " D_SG_REQ1 ,Destination single request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " D_SG_REQ0 ,Destination single request" "Not requested,Requested"
|
|
group.long 0x388++3
|
|
line.long 0x00 "DMAC_LstSrcReg,Last Source Transaction Request Register"
|
|
bitfld.long 0x00 9. " LSTSR_WE1 ,Source Last Transaction Request write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LSTSR_WE0 ,Source Last Transaction Request write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTSRC1 ,Source Last Transaction request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " LSTSRC0 ,Source Last Transaction request" "Not requested,Requested"
|
|
group.long 0x390++3
|
|
line.long 0x00 "DMAC_LstDstReg,Last Destination Transaction Request Register"
|
|
bitfld.long 0x00 9. " LSTSR_WE1 ,Destination Last Transaction Request write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LSTSR_WE0 ,Destination Last Transaction Request write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTSRC1 ,Destination Last Transaction request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " LSTSRC0 ,Destination Last Transaction request" "Not requested,Requested"
|
|
group.long 0x398++3
|
|
line.long 0x00 "DMAC_DmaCfgReg,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " DMA_EN ,DMA Controller Enable" "Disabled,Enabled"
|
|
group.long 0x3a0++3
|
|
line.long 0x00 "DMAC_ChEnReg,Channel Enable Register"
|
|
bitfld.long 0x00 9. " CH_EN_WE1 ,Channel 1 Write Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH_EN_WE0 ,Channel 0 Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH_EN1 ,Channel 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH_EN0 ,Channel 0 Enable" "Disabled,Enabled"
|
|
rgroup.long 0x3a8++3
|
|
line.long 0x00 "DMAC_IdReg,DMA ID Register"
|
|
group.long 0x3b0++3
|
|
line.long 0x00 "DMAC_DmaTestReg,DMA Test Register"
|
|
rgroup.long 0x3b8++3
|
|
line.long 0x00 "DMAC_VerIdReg,DMA Version ID Register"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xfffffc00
|
|
width 0x12
|
|
sif (cpu()=="AT91SAM9G10")
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x00 0. " PCK ,Processor Clock Disable" "No effect,Disable"
|
|
endif
|
|
group.long 0x08++03
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " HCK1_set/clr ,HClock Output 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " HCK0_set/clr ,HClock Output 0 Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9260"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PCK3_set/clr ,Programmable Clock 3 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK2_set/clr ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_set/clr ,USB Device Port Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G10")
|
|
textline " "
|
|
bitfld.long 0x0 0. " PCK ,Processor Clock Status" "Disabled,Enabled"
|
|
elif (cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " PCK_set/clr ,Processor Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Disable Register "
|
|
bitfld.long 0x0 0. " PCK ,Processor Clock Disable" "No effect,Disabled"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
bitfld.long 0x0 0. " PCK ,Processor Clock Status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PID31_set/clr ,Peripheral Clock 31 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " PID30_set/clr ,Peripheral Clock 30 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " PID29_set/clr ,Peripheral Clock 29 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " PID28_set/clr ,Peripheral Clock 28 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PID27_set/clr ,Peripheral Clock 27 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PID26_set/clr ,Peripheral Clock 26 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " PID25_set/clr ,Peripheral Clock 25 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " PID24_set/clr ,Peripheral Clock 24 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " PID23_set/clr ,Peripheral Clock 23 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " PID22_set/clr ,Peripheral Clock 22 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " PID21_set/clr ,Peripheral Clock 21 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " PID20_set/clr ,Peripheral Clock 20 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PID19_set/clr ,Peripheral Clock 19 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PID18_set/clr ,Peripheral Clock 18 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " PID17_set/clr ,Peripheral Clock 17 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " PID16_set/clr ,Peripheral Clock 16 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PID15_set/clr ,Peripheral Clock 15 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PID14_set/clr ,Peripheral Clock 14 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PID13_set/clr ,Peripheral Clock 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PID12_set/clr ,Peripheral Clock 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PID11_set/clr ,Peripheral Clock 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PID10_set/clr ,Peripheral Clock 10 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PID9_set/clr ,Peripheral Clock 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PID8_set/clr ,Peripheral Clock 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PID7_set/clr ,Peripheral Clock 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " PID6_set/clr ,Peripheral Clock 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PID5_set/clr ,Peripheral Clock 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " PID4_set/clr ,Peripheral Clock 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PID3_set/clr ,Peripheral Clock 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PID2_set/clr ,Peripheral Clock 2 Status" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OSCOUNT ,Main Oscillator Start-up Time"
|
|
bitfld.long 0x00 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0xB
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "80-200 MHz,Reserved,190-220 MHz,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "80-300 MHz,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "80-200 MHz,Reserved,190-240 MHz,?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
line.long 0x4 "CKGR_PLLBR,PMC Clock Generator PLL B Register"
|
|
bitfld.long 0x4 28.--29. " USBDIV ,Divider for USB Clock" "PLL B,PLL B/2,PLL B/4,?..."
|
|
hexmask.long.word 0x4 16.--26. 1. " MULB ,PLL Multiplier"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "Reserved,70-130 MHz,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "80-300 MHz,?..."
|
|
else
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "80-200 MHz,Reserved,190-240 MHz,?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " PLLBCOUNT ,PLL B Counter"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " DIVB ,Divider B"
|
|
line.long 0x8 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x8 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,?..."
|
|
bitfld.long 0x8 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9261"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9G10")
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x00 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
line.long 0x04 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x04 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x04 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
endif
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpu()!="AT91SAM9260"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
setclrfld.long 0x00 11. -0xc 11. -0x8 11. " PCKRDY3_set/clr ,Programmable Clock Ready 3 Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCKRDY2_set/clr ,Programmable Clock Ready 2 Interrupt Mask" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0xc 2. -0x8 2. " LOCKB_set/clr ,PLL B Lock Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Enabled,Disabled"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9G10")
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
sif (cpu()!="AT91SAM9260"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
bitfld.long 0x00 11. " PCKRDY3 ,Programmable Clock Ready 3 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " PCKRDY2 ,Programmable Clock Ready 2 Status" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 7. " OSC_SEL , Slow Clock Oscillator Selection" "Internal,External"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " LOCKB ,PLL B Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized"
|
|
endif
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9G10")
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "PMC_PLLICPR,Charge Pump Current Register"
|
|
bitfld.long 0x00 16. " ICPPLLB ,Charge pump current" "Reserved,1"
|
|
bitfld.long 0x00 0. " ICPPLLA ,Charge pump current" "Reserved,1"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "AIC (Advanced Interrupt Controller)"
|
|
base ad:0xfffff000
|
|
width 11.
|
|
tree "Source Mode Registers"
|
|
group.long 0x00++0x7f
|
|
line.long 0x0 "AIC_SMR0,AIC Source Mode Register 0"
|
|
bitfld.long 0x0 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x0 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
endif
|
|
line.long 0x4 "AIC_SMR1,AIC Source Mode Register 1"
|
|
bitfld.long 0x4 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x8 "AIC_SMR2,AIC Source Mode Register 2"
|
|
bitfld.long 0x8 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x8 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0xC "AIC_SMR3,AIC Source Mode Register 3"
|
|
bitfld.long 0xC 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0xC 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x10 "AIC_SMR4,AIC Source Mode Register 4"
|
|
bitfld.long 0x10 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x10 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x14 "AIC_SMR5,AIC Source Mode Register 5"
|
|
bitfld.long 0x14 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x14 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x18 "AIC_SMR6,AIC Source Mode Register 6"
|
|
bitfld.long 0x18 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x18 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x1C "AIC_SMR7,AIC Source Mode Register 7"
|
|
bitfld.long 0x1C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x1C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x20 "AIC_SMR8,AIC Source Mode Register 8"
|
|
bitfld.long 0x20 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x20 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x24 "AIC_SMR9,AIC Source Mode Register 9"
|
|
bitfld.long 0x24 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x24 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x28 "AIC_SMR10,AIC Source Mode Register 10"
|
|
bitfld.long 0x28 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x28 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x2C "AIC_SMR11,AIC Source Mode Register 11"
|
|
bitfld.long 0x2C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x2C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x30 "AIC_SMR12,AIC Source Mode Register 12"
|
|
bitfld.long 0x30 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x30 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x34 "AIC_SMR13,AIC Source Mode Register 13"
|
|
bitfld.long 0x34 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x34 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x38 "AIC_SMR14,AIC Source Mode Register 14"
|
|
bitfld.long 0x38 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x38 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x3C "AIC_SMR15,AIC Source Mode Register 15"
|
|
bitfld.long 0x3C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x3C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x40 "AIC_SMR16,AIC Source Mode Register 16"
|
|
bitfld.long 0x40 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x40 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x44 "AIC_SMR17,AIC Source Mode Register 17"
|
|
bitfld.long 0x44 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x44 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x48 "AIC_SMR18,AIC Source Mode Register 18"
|
|
bitfld.long 0x48 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x48 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x4C "AIC_SMR19,AIC Source Mode Register 19"
|
|
bitfld.long 0x4C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x50 "AIC_SMR20,AIC Source Mode Register 20"
|
|
bitfld.long 0x50 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x50 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x54 "AIC_SMR21,AIC Source Mode Register 21"
|
|
bitfld.long 0x54 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x54 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x58 "AIC_SMR22,AIC Source Mode Register 22"
|
|
bitfld.long 0x58 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x58 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x5C "AIC_SMR23,AIC Source Mode Register 23"
|
|
bitfld.long 0x5C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x5C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x60 "AIC_SMR24,AIC Source Mode Register 24"
|
|
bitfld.long 0x60 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x60 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x64 "AIC_SMR25,AIC Source Mode Register 25"
|
|
bitfld.long 0x64 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x64 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x68 "AIC_SMR26,AIC Source Mode Register 26"
|
|
bitfld.long 0x68 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x68 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x6C "AIC_SMR27,AIC Source Mode Register 27"
|
|
bitfld.long 0x6C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x6C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x70 "AIC_SMR28,AIC Source Mode Register 28"
|
|
bitfld.long 0x70 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x70 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x74 "AIC_SMR29,AIC Source Mode Register 29"
|
|
bitfld.long 0x74 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x74 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x78 "AIC_SMR30,AIC Source Mode Register 30"
|
|
bitfld.long 0x78 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x78 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x7C "AIC_SMR31,AIC Source Mode Register 31"
|
|
bitfld.long 0x7C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x7C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
tree.end
|
|
tree "Source Vector Registers"
|
|
group.long 0x80++0x7f
|
|
textline ""
|
|
line.long 0x0 "AIC_SVR0 ,AIC Source Vector Register 0 "
|
|
textline ""
|
|
line.long 0x4 "AIC_SVR1 ,AIC Source Vector Register 1 "
|
|
textline ""
|
|
line.long 0x8 "AIC_SVR2 ,AIC Source Vector Register 2 "
|
|
textline ""
|
|
line.long 0xC "AIC_SVR3 ,AIC Source Vector Register 3 "
|
|
textline ""
|
|
line.long 0x10 "AIC_SVR4 ,AIC Source Vector Register 4 "
|
|
textline ""
|
|
line.long 0x14 "AIC_SVR5 ,AIC Source Vector Register 5 "
|
|
textline ""
|
|
line.long 0x18 "AIC_SVR6 ,AIC Source Vector Register 6 "
|
|
textline ""
|
|
line.long 0x1C "AIC_SVR7 ,AIC Source Vector Register 7 "
|
|
textline ""
|
|
line.long 0x20 "AIC_SVR8 ,AIC Source Vector Register 8 "
|
|
textline ""
|
|
line.long 0x24 "AIC_SVR9 ,AIC Source Vector Register 9 "
|
|
textline ""
|
|
line.long 0x28 "AIC_SVR10,AIC Source Vector Register 10"
|
|
textline ""
|
|
line.long 0x2C "AIC_SVR11,AIC Source Vector Register 11"
|
|
textline ""
|
|
line.long 0x30 "AIC_SVR12,AIC Source Vector Register 12"
|
|
textline ""
|
|
line.long 0x34 "AIC_SVR13,AIC Source Vector Register 13"
|
|
textline ""
|
|
line.long 0x38 "AIC_SVR14,AIC Source Vector Register 14"
|
|
textline ""
|
|
line.long 0x3C "AIC_SVR15,AIC Source Vector Register 15"
|
|
textline ""
|
|
line.long 0x40 "AIC_SVR16,AIC Source Vector Register 16"
|
|
textline ""
|
|
line.long 0x44 "AIC_SVR17,AIC Source Vector Register 17"
|
|
textline ""
|
|
line.long 0x48 "AIC_SVR18,AIC Source Vector Register 18"
|
|
textline ""
|
|
line.long 0x4C "AIC_SVR19,AIC Source Vector Register 19"
|
|
textline ""
|
|
line.long 0x50 "AIC_SVR20,AIC Source Vector Register 20"
|
|
textline ""
|
|
line.long 0x54 "AIC_SVR21,AIC Source Vector Register 21"
|
|
textline ""
|
|
line.long 0x58 "AIC_SVR22,AIC Source Vector Register 22"
|
|
textline ""
|
|
line.long 0x5C "AIC_SVR23,AIC Source Vector Register 23"
|
|
textline ""
|
|
line.long 0x60 "AIC_SVR24,AIC Source Vector Register 24"
|
|
textline ""
|
|
line.long 0x64 "AIC_SVR25,AIC Source Vector Register 25"
|
|
textline ""
|
|
line.long 0x68 "AIC_SVR26,AIC Source Vector Register 26"
|
|
textline ""
|
|
line.long 0x6C "AIC_SVR27,AIC Source Vector Register 27"
|
|
textline ""
|
|
line.long 0x70 "AIC_SVR28,AIC Source Vector Register 28"
|
|
textline ""
|
|
line.long 0x74 "AIC_SVR29,AIC Source Vector Register 29"
|
|
textline ""
|
|
line.long 0x78 "AIC_SVR30,AIC Source Vector Register 30"
|
|
textline ""
|
|
line.long 0x7C "AIC_SVR31,AIC Source Vector Register 31"
|
|
tree.end
|
|
textline " "
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x00 "AIC_IVR,AIC Interrupt Vector Register"
|
|
line.long 0x04 "AIC_FVR,AIC FIQ Vector Register"
|
|
line.long 0x08 "AIC_ISR,AIC Interrupt Status Register"
|
|
bitfld.long 0x08 0.--4. " IRQID ,Current Interrupt Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x07
|
|
line.long 0x0 "AIC_IPR,AIC Interrupt Pending Register"
|
|
setclrfld.long 0x0 31. 0x20 31. 0x1C 31. " PID31_set/clr ,Interrupt 31 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 30. 0x20 30. 0x1C 30. " PID30_set/clr ,Interrupt 30 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x20 29. 0x1C 29. " PID29_set/clr ,Interrupt 29 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 28. 0x20 28. 0x1C 28. " PID28_set/clr ,Interrupt 28 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x20 27. 0x1C 27. " PID27_set/clr ,Interrupt 27 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 26. 0x20 26. 0x1C 26. " PID26_set/clr ,Interrupt 26 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x20 25. 0x1C 25. " PID25_set/clr ,Interrupt 25 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 24. 0x20 24. 0x1C 24. " PID24_set/clr ,Interrupt 24 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x20 23. 0x1C 23. " PID23_set/clr ,Interrupt 23 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 22. 0x20 22. 0x1C 22. " PID22_set/clr ,Interrupt 22 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x20 21. 0x1C 21. " PID21_set/clr ,Interrupt 21 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 20. 0x20 20. 0x1C 20. " PID20_set/clr ,Interrupt 20 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x20 19. 0x1C 19. " PID19_set/clr ,Interrupt 19 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 18. 0x20 18. 0x1C 18. " PID18_set/clr ,Interrupt 18 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x20 17. 0x1C 17. " PID17_set/clr ,Interrupt 17 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 16. 0x20 16. 0x1C 16. " PID16_set/clr ,Interrupt 16 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x20 15. 0x1C 15. " PID15_set/clr ,Interrupt 15 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 14. 0x20 14. 0x1C 14. " PID14_set/clr ,Interrupt 14 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x20 13. 0x1C 13. " PID13_set/clr ,Interrupt 13 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 12. 0x20 12. 0x1C 12. " PID12_set/clr ,Interrupt 12 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x20 11. 0x1C 11. " PID11_set/clr ,Interrupt 11 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 10. 0x20 10. 0x1C 10. " PID10_set/clr ,Interrupt 10 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x20 9. 0x1C 9. " PID9_set/clr ,Interrupt 9 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 8. 0x20 8. 0x1C 8. " PID8_set/clr ,Interrupt 8 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x20 7. 0x1C 7. " PID7_set/clr ,Interrupt 7 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 6. 0x20 6. 0x1C 6. " PID6_set/clr ,Interrupt 6 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x20 5. 0x1C 5. " PID5_set/clr ,Interrupt 5 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 4. 0x20 4. 0x1C 4. " PID4_set/clr ,Interrupt 4 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x20 3. 0x1C 3. " PID3_set/clr ,Interrupt 3 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 2. 0x20 2. 0x1C 2. " PID2_set/clr ,Interrupt 2 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x20 1. 0x1C 1. " SYS_set/clr ,SYS Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 0. 0x20 0. 0x1C 0. " FIQ_set/clr ,FIQ Interrupt Pending" "Not pending,Pending"
|
|
line.long 0x4 "AIC_IMR,AIC Interrupt Mask Register"
|
|
setclrfld.long 0x4 31. 0x14 31. 0x18 31. " PID31_set/clr ,Interrupt 31 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 30. 0x14 30. 0x18 30. " PID30_set/clr ,Interrupt 30 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 29. 0x14 29. 0x18 29. " PID29_set/clr ,Interrupt 29 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 28. 0x14 28. 0x18 28. " PID28_set/clr ,Interrupt 28 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 27. 0x14 27. 0x18 27. " PID27_set/clr ,Interrupt 27 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 26. 0x14 26. 0x18 26. " PID26_set/clr ,Interrupt 26 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 25. 0x14 25. 0x18 25. " PID25_set/clr ,Interrupt 25 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 24. 0x14 24. 0x18 24. " PID24_set/clr ,Interrupt 24 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 23. 0x14 23. 0x18 23. " PID23_set/clr ,Interrupt 23 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 22. 0x14 22. 0x18 22. " PID22_set/clr ,Interrupt 22 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 21. 0x14 21. 0x18 21. " PID21_set/clr ,Interrupt 21 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 20. 0x14 20. 0x18 20. " PID20_set/clr ,Interrupt 20 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 19. 0x14 19. 0x18 19. " PID19_set/clr ,Interrupt 19 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 18. 0x14 18. 0x18 18. " PID18_set/clr ,Interrupt 18 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 17. 0x14 17. 0x18 17. " PID17_set/clr ,Interrupt 17 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 16. 0x14 16. 0x18 16. " PID16_set/clr ,Interrupt 16 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 15. 0x14 15. 0x18 15. " PID15_set/clr ,Interrupt 15 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 14. 0x14 14. 0x18 14. " PID14_set/clr ,Interrupt 14 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 13. 0x14 13. 0x18 13. " PID13_set/clr ,Interrupt 13 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 12. 0x14 12. 0x18 12. " PID12_set/clr ,Interrupt 12 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 11. 0x14 11. 0x18 11. " PID11_set/clr ,Interrupt 11 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 10. 0x14 10. 0x18 10. " PID10_set/clr ,Interrupt 10 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 9. 0x14 9. 0x18 9. " PID9_set/clr ,Interrupt 9 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 8. 0x14 8. 0x18 8. " PID8_set/clr ,Interrupt 8 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 7. 0x14 7. 0x18 7. " PID7_set/clr ,Interrupt 7 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 6. 0x14 6. 0x18 6. " PID6_set/clr ,Interrupt 6 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 5. 0x14 5. 0x18 5. " PID5_set/clr ,Interrupt 5 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 4. 0x14 4. 0x18 4. " PID4_set/clr ,Interrupt 4 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 3. 0x14 3. 0x18 3. " PID3_set/clr ,Interrupt 3 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 2. 0x14 2. 0x18 2. " PID2_set/clr ,Interrupt 2 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 1. 0x14 1. 0x18 1. " SYS_set/clr ,SYS Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 0. 0x14 0. 0x18 0. " FIQ_set/clr ,FIQ Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x0 "AIC_CISR,AIC Core Interrupt Status Register"
|
|
bitfld.long 0x0 1. " NIRQ ,NIRQ Status" "Deactivated,Activated"
|
|
bitfld.long 0x0 0. " NFIQ ,NFIQ Status" "Deactivated,Activated"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x0 "AIC_EOICR,AIC End of Interrupt Command Register"
|
|
group.long 0x134++0x07
|
|
line.long 0x00 "AIC_SPU,AIC Spurious Interrupt Vector Register"
|
|
line.long 0x04 "AIC_DEBUG,AIC Debug Control Register"
|
|
bitfld.long 0x04 1. " GMSK ,General Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " PROT ,Protection Mode" "Disabled,Enabled"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "AIC_FFSR,Fast Forcing Status Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " PID31_set/clr ,Interrupt 31 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " PID30_set/clr ,Interrupt 30 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " PID29_set/clr ,Interrupt 29 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " PID28_set/clr ,Interrupt 28 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " PID27_set/clr ,Interrupt 27 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " PID26_set/clr ,Interrupt 26 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " PID25_set/clr ,Interrupt 25 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " PID24_set/clr ,Interrupt 24 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " PID23_set/clr ,Interrupt 23 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " PID22_set/clr ,Interrupt 22 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " PID21_set/clr ,Interrupt 21 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " PID20_set/clr ,Interrupt 20 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " PID19_set/clr ,Interrupt 19 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " PID18_set/clr ,Interrupt 18 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " PID17_set/clr ,Interrupt 17 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " PID16_set/clr ,Interrupt 16 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " PID15_set/clr ,Interrupt 15 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " PID14_set/clr ,Interrupt 14 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " PID13_set/clr ,Interrupt 13 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " PID12_set/clr ,Interrupt 12 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " PID11_set/clr ,Interrupt 11 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " PID10_set/clr ,Interrupt 10 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " PID9_set/clr ,Interrupt 9 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " PID8_set/clr ,Interrupt 8 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PID7_set/clr ,Interrupt 7 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " PID6_set/clr ,Interrupt 6 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " PID5_set/clr ,Interrupt 5 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " PID4_set/clr ,Interrupt 4 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " PID3_set/clr ,Interrupt 3 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " PID2_set/clr ,Interrupt 2 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " SYS_set/clr ,SYS Interrupt Fast Forcing Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "AIC_WPMR,AIC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "AIC_WPSR,AIC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DBGU (Debug Unit)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xffffee00
|
|
else
|
|
base ad:0xfffff200
|
|
endif
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DBGU_CR,Debug Unit Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBGU_MR,Debug Unit Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,No parity,No parity"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DBGU_IMR,Debug Unit Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " COMMRX_set/clr ,Mask COMMRX Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " COMMTX_set/clr ,Mask COMMTX Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " RXBUFF_set/clr ,Mask RXBUFF Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " TXBUFE_set/clr ,Mask TXBUFE Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " TXEMPTY_set/clr ,Mask TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PARE_set/clr ,Mask Parity Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " FRAME_set/clr ,Mask Framing Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRE_set/clr ,Mask Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " ENDTX_set/clr ,Mask End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " ENDRX_set/clr ,Mask End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXRDY_set/clr ,Disable TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RXRDY_set/clr ,Mask RXRDY Interrupt" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "DBGU_SR,Debug Unit Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x14--0x17
|
|
line.long 0x0 "DBGU_SR,Debug Unit Status Register"
|
|
bitfld.long 0x0 31. " COMMRX ,Debug Communication Channel Read Status" "Inactive,Active"
|
|
bitfld.long 0x0 30. " COMMTX ,Debug Communication Channel Write Status" "Inactive,Active"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25")
|
|
bitfld.long 0x0 12. " RXBUFF ,Receive Buffer Full" "Inactive,Active"
|
|
bitfld.long 0x0 11. " TXBUFE ,Transmission Buffer Empty" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 7. " PARE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x0 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25")
|
|
bitfld.long 0x0 4. " ENDTX ,End of Transmitter Transfer" "Inactive,Active"
|
|
bitfld.long 0x0 3. " ENDRX ,End of Receiver Transfer" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
hgroup.long 0x18--0x1B
|
|
hide.long 0x0 "DBGU_RHR,Debug Unit Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "DBGU_THR,Debug Unit Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DBGU_BRGR,Debug Unit Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "DBGU_CIDR,Debug Unit Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "Not extended,Extended"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMless/on-chip Flash,Embedded Flash,ROM and Embedded,SRAM em ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpuis("AT91SAM9G*")||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9M46")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "Reserved,1K bytes,2K bytes,6K bytes,112K bytes,4K bytes,80K bytes,160K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,96K bytes,512K bytes"
|
|
else
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "Reserved,1K bytes,2K bytes,Reserved,112K bytes,4K bytes,80K bytes,160K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,96K bytes,512K bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "None,8K bytes,16K bytes,32K bytes,Reserved,64K bytes,Reserved,128K bytes,Reserved,256K bytes,512K bytes,Reserved,1024K bytes,Reserved,2048K bytes,?..."
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "None,8K bytes,16K bytes,32K bytes,Reserved,64K bytes,Reserved,128K bytes,Reserved,256K bytes,512K bytes,Reserved,1024K bytes,Reserved,2048K bytes,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" "Reserved,ARM946ES,ARM7TDMI,Cortex-M3,ARM920T,ARM926EJS,Cortex-A5,?..."
|
|
else
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" "Reserved,ARM946ES,ARM7TDMI,Reserved,ARM920T,ARM926EJS,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Version of the Device"
|
|
line.long 0x4 "DBGU_EXID,Debug Unit Chip ID Extension Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DBGU_FNR,Debug Unit Force NTRST Register"
|
|
bitfld.long 0x00 0. " FNTRST ,Force NTRST" "Power-on reset,Held low"
|
|
width 0xb
|
|
tree "PDC_DBGU"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xffffee00
|
|
else
|
|
base ad:0xfffff200
|
|
endif
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "DBGU_RPR,Debug Unit Receive Pointer Register"
|
|
line.long 0x04 "DBGU_RCR,Debug Unit Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "DBGU_TPR,Debug Unit Transmit Pointer Register"
|
|
line.long 0x0c "DBGU_TCR,Debug Unit Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "DBGU_RNPR,Debug Unit Receive Next Pointer Register"
|
|
line.long 0x14 "DBGU_RNCR,Debug Unit Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "DBGU_TNPR,Debug Unit Transmit Next Pointer Register"
|
|
line.long 0x1c "DBGU_TNCR,Debug Unit Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "DBGU_PTCR,Debug Unit PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DBGU_PTSR,Debug Unit PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output Controller)"
|
|
tree "PIOA"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffff200
|
|
else
|
|
base ad:0xfffff400
|
|
endif
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "DMARQ1,ISI_D11"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TIOB0,ISI_D10"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TIOA0,ISI_D9"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "SPI0_NPCS3,ISI_D8"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "PCK1,ISI_MCK"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "SCK0,ISI_VSYNC"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "CTS0,ISI_HSYNC"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "RTS0,ISI_PCK"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "RXD0,ISI_D7"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TXD0,ISI_D6"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "MCI1_D3,ISI_D5"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "MCI1_D2,ISI_D4"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "MCI1_D1,ISI_D3"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "MCI1_D0,ISI_D2"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "MCI1_CD,ISI_D1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "MCI1_CK,ISI_D0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "DMARQ3,PCK2"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TCLK2,IRQ1"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "CANRX,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "CANTX,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "DMARQ0,PWM3"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "IRQ0,PWM1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "AC97RX,?..."
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "AC97TX,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "AC97CK,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "AC97FS,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "MCI0_D3,SPI0_NPCS0"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "MCI0_D2,SPI0_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "MCI0_D1,SPI0_NPCS1"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "MCI0_CK,SPI0_SPCK"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "MCI0_CD,SPI0_MOSI"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "MCI0_D0,SPI0_MISO"
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "TPK15,A24"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TPK14,A23"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TPK13,SPI0_NPCS3"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "TPK12,SPI0_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "TPK11,SPI0_NPCS1"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "TPK10,SPI1_NPCS3"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "TPK9,SPI1_NPCS2"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "TPK8,SPI1_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TPK7,RTS0"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TPK6,RF1"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TPK5,RK1"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TPK4,RD1"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "TPK3,TD1"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "TPK2,TK1"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "TPK1,TF1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "TPK0,CTS2"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "TPS2,RTS2"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TPS1,SCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "TPS0,CTS1"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TCLK,RTS1"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "TSYNC,SCK1"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "DTXD,PCK3"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "DRXD,PCK2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TWCK,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "TWD,PCK0"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "SPI0_NPCS3,MCDA3"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "SPI0_NPCS2,MCDA2"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "SPI0_NPCS1,MCDA1"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "SPI0_NPCS0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "SPI0_SPCK,MCCK"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "SPI0_MOSI,MCCDA"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "SPI0_MISO,MCDA0"
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "MCI1_CK,PCK0"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "MCI1_DA7,ECOL"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "MCI1_DA6,ECRS"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "MCI1_DA5,ERXCK"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "MCI1_DA4,ETXER"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "MCI1_DA3,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "MCI1_DA2,PWM3"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "MCI1_DA1,CTS3"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "MCI1_DA0,RTS3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "MCI1_CDA,SCK3"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TWCK0,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TWD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "EMDIO,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "EMDC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "ETXCK,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "ERXER,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "ERXDV,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "ETXEN,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "ERX1,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "ERX0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "ETX1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "ETX0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "MCI0_DA7,ERX3"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "MCI0_DA6,ERX2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "MCI0_DA5,ETX3"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "MCI0_DA4,ETX2"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "MCI0_DA3,TIOB4"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "MCI0_DA2,TIOA4"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "MCI0_DA1,TCKL4"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "MCI0_DA0,TIOB3"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "MCI0_CDA,TIOA3"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "MCI0_CK,TCLK3"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffff400
|
|
else
|
|
base ad:0xfffff600
|
|
endif
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "ADTRIG,EF100"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "EMDIO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "EMDC,PWM3"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "ETXEN,TCLK0"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "ERXER,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "ERX1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "ERX0,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "ETX1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "ETX0,PCK3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "ERXDV,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "ETXCK/EREFCK,TIOA2"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "PWM1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "PWM0,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "SPI1_NPCS3,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "SPI1_NPCS2,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "SPI1_NPCS1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "SPI1_NPCS0,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "SPI1_SPCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "SPI1_MOSI,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "SPI1_MISO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "RF1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "RK1,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RD1,LCDCC"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TD1,PWM2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "TK1,TIOB1"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "TF1,TIOA1"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RF0,TWCK"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "RK0,TWD"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RD0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "TK0,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TF0,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "SPI1_MOSI,PCK2"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "SPI1_MISO,IRQ1"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "SPI1_SPCK,IRQ2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "SPI1_NPCS0,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "SPI1_NPCS1,LCDD22"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "RF0,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "RK0,LCDD20"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "RD0,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TD0,LCDD18"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TK0,LCDD17"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TF0,LCDD16"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD15,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD14,LCDD22"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD13,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD12,LCDD20"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD11,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD10,LCDD15"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD9,LCDD14"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD8,LCDD13"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD7,LCDD12"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD6,LCDD11"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD5,LCDD10"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD4,LCDD7"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD3,LCDD6"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD2,LCDD5"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDD1,LCDD4"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDD0,LCDD3"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDCC,LCDD2"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDDEN,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDDOTCK,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDHSYNC,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDVSYNC,?..."
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "ISI_MCK,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "ISI_HSYNC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "ISI_VSYNC,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "ISI_PCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "ISI_D7,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "ISI_D6,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "ISI_D5,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "ISI_D4,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "ISI_D3,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "ISI_D2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "ISI_D1,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "ISI_D0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "TXD0,SPI0_NPCS2"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "RXD0,SPI0_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "SPI1_NPCS0,RTS0"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "SPI1_SPCK,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "SPI1_MOSI,CTS0"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "SPI1_MISO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "DTXD,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "DRXD,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "TWCK1,ISI_D11"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "TWD1,ISI_D10"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RXD3,ISI_D9"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TXD3,ISI_D8"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "RXD2,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "TXD2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RXD1,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "TXD1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "SPI0_NPCS0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "SPI0_SPCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "SPI0_MOSI,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "SPI0_MISO,?..."
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffff600
|
|
else
|
|
base ad:0xfffff800
|
|
endif
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "DTXD,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "DRXD,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "PCK0,PWM2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "PWM0,TCLK1"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "LCDD23,ERXCK"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "LCDD22,ECOL"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "LCDD21,ECRS"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "LCDD20,ETXER"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "LCDD19,ERX3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "LCDD18,ERX2"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "LCDD17,ETX3"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD16,ETX2"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD15,LCDD23"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD14,LCDD22"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD13,LCDD21"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD12,LCDD20"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD11,LCDD19"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD10,LCDD15"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD9,LCDD14"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD8,LCDD13"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD7,LCDD12"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD6,LCDD11"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD5,LCDD10"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD4,LCDD7"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD3,LCDD6"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDD2,LCDD5"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDD1,LCDD4"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDD0,LCDD3"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDDEN,PWM1"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDDOTCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDHSYNC,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDVSYNC,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,RF2"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,RK2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,RD2"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,TD2"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,TK2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,TF2"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,TIOA2"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,TIOB1"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,TIOA1"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,TIOB0"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,TIOA0"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,TCLK1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,TCLK0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "RXD2,SPI1_NPCS3"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TXD2,SPI1_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "RXD1,NCS7"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TXD1,NCS6"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "CTS0,FIQ"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "RTS0,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RXD0,PCK3"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TXD0,PCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "CFCE2,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "CFCE1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "NCS5/CFCS1,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "NCS4/CFCS0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A25/CFRNW,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "NWAIT,IRQ0"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "NANDWE,NCS7"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "NANDOE,NCS6"
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "NWAIT,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "NCS3/NANDCS,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "NCS2,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A25/CFRNW,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "NCS5/CFCS1,CTS2"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "NCS4/CFCS0,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "CFCE2,RTS2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "CFCE1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A24,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A22/NANDCLE,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A21/NANDALE,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A20,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A19,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "DQM3,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "DQM2,?..."
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "PIOD"
|
|
base ad:0xfffff800
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOD_PSR,PIOD Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOD_OSR,PIOD Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOD_IFSR,PIOD Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOD_ODSR,PIOD Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOD_PDSR,PIOD Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOD_IMR,PIOD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOD_ISR,PIOD Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOD_MDSR,PIOD Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOD_PUSR,PIOD Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "NCS3/NANDCS,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A25/CFRNW,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A24,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "NCS2,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "CFCE2,SCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "CFCE1,SCK2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "NCS5/CFCS1,CTS1"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "NCS4/CFCS0,RTS1"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "NWAIT,CTS2"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "DMARQ2,RTS2"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "FIQ,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RXD2,SPI1_NPCS3"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TXD2,SPI1_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "RXD1,SPI0_NPCS3"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TXD1,SPI0_NPCS2"
|
|
elif (cpu()=="AT91SAM9G10")
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "TIOB1,PWM1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TIOB0,SCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TCLK1,SCK1"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "TSADTRG,SPI1_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "PCK1,SPI0_NPCS3"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "PCK0,PWM2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "SPI0_NPCS2,PWM1"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "SPI0_NPCS1,PWM0"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TCLK0,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TIOA2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TIOA1,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TIOA0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "SPI1_NPCS3,FIQ"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "SPI1_NPCS2,IRQ"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "CTS1,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "RTS1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "RF1,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TF1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "RK1,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TK1,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "RD1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "TD1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "AC97CK,TCLK5"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "AC97FS,TIOB5"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "AC97TX,TIOA5"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "AC97RX,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RF0,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "RK0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RD0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "TF0,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TK0,PWM3"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOD_OWSR,PIOD Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOE"
|
|
base ad:0xfffffa00
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOE_PSR,PIOE Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOE_OSR,PIOE Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOE_IFSR,PIOE Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOE_ODSR,PIOE Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOE_PDSR,PIOE Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOE_IMR,PIOE Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOE_ISR,PIOE Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOE_MDSR,PIOE Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOE_PUSR,PIOE Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
elif (cpu()=="AT91SAM9G10")
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOE_ABSR,PIOE Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "PWM2,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "LCDD23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "LCDD22,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "LCDD21,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "LCDD20,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "LCDD19,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "LCDD18,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "LCDD17,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "LCDD16,LCDD22"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "LCDD15,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "LCDD14,LCDD20"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD13,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD12,LCDD18"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD11,LCDD15"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD10,LCDD14"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD9,LCDD13"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD8,LCDD12"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD7,LCDD11"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD6,LCDD10"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD5,LCDD7"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD4,LCDD6"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD3,LCDD5"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD2,LCDD4"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD1,LCDD3"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD0,LCDD2"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDDEN,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDDOTCK,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDHSYNC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDVSYNC,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDCC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDMOD,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDPWR,PCK0"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOE_ABSR,PIOE Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOE_OWSR,PIOE Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffa4000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI0_CR,SPI0 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffa4000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffa4000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffa4000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI0_SR,SPI0 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI0_IMR,SPI0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI0 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffc8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI0_CR,SPI0 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffc8000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffc8000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffc8000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI0_SR,SPI0 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI0_IMR,SPI0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI0 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_SPI0"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffa4000
|
|
else
|
|
base ad:0xfffc8000
|
|
endif
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SPI0_RPR,Serial Peripheral Interface 0 Receive Pointer Register"
|
|
line.long 0x04 "SPI0_RCR,Serial Peripheral Interface 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI0_TPR,Serial Peripheral Interface 0 Transmit Pointer Register"
|
|
line.long 0x0c "SPI0_TCR,Serial Peripheral Interface 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI0_RNPR,Serial Peripheral Interface 0 Receive Next Pointer Register"
|
|
line.long 0x14 "SPI0_RNCR,Serial Peripheral Interface 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI0_TNPR,Serial Peripheral Interface 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI0_TNCR,Serial Peripheral Interface 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI0_PTCR,Serial Peripheral Interface 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI0_PTSR,Serial Peripheral Interface 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SPI1"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffa8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI1_CR,SPI1 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffa8000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffa8000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffa8000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI1_SR,SPI1 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI1_IMR,SPI1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI1 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffcc000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI1_CR,SPI1 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffcc000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffcc000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffcc000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI1_SR,SPI1 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI1_IMR,SPI1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI1 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_SPI1"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfffa8000
|
|
else
|
|
base ad:0xfffcc000
|
|
endif
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SPI1_RPR,Serial Peripheral Interface 1 Receive Pointer Register"
|
|
line.long 0x04 "SPI1_RCR,Serial Peripheral Interface 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI1_TPR,Serial Peripheral Interface 1 Transmit Pointer Register"
|
|
line.long 0x0c "SPI1_TCR,Serial Peripheral Interface 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI1_RNPR,Serial Peripheral Interface 1 Receive Next Pointer Register"
|
|
line.long 0x14 "SPI1_RNCR,Serial Peripheral Interface 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI1_TNPR,Serial Peripheral Interface 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI1_TNCR,Serial Peripheral Interface 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI1_PTCR,Serial Peripheral Interface 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI1_PTSR,Serial Peripheral Interface 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "TWI (Two-wire Interface)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff88000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l(ad:(0xfff88000+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:(0xfff88000+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:(0xfff88000+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
in
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_Clear/Set , TX Buffer Empty" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_Clear/Set , RX Buffer Full" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_Clear/Set , End of TX buffer" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_Clear/Set , End of RX buffer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_Clear/Set ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_Clear/Set ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_Clear/Set ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_Clear/Set ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9261")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_Clear/Set ,Underrun Error" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_Clear/Set ,Overrun Error" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_Clear/Set ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_Clear/Set ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_Clear/Set ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_Clear/Set ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_Clear/Set ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
width 0xb
|
|
else
|
|
base ad:0xfffac000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l(ad:(0xfffac000+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:(0xfffac000+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:(0xfffac000+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
in
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_Clear/Set , TX Buffer Empty" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_Clear/Set , RX Buffer Full" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_Clear/Set , End of TX buffer" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_Clear/Set , End of RX buffer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_Clear/Set ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_Clear/Set ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_Clear/Set ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_Clear/Set ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9261")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_Clear/Set ,Underrun Error" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_Clear/Set ,Overrun Error" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_Clear/Set ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_Clear/Set ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_Clear/Set ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_Clear/Set ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_Clear/Set ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
tree "USART0"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff8c000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfff8c000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US0_IER,USART0 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfff8c000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfff8c000
|
|
width 0xb
|
|
else
|
|
base ad:0xfffb0000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb0000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US0_IER,USART0 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffb0000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb0000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_USART0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART0_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART1"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff90000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfff90000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US1_IER,USART1 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfff90000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfff90000
|
|
width 0xb
|
|
else
|
|
base ad:0xfffb4000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb4000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US1_IER,USART1 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffb4000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb4000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_USART1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART1_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART2"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff94000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfff94000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US2_IER,USART2 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfff94000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfff94000
|
|
width 0xb
|
|
else
|
|
base ad:0xfffb8000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb8000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US2_IER,USART2 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffb8000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb8000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_USART2"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART2_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Pointer Register"
|
|
line.long 0x04 "USART2_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART2_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Pointer Register"
|
|
line.long 0x0c "USART2_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART2_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Next Pointer Register"
|
|
line.long 0x14 "USART2_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART2_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART2_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART2_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART2_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9260")
|
|
tree "USART3"
|
|
base ad:0xfffd0000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffd0000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US0_IER,USART0 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffd0000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffd0000
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART3"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART3_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Pointer Register"
|
|
line.long 0x04 "USART3_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART3_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Pointer Register"
|
|
line.long 0x0c "USART3_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART3_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Next Pointer Register"
|
|
line.long 0x14 "USART3_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART3_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART3_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART3_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART3_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0xfffd4000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffd4000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US1_IER,USART1 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffd4000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffd4000
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART4"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART4_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Pointer Register"
|
|
line.long 0x04 "USART4_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART4_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Pointer Register"
|
|
line.long 0x0c "USART4_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART4_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Next Pointer Register"
|
|
line.long 0x14 "USART4_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART4_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART4_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART4_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART4_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART5"
|
|
base ad:0xfffd8000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffd8000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US2_IER,USART2 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffd8000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffd8000
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART5"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART5_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Pointer Register"
|
|
line.long 0x04 "USART5_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART5_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Pointer Register"
|
|
line.long 0x0c "USART5_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART5_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Next Pointer Register"
|
|
line.long 0x14 "USART5_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART5_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART5_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART5_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART5_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "SSC (Synchronous Serial Controller)"
|
|
tree "SSC0"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff98000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC0_CR,SSC0 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC0_CMR,SSC0 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC0_RCMR,SSC0 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC0_RFMR,SSC0 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC0_TCMR,SSC0 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC0_TFMR,SSC0 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC0_THR,SSC0 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC0_TSHR,SSC0 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC0_RC0R,SSC0 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC0_RC1R,SSC0 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC0_SR,SSC0 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC0_IMR,SSC0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffbc000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC0_CR,SSC0 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC0_CMR,SSC0 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC0_RCMR,SSC0 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC0_RFMR,SSC0 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC0_TCMR,SSC0 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC0_TFMR,SSC0 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC0_THR,SSC0 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC0_TSHR,SSC0 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC0_RC0R,SSC0 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC0_RC1R,SSC0 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC0_SR,SSC0 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC0_IMR,SSC0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_SSC0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC0_RPR,Synchronous Serial Controller 0 Receive Pointer Register"
|
|
line.long 0x04 "SSC0_RCR,Synchronous Serial Controller 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC0_TPR,Synchronous Serial Controller 0 Transmit Pointer Register"
|
|
line.long 0x0c "SSC0_TCR,Synchronous Serial Controller 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC0_RNPR,Synchronous Serial Controller 0 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC0_RNCR,Synchronous Serial Controller 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC0_TNPR,Synchronous Serial Controller 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC0_TNCR,Synchronous Serial Controller 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC0_PTCR,Synchronous Serial Controller 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC0_PTSR,Synchronous Serial Controller 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9263")
|
|
tree "SSC1"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff9c000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC1_CR,SSC1 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC1_CMR,SSC1 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC1_RCMR,SSC1 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC1_RFMR,SSC1 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC1_TCMR,SSC1 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC1_TFMR,SSC1 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC1_THR,SSC1 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC1_TSHR,SSC1 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC1_RC0R,SSC1 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC1_RC1R,SSC1 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC1_SR,SSC1 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC1_IMR,SSC1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffc0000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC1_CR,SSC1 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC1_CMR,SSC1 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC1_RCMR,SSC1 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC1_RFMR,SSC1 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC1_TCMR,SSC1 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC1_TFMR,SSC1 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC1_THR,SSC1 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC1_TSHR,SSC1 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC1_RC0R,SSC1 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC1_RC1R,SSC1 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC1_SR,SSC1 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC1_IMR,SSC1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_SSC1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC1_RPR,Synchronous Serial Controller 1 Receive Pointer Register"
|
|
line.long 0x04 "SSC1_RCR,Synchronous Serial Controller 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC1_TPR,Synchronous Serial Controller 1 Transmit Pointer Register"
|
|
line.long 0x0c "SSC1_TCR,Synchronous Serial Controller 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC1_RNPR,Synchronous Serial Controller 1 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC1_RNCR,Synchronous Serial Controller 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC1_TNPR,Synchronous Serial Controller 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC1_TNCR,Synchronous Serial Controller 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC1_PTCR,Synchronous Serial Controller 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC1_PTSR,Synchronous Serial Controller 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
tree "SSC2"
|
|
base ad:0xfffc4000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC2_CR,SSC2 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC2_CMR,SSC2 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC2_RCMR,SSC2 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC2_RFMR,SSC2 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC2_TCMR,SSC2 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC2_TFMR,SSC2 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC2_RHR,SSC2 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC2_RHR,SSC2 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC2_THR,SSC2 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC2_RSHR,SSC2 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC2_RSHR,SSC2 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC2_TSHR,SSC2 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC2_RC0R,SSC2 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC2_RC1R,SSC2 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC2_SR,SSC2 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC2_IMR,SSC2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_SSC2"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC2_RPR,Synchronous Serial Controller 2 Receive Pointer Register"
|
|
line.long 0x04 "SSC2_RCR,Synchronous Serial Controller 2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC2_TPR,Synchronous Serial Controller 2 Transmit Pointer Register"
|
|
line.long 0x0c "SSC2_TCR,Synchronous Serial Controller 2 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC2_RNPR,Synchronous Serial Controller 2 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC2_RNCR,Synchronous Serial Controller 2 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC2_TNPR,Synchronous Serial Controller 2 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC2_TNCR,Synchronous Serial Controller 2 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC2_PTCR,Synchronous Serial Controller 2 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC2_PTSR,Synchronous Serial Controller 2 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree.open "AC97C (AC'97 Controller)"
|
|
tree "AC97C"
|
|
base ad:0xfffa0000
|
|
width 0xd
|
|
group.long 0x8++3
|
|
line.long 0x00 "AC97C_MR,Mode Register"
|
|
bitfld.long 0x00 2. " VRA ,Variable Rate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " WRST ,Warm Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA ,AC97 Controller Global Enable" "No effect,Enabled"
|
|
group.long 0x10++7
|
|
line.long 0x00 "AC97C_ICA,Input Channel Assignment Register"
|
|
bitfld.long 0x00 27.--29. " CHID12 ,Channel ID for the input slot 12" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 24.--26. " CHID11 ,Channel ID for the input slot 11" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CHID10 ,Channel ID for the input slot 10" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 18.--20. " CHID9 ,Channel ID for the input slot 9" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CHID8 ,Channel ID for the input slot 8" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 12.--14. " CHID7 ,Channel ID for the input slot 7" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CHID6 ,Channel ID for the input slot 6" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 6.--8. " CHID5 ,Channel ID for the input slot 5" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CHID4 ,Channel ID for the input slot 4" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 0.--2. " CHID3 ,Channel ID for the input slot 3" "None,Channel A,Channel B,?..."
|
|
line.long 0x04 "AC97C_OCA,Output Channel Assignment Register"
|
|
bitfld.long 0x04 27.--29. " CHID12 ,Channel ID for the output slot 12" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 24.--26. " CHID11 ,Channel ID for the output slot 11" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " CHID10 ,Channel ID for the output slot 10" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 18.--20. " CHID9 ,Channel ID for the output slot 9" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " CHID8 ,Channel ID for the output slot 8" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 12.--14. " CHID7 ,Channel ID for the output slot 7" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " CHID6 ,Channel ID for the output slot 6" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 6.--8. " CHID5 ,Channel ID for the output slot 5" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " CHID4 ,Channel ID for the output slot 4" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 0.--2. " CHID3 ,Channel ID for the output slot 3" "None,Channel A,Channel B,?..."
|
|
rgroup.long 0x20++3
|
|
line.long 0x00 "AC97C_CARHR,Channel A Receive Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDATA ,Receive Data"
|
|
wgroup.long 0x24++3
|
|
line.long 0x00 "AC97C_CATHR,Channel A Transmit Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TDATA ,Data to Transmit"
|
|
rgroup.long 0x28++3
|
|
line.long 0x00 "AC97C_CASR,Channel A Status Register"
|
|
bitfld.long 0x00 15. " RXBUFF ,Receive Buffer Full for Channel A" "Not empty,Empty"
|
|
bitfld.long 0x00 14. " ENDRX ,End of Reception for Channel A" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmit Buffer Empty for Channel A" "Not full,Full"
|
|
bitfld.long 0x00 10. " ENDTX ,End of Transmission for Channel A" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun" "No underrun,Underrun"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready" "Not ready,Ready"
|
|
group.long 0x2c++3
|
|
line.long 0x00 "AC97C_CAMR,Channel A Mode Register"
|
|
bitfld.long 0x00 22. " PDCEN ,Peripheral Data Controller Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CEN ,Channel A Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CEM ,Channel A Endian Mode" "Little,Big"
|
|
bitfld.long 0x00 16.--17. " SIZE ,Channel A Data Size" "20 bits,18 bits,16 bits,10 bits"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXBUFF ,Receive Buffer Full for channel x Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENDRX ,End of Reception for channel x Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmit Buffer Empty for channel x Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENDTX ,End of Transmission for channel x Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun" "No underrun,Underrun"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready" "Not ready,Ready"
|
|
rgroup.long 0x30++3
|
|
line.long 0x00 "AC97C_CBRHR,Channel B Receive Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDATA ,Receive Data"
|
|
wgroup.long 0x34++3
|
|
line.long 0x00 "AC97C_CBTHR,Channel B Transmit Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TDATA ,Data to Transmit"
|
|
rgroup.long 0x38++3
|
|
line.long 0x00 "AC97C_CBSR,Channel B Status Register"
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun" "No underrun,Underrun"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready" "Not ready,Ready"
|
|
group.long 0x3c++3
|
|
line.long 0x00 "AC97C_CBMR,Channel B Mode Register"
|
|
bitfld.long 0x00 21. " CEN ,Channel A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CEM ,Channel A Endian Mode" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Channel A Data Size" "20 bits,18 bits,16 bits,10 bits"
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready" "Not ready,Ready"
|
|
rgroup.long 0x40++3
|
|
line.long 0x00 "AC97C_CORHR,Codec Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDATA ,Status Data"
|
|
wgroup.long 0x44++3
|
|
line.long 0x00 "AC97C_COTHR,Codec Transmit Holding Register"
|
|
bitfld.long 0x00 23. " READ ,Read/Write command" "Write,Read"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CADDR ,CODEC control register index"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CDATA ,Command Data"
|
|
rgroup.long 0x48++3
|
|
line.long 0x00 "AC97C_COSR,Codec Status Register"
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun" "No underrun,Underrun"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready" "Not ready,Ready"
|
|
group.long 0x4c++3
|
|
line.long 0x00 "AC97C_COMR,Codec Mode Register"
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun" "No underrun,Underrun"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready" "Not ready,Ready"
|
|
rgroup.long 0x50++3
|
|
line.long 0x00 "AC97C_SR,Status Register"
|
|
bitfld.long 0x00 4. " CBEVT ,Channel B Event" "No event,Event"
|
|
bitfld.long 0x00 3. " CAEVT ,Channel A Event" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 2. " COEVT ,CODEC Channel Event" "No event,Event"
|
|
bitfld.long 0x00 1. " WKUP ,Wake Up detection" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOF ,Start Of Frame" "Not detected,Detected"
|
|
textline " "
|
|
width 0xf
|
|
group.long 0x5c++3
|
|
line.long 0x00 "AC97C_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CBEVT_Set/Clr ,Channel B Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CAEVT_Set/Clr ,Channel A Event" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " COEVT_Set/Clr ,CODEC Channel Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " WKUP_Set/Clr ,Wake Up detection" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " SOF_Set/Clr ,Start Of Frame" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_AC97C"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "AC97C_RPR,AC97 Controller Receive Pointer Register"
|
|
line.long 0x04 "AC97C_RCR,AC97 Controller Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "AC97C_TPR,AC97 Controller Transmit Pointer Register"
|
|
line.long 0x0c "AC97C_TCR,AC97 Controller Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "AC97C_RNPR,AC97 Controller Receive Next Pointer Register"
|
|
line.long 0x14 "AC97C_RNCR,AC97 Controller Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "AC97C_TNPR,AC97 Controller Transmit Next Pointer Register"
|
|
line.long 0x1c "AC97C_TNCR,AC97 Controller Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "AC97C_PTCR,AC97 Controller PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "AC97C_PTSR,AC97 Controller PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "TC (Timer/Counter)"
|
|
tree "TC Channel 0"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff7c000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
else
|
|
base ad:0xfffa0000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffa0000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffa0000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff7c040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
else
|
|
base ad:0xfffa0040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffa0040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffa0040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff7c080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
else
|
|
base ad:0xfffa0080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffa0080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffa0080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "Block Registers"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff7c000
|
|
else
|
|
base ad:0xfffa0000
|
|
endif
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9260")
|
|
tree "TC Channel 3"
|
|
base ad:0xfffdc000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffdc000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffdc000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
base ad:0xfffdc040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffdc040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffdc040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
base ad:0xfffdc080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffdc080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffdc080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers"
|
|
base ad:0xfffdc000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0xfffac000
|
|
width 0x0d
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CAN_MR,CAN Mode Register"
|
|
bitfld.long 0x00 7. " DRPT ,Repeat Disable" "Pending,Aborted"
|
|
bitfld.long 0x00 6. " TIMFRZ ,Timer Freeze Enable" "Not frozen,Frozen"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TTM ,Time Triggered Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TEOF ,Timestamp Messages at Each Frame End" "SOF,EOF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OVL ,Overload Frame Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ABM ,Autobaud/Listen mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPM ,Low Power Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CANEN ,CAN Controller Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x03
|
|
line.long 0x0 "CAN_IMR,CAN Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x04 28. " BERR_set/clr ,Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x04 27. " FERR_set/clr ,Form Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x04 26. " AERR_set/clr ,Acknowledgment Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x04 25. " SERR_set/clr ,Stuffing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x04 24. " CERR_set/clr ,CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 23. -0x8 23. -0x04 23. " TSTP_set/clr ,Timestamp Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x8 22. -0x04 22. " TOVF_set/clr ,Timer Overflow Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x04 21. " WAKEUP_set/clr ,Wakeup Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x04 20. " SLEEP_set/clr ,Sleep Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x04 19. " BOFF_set/clr ,Bus-Off Mode Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x04 18. " ERRP_set/clr ,Error Passive Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x04 17. " WARN_set/clr ,Warning Limit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x04 16. " ERRA_set/clr ,Error Active Mode Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X25"||cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x0 15. -0x8 15. -0x04 15. " MB15_set/clr ,Mailbox 15 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x04 14. " MB14_set/clr ,Mailbox 14 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x04 13. " MB13_set/clr ,Mailbox 13 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x04 12. " MB12_set/clr ,Mailbox 12 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x04 11. " MB11_set/clr ,Mailbox 11 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x04 10. " MB10_set/clr ,Mailbox 10 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 09. -0x8 09. -0x04 09. " MB9_set/clr ,Mailbox 9 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 08. -0x8 08. -0x04 08. " MB8_set/clr ,Mailbox 8 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 07. -0x8 07. -0x04 07. " MB7_set/clr ,Mailbox 7 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 06. -0x8 06. -0x04 06. " MB6_set/clr ,Mailbox 6 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 05. -0x8 05. -0x04 05. " MB5_set/clr ,Mailbox 5 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 04. -0x8 04. -0x04 04. " MB4_set/clr ,Mailbox 4 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 03. -0x8 03. -0x04 03. " MB3_set/clr ,Mailbox 3 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 02. -0x8 02. -0x04 02. " MB2_set/clr ,Mailbox 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 01. -0x8 01. -0x04 01. " MB1_set/clr ,Mailbox 1 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 00. -0x8 00. -0x04 00. " MB0_set/clr ,Mailbox 0 Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CAN_SR,CAN Status Register"
|
|
in
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAN_BR,CAN Baudrate Register"
|
|
bitfld.long 0x00 24. " SMP ,Sampling Mode" "1 sample,3 samples"
|
|
hexmask.long.byte 0x00 16.--22. 1. " BRP ,Baudrate Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SJW ,Re-Synchronization Jump Width" "tCSCx1,tCSCx2,tCSCx3,tCSCx4"
|
|
bitfld.long 0x00 8.--10. " PROPAG ,Programming Time Segment" "tCSCx1,tCSCx2,tCSCx3,tCSCx4,tCSCx5,tCSCx6,tCSCx7,tCSCx8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PHASE1 ,Phase 1 Segment" "tCSCx1,tCSCx2,tCSCx3,tCSCx4,tCSCx5,tCSCx6,tCSCx7,tCSCx8"
|
|
bitfld.long 0x00 0.--2. " PHASE2 ,Phase 2 Segment" "tCSCx1,tCSCx2,tCSCx3,tCSCx4,tCSCx5,tCSCx6,tCSCx7,tCSCx8"
|
|
rgroup.long 0x18--0x23
|
|
line.long 0x00 "CAN_TIM,CAN Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " Timer ,CAN Timer Value"
|
|
line.long 0x04 "CAN_TIMESTP,CAN Timestamp Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TIMESTAMP ,CAN Timestamp Value"
|
|
line.long 0x08 "CAN_ECR,CAN Error Counter Register"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hexmask.long.byte 0x08 16.--24. 1. " TEC ,Transmit Error Counter"
|
|
else
|
|
hexmask.long.byte 0x08 16.--23. 1. " TEC ,Transmit Error Counter"
|
|
endif
|
|
hexmask.long.byte 0x08 0.--7. 1. " REC ,Receive Error Counter"
|
|
;if (((data.long(ad:ad:0xfffac000))&0x20)==0x20)
|
|
wgroup.long 0x24++0x07
|
|
line.long 0x00 "CAN_TCR,CAN Transfer Command Register"
|
|
bitfld.long 0x00 31. " TIMRST ,Timer Reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X25"||cpu()!="AT91SAM9X35")
|
|
bitfld.long 0x00 15. " MB15 ,Mailbox 15 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " MB14 ,Mailbox 14 Transfer Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB13 ,Mailbox 13 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " MB12 ,Mailbox 12 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " MB11 ,Mailbox 11 Transfer Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB10 ,Mailbox 10 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " MB9 ,Mailbox 9 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " MB8 ,Mailbox 8 Transfer Request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7 ,Mailbox 7 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " MB6 ,Mailbox 6 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " MB5 ,Mailbox 5 Transfer Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB4 ,Mailbox 4 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " MB3 ,Mailbox 3 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MB2 ,Mailbox 2 Transfer Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB1 ,Mailbox 1 Transfer Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " MB0 ,Mailbox 0 Transfer Request" "Not requested,Requested"
|
|
;else
|
|
; wgroup.long 0x24++0x07
|
|
; line.long 0x00 "CAN_TCR,CAN Transfer Command Register"
|
|
; bitfld.long 0x00 7. " MB7 ,Mailbox 7 Transfer Request" "Not requested,Requested"
|
|
; bitfld.long 0x00 6. " MB6 ,Mailbox 6 Transfer Request" "Not requested,Requested"
|
|
; textline " "
|
|
; bitfld.long 0x00 5. " MB5 ,Mailbox 5 Transfer Request" "Not requested,Requested"
|
|
; bitfld.long 0x00 4. " MB4 ,Mailbox 4 Transfer Request" "Not requested,Requested"
|
|
; textline " "
|
|
; bitfld.long 0x00 3. " MB3 ,Mailbox 3 Transfer Request" "Not requested,Requested"
|
|
; bitfld.long 0x00 2. " MB2 ,Mailbox 2 Transfer Request" "Not requested,Requested"
|
|
; textline " "
|
|
; bitfld.long 0x00 1. " MB1 ,Mailbox 1 Transfer Request" "Not requested,Requested"
|
|
; bitfld.long 0x00 0. " MB0 ,Mailbox 0 Transfer Request" "Not requested,Requested"
|
|
;endif
|
|
line.long 0x04 "CAN_ACR,CAN Abort Command Register"
|
|
sif (cpu()!="AT91SAM9X25"||cpu()!="AT91SAM9X35")
|
|
bitfld.long 0x04 15. " MB15 ,Mailbox 15 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " MB14 ,Mailbox 14 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " MB13 ,Mailbox 13 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 12. " MB12 ,Mailbox 12 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 11. " MB11 ,Mailbox 11 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " MB10 ,Mailbox 10 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 9. " MB9 ,Mailbox 9 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " MB8 ,Mailbox 8 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " MB7 ,Mailbox 7 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MB6 ,Mailbox 6 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " MB5 ,Mailbox 5 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " MB4 ,Mailbox 4 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MB3 ,Mailbox 3 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " MB2 ,Mailbox 2 Abort Request" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " MB1 ,Mailbox 1 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MB0 ,Mailbox 0 Abort Request" "Not requested,Requested"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "CAN_WPMR,ADC Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "CAN_WPSR,ADC Write Protect Status Register"
|
|
in
|
|
endif
|
|
tree.open "CAN Message Registers"
|
|
width 0xc
|
|
tree "CAN Message 0x0 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x0)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x0)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x0))++0x3
|
|
line.long 0x00 "CAN_MMR0x0,CAN Message 0x0 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x0)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x0)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x0))++0x3
|
|
line.long 0x00 "CAN_MMR0x0,CAN Message 0x0 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x0)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x0)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x0))++0x3
|
|
line.long 0x00 "CAN_MMR0x0,CAN Message 0x0 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x0))++0x3
|
|
line.long 0x00 "CAN_MMR0x0,CAN Message 0x0 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x0))++0x7
|
|
line.long 0x0 "CAN_MAM0x0,CAN Message 0x0 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x0,CAN Message 0x0 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x0))++0x3
|
|
line.long 0x00 "CAN_MFID0x0,CAN Message 0x0 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x0))++0x3
|
|
hide.long 0x0 "CAN_MSR0x0,CAN Message 0x0 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x0))++0x03
|
|
hide.long 0x00 "CAN_MDL0x0,CAN Message 0x0 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x0))++0x03
|
|
hide.long 0x00 "CAN_MDH0x0,CAN Message 0x0 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x0))++0x03
|
|
line.long 0x00 "CAN_MCR0x0,CAN Message 0x0 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x0 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x1 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x1)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x1)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x1))++0x3
|
|
line.long 0x00 "CAN_MMR0x1,CAN Message 0x1 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x1)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x1)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x1))++0x3
|
|
line.long 0x00 "CAN_MMR0x1,CAN Message 0x1 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x1)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x1)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x1))++0x3
|
|
line.long 0x00 "CAN_MMR0x1,CAN Message 0x1 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x1))++0x3
|
|
line.long 0x00 "CAN_MMR0x1,CAN Message 0x1 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x1))++0x7
|
|
line.long 0x0 "CAN_MAM0x1,CAN Message 0x1 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x1,CAN Message 0x1 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x1))++0x3
|
|
line.long 0x00 "CAN_MFID0x1,CAN Message 0x1 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x1))++0x3
|
|
hide.long 0x0 "CAN_MSR0x1,CAN Message 0x1 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x1))++0x03
|
|
hide.long 0x00 "CAN_MDL0x1,CAN Message 0x1 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x1))++0x03
|
|
hide.long 0x00 "CAN_MDH0x1,CAN Message 0x1 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x1))++0x03
|
|
line.long 0x00 "CAN_MCR0x1,CAN Message 0x1 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x1 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x2 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x2)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x2)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x2))++0x3
|
|
line.long 0x00 "CAN_MMR0x2,CAN Message 0x2 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x2)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x2)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x2))++0x3
|
|
line.long 0x00 "CAN_MMR0x2,CAN Message 0x2 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x2)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x2)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x2))++0x3
|
|
line.long 0x00 "CAN_MMR0x2,CAN Message 0x2 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x2))++0x3
|
|
line.long 0x00 "CAN_MMR0x2,CAN Message 0x2 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x2))++0x7
|
|
line.long 0x0 "CAN_MAM0x2,CAN Message 0x2 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x2,CAN Message 0x2 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x2))++0x3
|
|
line.long 0x00 "CAN_MFID0x2,CAN Message 0x2 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x2))++0x3
|
|
hide.long 0x0 "CAN_MSR0x2,CAN Message 0x2 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x2))++0x03
|
|
hide.long 0x00 "CAN_MDL0x2,CAN Message 0x2 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x2))++0x03
|
|
hide.long 0x00 "CAN_MDH0x2,CAN Message 0x2 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x2))++0x03
|
|
line.long 0x00 "CAN_MCR0x2,CAN Message 0x2 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x2 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x3 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x3)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x3)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x3))++0x3
|
|
line.long 0x00 "CAN_MMR0x3,CAN Message 0x3 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x3)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x3)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x3))++0x3
|
|
line.long 0x00 "CAN_MMR0x3,CAN Message 0x3 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x3)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x3)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x3))++0x3
|
|
line.long 0x00 "CAN_MMR0x3,CAN Message 0x3 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x3))++0x3
|
|
line.long 0x00 "CAN_MMR0x3,CAN Message 0x3 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x3))++0x7
|
|
line.long 0x0 "CAN_MAM0x3,CAN Message 0x3 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x3,CAN Message 0x3 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x3))++0x3
|
|
line.long 0x00 "CAN_MFID0x3,CAN Message 0x3 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x3))++0x3
|
|
hide.long 0x0 "CAN_MSR0x3,CAN Message 0x3 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x3))++0x03
|
|
hide.long 0x00 "CAN_MDL0x3,CAN Message 0x3 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x3))++0x03
|
|
hide.long 0x00 "CAN_MDH0x3,CAN Message 0x3 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x3))++0x03
|
|
line.long 0x00 "CAN_MCR0x3,CAN Message 0x3 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x3 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x4 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x4)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x4)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x4))++0x3
|
|
line.long 0x00 "CAN_MMR0x4,CAN Message 0x4 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x4)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x4)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x4))++0x3
|
|
line.long 0x00 "CAN_MMR0x4,CAN Message 0x4 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x4)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x4)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x4))++0x3
|
|
line.long 0x00 "CAN_MMR0x4,CAN Message 0x4 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x4))++0x3
|
|
line.long 0x00 "CAN_MMR0x4,CAN Message 0x4 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x4))++0x7
|
|
line.long 0x0 "CAN_MAM0x4,CAN Message 0x4 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x4,CAN Message 0x4 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x4))++0x3
|
|
line.long 0x00 "CAN_MFID0x4,CAN Message 0x4 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x4))++0x3
|
|
hide.long 0x0 "CAN_MSR0x4,CAN Message 0x4 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x4))++0x03
|
|
hide.long 0x00 "CAN_MDL0x4,CAN Message 0x4 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x4))++0x03
|
|
hide.long 0x00 "CAN_MDH0x4,CAN Message 0x4 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x4))++0x03
|
|
line.long 0x00 "CAN_MCR0x4,CAN Message 0x4 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x4 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x5 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x5)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x5)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x5))++0x3
|
|
line.long 0x00 "CAN_MMR0x5,CAN Message 0x5 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x5)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x5)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x5))++0x3
|
|
line.long 0x00 "CAN_MMR0x5,CAN Message 0x5 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x5)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x5)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x5))++0x3
|
|
line.long 0x00 "CAN_MMR0x5,CAN Message 0x5 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x5))++0x3
|
|
line.long 0x00 "CAN_MMR0x5,CAN Message 0x5 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x5))++0x7
|
|
line.long 0x0 "CAN_MAM0x5,CAN Message 0x5 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x5,CAN Message 0x5 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x5))++0x3
|
|
line.long 0x00 "CAN_MFID0x5,CAN Message 0x5 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x5))++0x3
|
|
hide.long 0x0 "CAN_MSR0x5,CAN Message 0x5 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x5))++0x03
|
|
hide.long 0x00 "CAN_MDL0x5,CAN Message 0x5 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x5))++0x03
|
|
hide.long 0x00 "CAN_MDH0x5,CAN Message 0x5 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x5))++0x03
|
|
line.long 0x00 "CAN_MCR0x5,CAN Message 0x5 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x5 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x6 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x6)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x6)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x6))++0x3
|
|
line.long 0x00 "CAN_MMR0x6,CAN Message 0x6 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x6)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x6)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x6))++0x3
|
|
line.long 0x00 "CAN_MMR0x6,CAN Message 0x6 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x6)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x6)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x6))++0x3
|
|
line.long 0x00 "CAN_MMR0x6,CAN Message 0x6 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x6))++0x3
|
|
line.long 0x00 "CAN_MMR0x6,CAN Message 0x6 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x6))++0x7
|
|
line.long 0x0 "CAN_MAM0x6,CAN Message 0x6 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x6,CAN Message 0x6 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x6))++0x3
|
|
line.long 0x00 "CAN_MFID0x6,CAN Message 0x6 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x6))++0x3
|
|
hide.long 0x0 "CAN_MSR0x6,CAN Message 0x6 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x6))++0x03
|
|
hide.long 0x00 "CAN_MDL0x6,CAN Message 0x6 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x6))++0x03
|
|
hide.long 0x00 "CAN_MDH0x6,CAN Message 0x6 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x6))++0x03
|
|
line.long 0x00 "CAN_MCR0x6,CAN Message 0x6 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x6 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x7 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x7)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x7)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x7))++0x3
|
|
line.long 0x00 "CAN_MMR0x7,CAN Message 0x7 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x7)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x7)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x7))++0x3
|
|
line.long 0x00 "CAN_MMR0x7,CAN Message 0x7 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x7)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x7)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x7))++0x3
|
|
line.long 0x00 "CAN_MMR0x7,CAN Message 0x7 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x7))++0x3
|
|
line.long 0x00 "CAN_MMR0x7,CAN Message 0x7 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x7))++0x7
|
|
line.long 0x0 "CAN_MAM0x7,CAN Message 0x7 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x7,CAN Message 0x7 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x7))++0x3
|
|
line.long 0x00 "CAN_MFID0x7,CAN Message 0x7 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x7))++0x3
|
|
hide.long 0x0 "CAN_MSR0x7,CAN Message 0x7 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x7))++0x03
|
|
hide.long 0x00 "CAN_MDL0x7,CAN Message 0x7 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x7))++0x03
|
|
hide.long 0x00 "CAN_MDH0x7,CAN Message 0x7 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x7))++0x03
|
|
line.long 0x00 "CAN_MCR0x7,CAN Message 0x7 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x7 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x8 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x8)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x8)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x8))++0x3
|
|
line.long 0x00 "CAN_MMR0x8,CAN Message 0x8 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x8)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x8)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x8))++0x3
|
|
line.long 0x00 "CAN_MMR0x8,CAN Message 0x8 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x8)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x8)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x8))++0x3
|
|
line.long 0x00 "CAN_MMR0x8,CAN Message 0x8 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x8))++0x3
|
|
line.long 0x00 "CAN_MMR0x8,CAN Message 0x8 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x8))++0x7
|
|
line.long 0x0 "CAN_MAM0x8,CAN Message 0x8 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x8,CAN Message 0x8 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x8))++0x3
|
|
line.long 0x00 "CAN_MFID0x8,CAN Message 0x8 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x8))++0x3
|
|
hide.long 0x0 "CAN_MSR0x8,CAN Message 0x8 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x8))++0x03
|
|
hide.long 0x00 "CAN_MDL0x8,CAN Message 0x8 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x8))++0x03
|
|
hide.long 0x00 "CAN_MDH0x8,CAN Message 0x8 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x8))++0x03
|
|
line.long 0x00 "CAN_MCR0x8,CAN Message 0x8 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x8 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0x9 Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x9)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x9)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x9))++0x3
|
|
line.long 0x00 "CAN_MMR0x9,CAN Message 0x9 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0x9)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0x9)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0x9))++0x3
|
|
line.long 0x00 "CAN_MMR0x9,CAN Message 0x9 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x9)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0x9)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0x9))++0x3
|
|
line.long 0x00 "CAN_MMR0x9,CAN Message 0x9 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0x9))++0x3
|
|
line.long 0x00 "CAN_MMR0x9,CAN Message 0x9 Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0x9))++0x7
|
|
line.long 0x0 "CAN_MAM0x9,CAN Message 0x9 Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0x9,CAN Message 0x9 ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0x9))++0x3
|
|
line.long 0x00 "CAN_MFID0x9,CAN Message 0x9 Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0x9))++0x3
|
|
hide.long 0x0 "CAN_MSR0x9,CAN Message 0x9 Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0x9))++0x03
|
|
hide.long 0x00 "CAN_MDL0x9,CAN Message 0x9 Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0x9))++0x03
|
|
hide.long 0x00 "CAN_MDH0x9,CAN Message 0x9 Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0x9))++0x03
|
|
line.long 0x00 "CAN_MCR0x9,CAN Message 0x9 Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0x9 Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0xA Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xA)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xA)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xA))++0x3
|
|
line.long 0x00 "CAN_MMR0xA,CAN Message 0xA Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0xA)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0xA)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0xA))++0x3
|
|
line.long 0x00 "CAN_MMR0xA,CAN Message 0xA Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xA)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xA)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xA))++0x3
|
|
line.long 0x00 "CAN_MMR0xA,CAN Message 0xA Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0xA))++0x3
|
|
line.long 0x00 "CAN_MMR0xA,CAN Message 0xA Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0xA))++0x7
|
|
line.long 0x0 "CAN_MAM0xA,CAN Message 0xA Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0xA,CAN Message 0xA ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0xA))++0x3
|
|
line.long 0x00 "CAN_MFID0xA,CAN Message 0xA Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0xA))++0x3
|
|
hide.long 0x0 "CAN_MSR0xA,CAN Message 0xA Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0xA))++0x03
|
|
hide.long 0x00 "CAN_MDL0xA,CAN Message 0xA Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0xA))++0x03
|
|
hide.long 0x00 "CAN_MDH0xA,CAN Message 0xA Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0xA))++0x03
|
|
line.long 0x00 "CAN_MCR0xA,CAN Message 0xA Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0xA Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0xB Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xB)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xB)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xB))++0x3
|
|
line.long 0x00 "CAN_MMR0xB,CAN Message 0xB Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0xB)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0xB)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0xB))++0x3
|
|
line.long 0x00 "CAN_MMR0xB,CAN Message 0xB Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xB)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xB)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xB))++0x3
|
|
line.long 0x00 "CAN_MMR0xB,CAN Message 0xB Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0xB))++0x3
|
|
line.long 0x00 "CAN_MMR0xB,CAN Message 0xB Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0xB))++0x7
|
|
line.long 0x0 "CAN_MAM0xB,CAN Message 0xB Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0xB,CAN Message 0xB ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0xB))++0x3
|
|
line.long 0x00 "CAN_MFID0xB,CAN Message 0xB Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0xB))++0x3
|
|
hide.long 0x0 "CAN_MSR0xB,CAN Message 0xB Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0xB))++0x03
|
|
hide.long 0x00 "CAN_MDL0xB,CAN Message 0xB Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0xB))++0x03
|
|
hide.long 0x00 "CAN_MDH0xB,CAN Message 0xB Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0xB))++0x03
|
|
line.long 0x00 "CAN_MCR0xB,CAN Message 0xB Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0xB Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0xC Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xC)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xC)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xC))++0x3
|
|
line.long 0x00 "CAN_MMR0xC,CAN Message 0xC Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0xC)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0xC)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0xC))++0x3
|
|
line.long 0x00 "CAN_MMR0xC,CAN Message 0xC Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xC)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xC)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xC))++0x3
|
|
line.long 0x00 "CAN_MMR0xC,CAN Message 0xC Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0xC))++0x3
|
|
line.long 0x00 "CAN_MMR0xC,CAN Message 0xC Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0xC))++0x7
|
|
line.long 0x0 "CAN_MAM0xC,CAN Message 0xC Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0xC,CAN Message 0xC ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0xC))++0x3
|
|
line.long 0x00 "CAN_MFID0xC,CAN Message 0xC Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0xC))++0x3
|
|
hide.long 0x0 "CAN_MSR0xC,CAN Message 0xC Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0xC))++0x03
|
|
hide.long 0x00 "CAN_MDL0xC,CAN Message 0xC Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0xC))++0x03
|
|
hide.long 0x00 "CAN_MDH0xC,CAN Message 0xC Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0xC))++0x03
|
|
line.long 0x00 "CAN_MCR0xC,CAN Message 0xC Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0xC Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0xD Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xD)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xD)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xD))++0x3
|
|
line.long 0x00 "CAN_MMR0xD,CAN Message 0xD Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0xD)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0xD)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0xD))++0x3
|
|
line.long 0x00 "CAN_MMR0xD,CAN Message 0xD Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xD)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xD)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xD))++0x3
|
|
line.long 0x00 "CAN_MMR0xD,CAN Message 0xD Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0xD))++0x3
|
|
line.long 0x00 "CAN_MMR0xD,CAN Message 0xD Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0xD))++0x7
|
|
line.long 0x0 "CAN_MAM0xD,CAN Message 0xD Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0xD,CAN Message 0xD ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0xD))++0x3
|
|
line.long 0x00 "CAN_MFID0xD,CAN Message 0xD Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0xD))++0x3
|
|
hide.long 0x0 "CAN_MSR0xD,CAN Message 0xD Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0xD))++0x03
|
|
hide.long 0x00 "CAN_MDL0xD,CAN Message 0xD Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0xD))++0x03
|
|
hide.long 0x00 "CAN_MDH0xD,CAN Message 0xD Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0xD))++0x03
|
|
line.long 0x00 "CAN_MCR0xD,CAN Message 0xD Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0xD Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0xE Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xE)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xE)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xE))++0x3
|
|
line.long 0x00 "CAN_MMR0xE,CAN Message 0xE Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0xE)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0xE)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0xE))++0x3
|
|
line.long 0x00 "CAN_MMR0xE,CAN Message 0xE Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xE)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xE)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xE))++0x3
|
|
line.long 0x00 "CAN_MMR0xE,CAN Message 0xE Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0xE))++0x3
|
|
line.long 0x00 "CAN_MMR0xE,CAN Message 0xE Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0xE))++0x7
|
|
line.long 0x0 "CAN_MAM0xE,CAN Message 0xE Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0xE,CAN Message 0xE ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0xE))++0x3
|
|
line.long 0x00 "CAN_MFID0xE,CAN Message 0xE Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0xE))++0x3
|
|
hide.long 0x0 "CAN_MSR0xE,CAN Message 0xE Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0xE))++0x03
|
|
hide.long 0x00 "CAN_MDL0xE,CAN Message 0xE Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0xE))++0x03
|
|
hide.long 0x00 "CAN_MDH0xE,CAN Message 0xE Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0xE))++0x03
|
|
line.long 0x00 "CAN_MCR0xE,CAN Message 0xE Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0xE Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xc
|
|
tree "CAN Message 0xF Registers"
|
|
if ((((data.long(ad:0xfffac000))&0x20)==0x20)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xF)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xF)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xF))++0x3
|
|
line.long 0x00 "CAN_MMR0xF,CAN Message 0xF Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x20)&&((((data.long(ad:0xfffac000+0x200+(0x20*0xF)))&0x7000000)==0x1000000)||(((data.long(ad:0xfffac000+0x200+(0x20*0xF)))&0x7000000)==0x2000000)))
|
|
group.long (0x200+(0x20*0xF))++0x3
|
|
line.long 0x00 "CAN_MMR0xF,CAN Message 0xF Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark Value"
|
|
elif ((((data.long(ad:0xfffac000))&0x20)==0x00)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xF)))&0x7000000)!=0x1000000)&&(((data.long(ad:0xfffac000+0x200+(0x20*0xF)))&0x7000000)!=0x2000000))
|
|
group.long (0x200+(0x20*0xF))++0x3
|
|
line.long 0x00 "CAN_MMR0xF,CAN Message 0xF Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "Priority 0,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Priority 7,Priority 8,Priority 9,Priority 10,Priority 11,Priority 12,Priority 13,Priority 14,Priority 15"
|
|
else
|
|
group.long (0x200+(0x20*0xF))++0x3
|
|
line.long 0x00 "CAN_MMR0xF,CAN Message 0xF Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception/overwrite,Transmit,Consumer,Producer,?..."
|
|
endif
|
|
group.long (0x204+(0x20*0xF))++0x7
|
|
line.long 0x0 "CAN_MAM0xF,CAN Message 0xF Acceptance Mask Register"
|
|
bitfld.long 0x0 29. " MIDE ,Identifier Version" "IDvA,IDvA/IDvB"
|
|
hexmask.long.word 0x0 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
line.long 0x4 "CAN_MID0xF,CAN Message 0xF ID Register"
|
|
bitfld.long 0x4 29. " MIDE ,Identifier Version" "A,B"
|
|
hexmask.long.word 0x4 18.--28. 1. " MIDvA ,Identifier Complementary Bits (Standard Frame Mode)"
|
|
textline " "
|
|
hexmask.long.tbyte 0x4 0.--17. 1. " MIDvB ,Identifier Complementary Bits (Extended Frame Mode)"
|
|
rgroup.long (0x20c+(0x20*0xF))++0x3
|
|
line.long 0x00 "CAN_MFID0xF,CAN Message 0xF Family ID Register"
|
|
hexmask.long 0x00 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x210+(0x20*0xF))++0x3
|
|
hide.long 0x0 "CAN_MSR0xF,CAN Message 0xF Status Register"
|
|
in
|
|
hgroup.long (0x214+(0x20*0xF))++0x03
|
|
hide.long 0x00 "CAN_MDL0xF,CAN Message 0xF Data Low Register"
|
|
in
|
|
hgroup.long (0x218+(0x20*0xF))++0x03
|
|
hide.long 0x00 "CAN_MDH0xF,CAN Message 0xF Data High Register"
|
|
in
|
|
wgroup.long (0x21c+(0x20*0xF))++0x03
|
|
line.long 0x00 "CAN_MCR0xF,CAN Message 0xF Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not transferred,Transferred"
|
|
bitfld.long 0x00 22. " MACR ,Mailbox 0xF Abort Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation)"
|
|
base ad:0xfffb8000
|
|
width 0x9
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PWM_MR,PWM Mode Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0xc++3
|
|
line.long 0x0 "PWM_SR,PWM Status Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM Output for Channel 3 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM Output for Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM Output for Channel 1 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM Output for Channel 0 Enable" "Disabled,Enabled"
|
|
group.long 0x18++3
|
|
line.long 0x0 "PWM_IMR,PWM Interrupt Mask Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Enable Interrupt for PWM Channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Enable Interrupt for PWM Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Enable Interrupt for PWM Channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,Enable Interrupt for PWM Channel 0" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PWM_ISR,PWM Interrupt Status Register"
|
|
in
|
|
wgroup 0x0++0x0
|
|
width 0xb
|
|
tree "Channel 0 Registers"
|
|
group.long (0x200+(0*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR0,PWM Channel 0 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD0,PWM Channel 0 Period Register"
|
|
rgroup.long (0x20C+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
wgroup.long (0x210+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD0,PWM Channel 0 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 1 Registers"
|
|
group.long (0x200+(1*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR1,PWM Channel 1 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD1,PWM Channel 1 Period Register"
|
|
rgroup.long (0x20C+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
wgroup.long (0x210+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD1,PWM Channel 1 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 2 Registers"
|
|
group.long (0x200+(2*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR2,PWM Channel 2 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD2,PWM Channel 2 Period Register"
|
|
rgroup.long (0x20C+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
wgroup.long (0x210+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD2,PWM Channel 2 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 3 Registers"
|
|
group.long (0x200+(3*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR3,PWM Channel 3 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD3,PWM Channel 3 Period Register"
|
|
rgroup.long (0x20C+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
wgroup.long (0x210+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD3,PWM Channel 3 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.open "MCI (MultiMedia Card Interface)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "MCI0"
|
|
base ad:0xfff80000
|
|
width 0xb
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "MCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " MCIDIS ,Multi-Media Interface Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enabled"
|
|
sif (cpu()=="AT91SAM9261")
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
else
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " PDCFBYTE ,PDC Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "MCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0 x Multiplier,1 x Multiplier,2 x Multiplier,3 x Multiplier,4 x Multiplier,5 x Multiplier,6 x Multiplier,7 x Multiplier,8 x Multiplier,9 x Multiplier,10 x Multiplier,11 x Multiplier,12 x Multiplier,13 x Multiplier,14 x Multiplier,15 x Multiplier"
|
|
line.long 0x04 "MCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 7. " SDCBUS ,SDCard Bus Width" "1-bit,4-bit"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*"))
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,B,?..."
|
|
endif
|
|
line.long 0x08 "MCI_ARGR,MCI Argument Register"
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 19.--20. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,?..."
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
else
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*"))
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "MCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
endif
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "MCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "MCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "MCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "MCI_RSPR3,MCI Response Register 3"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "MCI_RDR,MCI Receive Data Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "MCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "MCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "MCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " SDIOIRQB_set/clr ,SDIOIRQB Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_MCI0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI_RPR,MultiMedia Card Interface Receive Pointer Register"
|
|
line.long 0x04 "MCI_RCR,MultiMedia Card Interface Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI_TPR,MultiMedia Card Interface Transmit Pointer Register"
|
|
line.long 0x0c "MCI_TCR,MultiMedia Card Interface Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI_RNPR,MultiMedia Card Interface Receive Next Pointer Register"
|
|
line.long 0x14 "MCI_RNCR,MultiMedia Card Interface Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI_TNPR,MultiMedia Card Interface Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI_TNCR,MultiMedia Card Interface Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI_PTCR,MultiMedia Card Interface PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI_PTSR,MultiMedia Card Interface PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "MCI1"
|
|
base ad:0xfff84000
|
|
width 0xb
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "MCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " MCIDIS ,Multi-Media Interface Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enabled"
|
|
sif (cpu()=="AT91SAM9261")
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
else
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " PDCFBYTE ,PDC Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "MCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0 x Multiplier,1 x Multiplier,2 x Multiplier,3 x Multiplier,4 x Multiplier,5 x Multiplier,6 x Multiplier,7 x Multiplier,8 x Multiplier,9 x Multiplier,10 x Multiplier,11 x Multiplier,12 x Multiplier,13 x Multiplier,14 x Multiplier,15 x Multiplier"
|
|
line.long 0x04 "MCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 7. " SDCBUS ,SDCard Bus Width" "1-bit,4-bit"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*"))
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,B,?..."
|
|
endif
|
|
line.long 0x08 "MCI_ARGR,MCI Argument Register"
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 19.--20. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,?..."
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
else
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*"))
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "MCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
endif
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "MCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "MCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "MCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "MCI_RSPR3,MCI Response Register 3"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "MCI_RDR,MCI Receive Data Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "MCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "MCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "MCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " SDIOIRQB_set/clr ,SDIOIRQB Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_MCI1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI_RPR,MultiMedia Card Interface Receive Pointer Register"
|
|
line.long 0x04 "MCI_RCR,MultiMedia Card Interface Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI_TPR,MultiMedia Card Interface Transmit Pointer Register"
|
|
line.long 0x0c "MCI_TCR,MultiMedia Card Interface Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI_RNPR,MultiMedia Card Interface Receive Next Pointer Register"
|
|
line.long 0x14 "MCI_RNCR,MultiMedia Card Interface Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI_TNPR,MultiMedia Card Interface Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI_TNCR,MultiMedia Card Interface Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI_PTCR,MultiMedia Card Interface PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI_PTSR,MultiMedia Card Interface PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree "MCI Registers"
|
|
base ad:0xfffa8000
|
|
width 0xb
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "MCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " MCIDIS ,Multi-Media Interface Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enabled"
|
|
sif (cpu()=="AT91SAM9261")
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
else
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " PDCFBYTE ,PDC Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "MCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0 x Multiplier,1 x Multiplier,2 x Multiplier,3 x Multiplier,4 x Multiplier,5 x Multiplier,6 x Multiplier,7 x Multiplier,8 x Multiplier,9 x Multiplier,10 x Multiplier,11 x Multiplier,12 x Multiplier,13 x Multiplier,14 x Multiplier,15 x Multiplier"
|
|
line.long 0x04 "MCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 7. " SDCBUS ,SDCard Bus Width" "1-bit,4-bit"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*"))
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,B,?..."
|
|
endif
|
|
line.long 0x08 "MCI_ARGR,MCI Argument Register"
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 19.--20. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,?..."
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
else
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
endif
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*"))
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "MCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
endif
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "MCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "MCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "MCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "MCI_RSPR3,MCI Response Register 3"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "MCI_RDR,MCI Receive Data Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "MCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "MCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "MCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " SDIOIRQB_set/clr ,SDIOIRQB Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_MCI"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI_RPR,MultiMedia Card Interface Receive Pointer Register"
|
|
line.long 0x04 "MCI_RCR,MultiMedia Card Interface Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI_TPR,MultiMedia Card Interface Transmit Pointer Register"
|
|
line.long 0x0c "MCI_TCR,MultiMedia Card Interface Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI_RNPR,MultiMedia Card Interface Receive Next Pointer Register"
|
|
line.long 0x14 "MCI_RNCR,MultiMedia Card Interface Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI_TNPR,MultiMedia Card Interface Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI_TNCR,MultiMedia Card Interface Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI_PTCR,MultiMedia Card Interface PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI_PTSR,MultiMedia Card Interface PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9260")
|
|
tree "EMAC (Ethernet MAC 10/100)"
|
|
base ad:0xfffc4000
|
|
width 0xC
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EMAC_NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit Halt" "No effect,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Transmission Start" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back Pressure" "No effect,Collisions"
|
|
bitfld.long 0x00 7. " WESTAT ,Statistics Registers Write Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Statistics Registers Increment" "No effect,Incremented"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Statistics Registers Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Loopback Local" "No loopback,Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LB ,Loopback" "No loopback,Loopback"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
line.long 0x04 "EMAC_NCFG,Network Configuration Register"
|
|
else
|
|
line.long 0x04 "EMAC_NCFGR,Network Configuration Register"
|
|
endif
|
|
bitfld.long 0x04 19. " IRXFCS ,RX FCS Ignore" "Normal,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Half-Duplex Receive Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DRFCS ,Receive FCS Discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length Field Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " RBOF ,Receive Buffer Offset" "No offset,1-byte,2-byte,3-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry Test" "Normal,Retry"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC Clock Divider" "MCK/8,MCK/16,MCK/32,MCK/64"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BIG ,1536 Bytes Frames Receive" "Not received,Received"
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,All Frames Copy" "Not copied,Copied"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full Duplex Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mb/s,100 Mb/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMAC_NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic IDLE" "Running,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIO ,MDIO Pin Status" "Low,High"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "EMAC_TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No underrun,Underrun"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BEX ,Buffers Mid Frame Exhaust" "Not exhausted,Exhausted"
|
|
bitfld.long 0x00 3. " TGO ,Transmit Go" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
eventfld.long 0x00 2. " RLES ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
else
|
|
eventfld.long 0x00 2. " RLE ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
endif
|
|
eventfld.long 0x00 1. " COL ,Collision Occurence" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "Not read,Read"
|
|
line.long 0x04 "EMAC_RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 4. " ADDR ,Receive Buffer Queue Pointer Address"
|
|
if (((data.long(ad:(0xfffc4000+0x14)))&0x8)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "EMAC_RSR,Receive Status Register"
|
|
eventfld.long 0x0 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0 1. " REC ,Frame Receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x0 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x0 "EMAC_ISR,Interrupt Status Register"
|
|
in
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EMAC_IMR,Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT91CAP9")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " WOL_set/clr , Wake On LAN" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause Time Zero" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PFR_set/clr ,Pause Frame Receive" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " HRESP_set/clr ,Hresp Not OK" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive Overrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 07. -0x8 07. -0x4 7. " TCOMP_set/clr ,Transmit Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 06. -0x8 06. -0x4 6. " TXERR_set/clr ,Transmit Buffers Mid-Frame Exhaust Interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 05. -0x8 05. -0x4 5. " RLE_set/clr ,Retry Limit Exceed" "Enabled,Disabled"
|
|
setclrfld.long 0x0 04. -0x8 04. -0x4 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 03. -0x8 03. -0x4 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Enabled,Disabled"
|
|
setclrfld.long 0x0 02. -0x8 02. -0x4 2. " RXUBR_set/clr ,Receive Used Bit Read" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 01. -0x8 01. -0x4 1. " RCOMP_set/clr ,Receive Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 00. -0x8 00. -0x4 0. " MFD_set/clr ,Management Frame Send" "Enabled,Disabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "EMAC_MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. " SOF ,Frame Start" "Not valid,Valid,Not valid,Not valid"
|
|
bitfld.long 0x0 28.--29. " RW ,Read/Write" "Reserved,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--27. 1. " PHYA ,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. " REGA ,Register Address"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " CODE ,Code" "00,01,10,11"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,PHY Data"
|
|
line.long 0x4 "EMAC_PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "EMAC_HRB,Hash Register Bottom"
|
|
line.long 0x04 "EMAC_HRT,Hash Register Top"
|
|
tree "Specific Address Registers"
|
|
textline " "
|
|
group.long 0x98++0x1F
|
|
line.long 0x0 "EMAC_SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x4 "EMAC_SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x8 "EMAC_SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0xC "EMAC_SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x10 "EMAC_SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x14 "EMAC_SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x18 "EMAC_SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x1C "EMAC_SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "EMAC_TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TID ,Type ID Checking"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "EMAC_USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Transceiver Input Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RMII ,RMII Operation Mode Enable" "MII,RMII"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT9CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "EMAC_WOL, Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI , Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 , Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP , ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG , Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " IP , ARP request IP address"
|
|
endif
|
|
tree "EMAC Statistic Registers"
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "EMAC_PFR,Pause Frames Received Register"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "EMAC_FTO,Frames Transmitted Ok Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x0 "EMAC_SCF,Single Collision Frames Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "EMAC_MCF,Multicollision Frames Register"
|
|
in
|
|
hgroup.long 0x4c++0x3
|
|
hide.long 0x0 "EMAC_FRO,Frames Received Ok Register"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "EMAC_FCSE,Frames Check Sequence Errors Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x0 "EMAC_ALE,Alignment Errors Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x0 "EMAC_DTF,Deferred Transmission Frames Register"
|
|
in
|
|
hgroup.long 0x5c++0x3
|
|
hide.long 0x0 "EMAC_LCOL,Late Collisions Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_ECOL,Excessive Collisions Register"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_EXCOL,Excessive Collisions Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "EMAC_TUND,Transmit Underrun Errors Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "EMAC_CSE,Carrier Sense Errors Register"
|
|
in
|
|
hgroup.long 0x6c++0x3
|
|
hide.long 0x0 "EMAC_RRE,Receive Resource Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROV,Receive Overrun Errors Register"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROVR,Receive Overrun Errors Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x0 "EMAC_RSE,Receive Symbol Errors Register"
|
|
in
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x0 "EMAC_ELE,Excessive Length Errors Register"
|
|
in
|
|
hgroup.long 0x7c++0x3
|
|
hide.long 0x0 "EMAC_RJA,Receive Jabbers Register"
|
|
in
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x0 "EMAC_USF,Undersize Frames Register"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x0 "EMAC_STE,SQE Test Errors Register"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x0 "EMAC_RLE,Received Length Field Mismatch Register"
|
|
in
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25")
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "EMAC (Ethernet MAC 10/100)"
|
|
base ad:0xfffbc000
|
|
width 0xC
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EMAC_NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit Halt" "No effect,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Transmission Start" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back Pressure" "No effect,Collisions"
|
|
bitfld.long 0x00 7. " WESTAT ,Statistics Registers Write Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Statistics Registers Increment" "No effect,Incremented"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Statistics Registers Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Loopback Local" "No loopback,Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LB ,Loopback" "No loopback,Loopback"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
line.long 0x04 "EMAC_NCFG,Network Configuration Register"
|
|
else
|
|
line.long 0x04 "EMAC_NCFGR,Network Configuration Register"
|
|
endif
|
|
bitfld.long 0x04 19. " IRXFCS ,RX FCS Ignore" "Normal,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Half-Duplex Receive Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DRFCS ,Receive FCS Discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length Field Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " RBOF ,Receive Buffer Offset" "No offset,1-byte,2-byte,3-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry Test" "Normal,Retry"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC Clock Divider" "MCK/8,MCK/16,MCK/32,MCK/64"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BIG ,1536 Bytes Frames Receive" "Not received,Received"
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,All Frames Copy" "Not copied,Copied"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full Duplex Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mb/s,100 Mb/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMAC_NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic IDLE" "Running,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIO ,MDIO Pin Status" "Low,High"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "EMAC_TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No underrun,Underrun"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BEX ,Buffers Mid Frame Exhaust" "Not exhausted,Exhausted"
|
|
bitfld.long 0x00 3. " TGO ,Transmit Go" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
eventfld.long 0x00 2. " RLES ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
else
|
|
eventfld.long 0x00 2. " RLE ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
endif
|
|
eventfld.long 0x00 1. " COL ,Collision Occurence" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "Not read,Read"
|
|
line.long 0x04 "EMAC_RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 4. " ADDR ,Receive Buffer Queue Pointer Address"
|
|
if (((data.long(ad:(0xfffbc000+0x14)))&0x8)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "EMAC_RSR,Receive Status Register"
|
|
eventfld.long 0x0 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0 1. " REC ,Frame Receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x0 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x0 "EMAC_ISR,Interrupt Status Register"
|
|
in
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EMAC_IMR,Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT91CAP9")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " WOL_set/clr , Wake On LAN" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause Time Zero" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PFR_set/clr ,Pause Frame Receive" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " HRESP_set/clr ,Hresp Not OK" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive Overrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 07. -0x8 07. -0x4 7. " TCOMP_set/clr ,Transmit Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 06. -0x8 06. -0x4 6. " TXERR_set/clr ,Transmit Buffers Mid-Frame Exhaust Interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 05. -0x8 05. -0x4 5. " RLE_set/clr ,Retry Limit Exceed" "Enabled,Disabled"
|
|
setclrfld.long 0x0 04. -0x8 04. -0x4 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 03. -0x8 03. -0x4 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Enabled,Disabled"
|
|
setclrfld.long 0x0 02. -0x8 02. -0x4 2. " RXUBR_set/clr ,Receive Used Bit Read" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 01. -0x8 01. -0x4 1. " RCOMP_set/clr ,Receive Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 00. -0x8 00. -0x4 0. " MFD_set/clr ,Management Frame Send" "Enabled,Disabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "EMAC_MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. " SOF ,Frame Start" "Not valid,Valid,Not valid,Not valid"
|
|
bitfld.long 0x0 28.--29. " RW ,Read/Write" "Reserved,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--27. 1. " PHYA ,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. " REGA ,Register Address"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " CODE ,Code" "00,01,10,11"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,PHY Data"
|
|
line.long 0x4 "EMAC_PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "EMAC_HRB,Hash Register Bottom"
|
|
line.long 0x04 "EMAC_HRT,Hash Register Top"
|
|
tree "Specific Address Registers"
|
|
textline " "
|
|
group.long 0x98++0x1F
|
|
line.long 0x0 "EMAC_SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x4 "EMAC_SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x8 "EMAC_SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0xC "EMAC_SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x10 "EMAC_SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x14 "EMAC_SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x18 "EMAC_SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x1C "EMAC_SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "EMAC_TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TID ,Type ID Checking"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "EMAC_USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Transceiver Input Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RMII ,RMII Operation Mode Enable" "MII,RMII"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT9CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "EMAC_WOL, Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI , Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 , Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP , ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG , Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " IP , ARP request IP address"
|
|
endif
|
|
tree "EMAC Statistic Registers"
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "EMAC_PFR,Pause Frames Received Register"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "EMAC_FTO,Frames Transmitted Ok Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x0 "EMAC_SCF,Single Collision Frames Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "EMAC_MCF,Multicollision Frames Register"
|
|
in
|
|
hgroup.long 0x4c++0x3
|
|
hide.long 0x0 "EMAC_FRO,Frames Received Ok Register"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "EMAC_FCSE,Frames Check Sequence Errors Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x0 "EMAC_ALE,Alignment Errors Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x0 "EMAC_DTF,Deferred Transmission Frames Register"
|
|
in
|
|
hgroup.long 0x5c++0x3
|
|
hide.long 0x0 "EMAC_LCOL,Late Collisions Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_ECOL,Excessive Collisions Register"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_EXCOL,Excessive Collisions Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "EMAC_TUND,Transmit Underrun Errors Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "EMAC_CSE,Carrier Sense Errors Register"
|
|
in
|
|
hgroup.long 0x6c++0x3
|
|
hide.long 0x0 "EMAC_RRE,Receive Resource Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROV,Receive Overrun Errors Register"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROVR,Receive Overrun Errors Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x0 "EMAC_RSE,Receive Symbol Errors Register"
|
|
in
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x0 "EMAC_ELE,Excessive Length Errors Register"
|
|
in
|
|
hgroup.long 0x7c++0x3
|
|
hide.long 0x0 "EMAC_RJA,Receive Jabbers Register"
|
|
in
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x0 "EMAC_USF,Undersize Frames Register"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x0 "EMAC_STE,SQE Test Errors Register"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x0 "EMAC_RLE,Received Length Field Mismatch Register"
|
|
in
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25")
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "UDP (USB Device Port)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0xfff78000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UDP_FRM_NUM,UDP Frame Number Register"
|
|
bitfld.long 0x00 17. " FRM_OK ,Frame OK" "SOF_PID,SOF_EOP"
|
|
bitfld.long 0x00 16. " FRM_ERR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FRM_NUM[10:0] ,Frame Number as Defined In the Packet Field Formats"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "UDP_GLB_STAT,UDP Global State Register"
|
|
sif (cpu()!="AT91SAM9263"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
bitfld.long 0x00 4. " RMWUPE ,Remote Wake Up Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9263")
|
|
bitfld.long 0x00 3. " RSMINPR ,A Resume Has Been Sent to the Host" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
bitfld.long 0x00 2. " ESR ,Enable Send Resume" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONFG ,Configured" "Not configured,Configured"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FADDEN ,Function Address Enable" "Disabled,Enabled"
|
|
line.long 0x4 "UDP_FADDR,UDP Function Address Register"
|
|
bitfld.long 0x4 8. " FEN ,Function Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--6. 1. " FADD[6:0] ,Function Address Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "UDP_IMR,UDP Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " WAKEUP_Clear/Set ,Mask UDP bus Wakeup Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " SOFINT_Clear/Set ,Mask Start Of Frame Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " EXTRSM_Clear/Set ,Disable External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " RXRSM_Clear/Set ,Mask UDP Resume Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " RXSUSP_Clear/Set ,Mask UDP Suspend Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " EP5INT_Clear/Set ,Mask Endpoint 5 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " EP4INT_Clear/Set ,Mask Endpoint 4 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " EP3INT_Clear/Set ,Mask Endpoint 3 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EP2INT_Clear/Set ,Mask Endpoint 2 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " EP1INT_Clear/Set ,Mask Endpoint 1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " EP0INT_Clear/Set ,Mask Endpoint 0 Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "UDP_ISR,UDP Interrupt Status Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 13. " WAKEUP ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 12. " ENDBUSRES ,End of BUS Reset Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SOFINT ,Start of Frame Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 10. " EXTRSM ,Disable External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 9. " RXRSM ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 8. " RXSUSP ,UDP Suspend Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EP5INT ,Endpoint 5 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " EP4INT ,Endpoint 4 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " EP3INT ,Endpoint 3 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " EP2INT ,Endpoint 2 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP1INT ,Endpoint 1 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " EP0INT ,Endpoint 0 Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UDP_ICR,UDP Interrupt Clear Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 13. " WAKEUP ,Clear Wakeup Interrupt" "No effect,Cleared"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENDBUSRES ,Clear End of BUS Reset Interrupt" "No effect,Cleared"
|
|
bitfld.long 0x0 11. " SOFINT ,Clear Start Of Frame Interrupt" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 10. " EXTRSM ,Disable External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXRSM ,Clear UDP Resume Interrupt" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " RXSUSP ,Clear UDP Suspend Interrupt" "No effect,Cleared"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UDP_RST_EP,UDP Reset Endpoint Register"
|
|
bitfld.long 0x00 5. " EP5 ,Reset Endpoint 5" "No reset,Reset"
|
|
bitfld.long 0x00 4. " EP4 ,Reset Endpoint 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EP3 ,Reset Endpoint 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " EP2 ,Reset Endpoint 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP1 ,Reset Endpoint 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " EP0 ,Reset Endpoint 0" "No reset,Reset"
|
|
width 0xA
|
|
tree "Endpoint Control and Status Registers"
|
|
if (((d.l(ad:(0xfff78000+0x30+0x0)))&0x700)==0x000)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfff78000+0x30+0x0)))&0x700)==0x100)||(((d.l(ad:(0xfff78000+0x30+0x0)))&0x700)==0x500))
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfff78000+0x30+0x0)))&0x700)==0x400)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x30+0x4)))&0x700)==0x000)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfff78000+0x30+0x4)))&0x700)==0x100)||(((d.l(ad:(0xfff78000+0x30+0x4)))&0x700)==0x500))
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfff78000+0x30+0x4)))&0x700)==0x400)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x30+0x8)))&0x700)==0x000)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfff78000+0x30+0x8)))&0x700)==0x100)||(((d.l(ad:(0xfff78000+0x30+0x8)))&0x700)==0x500))
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfff78000+0x30+0x8)))&0x700)==0x400)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x30+0xC)))&0x700)==0x000)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfff78000+0x30+0xC)))&0x700)==0x100)||(((d.l(ad:(0xfff78000+0x30+0xC)))&0x700)==0x500))
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfff78000+0x30+0xC)))&0x700)==0x400)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x30+0x10)))&0x700)==0x000)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfff78000+0x30+0x10)))&0x700)==0x100)||(((d.l(ad:(0xfff78000+0x30+0x10)))&0x700)==0x500))
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfff78000+0x30+0x10)))&0x700)==0x400)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x30+0x14)))&0x700)==0x000)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfff78000+0x30+0x14)))&0x700)==0x100)||(((d.l(ad:(0xfff78000+0x30+0x14)))&0x700)==0x500))
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfff78000+0x30+0x14)))&0x700)==0x400)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
tree.end
|
|
tree "UDP Endpoint FIFO Data Registers"
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "UDP_FDR0,UDP Endpoint 0 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x00 "UDP_FDR1,UDP Endpoint 1 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x00 "UDP_FDR2,UDP Endpoint 2 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x5C++0x3
|
|
hide.long 0x00 "UDP_FDR3,UDP Endpoint 3 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x00 "UDP_FDR4,UDP Endpoint 4 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "UDP_FDR5,UDP Endpoint 5 FIFO Data Register"
|
|
in
|
|
tree.end
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "UDP_TXVC,UDP Transceiver Control Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9260")
|
|
bitfld.long 0x00 9. " PUON ,Pullup On" "Disconnected,Connected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "Enabled,Disabled"
|
|
width 0xb
|
|
else
|
|
base ad:0xfffa4000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UDP_FRM_NUM,UDP Frame Number Register"
|
|
bitfld.long 0x00 17. " FRM_OK ,Frame OK" "SOF_PID,SOF_EOP"
|
|
bitfld.long 0x00 16. " FRM_ERR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FRM_NUM[10:0] ,Frame Number as Defined In the Packet Field Formats"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "UDP_GLB_STAT,UDP Global State Register"
|
|
sif (cpu()!="AT91SAM9263"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
bitfld.long 0x00 4. " RMWUPE ,Remote Wake Up Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9263")
|
|
bitfld.long 0x00 3. " RSMINPR ,A Resume Has Been Sent to the Host" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
bitfld.long 0x00 2. " ESR ,Enable Send Resume" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONFG ,Configured" "Not configured,Configured"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FADDEN ,Function Address Enable" "Disabled,Enabled"
|
|
line.long 0x4 "UDP_FADDR,UDP Function Address Register"
|
|
bitfld.long 0x4 8. " FEN ,Function Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--6. 1. " FADD[6:0] ,Function Address Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "UDP_IMR,UDP Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " WAKEUP_Clear/Set ,Mask UDP bus Wakeup Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " SOFINT_Clear/Set ,Mask Start Of Frame Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " EXTRSM_Clear/Set ,Disable External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " RXRSM_Clear/Set ,Mask UDP Resume Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " RXSUSP_Clear/Set ,Mask UDP Suspend Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " EP5INT_Clear/Set ,Mask Endpoint 5 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " EP4INT_Clear/Set ,Mask Endpoint 4 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " EP3INT_Clear/Set ,Mask Endpoint 3 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EP2INT_Clear/Set ,Mask Endpoint 2 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " EP1INT_Clear/Set ,Mask Endpoint 1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " EP0INT_Clear/Set ,Mask Endpoint 0 Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "UDP_ISR,UDP Interrupt Status Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 13. " WAKEUP ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 12. " ENDBUSRES ,End of BUS Reset Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SOFINT ,Start of Frame Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 10. " EXTRSM ,Disable External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 9. " RXRSM ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 8. " RXSUSP ,UDP Suspend Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EP5INT ,Endpoint 5 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " EP4INT ,Endpoint 4 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " EP3INT ,Endpoint 3 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " EP2INT ,Endpoint 2 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP1INT ,Endpoint 1 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " EP0INT ,Endpoint 0 Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UDP_ICR,UDP Interrupt Clear Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 13. " WAKEUP ,Clear Wakeup Interrupt" "No effect,Cleared"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENDBUSRES ,Clear End of BUS Reset Interrupt" "No effect,Cleared"
|
|
bitfld.long 0x0 11. " SOFINT ,Clear Start Of Frame Interrupt" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x0 10. " EXTRSM ,Disable External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXRSM ,Clear UDP Resume Interrupt" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " RXSUSP ,Clear UDP Suspend Interrupt" "No effect,Cleared"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UDP_RST_EP,UDP Reset Endpoint Register"
|
|
bitfld.long 0x00 5. " EP5 ,Reset Endpoint 5" "No reset,Reset"
|
|
bitfld.long 0x00 4. " EP4 ,Reset Endpoint 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EP3 ,Reset Endpoint 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " EP2 ,Reset Endpoint 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP1 ,Reset Endpoint 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " EP0 ,Reset Endpoint 0" "No reset,Reset"
|
|
width 0xA
|
|
tree "Endpoint Control and Status Registers"
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x000)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x500))
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x400)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x000)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x500))
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x400)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x000)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x500))
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x400)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x000)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x500))
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x400)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x000)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x500))
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x400)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x000)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x500))
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x400)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
tree.end
|
|
tree "UDP Endpoint FIFO Data Registers"
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "UDP_FDR0,UDP Endpoint 0 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x00 "UDP_FDR1,UDP Endpoint 1 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x00 "UDP_FDR2,UDP Endpoint 2 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x5C++0x3
|
|
hide.long 0x00 "UDP_FDR3,UDP Endpoint 3 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x00 "UDP_FDR4,UDP Endpoint 4 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "UDP_FDR5,UDP Endpoint 5 FIFO Data Register"
|
|
in
|
|
tree.end
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "UDP_TXVC,UDP Transceiver Control Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9260")
|
|
bitfld.long 0x00 9. " PUON ,Pullup On" "Disconnected,Connected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "Enabled,Disabled"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "UHP (USB Host Port)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0x00a00000
|
|
width 20.
|
|
tree "Control and Status Partition"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IR ,Interrupt Routing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio (Control/Bulk)" "1 : 1,2 : 1,3 : 1,4 : 1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
width 20.
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
eventfld.long 0x00 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "HCINTERRUPTENABLE,HcInterruptEnable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OC ,OC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,RHSC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,FNO Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,UE Interrupt Enable" "Inore,Enabled"
|
|
bitfld.long 0x00 3. " RD ,RD Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 2. " SF ,SF Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,WDH Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 0. " SO ,SO Interrupt Enable" "Ignore,Enabled"
|
|
line.long 0x04 "HCINTERRUPTDISABLE,HcInterruptDisable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 30. " OC ,OC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 6. " RHSC ,RHSC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 5. " FNO ,FNO Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,UE Interrupt Disable" "Inore,Disabled"
|
|
bitfld.long 0x04 3. " RD ,RD Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 2. " SF ,SF Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,WDH Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 0. " SO ,SO Interrupt Disable" "Ignore,Disabled"
|
|
tree.end
|
|
tree "Memory Pointer Partition"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "HCHCCA,Hc HCCA Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
line.long 0x04 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PCED ,Period Current ED"
|
|
line.long 0x08 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " CHED ,Control Head ED"
|
|
line.long 0x0c "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " CCED ,Control Current ED"
|
|
line.long 0x10 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
line.long 0x14 "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x14 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Done Head"
|
|
tree.end
|
|
width 17.
|
|
tree "Frame Counter Partition"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Threshold"
|
|
tree.end
|
|
width 20.
|
|
tree "Root Hub Partition"
|
|
if (((d.l(ad:(0x00a00000+0x48)))&0x1100)==0x0)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00a00000+0x48)))&0x1100)==0x1000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00a00000+0x48)))&0x1100)==0x100)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
endif
|
|
width 20.
|
|
if (((d.l(ad:(0x00a00000+0x48)))&0x200)==0x200)
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 31. " PPCM[15] ,Port Power Control Mask[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " PPCM[14] ,Port Power Control Mask[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PPCM[13] ,Port Power Control Mask[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " PPCM[12] ,Port Power Control Mask[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PPCM[11] ,Port Power Control Mask[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " PPCM[10] ,Port Power Control Mask[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPCM[9] ,Port Power Control Mask[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PPCM[8] ,Port Power Control Mask[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PPCM[7] ,Port Power Control Mask[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PPCM[6] ,Port Power Control Mask[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCM[5] ,Port Power Control Mask[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " PPCM[4] ,Port Power Control Mask[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port Power Control Mask[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port Power Control Mask[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port Power Control Mask[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CCIC ,Over Current Indicator Change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local Power Status Change/Set Global Power" "No effect,On all ports"
|
|
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Over Current Indicator" "Low,High"
|
|
bitfld.long 0x00 0. " LPS ,Local Power Status/Clear Global Power" "No effect,Off all ports"
|
|
width 20.
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[0],Hc Rh Port Status [0]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[1],Hc Rh Port Status [1]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[2],Hc Rh Port Status [2]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[3],Hc Rh Port Status [3]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[4],Hc Rh Port Status [4]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[5],Hc Rh Port Status [5]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[6],Hc Rh Port Status [6]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[7],Hc Rh Port Status [7]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[8],Hc Rh Port Status [8]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[9],Hc Rh Port Status [9]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[10],Hc Rh Port Status [10]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[11],Hc Rh Port Status [11]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[12],Hc Rh Port Status [12]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[13],Hc Rh Port Status [13]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[14],Hc Rh Port Status [14]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
tree.end
|
|
width 0xb
|
|
endif
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9260")
|
|
base ad:0x00500000
|
|
width 20.
|
|
tree "Control and Status Partition"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IR ,Interrupt Routing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio (Control/Bulk)" "1 : 1,2 : 1,3 : 1,4 : 1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
width 20.
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
eventfld.long 0x00 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "HCINTERRUPTENABLE,HcInterruptEnable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OC ,OC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,RHSC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,FNO Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,UE Interrupt Enable" "Inore,Enabled"
|
|
bitfld.long 0x00 3. " RD ,RD Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 2. " SF ,SF Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,WDH Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 0. " SO ,SO Interrupt Enable" "Ignore,Enabled"
|
|
line.long 0x04 "HCINTERRUPTDISABLE,HcInterruptDisable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 30. " OC ,OC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 6. " RHSC ,RHSC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 5. " FNO ,FNO Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,UE Interrupt Disable" "Inore,Disabled"
|
|
bitfld.long 0x04 3. " RD ,RD Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 2. " SF ,SF Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,WDH Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 0. " SO ,SO Interrupt Disable" "Ignore,Disabled"
|
|
tree.end
|
|
tree "Memory Pointer Partition"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "HCHCCA,Hc HCCA Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
line.long 0x04 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PCED ,Period Current ED"
|
|
line.long 0x08 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " CHED ,Control Head ED"
|
|
line.long 0x0c "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " CCED ,Control Current ED"
|
|
line.long 0x10 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
line.long 0x14 "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x14 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Done Head"
|
|
tree.end
|
|
width 17.
|
|
tree "Frame Counter Partition"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Threshold"
|
|
tree.end
|
|
width 20.
|
|
tree "Root Hub Partition"
|
|
if (((d.l(ad:(0x00500000+0x48)))&0x1100)==0x0)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00500000+0x48)))&0x1100)==0x1000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00500000+0x48)))&0x1100)==0x100)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
endif
|
|
width 20.
|
|
if (((d.l(ad:(0x00500000+0x48)))&0x200)==0x200)
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 31. " PPCM[15] ,Port Power Control Mask[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " PPCM[14] ,Port Power Control Mask[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PPCM[13] ,Port Power Control Mask[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " PPCM[12] ,Port Power Control Mask[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PPCM[11] ,Port Power Control Mask[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " PPCM[10] ,Port Power Control Mask[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPCM[9] ,Port Power Control Mask[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PPCM[8] ,Port Power Control Mask[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PPCM[7] ,Port Power Control Mask[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PPCM[6] ,Port Power Control Mask[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCM[5] ,Port Power Control Mask[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " PPCM[4] ,Port Power Control Mask[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port Power Control Mask[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port Power Control Mask[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port Power Control Mask[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CCIC ,Over Current Indicator Change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local Power Status Change/Set Global Power" "No effect,On all ports"
|
|
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Over Current Indicator" "Low,High"
|
|
bitfld.long 0x00 0. " LPS ,Local Power Status/Clear Global Power" "No effect,Off all ports"
|
|
width 20.
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[0],Hc Rh Port Status [0]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[1],Hc Rh Port Status [1]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[2],Hc Rh Port Status [2]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[3],Hc Rh Port Status [3]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[4],Hc Rh Port Status [4]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[5],Hc Rh Port Status [5]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[6],Hc Rh Port Status [6]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[7],Hc Rh Port Status [7]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[8],Hc Rh Port Status [8]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[9],Hc Rh Port Status [9]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[10],Hc Rh Port Status [10]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[11],Hc Rh Port Status [11]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[12],Hc Rh Port Status [12]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[13],Hc Rh Port Status [13]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[14],Hc Rh Port Status [14]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
tree.end
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9263")
|
|
tree "LCDC (LCD Controller)"
|
|
sif (cpu()=="AT91SAM9263")
|
|
base ad:0x00700000
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
sif (cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
hexmask.long 0x00 2.--31. 0x4 " BADDR-U ,Base Address for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
else
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
endif
|
|
line.long 0x04 "DMABADDR2,DMA Base Address Register 2"
|
|
rgroup.long 0x08++0xf
|
|
line.long 0x00 "DMAFRMPT1,DMA Frame Pointer Register 1"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMPT-U ,Current value of frame pointer for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
line.long 0x04 "DMAFRMPT2,DMA Frame Pointer Register 2"
|
|
hexmask.long.tbyte 0x04 0.--22. 1. " FRMPT-L ,Current value of frame pointer for the Lower panel in dual scan mode"
|
|
line.long 0x8 "DMAFRMADD1,DMA Frame Address Register 1"
|
|
line.long 0xC "DMAFRMADD2,DMA Frame Address Register 2"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DMAFRMCFG,DMA Frame Configuration Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BRSTLN ,Burst Length"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMSIZE ,Frame Size"
|
|
line.long 0x4 "DMACON,DMA Control Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x4 4. " DMA2DEN ,DMA 2D Adressing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " DMAUPDT ,DMA Configuration Update" "No effect,Updated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 2. " DMABUSY ,DMA Busy" "Idle,Busy"
|
|
bitfld.long 0x4 1. " DMARST ,DMA Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x20++0x03
|
|
line.long 0x0 "DMA2DCFG,DMA 2D Adressing Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " PIXELOFF ,DAM2D Addressing Pixel Offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRINC ,DMA 2D Addressing Address increment"
|
|
endif
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "LCDCON1,LCD Control Register 1"
|
|
hexmask.long.word 0x00 21.--31. 1. " LINECNT ,Line Counter"
|
|
hexmask.long.word 0x00 12.--20. 1. " CLKVAL ,Clock Divider"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass lcd_pclk Divider" "Not bypassed,Bypassed"
|
|
if ((d.l(ad:0x00700000+0x804)&0x3)==0x2)
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,24 bpp/unpacked,?..."
|
|
else
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00700000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00700000+0x804)&0x4)==(0x4)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "Reserved,8-bit,16-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00700000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00700000+0x804)&0x4)==(0x0)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "4-bit,8-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
else
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
endif
|
|
group.long 0x808++0xf
|
|
line.long 0x0 "LCDTIM1,LCD Timing Configuration Register 1"
|
|
bitfld.long 0x0 24.--27. " VHDLY ,Vertical to horizontal delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
hexmask.long.byte 0x0 16.--21. 1. 1. " VPW ,Vertical Synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.byte 0x0 0.--7. 1. " VFP ,Vertical Front Porch"
|
|
line.long 0x4 "LCDTIM2,LCD Timing Configuration Register 2"
|
|
hexmask.long.word 0x4 21.--31. 1. 1. " HFP ,Horizontal Front Porch"
|
|
hexmask.long.byte 0x4 8.--13. 1. 1. " HPW ,Horizontal synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. 1. " HBP ,Horizontal Back Porch"
|
|
line.long 0x8 "LCDFRMCFG,LCD Frame Configuration Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
hexmask.long.word 0x8 21.--31. 1. " LINESIZE ,Horizontal size of LCD module"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x8 21.--31. 1. " HOZVAL ,Horizontal size of LCD module"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x8 0.--10. 1. " LINEVAL ,Vertical size of LCD module"
|
|
line.long 0xC "LCDFIFO,LCD FIFO Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " FIFOTH ,FIFO Threshold"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x818++0x3
|
|
line.long 0x0 "LCDMVAL,LCD_MODE Toggle Rate Value Register"
|
|
bitfld.long 0x0 31. " MMODE ,LCD_MODE toggle rate select" "Each frame,MVAL"
|
|
hexmask.long.byte 0x0 0.--7. 1. 1. " MVAL ,LCD_MODE toggle rate value"
|
|
endif
|
|
group.long 0x81c--0x847
|
|
line.long 0x00 "DP1_2,Dithering Pattern DP1_2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DP1_2 ,Pattern value for 1/2 duty cycle"
|
|
line.long 0x04 "DP4_7,Dithering Pattern DP4_7 Register"
|
|
hexmask.long 0x04 0.--27. 1. " DP4_7 ,Pattern value for 4/7 duty cycle"
|
|
line.long 0x8 "DP3_5,Dithering Pattern DP3_5 Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. " DP3_5 ,Pattern value for 3/5 duty cycle"
|
|
line.long 0xc "DP2_3,Dithering Pattern DP2_3 Register"
|
|
hexmask.long.word 0xc 0.--11. 1. " DP2_3 ,Pattern value for 2/3 duty cycle"
|
|
line.long 0x10 "DP5_7,Dithering Pattern DP5_7 Register"
|
|
hexmask.long 0x10 0.--27. 1. " DP5_7 ,Pattern value for 5/7 duty cycle"
|
|
line.long 0x14 "DP3_4,Dithering Pattern DP3_4 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DP3_4 ,Pattern value for 3/4 duty cycle"
|
|
line.long 0x18 "DP4_5,Dithering Pattern DP4_5 Register"
|
|
hexmask.long.tbyte 0x18 0.--19. 1. " DP4_5 ,Pattern value for 4/5 duty cycle"
|
|
line.long 0x1c "DP6_7,Dithering Pattern DP6_7 Register"
|
|
hexmask.long 0x1c 0.--27. 1. " DP6_7 ,Pattern value for 6/7 duty cycle"
|
|
line.long 0x20 "PWRCON,Power Control Register"
|
|
bitfld.long 0x20 31. " LCD_BUSY ,LCD Busy" "Idle,Busy"
|
|
hexmask.long.byte 0x20 1.--7. 1. " GUARD_TIME ,Guard Time"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LCD_PWR ,LCD module power control" "Low,High"
|
|
line.long 0x24 "CONTRAST_CTR,Contrast Control Register"
|
|
bitfld.long 0x24 3. " ENA ,PWM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " POL ,Output polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " PS ,Prescaler" "fLCDC_CLOCK,fLCDC_CLOCK/2,fLCDC_CLOCK/4,fLCDC_CLOCK/8"
|
|
line.long 0x28 "CONTRAST_VAL,Contrast Value Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " CVAL ,PWM compare value"
|
|
group.long 0x850++0x3
|
|
line.long 0x0 "LCD_IMR,LCD Interrupt Mask Register"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " MERIM_set/clr ,DMA Memory error Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OWRIM_set/clr ,FIFO overwrite Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " UFLWIM_set/clr ,FIFO underflow Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EOFIM_set/clr ,DMA End of frame Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " LSTLNIM_set/clr ,Last line Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " LNIM_set/clr ,Line Interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x3
|
|
line.long 0x0 "LCD_ISR,LCD Interrupt Status Register"
|
|
bitfld.long 0x0 6. " MERIS ,DMA Memory error Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 5. " OWRIS ,FIFO overwrite Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UFLWIS ,FIFO underflow Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 2. " EOFIS ,DMA End of frame Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LSTLNIS ,Last line Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 0. " LNIS ,Line Interrupt status" "Not active,Active"
|
|
wgroup.long 0x858++0x3
|
|
line.long 0x00 "LCD_ICR,LCD Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " MERIC ,DMA Memory error Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " OWRIC ,FIFO overwrite Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIC ,FIFO underflow Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " EOFIC ,DMA End of frame Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIC ,Last line Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " LNIC ,Line Interrupt clear" "No effect,Clear"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x860++03
|
|
line.long 0x00 "LCD_ITR,LCD Interrupt Test Register"
|
|
bitfld.long 0x00 6. " MERIT ,DMA Memory error interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 5. " OWRIT ,FIFO overwrite interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIT ,FIFO underflow interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 2. " EOFIT ,DMA End of frame interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIT ,Last line interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 0. " LNIT ,Line interrupt test" "No effect,Set"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
else
|
|
rgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "LCD_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "LCD_WPSR,LCD Write Protect Status Register"
|
|
in
|
|
endif
|
|
tree "Palette Entry Registers"
|
|
tree "0-63"
|
|
group.long 0xc00++0xff
|
|
line.long 0x0 "LUT_ENTRY_0 ,Palette Entry 0 "
|
|
line.long 0x4 "LUT_ENTRY_1 ,Palette Entry 1 "
|
|
line.long 0x8 "LUT_ENTRY_2 ,Palette Entry 2 "
|
|
line.long 0xC "LUT_ENTRY_3 ,Palette Entry 3 "
|
|
line.long 0x10 "LUT_ENTRY_4 ,Palette Entry 4 "
|
|
line.long 0x14 "LUT_ENTRY_5 ,Palette Entry 5 "
|
|
line.long 0x18 "LUT_ENTRY_6 ,Palette Entry 6 "
|
|
line.long 0x1C "LUT_ENTRY_7 ,Palette Entry 7 "
|
|
line.long 0x20 "LUT_ENTRY_8 ,Palette Entry 8 "
|
|
line.long 0x24 "LUT_ENTRY_9 ,Palette Entry 9 "
|
|
line.long 0x28 "LUT_ENTRY_10 ,Palette Entry 10 "
|
|
line.long 0x2C "LUT_ENTRY_11 ,Palette Entry 11 "
|
|
line.long 0x30 "LUT_ENTRY_12 ,Palette Entry 12 "
|
|
line.long 0x34 "LUT_ENTRY_13 ,Palette Entry 13 "
|
|
line.long 0x38 "LUT_ENTRY_14 ,Palette Entry 14 "
|
|
line.long 0x3C "LUT_ENTRY_15 ,Palette Entry 15 "
|
|
line.long 0x40 "LUT_ENTRY_16 ,Palette Entry 16 "
|
|
line.long 0x44 "LUT_ENTRY_17 ,Palette Entry 17 "
|
|
line.long 0x48 "LUT_ENTRY_18 ,Palette Entry 18 "
|
|
line.long 0x4C "LUT_ENTRY_19 ,Palette Entry 19 "
|
|
line.long 0x50 "LUT_ENTRY_20 ,Palette Entry 20 "
|
|
line.long 0x54 "LUT_ENTRY_21 ,Palette Entry 21 "
|
|
line.long 0x58 "LUT_ENTRY_22 ,Palette Entry 22 "
|
|
line.long 0x5C "LUT_ENTRY_23 ,Palette Entry 23 "
|
|
line.long 0x60 "LUT_ENTRY_24 ,Palette Entry 24 "
|
|
line.long 0x64 "LUT_ENTRY_25 ,Palette Entry 25 "
|
|
line.long 0x68 "LUT_ENTRY_26 ,Palette Entry 26 "
|
|
line.long 0x6C "LUT_ENTRY_27 ,Palette Entry 27 "
|
|
line.long 0x70 "LUT_ENTRY_28 ,Palette Entry 28 "
|
|
line.long 0x74 "LUT_ENTRY_29 ,Palette Entry 29 "
|
|
line.long 0x78 "LUT_ENTRY_30 ,Palette Entry 30 "
|
|
line.long 0x7C "LUT_ENTRY_31 ,Palette Entry 31 "
|
|
line.long 0x80 "LUT_ENTRY_32 ,Palette Entry 32 "
|
|
line.long 0x84 "LUT_ENTRY_33 ,Palette Entry 33 "
|
|
line.long 0x88 "LUT_ENTRY_34 ,Palette Entry 34 "
|
|
line.long 0x8C "LUT_ENTRY_35 ,Palette Entry 35 "
|
|
line.long 0x90 "LUT_ENTRY_36 ,Palette Entry 36 "
|
|
line.long 0x94 "LUT_ENTRY_37 ,Palette Entry 37 "
|
|
line.long 0x98 "LUT_ENTRY_38 ,Palette Entry 38 "
|
|
line.long 0x9C "LUT_ENTRY_39 ,Palette Entry 39 "
|
|
line.long 0xA0 "LUT_ENTRY_40 ,Palette Entry 40 "
|
|
line.long 0xA4 "LUT_ENTRY_41 ,Palette Entry 41 "
|
|
line.long 0xA8 "LUT_ENTRY_42 ,Palette Entry 42 "
|
|
line.long 0xAC "LUT_ENTRY_43 ,Palette Entry 43 "
|
|
line.long 0xB0 "LUT_ENTRY_44 ,Palette Entry 44 "
|
|
line.long 0xB4 "LUT_ENTRY_45 ,Palette Entry 45 "
|
|
line.long 0xB8 "LUT_ENTRY_46 ,Palette Entry 46 "
|
|
line.long 0xBC "LUT_ENTRY_47 ,Palette Entry 47 "
|
|
line.long 0xC0 "LUT_ENTRY_48 ,Palette Entry 48 "
|
|
line.long 0xC4 "LUT_ENTRY_49 ,Palette Entry 49 "
|
|
line.long 0xC8 "LUT_ENTRY_50 ,Palette Entry 50 "
|
|
line.long 0xCC "LUT_ENTRY_51 ,Palette Entry 51 "
|
|
line.long 0xD0 "LUT_ENTRY_52 ,Palette Entry 52 "
|
|
line.long 0xD4 "LUT_ENTRY_53 ,Palette Entry 53 "
|
|
line.long 0xD8 "LUT_ENTRY_54 ,Palette Entry 54 "
|
|
line.long 0xDC "LUT_ENTRY_55 ,Palette Entry 55 "
|
|
line.long 0xE0 "LUT_ENTRY_56 ,Palette Entry 56 "
|
|
line.long 0xE4 "LUT_ENTRY_57 ,Palette Entry 57 "
|
|
line.long 0xE8 "LUT_ENTRY_58 ,Palette Entry 58 "
|
|
line.long 0xEC "LUT_ENTRY_59 ,Palette Entry 59 "
|
|
line.long 0xF0 "LUT_ENTRY_60 ,Palette Entry 60 "
|
|
line.long 0xF4 "LUT_ENTRY_61 ,Palette Entry 61 "
|
|
line.long 0xF8 "LUT_ENTRY_62 ,Palette Entry 62 "
|
|
line.long 0xFC "LUT_ENTRY_63 ,Palette Entry 63 "
|
|
tree.end
|
|
tree "64-127"
|
|
group.long 0xd00++0xff
|
|
line.long 0x0 "LUT_ENTRY_64 ,Palette Entry 64 "
|
|
line.long 0x4 "LUT_ENTRY_65 ,Palette Entry 65 "
|
|
line.long 0x8 "LUT_ENTRY_66 ,Palette Entry 66 "
|
|
line.long 0xC "LUT_ENTRY_67 ,Palette Entry 67 "
|
|
line.long 0x10 "LUT_ENTRY_68 ,Palette Entry 68 "
|
|
line.long 0x14 "LUT_ENTRY_69 ,Palette Entry 69 "
|
|
line.long 0x18 "LUT_ENTRY_70 ,Palette Entry 70 "
|
|
line.long 0x1C "LUT_ENTRY_71 ,Palette Entry 71 "
|
|
line.long 0x20 "LUT_ENTRY_72 ,Palette Entry 72 "
|
|
line.long 0x24 "LUT_ENTRY_73 ,Palette Entry 73 "
|
|
line.long 0x28 "LUT_ENTRY_74 ,Palette Entry 74 "
|
|
line.long 0x2C "LUT_ENTRY_75 ,Palette Entry 75 "
|
|
line.long 0x30 "LUT_ENTRY_76 ,Palette Entry 76 "
|
|
line.long 0x34 "LUT_ENTRY_77 ,Palette Entry 77 "
|
|
line.long 0x38 "LUT_ENTRY_78 ,Palette Entry 78 "
|
|
line.long 0x3C "LUT_ENTRY_79 ,Palette Entry 79 "
|
|
line.long 0x40 "LUT_ENTRY_80 ,Palette Entry 80 "
|
|
line.long 0x44 "LUT_ENTRY_81 ,Palette Entry 81 "
|
|
line.long 0x48 "LUT_ENTRY_82 ,Palette Entry 82 "
|
|
line.long 0x4C "LUT_ENTRY_83 ,Palette Entry 83 "
|
|
line.long 0x50 "LUT_ENTRY_84 ,Palette Entry 84 "
|
|
line.long 0x54 "LUT_ENTRY_85 ,Palette Entry 85 "
|
|
line.long 0x58 "LUT_ENTRY_86 ,Palette Entry 86 "
|
|
line.long 0x5C "LUT_ENTRY_87 ,Palette Entry 87 "
|
|
line.long 0x60 "LUT_ENTRY_88 ,Palette Entry 88 "
|
|
line.long 0x64 "LUT_ENTRY_89 ,Palette Entry 89 "
|
|
line.long 0x68 "LUT_ENTRY_90 ,Palette Entry 90 "
|
|
line.long 0x6C "LUT_ENTRY_91 ,Palette Entry 91 "
|
|
line.long 0x70 "LUT_ENTRY_92 ,Palette Entry 92 "
|
|
line.long 0x74 "LUT_ENTRY_93 ,Palette Entry 93 "
|
|
line.long 0x78 "LUT_ENTRY_94 ,Palette Entry 94 "
|
|
line.long 0x7C "LUT_ENTRY_95 ,Palette Entry 95 "
|
|
line.long 0x80 "LUT_ENTRY_96 ,Palette Entry 96 "
|
|
line.long 0x84 "LUT_ENTRY_97 ,Palette Entry 97 "
|
|
line.long 0x88 "LUT_ENTRY_98 ,Palette Entry 98 "
|
|
line.long 0x8C "LUT_ENTRY_99 ,Palette Entry 99 "
|
|
line.long 0x90 "LUT_ENTRY_100,Palette Entry 100"
|
|
line.long 0x94 "LUT_ENTRY_101,Palette Entry 101"
|
|
line.long 0x98 "LUT_ENTRY_102,Palette Entry 102"
|
|
line.long 0x9C "LUT_ENTRY_103,Palette Entry 103"
|
|
line.long 0xA0 "LUT_ENTRY_104,Palette Entry 104"
|
|
line.long 0xA4 "LUT_ENTRY_105,Palette Entry 105"
|
|
line.long 0xA8 "LUT_ENTRY_106,Palette Entry 106"
|
|
line.long 0xAC "LUT_ENTRY_107,Palette Entry 107"
|
|
line.long 0xB0 "LUT_ENTRY_108,Palette Entry 108"
|
|
line.long 0xB4 "LUT_ENTRY_109,Palette Entry 109"
|
|
line.long 0xB8 "LUT_ENTRY_110,Palette Entry 110"
|
|
line.long 0xBC "LUT_ENTRY_111,Palette Entry 111"
|
|
line.long 0xC0 "LUT_ENTRY_112,Palette Entry 112"
|
|
line.long 0xC4 "LUT_ENTRY_113,Palette Entry 113"
|
|
line.long 0xC8 "LUT_ENTRY_114,Palette Entry 114"
|
|
line.long 0xCC "LUT_ENTRY_115,Palette Entry 115"
|
|
line.long 0xD0 "LUT_ENTRY_116,Palette Entry 116"
|
|
line.long 0xD4 "LUT_ENTRY_117,Palette Entry 117"
|
|
line.long 0xD8 "LUT_ENTRY_118,Palette Entry 118"
|
|
line.long 0xDC "LUT_ENTRY_119,Palette Entry 119"
|
|
line.long 0xE0 "LUT_ENTRY_120,Palette Entry 120"
|
|
line.long 0xE4 "LUT_ENTRY_121,Palette Entry 121"
|
|
line.long 0xE8 "LUT_ENTRY_122,Palette Entry 122"
|
|
line.long 0xEC "LUT_ENTRY_123,Palette Entry 123"
|
|
line.long 0xF0 "LUT_ENTRY_124,Palette Entry 124"
|
|
line.long 0xF4 "LUT_ENTRY_125,Palette Entry 125"
|
|
line.long 0xF8 "LUT_ENTRY_126,Palette Entry 126"
|
|
line.long 0xFC "LUT_ENTRY_127,Palette Entry 127"
|
|
tree.end
|
|
tree "128-191"
|
|
group.long 0xe00++0xff
|
|
line.long 0x0 "LUT_ENTRY_128,Palette Entry 128"
|
|
line.long 0x4 "LUT_ENTRY_129,Palette Entry 129"
|
|
line.long 0x8 "LUT_ENTRY_130,Palette Entry 130"
|
|
line.long 0xC "LUT_ENTRY_131,Palette Entry 131"
|
|
line.long 0x10 "LUT_ENTRY_132,Palette Entry 132"
|
|
line.long 0x14 "LUT_ENTRY_133,Palette Entry 133"
|
|
line.long 0x18 "LUT_ENTRY_134,Palette Entry 134"
|
|
line.long 0x1C "LUT_ENTRY_135,Palette Entry 135"
|
|
line.long 0x20 "LUT_ENTRY_136,Palette Entry 136"
|
|
line.long 0x24 "LUT_ENTRY_137,Palette Entry 137"
|
|
line.long 0x28 "LUT_ENTRY_138,Palette Entry 138"
|
|
line.long 0x2C "LUT_ENTRY_139,Palette Entry 139"
|
|
line.long 0x30 "LUT_ENTRY_140,Palette Entry 140"
|
|
line.long 0x34 "LUT_ENTRY_141,Palette Entry 141"
|
|
line.long 0x38 "LUT_ENTRY_142,Palette Entry 142"
|
|
line.long 0x3C "LUT_ENTRY_143,Palette Entry 143"
|
|
line.long 0x40 "LUT_ENTRY_144,Palette Entry 144"
|
|
line.long 0x44 "LUT_ENTRY_145,Palette Entry 145"
|
|
line.long 0x48 "LUT_ENTRY_146,Palette Entry 146"
|
|
line.long 0x4C "LUT_ENTRY_147,Palette Entry 147"
|
|
line.long 0x50 "LUT_ENTRY_148,Palette Entry 148"
|
|
line.long 0x54 "LUT_ENTRY_149,Palette Entry 149"
|
|
line.long 0x58 "LUT_ENTRY_150,Palette Entry 150"
|
|
line.long 0x5C "LUT_ENTRY_151,Palette Entry 151"
|
|
line.long 0x60 "LUT_ENTRY_152,Palette Entry 152"
|
|
line.long 0x64 "LUT_ENTRY_153,Palette Entry 153"
|
|
line.long 0x68 "LUT_ENTRY_154,Palette Entry 154"
|
|
line.long 0x6C "LUT_ENTRY_155,Palette Entry 155"
|
|
line.long 0x70 "LUT_ENTRY_156,Palette Entry 156"
|
|
line.long 0x74 "LUT_ENTRY_157,Palette Entry 157"
|
|
line.long 0x78 "LUT_ENTRY_158,Palette Entry 158"
|
|
line.long 0x7C "LUT_ENTRY_159,Palette Entry 159"
|
|
line.long 0x80 "LUT_ENTRY_160,Palette Entry 160"
|
|
line.long 0x84 "LUT_ENTRY_161,Palette Entry 161"
|
|
line.long 0x88 "LUT_ENTRY_162,Palette Entry 162"
|
|
line.long 0x8C "LUT_ENTRY_163,Palette Entry 163"
|
|
line.long 0x90 "LUT_ENTRY_164,Palette Entry 164"
|
|
line.long 0x94 "LUT_ENTRY_165,Palette Entry 165"
|
|
line.long 0x98 "LUT_ENTRY_166,Palette Entry 166"
|
|
line.long 0x9C "LUT_ENTRY_167,Palette Entry 167"
|
|
line.long 0xA0 "LUT_ENTRY_168,Palette Entry 168"
|
|
line.long 0xA4 "LUT_ENTRY_169,Palette Entry 169"
|
|
line.long 0xA8 "LUT_ENTRY_170,Palette Entry 170"
|
|
line.long 0xAC "LUT_ENTRY_171,Palette Entry 171"
|
|
line.long 0xB0 "LUT_ENTRY_172,Palette Entry 172"
|
|
line.long 0xB4 "LUT_ENTRY_173,Palette Entry 173"
|
|
line.long 0xB8 "LUT_ENTRY_174,Palette Entry 174"
|
|
line.long 0xBC "LUT_ENTRY_175,Palette Entry 175"
|
|
line.long 0xC0 "LUT_ENTRY_176,Palette Entry 176"
|
|
line.long 0xC4 "LUT_ENTRY_177,Palette Entry 177"
|
|
line.long 0xC8 "LUT_ENTRY_178,Palette Entry 178"
|
|
line.long 0xCC "LUT_ENTRY_179,Palette Entry 179"
|
|
line.long 0xD0 "LUT_ENTRY_180,Palette Entry 180"
|
|
line.long 0xD4 "LUT_ENTRY_181,Palette Entry 181"
|
|
line.long 0xD8 "LUT_ENTRY_182,Palette Entry 182"
|
|
line.long 0xDC "LUT_ENTRY_183,Palette Entry 183"
|
|
line.long 0xE0 "LUT_ENTRY_184,Palette Entry 184"
|
|
line.long 0xE4 "LUT_ENTRY_185,Palette Entry 185"
|
|
line.long 0xE8 "LUT_ENTRY_186,Palette Entry 186"
|
|
line.long 0xEC "LUT_ENTRY_187,Palette Entry 187"
|
|
line.long 0xF0 "LUT_ENTRY_188,Palette Entry 188"
|
|
line.long 0xF4 "LUT_ENTRY_189,Palette Entry 189"
|
|
line.long 0xF8 "LUT_ENTRY_190,Palette Entry 190"
|
|
line.long 0xFC "LUT_ENTRY_191,Palette Entry 191"
|
|
tree.end
|
|
tree "192-255"
|
|
group.long 0xf00++0xff
|
|
line.long 0x0 "LUT_ENTRY_192,Palette Entry 192"
|
|
line.long 0x4 "LUT_ENTRY_193,Palette Entry 193"
|
|
line.long 0x8 "LUT_ENTRY_194,Palette Entry 194"
|
|
line.long 0xC "LUT_ENTRY_195,Palette Entry 195"
|
|
line.long 0x10 "LUT_ENTRY_196,Palette Entry 196"
|
|
line.long 0x14 "LUT_ENTRY_197,Palette Entry 197"
|
|
line.long 0x18 "LUT_ENTRY_198,Palette Entry 198"
|
|
line.long 0x1C "LUT_ENTRY_199,Palette Entry 199"
|
|
line.long 0x20 "LUT_ENTRY_200,Palette Entry 200"
|
|
line.long 0x24 "LUT_ENTRY_201,Palette Entry 201"
|
|
line.long 0x28 "LUT_ENTRY_202,Palette Entry 202"
|
|
line.long 0x2C "LUT_ENTRY_203,Palette Entry 203"
|
|
line.long 0x30 "LUT_ENTRY_204,Palette Entry 204"
|
|
line.long 0x34 "LUT_ENTRY_205,Palette Entry 205"
|
|
line.long 0x38 "LUT_ENTRY_206,Palette Entry 206"
|
|
line.long 0x3C "LUT_ENTRY_207,Palette Entry 207"
|
|
line.long 0x40 "LUT_ENTRY_208,Palette Entry 208"
|
|
line.long 0x44 "LUT_ENTRY_209,Palette Entry 209"
|
|
line.long 0x48 "LUT_ENTRY_210,Palette Entry 210"
|
|
line.long 0x4C "LUT_ENTRY_211,Palette Entry 211"
|
|
line.long 0x50 "LUT_ENTRY_212,Palette Entry 212"
|
|
line.long 0x54 "LUT_ENTRY_213,Palette Entry 213"
|
|
line.long 0x58 "LUT_ENTRY_214,Palette Entry 214"
|
|
line.long 0x5C "LUT_ENTRY_215,Palette Entry 215"
|
|
line.long 0x60 "LUT_ENTRY_216,Palette Entry 216"
|
|
line.long 0x64 "LUT_ENTRY_217,Palette Entry 217"
|
|
line.long 0x68 "LUT_ENTRY_218,Palette Entry 218"
|
|
line.long 0x6C "LUT_ENTRY_219,Palette Entry 219"
|
|
line.long 0x70 "LUT_ENTRY_220,Palette Entry 220"
|
|
line.long 0x74 "LUT_ENTRY_221,Palette Entry 221"
|
|
line.long 0x78 "LUT_ENTRY_222,Palette Entry 222"
|
|
line.long 0x7C "LUT_ENTRY_223,Palette Entry 223"
|
|
line.long 0x80 "LUT_ENTRY_224,Palette Entry 224"
|
|
line.long 0x84 "LUT_ENTRY_225,Palette Entry 225"
|
|
line.long 0x88 "LUT_ENTRY_226,Palette Entry 226"
|
|
line.long 0x8C "LUT_ENTRY_227,Palette Entry 227"
|
|
line.long 0x90 "LUT_ENTRY_228,Palette Entry 228"
|
|
line.long 0x94 "LUT_ENTRY_229,Palette Entry 229"
|
|
line.long 0x98 "LUT_ENTRY_230,Palette Entry 230"
|
|
line.long 0x9C "LUT_ENTRY_231,Palette Entry 231"
|
|
line.long 0xA0 "LUT_ENTRY_232,Palette Entry 232"
|
|
line.long 0xA4 "LUT_ENTRY_233,Palette Entry 233"
|
|
line.long 0xA8 "LUT_ENTRY_234,Palette Entry 234"
|
|
line.long 0xAC "LUT_ENTRY_235,Palette Entry 235"
|
|
line.long 0xB0 "LUT_ENTRY_236,Palette Entry 236"
|
|
line.long 0xB4 "LUT_ENTRY_237,Palette Entry 237"
|
|
line.long 0xB8 "LUT_ENTRY_238,Palette Entry 238"
|
|
line.long 0xBC "LUT_ENTRY_239,Palette Entry 239"
|
|
line.long 0xC0 "LUT_ENTRY_240,Palette Entry 240"
|
|
line.long 0xC4 "LUT_ENTRY_241,Palette Entry 241"
|
|
line.long 0xC8 "LUT_ENTRY_242,Palette Entry 242"
|
|
line.long 0xCC "LUT_ENTRY_243,Palette Entry 243"
|
|
line.long 0xD0 "LUT_ENTRY_244,Palette Entry 244"
|
|
line.long 0xD4 "LUT_ENTRY_245,Palette Entry 245"
|
|
line.long 0xD8 "LUT_ENTRY_246,Palette Entry 246"
|
|
line.long 0xDC "LUT_ENTRY_247,Palette Entry 247"
|
|
line.long 0xE0 "LUT_ENTRY_248,Palette Entry 248"
|
|
line.long 0xE4 "LUT_ENTRY_249,Palette Entry 249"
|
|
line.long 0xE8 "LUT_ENTRY_250,Palette Entry 250"
|
|
line.long 0xEC "LUT_ENTRY_251,Palette Entry 251"
|
|
line.long 0xF0 "LUT_ENTRY_252,Palette Entry 252"
|
|
line.long 0xF4 "LUT_ENTRY_253,Palette Entry 253"
|
|
line.long 0xF8 "LUT_ENTRY_254,Palette Entry 254"
|
|
line.long 0xFC "LUT_ENTRY_255,Palette Entry 255"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
else
|
|
base ad:0x00600000
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
sif (cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
hexmask.long 0x00 2.--31. 0x4 " BADDR-U ,Base Address for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
else
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
endif
|
|
line.long 0x04 "DMABADDR2,DMA Base Address Register 2"
|
|
rgroup.long 0x08++0xf
|
|
line.long 0x00 "DMAFRMPT1,DMA Frame Pointer Register 1"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMPT-U ,Current value of frame pointer for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
line.long 0x04 "DMAFRMPT2,DMA Frame Pointer Register 2"
|
|
hexmask.long.tbyte 0x04 0.--22. 1. " FRMPT-L ,Current value of frame pointer for the Lower panel in dual scan mode"
|
|
line.long 0x8 "DMAFRMADD1,DMA Frame Address Register 1"
|
|
line.long 0xC "DMAFRMADD2,DMA Frame Address Register 2"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DMAFRMCFG,DMA Frame Configuration Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BRSTLN ,Burst Length"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMSIZE ,Frame Size"
|
|
line.long 0x4 "DMACON,DMA Control Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x4 4. " DMA2DEN ,DMA 2D Adressing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " DMAUPDT ,DMA Configuration Update" "No effect,Updated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 2. " DMABUSY ,DMA Busy" "Idle,Busy"
|
|
bitfld.long 0x4 1. " DMARST ,DMA Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x20++0x03
|
|
line.long 0x0 "DMA2DCFG,DMA 2D Adressing Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " PIXELOFF ,DAM2D Addressing Pixel Offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRINC ,DMA 2D Addressing Address increment"
|
|
endif
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "LCDCON1,LCD Control Register 1"
|
|
hexmask.long.word 0x00 21.--31. 1. " LINECNT ,Line Counter"
|
|
hexmask.long.word 0x00 12.--20. 1. " CLKVAL ,Clock Divider"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass lcd_pclk Divider" "Not bypassed,Bypassed"
|
|
if ((d.l(ad:0x00600000+0x804)&0x3)==0x2)
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,24 bpp/unpacked,?..."
|
|
else
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00600000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00600000+0x804)&0x4)==(0x4)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "Reserved,8-bit,16-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00600000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00600000+0x804)&0x4)==(0x0)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "4-bit,8-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
else
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
endif
|
|
group.long 0x808++0xf
|
|
line.long 0x0 "LCDTIM1,LCD Timing Configuration Register 1"
|
|
bitfld.long 0x0 24.--27. " VHDLY ,Vertical to horizontal delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
hexmask.long.byte 0x0 16.--21. 1. 1. " VPW ,Vertical Synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.byte 0x0 0.--7. 1. " VFP ,Vertical Front Porch"
|
|
line.long 0x4 "LCDTIM2,LCD Timing Configuration Register 2"
|
|
hexmask.long.word 0x4 21.--31. 1. 1. " HFP ,Horizontal Front Porch"
|
|
hexmask.long.byte 0x4 8.--13. 1. 1. " HPW ,Horizontal synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. 1. " HBP ,Horizontal Back Porch"
|
|
line.long 0x8 "LCDFRMCFG,LCD Frame Configuration Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
hexmask.long.word 0x8 21.--31. 1. " LINESIZE ,Horizontal size of LCD module"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x8 21.--31. 1. " HOZVAL ,Horizontal size of LCD module"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x8 0.--10. 1. " LINEVAL ,Vertical size of LCD module"
|
|
line.long 0xC "LCDFIFO,LCD FIFO Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " FIFOTH ,FIFO Threshold"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x818++0x3
|
|
line.long 0x0 "LCDMVAL,LCD_MODE Toggle Rate Value Register"
|
|
bitfld.long 0x0 31. " MMODE ,LCD_MODE toggle rate select" "Each frame,MVAL"
|
|
hexmask.long.byte 0x0 0.--7. 1. 1. " MVAL ,LCD_MODE toggle rate value"
|
|
endif
|
|
group.long 0x81c--0x847
|
|
line.long 0x00 "DP1_2,Dithering Pattern DP1_2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DP1_2 ,Pattern value for 1/2 duty cycle"
|
|
line.long 0x04 "DP4_7,Dithering Pattern DP4_7 Register"
|
|
hexmask.long 0x04 0.--27. 1. " DP4_7 ,Pattern value for 4/7 duty cycle"
|
|
line.long 0x8 "DP3_5,Dithering Pattern DP3_5 Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. " DP3_5 ,Pattern value for 3/5 duty cycle"
|
|
line.long 0xc "DP2_3,Dithering Pattern DP2_3 Register"
|
|
hexmask.long.word 0xc 0.--11. 1. " DP2_3 ,Pattern value for 2/3 duty cycle"
|
|
line.long 0x10 "DP5_7,Dithering Pattern DP5_7 Register"
|
|
hexmask.long 0x10 0.--27. 1. " DP5_7 ,Pattern value for 5/7 duty cycle"
|
|
line.long 0x14 "DP3_4,Dithering Pattern DP3_4 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DP3_4 ,Pattern value for 3/4 duty cycle"
|
|
line.long 0x18 "DP4_5,Dithering Pattern DP4_5 Register"
|
|
hexmask.long.tbyte 0x18 0.--19. 1. " DP4_5 ,Pattern value for 4/5 duty cycle"
|
|
line.long 0x1c "DP6_7,Dithering Pattern DP6_7 Register"
|
|
hexmask.long 0x1c 0.--27. 1. " DP6_7 ,Pattern value for 6/7 duty cycle"
|
|
line.long 0x20 "PWRCON,Power Control Register"
|
|
bitfld.long 0x20 31. " LCD_BUSY ,LCD Busy" "Idle,Busy"
|
|
hexmask.long.byte 0x20 1.--7. 1. " GUARD_TIME ,Guard Time"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LCD_PWR ,LCD module power control" "Low,High"
|
|
line.long 0x24 "CONTRAST_CTR,Contrast Control Register"
|
|
bitfld.long 0x24 3. " ENA ,PWM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " POL ,Output polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " PS ,Prescaler" "fLCDC_CLOCK,fLCDC_CLOCK/2,fLCDC_CLOCK/4,fLCDC_CLOCK/8"
|
|
line.long 0x28 "CONTRAST_VAL,Contrast Value Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " CVAL ,PWM compare value"
|
|
group.long 0x850++0x3
|
|
line.long 0x0 "LCD_IMR,LCD Interrupt Mask Register"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " MERIM_set/clr ,DMA Memory error Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OWRIM_set/clr ,FIFO overwrite Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " UFLWIM_set/clr ,FIFO underflow Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EOFIM_set/clr ,DMA End of frame Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " LSTLNIM_set/clr ,Last line Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " LNIM_set/clr ,Line Interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x3
|
|
line.long 0x0 "LCD_ISR,LCD Interrupt Status Register"
|
|
bitfld.long 0x0 6. " MERIS ,DMA Memory error Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 5. " OWRIS ,FIFO overwrite Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UFLWIS ,FIFO underflow Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 2. " EOFIS ,DMA End of frame Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LSTLNIS ,Last line Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 0. " LNIS ,Line Interrupt status" "Not active,Active"
|
|
wgroup.long 0x858++0x3
|
|
line.long 0x00 "LCD_ICR,LCD Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " MERIC ,DMA Memory error Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " OWRIC ,FIFO overwrite Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIC ,FIFO underflow Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " EOFIC ,DMA End of frame Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIC ,Last line Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " LNIC ,Line Interrupt clear" "No effect,Clear"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x860++03
|
|
line.long 0x00 "LCD_ITR,LCD Interrupt Test Register"
|
|
bitfld.long 0x00 6. " MERIT ,DMA Memory error interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 5. " OWRIT ,FIFO overwrite interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIT ,FIFO underflow interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 2. " EOFIT ,DMA End of frame interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIT ,Last line interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 0. " LNIT ,Line interrupt test" "No effect,Set"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
else
|
|
rgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "LCD_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "LCD_WPSR,LCD Write Protect Status Register"
|
|
in
|
|
endif
|
|
tree "Palette Entry Registers"
|
|
tree "0-63"
|
|
group.long 0xc00++0xff
|
|
line.long 0x0 "LUT_ENTRY_0 ,Palette Entry 0 "
|
|
line.long 0x4 "LUT_ENTRY_1 ,Palette Entry 1 "
|
|
line.long 0x8 "LUT_ENTRY_2 ,Palette Entry 2 "
|
|
line.long 0xC "LUT_ENTRY_3 ,Palette Entry 3 "
|
|
line.long 0x10 "LUT_ENTRY_4 ,Palette Entry 4 "
|
|
line.long 0x14 "LUT_ENTRY_5 ,Palette Entry 5 "
|
|
line.long 0x18 "LUT_ENTRY_6 ,Palette Entry 6 "
|
|
line.long 0x1C "LUT_ENTRY_7 ,Palette Entry 7 "
|
|
line.long 0x20 "LUT_ENTRY_8 ,Palette Entry 8 "
|
|
line.long 0x24 "LUT_ENTRY_9 ,Palette Entry 9 "
|
|
line.long 0x28 "LUT_ENTRY_10 ,Palette Entry 10 "
|
|
line.long 0x2C "LUT_ENTRY_11 ,Palette Entry 11 "
|
|
line.long 0x30 "LUT_ENTRY_12 ,Palette Entry 12 "
|
|
line.long 0x34 "LUT_ENTRY_13 ,Palette Entry 13 "
|
|
line.long 0x38 "LUT_ENTRY_14 ,Palette Entry 14 "
|
|
line.long 0x3C "LUT_ENTRY_15 ,Palette Entry 15 "
|
|
line.long 0x40 "LUT_ENTRY_16 ,Palette Entry 16 "
|
|
line.long 0x44 "LUT_ENTRY_17 ,Palette Entry 17 "
|
|
line.long 0x48 "LUT_ENTRY_18 ,Palette Entry 18 "
|
|
line.long 0x4C "LUT_ENTRY_19 ,Palette Entry 19 "
|
|
line.long 0x50 "LUT_ENTRY_20 ,Palette Entry 20 "
|
|
line.long 0x54 "LUT_ENTRY_21 ,Palette Entry 21 "
|
|
line.long 0x58 "LUT_ENTRY_22 ,Palette Entry 22 "
|
|
line.long 0x5C "LUT_ENTRY_23 ,Palette Entry 23 "
|
|
line.long 0x60 "LUT_ENTRY_24 ,Palette Entry 24 "
|
|
line.long 0x64 "LUT_ENTRY_25 ,Palette Entry 25 "
|
|
line.long 0x68 "LUT_ENTRY_26 ,Palette Entry 26 "
|
|
line.long 0x6C "LUT_ENTRY_27 ,Palette Entry 27 "
|
|
line.long 0x70 "LUT_ENTRY_28 ,Palette Entry 28 "
|
|
line.long 0x74 "LUT_ENTRY_29 ,Palette Entry 29 "
|
|
line.long 0x78 "LUT_ENTRY_30 ,Palette Entry 30 "
|
|
line.long 0x7C "LUT_ENTRY_31 ,Palette Entry 31 "
|
|
line.long 0x80 "LUT_ENTRY_32 ,Palette Entry 32 "
|
|
line.long 0x84 "LUT_ENTRY_33 ,Palette Entry 33 "
|
|
line.long 0x88 "LUT_ENTRY_34 ,Palette Entry 34 "
|
|
line.long 0x8C "LUT_ENTRY_35 ,Palette Entry 35 "
|
|
line.long 0x90 "LUT_ENTRY_36 ,Palette Entry 36 "
|
|
line.long 0x94 "LUT_ENTRY_37 ,Palette Entry 37 "
|
|
line.long 0x98 "LUT_ENTRY_38 ,Palette Entry 38 "
|
|
line.long 0x9C "LUT_ENTRY_39 ,Palette Entry 39 "
|
|
line.long 0xA0 "LUT_ENTRY_40 ,Palette Entry 40 "
|
|
line.long 0xA4 "LUT_ENTRY_41 ,Palette Entry 41 "
|
|
line.long 0xA8 "LUT_ENTRY_42 ,Palette Entry 42 "
|
|
line.long 0xAC "LUT_ENTRY_43 ,Palette Entry 43 "
|
|
line.long 0xB0 "LUT_ENTRY_44 ,Palette Entry 44 "
|
|
line.long 0xB4 "LUT_ENTRY_45 ,Palette Entry 45 "
|
|
line.long 0xB8 "LUT_ENTRY_46 ,Palette Entry 46 "
|
|
line.long 0xBC "LUT_ENTRY_47 ,Palette Entry 47 "
|
|
line.long 0xC0 "LUT_ENTRY_48 ,Palette Entry 48 "
|
|
line.long 0xC4 "LUT_ENTRY_49 ,Palette Entry 49 "
|
|
line.long 0xC8 "LUT_ENTRY_50 ,Palette Entry 50 "
|
|
line.long 0xCC "LUT_ENTRY_51 ,Palette Entry 51 "
|
|
line.long 0xD0 "LUT_ENTRY_52 ,Palette Entry 52 "
|
|
line.long 0xD4 "LUT_ENTRY_53 ,Palette Entry 53 "
|
|
line.long 0xD8 "LUT_ENTRY_54 ,Palette Entry 54 "
|
|
line.long 0xDC "LUT_ENTRY_55 ,Palette Entry 55 "
|
|
line.long 0xE0 "LUT_ENTRY_56 ,Palette Entry 56 "
|
|
line.long 0xE4 "LUT_ENTRY_57 ,Palette Entry 57 "
|
|
line.long 0xE8 "LUT_ENTRY_58 ,Palette Entry 58 "
|
|
line.long 0xEC "LUT_ENTRY_59 ,Palette Entry 59 "
|
|
line.long 0xF0 "LUT_ENTRY_60 ,Palette Entry 60 "
|
|
line.long 0xF4 "LUT_ENTRY_61 ,Palette Entry 61 "
|
|
line.long 0xF8 "LUT_ENTRY_62 ,Palette Entry 62 "
|
|
line.long 0xFC "LUT_ENTRY_63 ,Palette Entry 63 "
|
|
tree.end
|
|
tree "64-127"
|
|
group.long 0xd00++0xff
|
|
line.long 0x0 "LUT_ENTRY_64 ,Palette Entry 64 "
|
|
line.long 0x4 "LUT_ENTRY_65 ,Palette Entry 65 "
|
|
line.long 0x8 "LUT_ENTRY_66 ,Palette Entry 66 "
|
|
line.long 0xC "LUT_ENTRY_67 ,Palette Entry 67 "
|
|
line.long 0x10 "LUT_ENTRY_68 ,Palette Entry 68 "
|
|
line.long 0x14 "LUT_ENTRY_69 ,Palette Entry 69 "
|
|
line.long 0x18 "LUT_ENTRY_70 ,Palette Entry 70 "
|
|
line.long 0x1C "LUT_ENTRY_71 ,Palette Entry 71 "
|
|
line.long 0x20 "LUT_ENTRY_72 ,Palette Entry 72 "
|
|
line.long 0x24 "LUT_ENTRY_73 ,Palette Entry 73 "
|
|
line.long 0x28 "LUT_ENTRY_74 ,Palette Entry 74 "
|
|
line.long 0x2C "LUT_ENTRY_75 ,Palette Entry 75 "
|
|
line.long 0x30 "LUT_ENTRY_76 ,Palette Entry 76 "
|
|
line.long 0x34 "LUT_ENTRY_77 ,Palette Entry 77 "
|
|
line.long 0x38 "LUT_ENTRY_78 ,Palette Entry 78 "
|
|
line.long 0x3C "LUT_ENTRY_79 ,Palette Entry 79 "
|
|
line.long 0x40 "LUT_ENTRY_80 ,Palette Entry 80 "
|
|
line.long 0x44 "LUT_ENTRY_81 ,Palette Entry 81 "
|
|
line.long 0x48 "LUT_ENTRY_82 ,Palette Entry 82 "
|
|
line.long 0x4C "LUT_ENTRY_83 ,Palette Entry 83 "
|
|
line.long 0x50 "LUT_ENTRY_84 ,Palette Entry 84 "
|
|
line.long 0x54 "LUT_ENTRY_85 ,Palette Entry 85 "
|
|
line.long 0x58 "LUT_ENTRY_86 ,Palette Entry 86 "
|
|
line.long 0x5C "LUT_ENTRY_87 ,Palette Entry 87 "
|
|
line.long 0x60 "LUT_ENTRY_88 ,Palette Entry 88 "
|
|
line.long 0x64 "LUT_ENTRY_89 ,Palette Entry 89 "
|
|
line.long 0x68 "LUT_ENTRY_90 ,Palette Entry 90 "
|
|
line.long 0x6C "LUT_ENTRY_91 ,Palette Entry 91 "
|
|
line.long 0x70 "LUT_ENTRY_92 ,Palette Entry 92 "
|
|
line.long 0x74 "LUT_ENTRY_93 ,Palette Entry 93 "
|
|
line.long 0x78 "LUT_ENTRY_94 ,Palette Entry 94 "
|
|
line.long 0x7C "LUT_ENTRY_95 ,Palette Entry 95 "
|
|
line.long 0x80 "LUT_ENTRY_96 ,Palette Entry 96 "
|
|
line.long 0x84 "LUT_ENTRY_97 ,Palette Entry 97 "
|
|
line.long 0x88 "LUT_ENTRY_98 ,Palette Entry 98 "
|
|
line.long 0x8C "LUT_ENTRY_99 ,Palette Entry 99 "
|
|
line.long 0x90 "LUT_ENTRY_100,Palette Entry 100"
|
|
line.long 0x94 "LUT_ENTRY_101,Palette Entry 101"
|
|
line.long 0x98 "LUT_ENTRY_102,Palette Entry 102"
|
|
line.long 0x9C "LUT_ENTRY_103,Palette Entry 103"
|
|
line.long 0xA0 "LUT_ENTRY_104,Palette Entry 104"
|
|
line.long 0xA4 "LUT_ENTRY_105,Palette Entry 105"
|
|
line.long 0xA8 "LUT_ENTRY_106,Palette Entry 106"
|
|
line.long 0xAC "LUT_ENTRY_107,Palette Entry 107"
|
|
line.long 0xB0 "LUT_ENTRY_108,Palette Entry 108"
|
|
line.long 0xB4 "LUT_ENTRY_109,Palette Entry 109"
|
|
line.long 0xB8 "LUT_ENTRY_110,Palette Entry 110"
|
|
line.long 0xBC "LUT_ENTRY_111,Palette Entry 111"
|
|
line.long 0xC0 "LUT_ENTRY_112,Palette Entry 112"
|
|
line.long 0xC4 "LUT_ENTRY_113,Palette Entry 113"
|
|
line.long 0xC8 "LUT_ENTRY_114,Palette Entry 114"
|
|
line.long 0xCC "LUT_ENTRY_115,Palette Entry 115"
|
|
line.long 0xD0 "LUT_ENTRY_116,Palette Entry 116"
|
|
line.long 0xD4 "LUT_ENTRY_117,Palette Entry 117"
|
|
line.long 0xD8 "LUT_ENTRY_118,Palette Entry 118"
|
|
line.long 0xDC "LUT_ENTRY_119,Palette Entry 119"
|
|
line.long 0xE0 "LUT_ENTRY_120,Palette Entry 120"
|
|
line.long 0xE4 "LUT_ENTRY_121,Palette Entry 121"
|
|
line.long 0xE8 "LUT_ENTRY_122,Palette Entry 122"
|
|
line.long 0xEC "LUT_ENTRY_123,Palette Entry 123"
|
|
line.long 0xF0 "LUT_ENTRY_124,Palette Entry 124"
|
|
line.long 0xF4 "LUT_ENTRY_125,Palette Entry 125"
|
|
line.long 0xF8 "LUT_ENTRY_126,Palette Entry 126"
|
|
line.long 0xFC "LUT_ENTRY_127,Palette Entry 127"
|
|
tree.end
|
|
tree "128-191"
|
|
group.long 0xe00++0xff
|
|
line.long 0x0 "LUT_ENTRY_128,Palette Entry 128"
|
|
line.long 0x4 "LUT_ENTRY_129,Palette Entry 129"
|
|
line.long 0x8 "LUT_ENTRY_130,Palette Entry 130"
|
|
line.long 0xC "LUT_ENTRY_131,Palette Entry 131"
|
|
line.long 0x10 "LUT_ENTRY_132,Palette Entry 132"
|
|
line.long 0x14 "LUT_ENTRY_133,Palette Entry 133"
|
|
line.long 0x18 "LUT_ENTRY_134,Palette Entry 134"
|
|
line.long 0x1C "LUT_ENTRY_135,Palette Entry 135"
|
|
line.long 0x20 "LUT_ENTRY_136,Palette Entry 136"
|
|
line.long 0x24 "LUT_ENTRY_137,Palette Entry 137"
|
|
line.long 0x28 "LUT_ENTRY_138,Palette Entry 138"
|
|
line.long 0x2C "LUT_ENTRY_139,Palette Entry 139"
|
|
line.long 0x30 "LUT_ENTRY_140,Palette Entry 140"
|
|
line.long 0x34 "LUT_ENTRY_141,Palette Entry 141"
|
|
line.long 0x38 "LUT_ENTRY_142,Palette Entry 142"
|
|
line.long 0x3C "LUT_ENTRY_143,Palette Entry 143"
|
|
line.long 0x40 "LUT_ENTRY_144,Palette Entry 144"
|
|
line.long 0x44 "LUT_ENTRY_145,Palette Entry 145"
|
|
line.long 0x48 "LUT_ENTRY_146,Palette Entry 146"
|
|
line.long 0x4C "LUT_ENTRY_147,Palette Entry 147"
|
|
line.long 0x50 "LUT_ENTRY_148,Palette Entry 148"
|
|
line.long 0x54 "LUT_ENTRY_149,Palette Entry 149"
|
|
line.long 0x58 "LUT_ENTRY_150,Palette Entry 150"
|
|
line.long 0x5C "LUT_ENTRY_151,Palette Entry 151"
|
|
line.long 0x60 "LUT_ENTRY_152,Palette Entry 152"
|
|
line.long 0x64 "LUT_ENTRY_153,Palette Entry 153"
|
|
line.long 0x68 "LUT_ENTRY_154,Palette Entry 154"
|
|
line.long 0x6C "LUT_ENTRY_155,Palette Entry 155"
|
|
line.long 0x70 "LUT_ENTRY_156,Palette Entry 156"
|
|
line.long 0x74 "LUT_ENTRY_157,Palette Entry 157"
|
|
line.long 0x78 "LUT_ENTRY_158,Palette Entry 158"
|
|
line.long 0x7C "LUT_ENTRY_159,Palette Entry 159"
|
|
line.long 0x80 "LUT_ENTRY_160,Palette Entry 160"
|
|
line.long 0x84 "LUT_ENTRY_161,Palette Entry 161"
|
|
line.long 0x88 "LUT_ENTRY_162,Palette Entry 162"
|
|
line.long 0x8C "LUT_ENTRY_163,Palette Entry 163"
|
|
line.long 0x90 "LUT_ENTRY_164,Palette Entry 164"
|
|
line.long 0x94 "LUT_ENTRY_165,Palette Entry 165"
|
|
line.long 0x98 "LUT_ENTRY_166,Palette Entry 166"
|
|
line.long 0x9C "LUT_ENTRY_167,Palette Entry 167"
|
|
line.long 0xA0 "LUT_ENTRY_168,Palette Entry 168"
|
|
line.long 0xA4 "LUT_ENTRY_169,Palette Entry 169"
|
|
line.long 0xA8 "LUT_ENTRY_170,Palette Entry 170"
|
|
line.long 0xAC "LUT_ENTRY_171,Palette Entry 171"
|
|
line.long 0xB0 "LUT_ENTRY_172,Palette Entry 172"
|
|
line.long 0xB4 "LUT_ENTRY_173,Palette Entry 173"
|
|
line.long 0xB8 "LUT_ENTRY_174,Palette Entry 174"
|
|
line.long 0xBC "LUT_ENTRY_175,Palette Entry 175"
|
|
line.long 0xC0 "LUT_ENTRY_176,Palette Entry 176"
|
|
line.long 0xC4 "LUT_ENTRY_177,Palette Entry 177"
|
|
line.long 0xC8 "LUT_ENTRY_178,Palette Entry 178"
|
|
line.long 0xCC "LUT_ENTRY_179,Palette Entry 179"
|
|
line.long 0xD0 "LUT_ENTRY_180,Palette Entry 180"
|
|
line.long 0xD4 "LUT_ENTRY_181,Palette Entry 181"
|
|
line.long 0xD8 "LUT_ENTRY_182,Palette Entry 182"
|
|
line.long 0xDC "LUT_ENTRY_183,Palette Entry 183"
|
|
line.long 0xE0 "LUT_ENTRY_184,Palette Entry 184"
|
|
line.long 0xE4 "LUT_ENTRY_185,Palette Entry 185"
|
|
line.long 0xE8 "LUT_ENTRY_186,Palette Entry 186"
|
|
line.long 0xEC "LUT_ENTRY_187,Palette Entry 187"
|
|
line.long 0xF0 "LUT_ENTRY_188,Palette Entry 188"
|
|
line.long 0xF4 "LUT_ENTRY_189,Palette Entry 189"
|
|
line.long 0xF8 "LUT_ENTRY_190,Palette Entry 190"
|
|
line.long 0xFC "LUT_ENTRY_191,Palette Entry 191"
|
|
tree.end
|
|
tree "192-255"
|
|
group.long 0xf00++0xff
|
|
line.long 0x0 "LUT_ENTRY_192,Palette Entry 192"
|
|
line.long 0x4 "LUT_ENTRY_193,Palette Entry 193"
|
|
line.long 0x8 "LUT_ENTRY_194,Palette Entry 194"
|
|
line.long 0xC "LUT_ENTRY_195,Palette Entry 195"
|
|
line.long 0x10 "LUT_ENTRY_196,Palette Entry 196"
|
|
line.long 0x14 "LUT_ENTRY_197,Palette Entry 197"
|
|
line.long 0x18 "LUT_ENTRY_198,Palette Entry 198"
|
|
line.long 0x1C "LUT_ENTRY_199,Palette Entry 199"
|
|
line.long 0x20 "LUT_ENTRY_200,Palette Entry 200"
|
|
line.long 0x24 "LUT_ENTRY_201,Palette Entry 201"
|
|
line.long 0x28 "LUT_ENTRY_202,Palette Entry 202"
|
|
line.long 0x2C "LUT_ENTRY_203,Palette Entry 203"
|
|
line.long 0x30 "LUT_ENTRY_204,Palette Entry 204"
|
|
line.long 0x34 "LUT_ENTRY_205,Palette Entry 205"
|
|
line.long 0x38 "LUT_ENTRY_206,Palette Entry 206"
|
|
line.long 0x3C "LUT_ENTRY_207,Palette Entry 207"
|
|
line.long 0x40 "LUT_ENTRY_208,Palette Entry 208"
|
|
line.long 0x44 "LUT_ENTRY_209,Palette Entry 209"
|
|
line.long 0x48 "LUT_ENTRY_210,Palette Entry 210"
|
|
line.long 0x4C "LUT_ENTRY_211,Palette Entry 211"
|
|
line.long 0x50 "LUT_ENTRY_212,Palette Entry 212"
|
|
line.long 0x54 "LUT_ENTRY_213,Palette Entry 213"
|
|
line.long 0x58 "LUT_ENTRY_214,Palette Entry 214"
|
|
line.long 0x5C "LUT_ENTRY_215,Palette Entry 215"
|
|
line.long 0x60 "LUT_ENTRY_216,Palette Entry 216"
|
|
line.long 0x64 "LUT_ENTRY_217,Palette Entry 217"
|
|
line.long 0x68 "LUT_ENTRY_218,Palette Entry 218"
|
|
line.long 0x6C "LUT_ENTRY_219,Palette Entry 219"
|
|
line.long 0x70 "LUT_ENTRY_220,Palette Entry 220"
|
|
line.long 0x74 "LUT_ENTRY_221,Palette Entry 221"
|
|
line.long 0x78 "LUT_ENTRY_222,Palette Entry 222"
|
|
line.long 0x7C "LUT_ENTRY_223,Palette Entry 223"
|
|
line.long 0x80 "LUT_ENTRY_224,Palette Entry 224"
|
|
line.long 0x84 "LUT_ENTRY_225,Palette Entry 225"
|
|
line.long 0x88 "LUT_ENTRY_226,Palette Entry 226"
|
|
line.long 0x8C "LUT_ENTRY_227,Palette Entry 227"
|
|
line.long 0x90 "LUT_ENTRY_228,Palette Entry 228"
|
|
line.long 0x94 "LUT_ENTRY_229,Palette Entry 229"
|
|
line.long 0x98 "LUT_ENTRY_230,Palette Entry 230"
|
|
line.long 0x9C "LUT_ENTRY_231,Palette Entry 231"
|
|
line.long 0xA0 "LUT_ENTRY_232,Palette Entry 232"
|
|
line.long 0xA4 "LUT_ENTRY_233,Palette Entry 233"
|
|
line.long 0xA8 "LUT_ENTRY_234,Palette Entry 234"
|
|
line.long 0xAC "LUT_ENTRY_235,Palette Entry 235"
|
|
line.long 0xB0 "LUT_ENTRY_236,Palette Entry 236"
|
|
line.long 0xB4 "LUT_ENTRY_237,Palette Entry 237"
|
|
line.long 0xB8 "LUT_ENTRY_238,Palette Entry 238"
|
|
line.long 0xBC "LUT_ENTRY_239,Palette Entry 239"
|
|
line.long 0xC0 "LUT_ENTRY_240,Palette Entry 240"
|
|
line.long 0xC4 "LUT_ENTRY_241,Palette Entry 241"
|
|
line.long 0xC8 "LUT_ENTRY_242,Palette Entry 242"
|
|
line.long 0xCC "LUT_ENTRY_243,Palette Entry 243"
|
|
line.long 0xD0 "LUT_ENTRY_244,Palette Entry 244"
|
|
line.long 0xD4 "LUT_ENTRY_245,Palette Entry 245"
|
|
line.long 0xD8 "LUT_ENTRY_246,Palette Entry 246"
|
|
line.long 0xDC "LUT_ENTRY_247,Palette Entry 247"
|
|
line.long 0xE0 "LUT_ENTRY_248,Palette Entry 248"
|
|
line.long 0xE4 "LUT_ENTRY_249,Palette Entry 249"
|
|
line.long 0xE8 "LUT_ENTRY_250,Palette Entry 250"
|
|
line.long 0xEC "LUT_ENTRY_251,Palette Entry 251"
|
|
line.long 0xF0 "LUT_ENTRY_252,Palette Entry 252"
|
|
line.long 0xF4 "LUT_ENTRY_253,Palette Entry 253"
|
|
line.long 0xF8 "LUT_ENTRY_254,Palette Entry 254"
|
|
line.long 0xFC "LUT_ENTRY_255,Palette Entry 255"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "2DGC (2D Graphic Controller)"
|
|
base ad:0xfffc8000
|
|
width 0xd
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "2DGC_BTSXR,Block Transfer Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " XSIZE ,Size X of a bit block transfer in pixel units"
|
|
group.long 0x04++3
|
|
line.long 0x00 "2DGC_BTSYR,Block Transfer Size Y Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " YSIZE ,Size Y of a bit block transfer in pixel units"
|
|
group.long 0x08++3
|
|
line.long 0x00 "2DGC_SBXR,Source/Begin X Register"
|
|
group.long 0x0c++3
|
|
line.long 0x00 "2DGC_SBYR,Source/Begin Y Register"
|
|
group.long 0x10++3
|
|
line.long 0x00 "2DGC_TEXR,Target/End X Register"
|
|
group.long 0x14++3
|
|
line.long 0x00 "2DGC_TEYR,Target/End Y Register"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "2DGC_LWR,Line Width Register"
|
|
hexmask.long.byte 0x00 0.--3. 1. " LWD ,Line Width Register"
|
|
line.long 0x04 "2DGC_LPR,Line Pattern Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LPT ,Line Pattern"
|
|
if ((d.l(ad:0xfffc8070))&0x7)==0x0
|
|
group.long 0x20++3
|
|
line.long 0x0 "2DGC_CSR,Color Select Register"
|
|
bitfld.long 0x00 3. " CLR ,Color" "White,Black"
|
|
elif ((d.l(ad:0xfffc8070))&0x7)==0x1
|
|
group.long 0x20++3
|
|
line.long 0x0 "2DGC_CSR,Color Select Register"
|
|
bitfld.long 0x00 2.--3. " CLR ,Color" "White,Light grey,Dark grey,Black"
|
|
elif ((d.l(ad:0xfffc8070))&0x7)==0x2
|
|
group.long 0x20++3
|
|
line.long 0x0 "2DGC_CSR,Color Select Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CLR ,Color"
|
|
elif ((d.l(ad:0xfffc8070))&0x7)==0x3
|
|
group.long 0x20++3
|
|
line.long 0x0 "2DGC_CSR,Color Select Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLR ,Color"
|
|
elif ((d.l(ad:0xfffc8070))&0x7)==0x4
|
|
group.long 0x20++3
|
|
line.long 0x0 "2DGC_CSR,Color Select Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CLR ,Color"
|
|
elif ((d.l(ad:0xfffc8070))&0x7)==0x5
|
|
group.long 0x20++3
|
|
line.long 0x0 "2DGC_CSR,Color Select Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CLR ,Color"
|
|
else
|
|
hgroup.long 0x20++3
|
|
hide.long 0x0 "2DGC_CSR,Color Select Register"
|
|
endif
|
|
group.long 0x24--0x5b
|
|
line.long 0x0 "2DGC_LOR,Logic Operation Register"
|
|
bitfld.long 0x0 0.--3. " LOC ,Logic Operation Register" "MOV,OR,AND,XOR,NOT,NOR,NAND,XNOR,?..."
|
|
line.long 0x4 "2DGC_GOR,Graphics Operation Register"
|
|
bitfld.long 0x4 4.--7. " GOC ,Graphic Operation Code" "No Operation,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Block Transfer,Reserved,Line Drawing,Reserved,Polygon Fill"
|
|
bitfld.long 0x4 3. " OP3 ,Option 3" "No Transformation,Transformation"
|
|
textline " "
|
|
bitfld.long 0x4 2. " OP2 ,Option 2" "Relative,Absolute"
|
|
bitfld.long 0x4 1. " OP1 ,Option 1" "No update XY,Update XY"
|
|
textline " "
|
|
bitfld.long 0x4 0. " OP0 ,Option 0" "2D Pattern/No update Y,1D Pattern/Update Y"
|
|
line.long 0x8 "2DGC_EBXR,Extended Begin X Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " EXT_BX ,Extended Begin X Register"
|
|
line.long 0xc "2DGC_EBYR,Extended Begin Y Register"
|
|
hexmask.long.word 0xc 0.--15. 1. " EXT_BY ,Extended Begin Y Register"
|
|
line.long 0x10 "2DGC_EEXR,Extended End X Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " EXT_EX ,Extended End X Register"
|
|
line.long 0x14 "2DGC_EEYR,Extended End Y Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " EXT_EY ,Extended End Y Register"
|
|
line.long 0x18 "2DGC_ECSR,Extended Color Select Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " EXT_CSR ,Extended Color Select Register"
|
|
line.long 0x1c "2DGC_CCR,Clip Control Register"
|
|
bitfld.long 0x1c 0. " CEN ,Clipping Enable" "Disabled,Enabled"
|
|
line.long 0x20 "2DGC_CXMINR,Clip Rectangle X Minimum Register"
|
|
hexmask.long.word 0x20 0.--10. 1. " CXMIN ,Minimum x-coordinate boundary of the clip rectangle"
|
|
line.long 0x24 "2DGC_CXMAXR,Clip Rectangle X Maximum Register"
|
|
hexmask.long.word 0x24 0.--10. 1. " CXMAX ,Maximum x-coordinate boundary of the clip rectangle"
|
|
line.long 0x28 "2DGC_CYMINR,Clip Rectangle Y Minimum Register"
|
|
hexmask.long.word 0x28 0.--10. 1. " CYMIN ,Minimum y-coordinate boundary of the clip rectangle"
|
|
line.long 0x2c "2DGC_CYMAXR,Clip Rectangle Y Maximum Register"
|
|
hexmask.long.word 0x2c 0.--10. 1. " CYMAX ,Maximum y-coordinate boundary of the clip rectangle"
|
|
line.long 0x30 "2DGC_GSR,Graphics Status Register"
|
|
bitfld.long 0x30 1. " BTB ,Block transfer engine busy" "Available,Busy"
|
|
bitfld.long 0x30 0. " LTB ,Line drawing engine busy" "Available,Busy"
|
|
line.long 0x34 "2DGC_VSR,VRAM Size Register"
|
|
bitfld.long 0x34 0.--3. " VSIZE ,VRAM Size" "512/8-bit,1024/8-bit,2048/8-bit,256/8-bit,512/16-bit,1024/16-bit,2048/16-bit,256/16-bit,512/32-bit,1024/32-bit,2048/32-bit,256/32-bit,?..."
|
|
group.long 0x60++0xb
|
|
line.long 0x00 "2DGC_FCR,Fill Control Register"
|
|
hexmask.long.byte 0x00 1.--6. 1. " VCNT ,Fill Value Counter"
|
|
bitfld.long 0x00 0. " FD ,Indicates polygon fill done" "Not done,Done"
|
|
line.long 0x04 "2DGC_GIR,Graphics Interrupt Register"
|
|
eventfld.long 0x04 0. " BUFE ,Command queue buffer empty interrupt" "Not empty,Empty"
|
|
line.long 0x08 "2DGC_GIMR,Graphics Interrupt Mask Register"
|
|
bitfld.long 0x08 0. " BUFE ,Command queue buffer empty interrupt enable" "Disabled,Enabled"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "2DGC_BPPR,Bits Per Pixel Register"
|
|
bitfld.long 0x00 0.--2. " BPP ,Bits per pixel" "1 BPP,2 BPP,4 BPP,8 BPP,16 BPP,24 BPP,?..."
|
|
rgroup.long 0x74++0x7
|
|
line.long 0x0 "2DGC_CQCR,Command Queue Count Register"
|
|
hexmask.long.byte 0x0 6.--11. 1. " BUFW_CNTR ,Number of half words written to the FIFO by CPU"
|
|
hexmask.long.byte 0x0 0.--5. 1. " BUFR_CNTR ,Number of half words read from the FIFO by internal logic"
|
|
line.long 0x04 "2DGC_CQSR,Command Queue Status Register"
|
|
bitfld.long 0x04 0. " BE ,Buffer Empty" "Not empty,Empty"
|
|
wgroup.long 0x7c++0x3
|
|
line.long 0x0 "2DGC_CQR,Command Queue Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " Q_DATA ,Data stored in the queue"
|
|
width 0xc
|
|
tree "Vertex X Registers"
|
|
group.long 0x90--0xcf
|
|
line.long 0x0 "2DGC_VXR0 ,Vertex X Registers"
|
|
hexmask.long.word 0x0 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x4 "2DGC_VXR1 ,Vertex X Registers"
|
|
hexmask.long.word 0x4 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x8 "2DGC_VXR2 ,Vertex X Registers"
|
|
hexmask.long.word 0x8 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0xC "2DGC_VXR3 ,Vertex X Registers"
|
|
hexmask.long.word 0xC 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x10 "2DGC_VXR4 ,Vertex X Registers"
|
|
hexmask.long.word 0x10 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x14 "2DGC_VXR5 ,Vertex X Registers"
|
|
hexmask.long.word 0x14 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x18 "2DGC_VXR6 ,Vertex X Registers"
|
|
hexmask.long.word 0x18 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x1C "2DGC_VXR7 ,Vertex X Registers"
|
|
hexmask.long.word 0x1C 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x20 "2DGC_VXR8 ,Vertex X Registers"
|
|
hexmask.long.word 0x20 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x24 "2DGC_VXR9 ,Vertex X Registers"
|
|
hexmask.long.word 0x24 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x28 "2DGC_VXR10,Vertex X Registers"
|
|
hexmask.long.word 0x28 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x2C "2DGC_VXR11,Vertex X Registers"
|
|
hexmask.long.word 0x2C 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x30 "2DGC_VXR12,Vertex X Registers"
|
|
hexmask.long.word 0x30 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x34 "2DGC_VXR13,Vertex X Registers"
|
|
hexmask.long.word 0x34 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x38 "2DGC_VXR14,Vertex X Registers"
|
|
hexmask.long.word 0x38 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
line.long 0x3C "2DGC_VXR15,Vertex X Registers"
|
|
hexmask.long.word 0x3C 0.--10. 1. " FVX ,Adjacent X vertices for polygon fill"
|
|
tree.end
|
|
tree "Vertex Y Registers"
|
|
group.long 0x120--0x15f
|
|
line.long 0x0 "2DGC_VYR0 ,Vertex Y Registers"
|
|
hexmask.long.word 0x0 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x4 "2DGC_VYR1 ,Vertex Y Registers"
|
|
hexmask.long.word 0x4 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x8 "2DGC_VYR2 ,Vertex Y Registers"
|
|
hexmask.long.word 0x8 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0xC "2DGC_VYR3 ,Vertex Y Registers"
|
|
hexmask.long.word 0xC 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x10 "2DGC_VYR4 ,Vertex Y Registers"
|
|
hexmask.long.word 0x10 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x14 "2DGC_VYR5 ,Vertex Y Registers"
|
|
hexmask.long.word 0x14 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x18 "2DGC_VYR6 ,Vertex Y Registers"
|
|
hexmask.long.word 0x18 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x1C "2DGC_VYR7 ,Vertex Y Registers"
|
|
hexmask.long.word 0x1C 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x20 "2DGC_VYR8 ,Vertex Y Registers"
|
|
hexmask.long.word 0x20 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x24 "2DGC_VYR9 ,Vertex Y Registers"
|
|
hexmask.long.word 0x24 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x28 "2DGC_VYR10,Vertex Y Registers"
|
|
hexmask.long.word 0x28 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x2C "2DGC_VYR11,Vertex Y Registers"
|
|
hexmask.long.word 0x2C 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x30 "2DGC_VYR12,Vertex Y Registers"
|
|
hexmask.long.word 0x30 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x34 "2DGC_VYR13,Vertex Y Registers"
|
|
hexmask.long.word 0x34 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x38 "2DGC_VYR14,Vertex Y Registers"
|
|
hexmask.long.word 0x38 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
line.long 0x3C "2DGC_VYR15,Vertex Y Registers"
|
|
hexmask.long.word 0x3C 0.--10. 1. " FVY ,Adjacent Y vertices for polygon fill"
|
|
tree.end
|
|
width 0xa
|
|
tree "VRAM Offset and Data Format Registers"
|
|
group.long 0x200++7
|
|
line.long 0x00 "2DGC_VOR,VRAM Offset Register"
|
|
bitfld.long 0x00 17. " S8 ,Use 320 pixel offset for rows" "No allowed,Allowed"
|
|
bitfld.long 0x00 16. " PK ,Packed Mode" "Not selected,24 bpp"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET ,Offset into the VRAM"
|
|
line.long 0x04 "2DGC_DFR,Data Format Register"
|
|
bitfld.long 0x04 31. " ENDIAN ,ENDIANESS" "Big,Little"
|
|
bitfld.long 0x04 30. " WINCE ,DATA format is WINCE compliant" "Not compliant,Compliant"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9260")
|
|
tree "ISI (Image Sensor Interface)"
|
|
base ad:0xfffc0000
|
|
width 0xe
|
|
group.long 0x00++7
|
|
line.long 0x00 "ISI_CR1,ISI Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of Frame Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of Line Delay"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CODEC_ON ,Enable the codec path enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "4/8/16,8/16,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate captured" "All,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization" "No CRC,CRC"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising,Falling"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " ISI_DIS ,Image sensor disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ISI_RST ,Image sensor interface reset" "No action,Reset"
|
|
line.long 0x04 "ISI_CR2,ISI Control 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,Defines RGB pattern when RGB_MODE is set to 1" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,Defines the YCC image data" "Default,Mode1,Mode2,Mode3"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--26. 1. 1. " IM_HSIZE ,Horizontal size of the Image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB Swap" "D7 -> R7,D0 -> R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Gray Scale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8 24 bits,5:6:5 16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,GS Mode" "2 pixels per word,1 pixel per word"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. 1. " IM_VSIZE ,Vertical size of the Image sensor"
|
|
rgroup.long 0x08++3
|
|
line.long 0x00 "SI_SR,ISI Status Register"
|
|
bitfld.long 0x00 9. " FR_OVR ,Frame rate overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 8. " FO_C_EMP ,DMA transfer of the preview FIFO finished" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FO_P_EMP ,DMA transfer of the codec FIFO finished" "Not finished,Finished"
|
|
bitfld.long 0x00 6. " FO_P_OVF ,FIFO preview overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FO_C_OVF ,FIFO codec overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " CRC_ERR ,CRC synchronization error" "No error,Error"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 3. " CDC_PND , Codec request pending" "Not requested,Requested"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SOFTRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " DIS ,Image Sensor Interface disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOF ,Start of frame" "Not detected,Detected"
|
|
group.long 0x14++3
|
|
line.long 0x00 "ISI_IMR,ISI Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " FR_OVR_set/clr ,Frame overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " FO_C_EMP_set/clr ,Codec FIFO Empty" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " FO_P_EMP_set/clr ,Preview FIFO Empty" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FO_P_OVF_set/clr ,FIFO preview Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " FO_C_OVF_set/clr ,FIFO codec Overflow" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CRC_ERR_set/clr ,CRC synchronization error" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " SOFTRST_set/clr ,Soft Reset" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIS_set/clr ,Image Sensor Interface disable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " SOF_set/clr ,Start of Frame" "Disabled,Enabled"
|
|
group.long 0x20++0x23
|
|
line.long 0x00 "ISI_PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x00 16.--25. 1. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x00 0.--9. 1. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x04 "ISI_PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x08 "ISI_PPFBD,ISI Preview Primary FBD Register"
|
|
line.long 0x0c "ISI_CDBA,ISI Codec DMA Base Address Register"
|
|
line.long 0x10 "ISI_Y2R_SET0,ISI CSC YCrCb To RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color Space Conversion Matrix Coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "ISI_Y2R_SET1,ISI CSC YCrCb To RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " Cboff ,Color Space Conversion Blue Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " Croff ,Color Space Conversion Red Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 12. " Yoff ,Color Space Conversion Luminance default offset" "No offset,Offset=128"
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
line.long 0x18 "ISI_R2Y_SET0,ISI CSC RGB To YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " Roff ,Color Space Conversion Red component offset" "No offset,Offset=16"
|
|
hexmask.long.byte 0x18 16.--23. 1. " C2 ,Color Space Conversion Matrix coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " C1 ,Color Space Conversion Matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " C0 ,Color Space Conversion Matrix coefficient C0"
|
|
line.long 0x1c "ISI_R2Y_SET1,ISI CSC RGB To YCrCb Set 1 Register"
|
|
bitfld.long 0x1c 24. " Goff ,Color Space Conversion Green component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " C5 ,Color Space Conversion Matrix coefficient C5"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 8.--15. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " C3 ,Color Space Conversion Matrix coefficient C3"
|
|
line.long 0x20 "ISI_R2Y_SET2,ISI CSC RGB To YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " Boff ,Color Space Conversion Blue component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x20 16.--23. 1. " C8 ,Color Space Conversion Matrix coefficient C8"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " C7 ,Color Space Conversion Matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--7. 1. " C6 ,Color Space Conversion Matrix coefficient C6"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9263")
|
|
tree "ISI (Image Sensor Interface)"
|
|
base ad:0xfffc4000
|
|
width 0xe
|
|
group.long 0x00++7
|
|
line.long 0x00 "ISI_CR1,ISI Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of Frame Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of Line Delay"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CODEC_ON ,Enable the codec path enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "4/8/16,8/16,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate captured" "All,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization" "No CRC,CRC"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising,Falling"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " ISI_DIS ,Image sensor disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ISI_RST ,Image sensor interface reset" "No action,Reset"
|
|
line.long 0x04 "ISI_CR2,ISI Control 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,Defines RGB pattern when RGB_MODE is set to 1" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,Defines the YCC image data" "Default,Mode1,Mode2,Mode3"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--26. 1. 1. " IM_HSIZE ,Horizontal size of the Image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB Swap" "D7 -> R7,D0 -> R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Gray Scale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8 24 bits,5:6:5 16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,GS Mode" "2 pixels per word,1 pixel per word"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. 1. " IM_VSIZE ,Vertical size of the Image sensor"
|
|
rgroup.long 0x08++3
|
|
line.long 0x00 "SI_SR,ISI Status Register"
|
|
bitfld.long 0x00 9. " FR_OVR ,Frame rate overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 8. " FO_C_EMP ,DMA transfer of the preview FIFO finished" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FO_P_EMP ,DMA transfer of the codec FIFO finished" "Not finished,Finished"
|
|
bitfld.long 0x00 6. " FO_P_OVF ,FIFO preview overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FO_C_OVF ,FIFO codec overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " CRC_ERR ,CRC synchronization error" "No error,Error"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 3. " CDC_PND , Codec request pending" "Not requested,Requested"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SOFTRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " DIS ,Image Sensor Interface disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOF ,Start of frame" "Not detected,Detected"
|
|
group.long 0x14++3
|
|
line.long 0x00 "ISI_IMR,ISI Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " FR_OVR_set/clr ,Frame overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " FO_C_EMP_set/clr ,Codec FIFO Empty" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " FO_P_EMP_set/clr ,Preview FIFO Empty" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FO_P_OVF_set/clr ,FIFO preview Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " FO_C_OVF_set/clr ,FIFO codec Overflow" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CRC_ERR_set/clr ,CRC synchronization error" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " SOFTRST_set/clr ,Soft Reset" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIS_set/clr ,Image Sensor Interface disable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " SOF_set/clr ,Start of Frame" "Disabled,Enabled"
|
|
group.long 0x20++0x23
|
|
line.long 0x00 "ISI_PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x00 16.--25. 1. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x00 0.--9. 1. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x04 "ISI_PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x08 "ISI_PPFBD,ISI Preview Primary FBD Register"
|
|
line.long 0x0c "ISI_CDBA,ISI Codec DMA Base Address Register"
|
|
line.long 0x10 "ISI_Y2R_SET0,ISI CSC YCrCb To RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color Space Conversion Matrix Coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "ISI_Y2R_SET1,ISI CSC YCrCb To RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " Cboff ,Color Space Conversion Blue Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " Croff ,Color Space Conversion Red Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 12. " Yoff ,Color Space Conversion Luminance default offset" "No offset,Offset=128"
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
line.long 0x18 "ISI_R2Y_SET0,ISI CSC RGB To YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " Roff ,Color Space Conversion Red component offset" "No offset,Offset=16"
|
|
hexmask.long.byte 0x18 16.--23. 1. " C2 ,Color Space Conversion Matrix coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " C1 ,Color Space Conversion Matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " C0 ,Color Space Conversion Matrix coefficient C0"
|
|
line.long 0x1c "ISI_R2Y_SET1,ISI CSC RGB To YCrCb Set 1 Register"
|
|
bitfld.long 0x1c 24. " Goff ,Color Space Conversion Green component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " C5 ,Color Space Conversion Matrix coefficient C5"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 8.--15. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " C3 ,Color Space Conversion Matrix coefficient C3"
|
|
line.long 0x20 "ISI_R2Y_SET2,ISI CSC RGB To YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " Boff ,Color Space Conversion Blue component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x20 16.--23. 1. " C8 ,Color Space Conversion Matrix coefficient C8"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " C7 ,Color Space Conversion Matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--7. 1. " C6 ,Color Space Conversion Matrix coefficient C6"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9260")
|
|
tree "ADC (Analog-to-digital Converter)"
|
|
base ad:0xfffe0000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Started"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
sif (cpuis("AT91CAP9*")||cpuis("AT91SAM9XE*"))
|
|
bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "0,1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock"
|
|
else
|
|
bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock,16/clock"
|
|
endif
|
|
bitfld.long 0x00 16.--20. " STARTUP ,Start Up Time" "8/clock,16/clock,24/clock,32/clock,40/clock,48/clock,56/clock,64/clock,72/clock,80/clock,88/clock,96/clock,104/clock,112/clock,120/clock,128/clock,136/clock,144/clock,152/clock,160/clock,168/clock,176/clock,184/clock,192/clock,200/clock,208/clock,216/clock,224/clock,232/clock,240/clock,248/clock,256/clock"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " PRESCAL ,Prescaler Rate Selection" "MCK/2,MCK/4,MCK/6,MCK/8,MCK/10,MCK/12,MCK/14,MCK/16,MCK/18,MCK/20,MCK/22,MCK/24,MCK/26,MCK/28,MCK/30,MCK/32,MCK/34,MCK/36,MCK/38,MCK/40,MCK/42,MCK/44,MCK/46,MCK/48,MCK/50,MCK/52,MCK/54,MCK/56,MCK/58,MCK/60,MCK/62,MCK/64,MCK/66,MCK/68,MCK/70,MCK/72,MCK/74,MCK/76,MCK/78,MCK/80,MCK/82,MCK/84,MCK/86,MCK/88,MCK/90,MCK/92,MCK/94,MCK/96,MCK/98,MCK/100,MCK/102,MCK/104,MCK/106,MCK/108,MCK/110,MCK/112,MCK/114,MCK/116,MCK/118,MCK/120,MCK/122,MCK/124,MCK/126,MCK/128"
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|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit"
|
|
sif (cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "TIOA/Timer 0,TIOA/Timer 1,TIOA/Timer 2,TIOB/Timer 0,TIOB/Timer 1,TIOB/Timer 2,External,?..."
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|
else
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "Channel 0,Channel 1,Channel 2,Reserved,Reserved,Reserved,External,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
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|
group.long 0x18++0x03
|
|
line.long 0x0 "ADC_CHSR,ADC Channel Status Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
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|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
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|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
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|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "ADC_SR,ADC Status Register"
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|
in
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "ADC_LCDR,ADC Last Converted Data Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " OVRE7 ,Overrun Error Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " OVRE6 ,Overrun Error Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " OVRE5 ,Overrun Error Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " OVRE4 ,Overrun Error Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " OVRE3 ,Overrun Error Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " OVRE2 ,Overrun Error Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " OVRE1 ,Overrun Error Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " OVRE0 ,Overrun Error Interrupt Mask 0" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "ADC_CDR0,ADC Channel Data Register 0"
|
|
in
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x00 "ADC_CDR1,ADC Channel Data Register 1"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "ADC_CDR2,ADC Channel Data Register 2"
|
|
in
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "ADC_CDR3,ADC Channel Data Register 3"
|
|
in
|
|
sif (cpuis("AT91CAP9*"))
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "ADC_CDR4,ADC Channel Data Register 4"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "ADC_CDR5,ADC Channel Data Register 5"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "ADC_CDR3,ADC Channel Data Register 6"
|
|
in
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x00 "ADC_CDR3,ADC Channel Data Register 7"
|
|
in
|
|
endif
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
textline ""
|