17858 lines
1.2 MiB
17858 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: AT91SAM3N00A/00B/0A/0B/0C/1A/1B/1C/2A/2B/2C/4A/4B/4C On-Chip Peripherals
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; @Props: Released
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; @Author: EMK, TAT
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; @Changelog:
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; 2010-12-13
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; 2012-07-12
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: doc11011.pdf (2010-10-04); doc11011.pdf (2012-02-21)
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; @Core: Cortex-M3
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perat91sam3n.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "PID3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x400E1400
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RSTC_CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
sif !cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,NRST asserted"
|
|
endif
|
|
sif (cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Peripherals reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RSTC_SR,Status Register"
|
|
in
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RSTC_MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
sif (!cpuis("ATSAMA5D41")&&!cpuis("ATSAMA5D42")&&!cpuis("ATSAMA5D43")&&!cpuis("ATSAMA5D44")&&!cpuis("ATSAMA5D2?"))
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2 slow clock cycles (60 us),4 slow clock cycles (120 us),8 slow clock cycles (240 us),16 slow clock cycles (480 us),32 slow clock cycles (960 us),64 slow clock cycles (1.92 ms),128 slow clock cycles (3.84 ms),256 slow clock cycles (7.68 ms),512 slow clock cycles (15.36 ms),1024 slow clock cycles (30.72 ms),2048 slow clock cycles (61.44 ms),4096 slow clock cycles (122.88 ms),8192 slow clock cycles (245.76 ms),16384 slow clock cycles (491.52 ms),32768 slow clock cycles (0.98304 s),65536 slow clock cycles (1.96608 s)"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x400E1430
|
|
width 4.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MR,Real-Time Timer Mode Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*"))
|
|
bitfld.long 0x00 24. " RTC1HZ ,Real-time clock 1Hz clock selection" "16-bit prescaler,RTC 1 Hz clock"
|
|
bitfld.long 0x00 20. " RTTDIS ,Real-time timer disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " RTTRST ,Real-time timer restart" "No restart,Restart"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-time timer increment interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-time timer prescaler value"
|
|
line.long 0x04 "AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "VR,Real-Time Timer Value Register"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SR,Real-Time Timer Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0x400E1460
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,RTC Mode Register"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x04 28.--29. " TPERIO ,Period of the Output Pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x04 24.--26. " THIGH ,High Duration of the Output Pulse" "31.2 ms,15.6 ms,3.91 ms,967 u_s,488 u_s,122 u_s,30.5 u_s,15.2 u_s"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " OUT1 ,RTCOUT1 Output Source Selection" "No waveform,1 Hz square wave,32 Hz square wave,64 Hz square wave,512 Hz square wave,Output toggles when alarm flag rises,Output is a copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " OUT0 ,RTCOUT0 Output Source Selection" "No waveform,1 Hz square wave,32 Hz square wave,64 Hz square wave,512 Hz square wave,Output toggles when alarm flag rises,Output is a copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " HIGHPPM ,HIGH PPM Correction" "Lower,Higher"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CORRECTION ,Correction"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NEGPPM ,NEGative PPM Correction" "Positive,Negative"
|
|
bitfld.long 0x04 1. " PERSIAN ,PERSIAN Calendar" "Gregorian,Persian"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
if ((data.long(ad:0x400E1460+0x04)&0x1)==0x1)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" ",1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "0,1,2,3,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
if ((d.l(ad:0x400E1460+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
width 12.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or Date Free Running Error" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1C++0x0B
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 5. " TDERRCLR ,Time and/or Date Free Running Error Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "RTC_IER,Interrupt Enable Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x04 5. " TDERREN ,Time and/or Date Free Running Error Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " CALEN ,Calendar Event Interrupt Enable" "No effect,Enabled"
|
|
bitfld.long 0x04 3. " TIMEN ,Time Event Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SECEN ,Second Event Interrupt Enable" "No effect,Enabled"
|
|
bitfld.long 0x04 1. " ALREN ,Alarm Flag Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACKEN ,Acknowledge for Update Interrupt Enable" "No effect,Enabled"
|
|
line.long 0x08 "RTC_IDR,Interrupt Disable Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 5. " TDERRDIS ,Time and/or Date Free Running Error Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 4. " CALDIS ,Calendar Event Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x08 3. " TIMDIS ,Time Event Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SECDIS ,Second Event Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x08 1. " ALRDIS ,Alarm Flag Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ACKDIS ,Acknowledge for Update Interrupt Disable" "No,Yes"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 4. " CAL ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIM ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ALR ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACK ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
line.long 0x04 "RTC_VER,Valid Entry Register"
|
|
bitfld.long 0x04 3. " NVCAL ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " NVTAL ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NVC ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " NVT ,Non-Valid Time" "Not detected,Detected"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "RTC_WPMR,RTC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect access key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400E1450
|
|
width 4.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog restart" "No effect,Restart"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Not halted,Halted"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Not halted,Halted"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
if ((per.l(ad:0x400E1450+0x04)&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog reset processor" "All resets,Processor reset"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400E1410
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SUPC_CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x00 3. " XTALSEL , Crystal Oscillator Select " "No effect,Oscillator output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VROFF , Voltage Regulator Off" "No effect,Off"
|
|
group.long 0x04++0x0f
|
|
line.long 0x00 "SUPC_SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x00 13. " SMIEN , Supply Monitor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SMRSTEN , Supply Monitor Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SMSMPL , Supply Monitor Sampling Period" "Disabled,Continuous,Every 32 SLCK,Every 256 SLCK,Every 2048 SLCK,?..."
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "1.6 V,1.72 V,1.84 V,1.96 V,2.08 V,2.2 V,2.32 V,2.44 V,2.56 V,2.68 V,2.8 V,2.92 V,3.04 V,3.16 V,3.28 V,3.4 V"
|
|
else
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "1.9 V,2.0 V,2.1 V,2.2 V,2.3 V,2.4 V,2.5 V,2.6 V,2.7 V,2.8 V,2.9 V,3.0 V,3.1 V,3.2 V,3.3 V,3.4 V"
|
|
endif
|
|
line.long 0x04 "SUPC_MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x04 20. " OSCBYPASS , Oscillator Bypass" "No effect,Bypass"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x04 14. " ONREG ,Voltage Regulator Enabled" "Not used,Used"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 14. " VDDIORDY ,VDDIO Ready" "Removed,Present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 13. " BODDIS , Brownout Detector Disable" "No,Yes"
|
|
bitfld.long 0x04 12. " BODRSTEN , Brownout Detector Reset Enable" "Disabled,Enabled"
|
|
line.long 0x08 "SUPC_WUMR,Supply Controller Wake Up Mode Register"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 16.--18. " LPDBC ,Low Power DeBounCer Period" "Disabled,2_RTCOUT0,3_RTCOUT0,4_RTCOUT0,5_RTCOUT0,6_RTCOUT0,7_RTCOUT0,8_RTCOUT0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12.--14. " WKUPDBC , Wake Up Inputs Debouncer" "1 SLCK,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
textline " "
|
|
sif (cpuis("AT91SAM3U*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x08 8.--10. " FWUPDBC , Force Wake Up Debouncer" "1 SLCK,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 7. " LPDBCCLR ,Low power Debouncer Clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " LPDBCEN1 ,Low power Debouncer ENable WKUP1" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " LPDBCEN0 ,Low power Debouncer ENable WKUP0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " RTCEN , Real Time Clock Wake Up Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " RTTEN , Real Time Timer Wake Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SMEN , Supply Monitor Wake Up Enable" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3U*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x08 0. " FWUPEN , Force Wake Up Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0c "SUPC_WUIR,System Controller Wake Up Inputs Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x0c 31. " WKUPT15 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 30. " WKUPT14 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 29. " WKUPT13 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 27. " WKUPT11 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 26. " WKUPT10 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 24. " WKUPT8 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 23. " WKUPT7 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 21. " WKUPT5 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 20. " WKUPT4 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 18. " WKUPT2 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 17. " WKUPT1 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0c 31. " WKUPT15 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 30. " WKUPT14 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 29. " WKUPT13 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 27. " WKUPT11 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 26. " WKUPT10 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 24. " WKUPT8 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 23. " WKUPT7 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 21. " WKUPT5 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 20. " WKUPT4 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 18. " WKUPT2 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 17. " WKUPT1 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 15. " WKUPEN15 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " WKUPEN14 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " WKUPEN13 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " WKUPEN12 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 11. " WKUPEN11 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " WKUPEN10 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " WKUPEN9 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " WKUPEN8 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " WKUPEN7 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " WKUPEN6 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " WKUPEN5 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " WKUPEN4 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 3. " WKUPEN3 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " WKUPEN2 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " WKUPEN1 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " WKUPEN0 , Wake Up Input Transition" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SUPC_SR,Supply Controller Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0x400E1490
|
|
width 8.
|
|
sif (cpuis("AT91SAM3S8*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMG5*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
elif (cpuis("ATSAM4E*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPBR8,General Purpose Backup Register 8"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPBR9,General Purpose Backup Register 9"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GPBR10,General Purpose Backup Register 10"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPBR11,General Purpose Backup Register 11"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPBR12,General Purpose Backup Register 12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPBR13,General Purpose Backup Register 13"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPBR14,General Purpose Backup Register 14"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GPBR15,General Purpose Backup Register 15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPBR16,General Purpose Backup Register 16"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPBR17,General Purpose Backup Register 17"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPBR18,General Purpose Backup Register 18"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPBR19,General Purpose Backup Register 19"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "EEFC (Enhanced Embedded Flash Controller)"
|
|
base ad:0x400E0A00
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 26. " CLOE ,Code Loops Optimization Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " FAM , Flash Access Mode" "128-bit,64-bit"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRDY ,Flash Ready Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "EEFC_FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY , Flash Writing Protection Key"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash Command Argument"
|
|
textline " "
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--4. " FCMD ,Flash Command" "GETD,WP,WPL,EWP,EWPL,EA,,EPA,SLB,CLB,GLB,SGPB,CGPB,GGPB,STUI,SPUI,GCALB,ES,WUS,EUS,STUS,SPUS,?..."
|
|
else
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCMD ,Flash Command"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "EEFC_FSR,EEFC Flash Status Register"
|
|
in
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "EEFC_FRR,EEFC Flash Result Register"
|
|
hexmask.long 0x00 0.--31. 1. " FVALUE , Flash Result Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "MATRIX (Bus Matrix)"
|
|
base ad:0x400E0200
|
|
width 14.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
if ((d.l(ad:0x400E0200+0x40)&0x30000)==0x20000)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("AT91SAM3N*"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0200+0x44)&0x30000)==0x20000)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("AT91SAM3N*"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0200+0x48)&0x30000)==0x20000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("AT91SAM3N*"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0200+0x4C)&0x30000)==0x20000)
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("AT91SAM3N*"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/OConfiguration Register"
|
|
bitfld.long 0x00 12. " SYSIO12 ,PB12 or ERASE Assignment" "ERASE,PB12"
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK Assignment" "TCK/SWCLK,PB7"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SYSIO6 ,PB6 or TMS/SWDIO Assignment" "TMS/SWDIO,PB6"
|
|
bitfld.long 0x00 5. " SYSIO5 ,PB5 or TDO/TRACESWO Assignment" "TDO/TRACESWO,PB5"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYSIO4 ,PB4 or TDI Assignment" "TDI,PB4"
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0x1e8++0x3
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x400E0400
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " PCK2_set/clr ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM_set/clr ,Pulse Width Modulation (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " DACC_set/clr ,Digital-to-Analog Converter (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ADC_set/clr ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TC5_set/clr ,Timer/Counter 5 (Peripheral ID 28)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " TC4_set/clr ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " TC3_set/clr ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " TC2_set/clr ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TWI2_set/clr ,Two Wire Interface 2 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SPI_set/clr ,Serial Peripheral Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWI1_set/clr ,Two Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
sif cpuis("ATSAM4N8C")||cpuis("ATSAM4N16C")
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " USART2_set/clr ,Two-Wire Interface 0 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " UART3_set/clr ,Two-Wire Interface 0 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " USART1_set/clr ,USART 1 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " USART0_set/clr ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " UART2_set/clr ,Universal Asynchronous Receiver Transmitter 2 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " UART1_set/clr ,Universal Asynchronous Receiver Transmitter 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " UART1_set/clr ,Universal Asynchronous Receiver Transmitter 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " UART0_set/clr ,Universal Asynchronous Receiver Transmitter 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EEFC_set/clr ,Enhanced Flash Controller (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PMC_set/clr ,Power Management Controller (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " WDT_set/clr ,Watchdog Timer (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RTT_set/clr ,Real Time Timer (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RTC_set/clr ,Real Time Clock (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 26. " XT32KFME ,Slow Crystal Oscillator Frequency Monitoring Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "Main On-Chip RC,Main Crystal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Password"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4S16C")
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command" "No effect,Wait"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
sif (cpu()=="ATSAM4S16C")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure" "No effect,Restart"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
sif (cpu()=="ATSAM4S16C")
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
bitfld.long 0x00 29. " ONE ,Must Be Set to 1" "0,1"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLLA Multiplier"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLLA Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider"
|
|
line.long 0x04 "CKGR_PLLBR,PMC Clock Generator PLLB Register"
|
|
bitfld.long 0x04 29. " ONE ,Must Be Set to 1" "0,1"
|
|
hexmask.long.word 0x04 16.--26. 1. " MULB ,PLLB Multiplier"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " PLLBCOUNT ,PLLB Counter"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIVB ,Divider"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLR,PMC Clock Generator PLL Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MUL ,PLL Multiplier"
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLCOUNT ,PLL Counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Divider"
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PMC_MCKR,PMC Master Clock Register"
|
|
sif (cpu()=="ATSAM4S16C")
|
|
bitfld.long 0x0 13. " PLLBDIV2 ,PLLB Divisor by 2" "Clock,Clock/2"
|
|
bitfld.long 0x0 12. " PLLADIV2 ,PLLA Divisor by 2" "Clock,Clock/2"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0 12. " PLLDIV2 ,PLL Divisor by 2" "Clock,Clock/2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Source Selection" "Slow,Main,PLL,?..."
|
|
sif (cpu()=="ATSAM4S16C")
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB Clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " USBS ,USB Input Clock Selection" "PLLA,PLLB"
|
|
endif
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLA,,MCK,?..."
|
|
else
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLA,PLLB,MCK,?..."
|
|
endif
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLA,,MCK,?..."
|
|
else
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLA,PLLB,MCK,?..."
|
|
endif
|
|
line.long 0x8 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x8 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x8 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLA,,MCK,?..."
|
|
else
|
|
bitfld.long 0x8 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLA,PLLB,MCK,?..."
|
|
endif
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 21. -0xc 21. -0x8 21. " XT32KERR_set/clr ,Slow Crystal Oscillator Error Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 18. -0xc 18. -0x8 18. " CFDEV_set/clr ,Clock Failure Detector Event" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0xc 17. -0x8 17. " MOSCRCS_set/clr ,Main On-Chip RC Oscillator Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0xc 16. -0x8 16. " MOSCSELS_set/clr ,Main Oscillator Selection Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCKRDY2_set/clr ,Programmable Clock Ready 2 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCXTS_set/clr ,Main Oscillator Status Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
in
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
sif (cpu()=="ATSAM4S16C")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash Low Power Mode" "STANDBY,DEEP_POWERDOWN,IDLE,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 20. " LPM ,Low Power Mode" "Idle,Wait"
|
|
textline ""
|
|
sif (cpu()=="ATSAM4S16C")
|
|
bitfld.long 0x00 18. " USBAL ,USB Alarm Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT15 ,Fast Startup Input Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT14 ,Fast Startup Input Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Startup Input Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Startup Input Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Startup Input Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Startup Input Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Startup Input Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Startup Input Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Startup Input Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Startup Input Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Startup Input Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Startup Input Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Startup Input Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Startup Input Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Startup Input Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Startup Input Enable 0" "Disabled,Enabled"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x00 15. " FSTP15 ,Fast Startup Input Polarity 15" "Low,High"
|
|
bitfld.long 0x00 14. " FSTP14 ,Fast Startup Input Polarity 14" "Low,High"
|
|
bitfld.long 0x00 13. " FSTP13 ,Fast Startup Input Polarity 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSTP12 ,Fast Startup Input Polarity 12" "Low,High"
|
|
bitfld.long 0x00 11. " FSTP11 ,Fast Startup Input Polarity 11" "Low,High"
|
|
bitfld.long 0x00 10. " FSTP10 ,Fast Startup Input Polarity 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FSTP9 ,Fast Startup Input Polarity 9" "Low,High"
|
|
bitfld.long 0x00 8. " FSTP8 ,Fast Startup Input Polarity 8" "Low,High"
|
|
bitfld.long 0x00 7. " FSTP7 ,Fast Startup Input Polarity 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSTP6 ,Fast Startup Input Polarity 6" "Low,High"
|
|
bitfld.long 0x00 5. " FSTP5 ,Fast Startup Input Polarity 5" "Low,High"
|
|
bitfld.long 0x00 4. " FSTP4 ,Fast Startup Input Polarity 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FSTP3 ,Fast Startup Input Polarity 3" "Low,High"
|
|
bitfld.long 0x00 2. " FSTP2 ,Fast Startup Input Polarity 2" "Low,High"
|
|
bitfld.long 0x00 1. " FSTP1 ,Fast Startup Input Polarity 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSTP0 ,Fast Startup Input Polarity 0" "Low,High"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x00 "PMC_FOCR,PMC Fault Output Clear Register"
|
|
bitfld.long 0x00 0. " FOCLR ,Fault Output Clear" "No effect,Clear"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PMC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PMC_WPSR,Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="ATSAM4S16C")
|
|
wgroup.long 0x100++0x7
|
|
line.long 0x00 "PMC_PCER1,PMC Peripheral Clock Enable Register 1"
|
|
bitfld.long 0x00 2. " PID34 ,Peripheral Clock 4 Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " PID33 ,Peripheral Clock 3 Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " PID32 ,Peripheral Clock 2 Enable" "No effect,Enabled"
|
|
line.long 0x04 "PMC_PCDR1,PMC Peripheral Clock Disable Register 1"
|
|
bitfld.long 0x04 2. " PID34 ,Peripheral Clock 4 Disable" "No effect,Disabled"
|
|
bitfld.long 0x04 1. " PID33 ,Peripheral Clock 3 Disable" "No effect,Disabled"
|
|
bitfld.long 0x04 0. " PID32 ,Peripheral Clock 2 Disable" "No effect,Disabled"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
bitfld.long 0x00 2. " PID34 ,Peripheral Clock 4 Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PID33 ,Peripheral Clock 3 Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PID32 ,Peripheral Clock 2 Status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x0110++0x3
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,Selection of RC Oscillator Calibration bits for 12 MHz" "Default,CAL12 value"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,RC Oscillator Calibration bits for 12 MHz"
|
|
bitfld.long 0x00 15. " SEL8 ,Selection of RC Oscillator Calibration bits for 8 MHz" "Default,CAL8 value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,RC Oscillator Calibration bits for 8 MHz"
|
|
bitfld.long 0x00 7. " SEL4 ,Selection of RC Oscillator Calibration bits for 4 MHz" "Default,CAL4 value"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,RC Oscillator Calibration bits for 4 MHz"
|
|
width 0xb
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0740
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CHIPID_CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension flag" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile program memory type" "ROM,Romless/flash,Embedded flash,ROM & embedded flash,SRAM emulating ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture identifier"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,1-KB,2-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
elif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV7*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,192-KB,384-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
else
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,1-KB,2-KB,6-KB,112-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
sif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV7*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,160-KB,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
else
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-a5,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("AT91SAM3S*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3N*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV70*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-m7,ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-m7,ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
bitfld.long 0x00 0.--4. " VERSION ,Device version" "MRLA,MRLB,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31"
|
|
else
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946E-S,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJ-S,?..."
|
|
bitfld.long 0x00 0.--4. " VERSION ,Device version" "Version 0,Version 1,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31"
|
|
endif
|
|
sif (cpuis("ATSAM4LS*")||cpuis("ATSAM4LC*"))
|
|
line.long 0x04 "EXID,Extension Register"
|
|
bitfld.long 0x04 24.--26. " PACKAGE ,Package type" "24-pin,32-pin,48-pin,64-pin,100-pin,144-pin,?..."
|
|
bitfld.long 0x04 3. " LCD ,LCD option" "Not implemented,Implemented"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB configuration" "Device-only,Device and host"
|
|
elif (cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB configuration" "Device-only,?..."
|
|
endif
|
|
bitfld.long 0x04 1. " USB ,USB option" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AES ,AES option" "Not implemented,Implemented"
|
|
else
|
|
line.long 0x04 "CHIPID_EXID,Chip ID Extension Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output)"
|
|
tree "Port A"
|
|
base ad:0x400E0E00
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRA,PIO Controller PIO Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRA,PIO Controller Output Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
ENDIF
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRA,PIO Controller Input Filter Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRA,PIO Controller Output Data Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRA,PIO Controller Pin Data Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRA,PIO Controller Interrupt Mask Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRA,PIO Controller Interrupt Status Register A"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRA,PIO Multi-Driver Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRA,PIO Pull Up Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_Set/Clear ,Pull Up 31 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_Set/Clear ,Pull Up 30 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_Set/Clear ,Pull Up 29 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_Set/Clear ,Pull Up 28 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_Set/Clear ,Pull Up 27 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_Set/Clear ,Pull Up 26 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_Set/Clear ,Pull Up 25 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_Set/Clear ,Pull Up 24 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_Set/Clear ,Pull Up 23 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_Set/Clear ,Pull Up 22 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_Set/Clear ,Pull Up 21 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_Set/Clear ,Pull Up 20 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_Set/Clear ,Pull Up 19 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_Set/Clear ,Pull Up 18 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_Set/Clear ,Pull Up 17 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_Set/Clear ,Pull Up 16 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_Set/Clear ,Pull Up 15 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_Set/Clear ,Pull Up 31 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_Set/Clear ,Pull Up 30 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_Set/Clear ,Pull Up 29 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_Set/Clear ,Pull Up 28 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_Set/Clear ,Pull Up 27 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_Set/Clear ,Pull Up 26 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_Set/Clear ,Pull Up 25 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_Set/Clear ,Pull Up 24 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_Set/Clear ,Pull Up 23 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_Set/Clear ,Pull Up 22 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_Set/Clear ,Pull Up 21 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_Set/Clear ,Pull Up 20 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_Set/Clear ,Pull Up 19 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_Set/Clear ,Pull Up 18 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_Set/Clear ,Pull Up 17 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_Set/Clear ,Pull Up 16 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_Set/Clear ,Pull Up 15 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_Set/Clear ,Pull Up 20 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_Set/Clear ,Pull Up 19 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_Set/Clear ,Pull Up 18 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_Set/Clear ,Pull Up 17 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_Set/Clear ,Pull Up 16 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_Set/Clear ,Pull Up 15 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select(If P31 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select(If P30 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select(If P29 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select(If P28 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select(If P27 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select(If P26 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select(If P25 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select(If P24 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select(If P23 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select(If P22 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P29 ,Peripheral Select(If P21 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select(If P31 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select(If P30 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select(If P29 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select(If P28 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select(If P27 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select(If P26 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select(If P25 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select(If P24 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select(If P23 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select(If P22 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P29 ,Peripheral Select(If P21 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select(If P31 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select(If P30 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select(If P29 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select(If P28 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select(If P27 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select(If P26 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select(If P25 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select(If P24 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select(If P23 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select(If P22 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P29 ,Peripheral Select(If P21 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select(If P31 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select(If P30 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select(If P29 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select(If P28 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select(If P27 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select(If P26 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select(If P25 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select(If P24 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select(If P23 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select(If P22 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P29 ,Peripheral Select(If P21 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register "
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
endif
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRA,PIO Output Write Status Register A"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status 31" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status 30" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status 31" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status 30" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,I/O line 31 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,I/O line 30 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
bitfld.long 0x00 31. " P31 ,I/O line 31 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,I/O line 30 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRB,PIO Controller PIO Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRB,PIO Controller Output Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
ENDIF
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRB,PIO Controller Input Filter Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRB,PIO Controller Output Data Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRB,PIO Controller Pin Data Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRB,PIO Controller Interrupt Mask Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRB,PIO Controller Interrupt Status Register B"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRB,PIO Multi-Driver Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRB,PIO Pull Up Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register "
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
endif
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRB,PIO Output Write Status Register B"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpuis("AT91SAM3N0C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N4C"))
|
|
tree "Port C"
|
|
base ad:0x400E1200
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRC,PIO Controller PIO Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRC,PIO Controller Output Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
ENDIF
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRC,PIO Controller Input Filter Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRC,PIO Controller Output Data Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRC,PIO Controller Pin Data Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRC,PIO Controller Interrupt Mask Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRC,PIO Controller Interrupt Status Register C"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRC,PIO Multi-Driver Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRC,PIO Pull Up Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_Set/Clear ,Pull Up 31 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_Set/Clear ,Pull Up 30 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_Set/Clear ,Pull Up 29 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_Set/Clear ,Pull Up 28 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_Set/Clear ,Pull Up 27 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_Set/Clear ,Pull Up 26 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_Set/Clear ,Pull Up 25 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_Set/Clear ,Pull Up 24 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_Set/Clear ,Pull Up 23 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_Set/Clear ,Pull Up 22 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_Set/Clear ,Pull Up 21 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_Set/Clear ,Pull Up 20 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_Set/Clear ,Pull Up 19 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_Set/Clear ,Pull Up 18 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_Set/Clear ,Pull Up 17 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_Set/Clear ,Pull Up 16 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_Set/Clear ,Pull Up 15 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select(If P31 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select(If P30 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select(If P29 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select(If P28 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select(If P27 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select(If P26 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select(If P25 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select(If P24 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select(If P23 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select(If P22 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P29 ,Peripheral Select(If P21 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR2/set to 1)" "A/C,B/D"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select(If P31 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select(If P30 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select(If P29 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select(If P28 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select(If P27 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select(If P26 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select(If P25 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select(If P24 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select(If P23 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select(If P22 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P29 ,Peripheral Select(If P21 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 20. " P28 ,Peripheral Select(If P20 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select(If P19 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select(If P18 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select(If P17 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select(If P16 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select(If P15 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select(If P14 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select(If P13 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select(If P12 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select(If P11 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select(If P10 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select(If P9 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select(If P8 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select(If 7 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select(If 6 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select(If P5 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select(If P4 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select(If P3 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select(If P2 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select(If P1 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select(If P0 in is set to 0 in PIO_ABCDSR1/set to 1)" "A/B,C/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register "
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
endif
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRC,PIO Output Write Status Register C"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status 31" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status 30" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " P31 ,I/O line 31 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,I/O line 30 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif (cpuis("AT91SAM3N4C")||cpuis("AT91SAM3N2C")||cpuis("AT91SAM3N1C")||cpuis("AT91SAM3N0C"))
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
elif (cpuis("AT91SAM3N4B")||cpuis("AT91SAM3N2B")||cpuis("AT91SAM3N1B")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N00B"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40008000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 31. "FIFODIS,FIFO disable" "No effect,Disabled"
|
|
bitfld.long 0x00 30. "FIFOEN,FIFO enable" "No effect,Enabled"
|
|
endif
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 17. "RXFCLR,Receive FIFO clear" "Di,Enabled"
|
|
bitfld.long 0x00 16. "TXFCLR,Transmit FIFO clear" "No effect,Transmitted"
|
|
endif
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enabled"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
if (((per.l((ad:0x40008000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
sif cpuis("AT91SAM3S*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4S*")||cpuis("ATSAMG51")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE ,Transmit buffer empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF ,Receive buffer full interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX ,End of transmit buffer interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX ,End of receive buffer interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TWI (Two-wire Interface)"
|
|
tree "TWI 0"
|
|
base ad:0x40018000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x40018000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI 1"
|
|
base ad:0x4001C000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x4001C000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART 0"
|
|
base ad:0x400E0600
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal Mode,Automatic Echo,Local Loopback,Remote Loopback"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,No,No,No"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UART Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,RXBUFF Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,TXBUFE Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "UART 1"
|
|
base ad:0x400E0800
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal Mode,Automatic Echo,Local Loopback,Remote Loopback"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,No,No,No"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UART Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,RXBUFF Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,TXBUFE Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 0"
|
|
base ad:0x40024000
|
|
width 10.
|
|
if ((d.l((ad:0x40024000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40024000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x40024000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40024000+0x4))&0x1f)==0xE)||(d.l((ad:0x40024000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x40024000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif ((cpuis("AT91SAM3N*B"))||(cpuis("AT91SAM3N*C")))
|
|
tree "USART 1"
|
|
base ad:0x40028000
|
|
width 10.
|
|
if ((d.l((ad:0x40028000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40028000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x40028000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40028000+0x4))&0x1f)==0xE)||(d.l((ad:0x40028000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x40028000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "TC (Timer Counter)"
|
|
tree "TC 0"
|
|
base ad:0x40010000
|
|
width 0x8
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (!cpuis("AT91SAM3N*"))
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x9
|
|
sif cpuis("AT91SAM3N*A")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40010000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40010000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40010000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40010000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40010000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB0,TC0 Register AB"
|
|
line.long 0x04 "TC_CV0,TC0 Counter Value Register"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40010000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "TC_EMR0,TC0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB0,PWM0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA0,PWM0,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40010000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB1,TC1 Register AB"
|
|
line.long 0x04 "TC_CV1,TC1 Counter Value Register"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40010000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "TC_EMR1,TC1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB1,PWM1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA1,PWM1,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40010000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register 2"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB2,TC2 Register AB"
|
|
line.long 0x04 "TC_CV2,TC2 Counter Value Register"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40010000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "TC_EMR2,TC2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB2,PWM2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA2,PWM2,?..."
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TC 1"
|
|
base ad:0x40014000
|
|
width 0x8
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (!cpuis("AT91SAM3N*"))
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x9
|
|
sif cpuis("AT91SAM3N*A")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40014000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40014000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40014000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40014000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40014000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB0,TC0 Register AB"
|
|
line.long 0x04 "TC_CV0,TC0 Counter Value Register"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40014000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "TC_EMR0,TC0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB0,PWM0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA0,PWM0,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40014000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB1,TC1 Register AB"
|
|
line.long 0x04 "TC_CV1,TC1 Counter Value Register"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40014000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "TC_EMR1,TC1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB1,PWM1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA1,PWM1,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40014000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register 2"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB2,TC2 Register AB"
|
|
line.long 0x04 "TC_CV2,TC2 Counter Value Register"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40014000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "TC_EMR2,TC2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB2,PWM2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA2,PWM2,?..."
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0x40020000
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PWM_MR,PWM Mode Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Master clock selection for CLKB" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,Reseved,Reseved,Reseved,Reseved,Reseved"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Master clock selection for CLKA" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,Reseved,Reseved,Reseved,Reseved,Reseved"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWM_SR,PWM Status Register"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM output for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM output for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM output for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM output for channel 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PWM_IMR,PWM Interrupt Mask Register"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Interrupt for PWM channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Interrupt for PWM channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Interrupt for PWM channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CHID0_set/clr ,Interrupt for PWM channel 0" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x0 "PWM_ISR1,PWM Interrupt Status Register 1"
|
|
in
|
|
tree "Channel 0"
|
|
group.long (0x200+0x0)++0xB
|
|
line.long 0x00 "PWM_CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x04 0.--31. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
line.long 0x08 "PWM_CPRD0,PWM Channel 0 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x08 0.--31. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x08 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
rgroup.long (0x20C+0x0)++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
wgroup.long (0x210+0x0)++0x03
|
|
line.long 0x00 "PWM_CUPD0,PWM Channel Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CUPD ,Channel Update Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CUPD ,Channel Update Register"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long (0x200+0x20)++0xB
|
|
line.long 0x00 "PWM_CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x04 0.--31. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
line.long 0x08 "PWM_CPRD1,PWM Channel 1 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x08 0.--31. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x08 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
rgroup.long (0x20C+0x20)++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
wgroup.long (0x210+0x20)++0x03
|
|
line.long 0x00 "PWM_CUPD1,PWM Channel Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CUPD ,Channel Update Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CUPD ,Channel Update Register"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long (0x200+0x40)++0xB
|
|
line.long 0x00 "PWM_CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x04 0.--31. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
line.long 0x08 "PWM_CPRD2,PWM Channel 2 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x08 0.--31. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x08 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
rgroup.long (0x20C+0x40)++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
wgroup.long (0x210+0x40)++0x03
|
|
line.long 0x00 "PWM_CUPD2,PWM Channel Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CUPD ,Channel Update Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CUPD ,Channel Update Register"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long (0x200+0x60)++0xB
|
|
line.long 0x00 "PWM_CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x04 0.--31. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
line.long 0x08 "PWM_CPRD3,PWM Channel 3 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x08 0.--31. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x08 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
rgroup.long (0x20C+0x60)++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
wgroup.long (0x210+0x60)++0x03
|
|
line.long 0x00 "PWM_CUPD3,PWM Channel Update Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
hexmask.long 0x00 0.--31. 1. " CUPD ,Channel Update Register"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CUPD ,Channel Update Register"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PWM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PWM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PWM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PWM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PWM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PWM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PWM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PWM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PWM_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PWM_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40038000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User Sequence Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer Period" "3,5,7,9"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 23. " ANACH ,Analog Change" "None,Allowed"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 20.--21. " SETTLING ,Analog Settling Time" "3,5,9,17"
|
|
elif (!cpuis("AT91SAM3N*"))
|
|
bitfld.long 0x00 20.--21. " SETTLING ,Analog Settling Time" "1,2,3,4"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "0,8,16,24,64,80,96,112,512,576,640,704,768,832,896,960"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FWUP ,Fast Wake Up" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 4. " LOWRES ,Selected Resolution" "12 bit,10 bit"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,PWM Event Line 0,PWM Event Line 1,?..."
|
|
else
|
|
bitfld.long 0x00 4. " LOWRES ,Selected Resolution" "10 bit,8 bit"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
if (((data.long((ad:0x40038000+0x04)))&0x80000000)==0x80000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH8 ,User Sequence Number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif ((cpuis("AT91SAM3N*C")||cpuis("AT91SAM3N00A")||cpuis("AT91SAM3N00B")||cpuis("AT91SAM3N0A")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N0C"))||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
bitfld.long 0x00 28.--31. " USCH16 ,User Sequence Number 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " USCH15 ,User Sequence Number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " USCH14 ,User Sequence Number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " USCH13 ,User Sequence Number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " USCH12 ,User Sequence Number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " USCH11 ,User Sequence Number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " USCH10 ,User Sequence Number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " USCH9 ,User Sequence Number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
bitfld.long 0x00 4.--7. " USCH10 ,User Sequence Number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " USCH9 ,User Sequence Number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
sif ((cpuis("AT91SAM3N*B"))||(cpuis("AT91SAM3N*C"))||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x00 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
endif
|
|
endif
|
|
sif ((cpuis("AT91SAM3N*C")||cpuis("AT91SAM3N00A")||cpuis("AT91SAM3N00B")||cpuis("AT91SAM3N0A")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N0C"))||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " CH15_Clear/Set ,Channel 15 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " CH14_Clear/Set ,Channel 14 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " CH13_Clear/Set ,Channel 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " CH12_Clear/Set ,Channel 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " CH11_Clear/Set ,Channel 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " CH10_Clear/Set ,Channel 10 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CH9_Clear/Set ,Channel 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CH8_Clear/Set ,Channel 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 4. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CH9_Clear/Set ,Channel 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CH8_Clear/Set ,Channel 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 4. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 4. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "ADC_LCDR,ADC Last Data Converted"
|
|
in
|
|
sif (cpuis("AT91SAM3N*C")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " EOC15 ,Conversion End Interrupt Mask 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " EOC14 ,Conversion End Interrupt Mask 14" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " EOC13 ,Conversion End Interrupt Mask 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " EOC12 ,Conversion End Interrupt Mask 12" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOC11 ,Conversion End Interrupt Mask 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " EOC10 ,Conversion End Interrupt Mask 10" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " EOC9 ,Conversion End Interrupt Mask 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " EOC8 ,Conversion End Interrupt Mask 8" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " EOC9 ,Conversion End Interrupt Mask 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " EOC8 ,Conversion End Interrupt Mask 8" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ADC_ISR,ADC Interrupt Status Register"
|
|
in
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "ADC_OVER,ADC Overrun Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3N*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare Event Filtering" "1,2,3,4"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel(CMPALL must be 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
group.long 0x48++0x7
|
|
line.long 0x00 "ADC_CGR,ADC Channel Gain Register"
|
|
sif (!cpuis("AT91SAM3N*B"))
|
|
sif (!cpuis("AT91SAM3N*A"))
|
|
bitfld.long 0x00 30.--31. " GAIN15 ,Gain for channel 15(DIFF15 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 28.--29. " GAIN14 ,Gain for channel 14(DIFF14 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 26.--27. " GAIN13 ,Gain for channel 13(DIFF13 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " GAIN12 ,Gain for channel 12(DIFF12 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 22.--23. " GAIN11 ,Gain for channel 11(DIFF11 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 20.--21. " GAIN10 ,Gain for channel 10(DIFF10 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " GAIN9 ,Gain for channel 9(DIFF9 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 16.--17. " GAIN8 ,Gain for channel 8(DIFF8 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " GAIN7 ,Gain for channel 7(DIFF7 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " GAIN6 ,Gain for channel 6(DIFF6 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 10.--11. " GAIN5 ,Gain for channel 5(DIFF5 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 8.--9. " GAIN4 ,Gain for channel 4(DIFF4 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " GAIN3 ,Gain for channel 3(DIFF3 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 4.--5. " GAIN2 ,Gain for channel 2(DIFF2 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 2.--3. " GAIN1 ,Gain for channel 1(DIFF1 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GAIN0 ,Gain for channel 0(DIFF0 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
line.long 0x04 "ADC_COR,ADC Channel Offset Register"
|
|
sif (!cpuis("AT91SAM3N*B"))
|
|
sif (!cpuis("AT91SAM3N*A"))
|
|
bitfld.long 0x04 31. " DIFF15 ,Differential inputs for channel 15" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 30. " DIFF14 ,Differential inputs for channel 14" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 29. " DIFF13 ,Differential inputs for channel 13" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 28. " DIFF12 ,Differential inputs for channel 12" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 27. " DIFF11 ,Differential inputs for channel 11" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 26. " DIFF10 ,Differential inputs for channel 10" "Single Ended,Fully Differential"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 25. " DIFF9 ,Differential inputs for channel 9" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 24. " DIFF8 ,Differential inputs for channel 8" "Single Ended,Fully Differential"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " DIFF7 ,Differential inputs for channel 7" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 22. " DIFF6 ,Differential inputs for channel 6" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 21. " DIFF5 ,Differential inputs for channel 5" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 20. " DIFF4 ,Differential inputs for channel 4" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DIFF3 ,Differential inputs for channel 3" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 18. " DIFF2 ,Differential inputs for channel 2" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 17. " DIFF1 ,Differential inputs for channel 1" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DIFF0 ,Differential inputs for channel 0" "Single Ended,Fully Differential"
|
|
sif (!cpuis("AT91SAM3N*B"))
|
|
sif (!cpuis("AT91SAM3N*A"))
|
|
textline " "
|
|
bitfld.long 0x04 15. " OFF15 ,Offset for channel 15" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 14. " OFF14 ,Offset for channel 14" "No offset,Offset"
|
|
bitfld.long 0x04 13. " OFF13 ,Offset for channel 13" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFF12 ,Offset for channel 12" "No offset,Offset"
|
|
bitfld.long 0x04 11. " OFF11 ,Offset for channel 11" "No offset,Offset"
|
|
bitfld.long 0x04 10. " OFF10 ,Offset for channel 10" "No offset,Offset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " OFF9 ,Offset for channel 9" "No offset,Offset"
|
|
bitfld.long 0x04 8. " OFF8 ,Offset for channel 8" "No offset,Offset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " OFF7 ,Offset for channel 7" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OFF6 ,Offset for channel 6" "No offset,Offset"
|
|
bitfld.long 0x04 5. " OFF5 ,Offset for channel 5" "No offset,Offset"
|
|
bitfld.long 0x04 4. " OFF4 ,Offset for channel 4" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OFF3 ,Offset for channel 3" "No offset,Offset"
|
|
bitfld.long 0x04 2. " OFF2 ,Offset for channel 2" "No offset,Offset"
|
|
bitfld.long 0x04 1. " OFF1 ,Offset for channel 1" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OFF0 ,Offset for channel 0" "No offset,Offset"
|
|
endif
|
|
sif (cpuis("AT91SAM3A8C")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long 0x50++0x3F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel 8 Data Register"
|
|
hexmask.long.word 0x20 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel 9 Data Register"
|
|
hexmask.long.word 0x24 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x28 "ADC_CDR10,ADC Channel 10 Data Register"
|
|
hexmask.long.word 0x28 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x2C "ADC_CDR11,ADC Channel 11 Data Register"
|
|
hexmask.long.word 0x2C 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x30 "ADC_CDR12,ADC Channel 12 Data Register"
|
|
hexmask.long.word 0x30 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x34 "ADC_CDR13,ADC Channel 13 Data Register"
|
|
hexmask.long.word 0x34 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x38 "ADC_CDR14,ADC Channel 14 Data Register"
|
|
hexmask.long.word 0x38 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x3C "ADC_CDR15,ADC Channel 15 Data Register"
|
|
hexmask.long.word 0x3C 0.--11. 1. " DATA ,Converted Data"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x2B
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel 8 Data Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel 9 Data Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " DATA ,Converted Data"
|
|
elif (cpuis("AT91SAM3N*A"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x1F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
elif (cpuis("AT91SAM3N*C"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x3F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel 8 Data Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel 9 Data Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x28 "ADC_CDR10,ADC Channel 10 Data Register"
|
|
hexmask.long.word 0x28 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x2C "ADC_CDR11,ADC Channel 11 Data Register"
|
|
hexmask.long.word 0x2C 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x30 "ADC_CDR12,ADC Channel 12 Data Register"
|
|
hexmask.long.word 0x30 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x34 "ADC_CDR13,ADC Channel 13 Data Register"
|
|
hexmask.long.word 0x34 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x38 "ADC_CDR14,ADC Channel 14 Data Register"
|
|
hexmask.long.word 0x38 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x3C "ADC_CDR15,ADC Channel 15 Data Register"
|
|
hexmask.long.word 0x3C 0.--9. 1. " DATA ,Converted Data"
|
|
else
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x1f
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
endif
|
|
sif (cpuis("AT91SAM3A8C")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,ADC Bias Current Control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TSON ,Temperature Sensor On" "Off,On"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "ADC_WPMR,ADC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "ADC_WPSR,ADC Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "ADC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "ADC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "ADC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "ADC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "ADC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "ADC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "ADC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "ADC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "ADC_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "ADC_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif ((cpuis("AT91SAM3N*B"))||(cpuis("AT91SAM3N*C")))
|
|
tree "DACC (Digital-to-Analog Converter Controller)"
|
|
base ad:0x4003c000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DACC_CR,DACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
if (((data.long((ad:0x4003c000+0xE4)))&0x1)==0x0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC_MR,DACC Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CLKDIV ,DAC Clock Divider for Internal Trigger"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STARTUP ,Startup Time Selection"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WORD ,Word Transfer" "Half-Word,Word"
|
|
bitfld.long 0x00 4. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4L*"))
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,Peripheral event,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DACC_MR,DACC Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CLKDIV ,DAC Clock Divider for Internal Trigger"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STARTUP ,Startup Time Selection"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WORD ,Word Transfer" "Half-Word,Word"
|
|
bitfld.long 0x00 4. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4L*"))
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,Peripheral event,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,?..."
|
|
endif
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "DACC_CDR,DACC Conversion Data Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x0 "DACC_IMR,DACC Interrupt Mask Register"
|
|
sif (!cpuis("ATSAM4L*"))
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXBUFE ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " ENDTX ,End of PDC Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXRDY ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "DACC_ISR,DACC Interrupt Status Register"
|
|
in
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DACC_WPMR,DACC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DACC_WPSR,DACC Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "DACC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "DACC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "DACC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "DACC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "DACC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "DACC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "DACC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "DACC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "DACC_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DACC_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
textline ""
|